Chip system and working state configuration method

Abstract

The embodiment of the invention provides a chip system and a working state configuration method. The chip system provided by the embodiment of the invention comprises at least one layer of chip, each layer of chip is provided with at least one time sequence device, and the time sequence device comprises a configurable time sequence device with a configurable working state; the two ends of the connecting structure are correspondingly connected with one configurable time sequence device; when the chip system works, if it is determined that the data transmission requirement of the chip system is data transmission, the working state of the configurable time sequence device is configured according to the time sequence requirement of the chip system so as to change the effective transmission path of the chip system. According to the technical scheme provided by the embodiment of the invention, the working state of the configurable time sequence device is configured to change the effective transmission path of the chip system, so that the chip system meets the time sequence requirement of the chip system, the influence on the performance of the chip system due to the incorrect time sequence in the chip system is avoided, and the fault rate of the chip is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuits, and in particular to a chip system and a working state configuration method. Background Art

[0002] With the development of semiconductor chips and the increase in the complexity of integrated circuit design, the design of signal transmission paths in chip systems has become critical. Due to the complexity of the manufacturing process, the delay characteristics of signals transmitted in chip systems in some paths are difficult to accurately predict, and the actual delay may be significantly different from the simulation model, resulting in incorrect timing in the chip system, affecting the performance of the chip system, and in severe cases, may even cause the chip system to malfunction or fail.

[0003] In this context, how to provide a technical solution to ensure the correct timing in the chip system and reduce the failure rate of the chip system has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] To solve the above problems, an embodiment of the present invention provides a chip system and a working state configuration method.

[0005] In a first aspect, an embodiment of the present invention provides a chip system, including:

[0006] At least one layer of chips, each layer of chips is provided with at least one timing device, and the timing device includes a configurable timing device whose working state is configurable;

[0007] A connection structure, with two ends correspondingly connected to one of the configurable timing devices;

[0008] When the chip system is working, if it is determined that the data transmission requirement of the chip system is data transmission, the working state of the configurable timing device is configured according to the timing requirement of the chip system to change the effective transmission path of the chip system;

[0009] The effective transmission path is determined by timing devices in an effective working state connected to both ends of the connection structure and is adapted to the timing requirement.

[0010] In a second aspect, an embodiment of the present invention provides a working state configuration method, which is applied to the chip system according to the first aspect, and the working state configuration method includes:

[0011] Determining the data transmission requirements of the chip system when in operation;

[0012] If it is determined that the data transmission requirement is data transmission, based on the timing requirement of the chip system, configuring the working state of the configurable timing device in the chip system to change the effective transmission path of the chip system;

[0013] The effective transmission path is determined by timing devices in an effective working state connected to both ends of the connection structure, and is adapted to the timing requirements of the chip system.

[0014] The chip system provided by the embodiment of the present invention includes at least one layer of chips, each layer of chips is provided with at least one timing device, and the timing device includes a configurable timing device with a configurable working state; a connection structure, and one of the configurable timing devices is connected to each end; when the chip system is working, if it is determined that the data transmission requirement of the chip system is data transmission, the working state of the configurable timing device is configured according to the timing requirement of the chip system to change the effective transmission path of the chip system; wherein the effective transmission path is determined by the timing devices in the effective working state connected to the two ends of the connection structure, and is adapted to the timing requirement.

[0015] It can be seen that the technical solution provided by the embodiment of the present invention connects one of the configurable timing devices at both ends of the connection structure, so that when the chip system is working, if the data transmission requirement of the chip system is data transmission, the working state of the configurable timing device is configured according to the timing requirement of the chip system to change the effective transmission path of the chip system. The effective transmission path is adapted to the timing requirement, so by covering the effective transmission path, the timing requirement of the chip system can be met when the chip system transmits data, avoiding incorrect timing in the chip system from affecting the performance of the chip system and reducing the chip failure rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of a chip system provided by an embodiment of the present invention.

[0018] Figure 2 is another schematic diagram of a chip system provided by an embodiment of the present invention.

[0019] Figure 3This is another schematic diagram of a chip system provided by an embodiment of the present invention.

[0020] Figures 4 to 8 It is a flow chart of a working status configuration method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] As described in the background technology section, the delay characteristics of signals transmitted in a chip system in some paths are difficult to accurately predict, and the actual delay may be significantly different from the simulation model, resulting in incorrect timing in the chip system, affecting the performance of the chip system, and in severe cases may even cause the chip system to malfunction or fail.

[0022] Since the clock frequency of existing chip systems is relatively high, the higher the clock frequency, the shorter the clock cycle. For example, when the clock frequency of the chip system is 4 GHz, the clock cycle is only 250 ps. This places higher timing requirements on the internal circuits of the chip system.

[0023] However, in the chip system, some physical structures corresponding to effective transmission paths for transmitting data, such as long wires, TSV (Through-Silicon Via) and other structures, may have different manufacturing processes from different wafer manufacturers due to the complexity of production processes, interconnection, packaging and other processes, which may lead to a large gap between the electrical characteristics of some physical structures and the simulation models used in the chip design phase, and thus cause the transmission delay of the signal in some physical structures to be too large or too small, or the signal delay distribution to be very discrete. This problem may cause the circuits inside the chip system to fail to meet the timing requirements, affecting the chip performance, and in severe cases may even cause the chip to malfunction or fail.

[0024] To this end, the present invention provides a chip system and a working state configuration method to ensure the correct timing in the chip system and reduce the failure rate of the chip system.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figure 1 It is a schematic diagram of a chip system provided by an embodiment of the present invention.

[0027] refer to Figure 1 , a chip system 1 provided by an embodiment of the present invention includes:

[0028] At least one layer of chips, each layer of chips is provided with at least one timing device, and the timing device includes a configurable timing device 11 whose working state is configurable;

[0029] The connection structure 10 has two ends correspondingly connected to a configurable timing device 11;

[0030] When the chip system 1 is working, if it is determined that the data transmission requirement of the chip system 1 is data transmission, the working state of the configurable timing device 11 is configured according to the timing requirement of the chip system 1 to change the effective transmission path of the chip system 1;

[0031] The effective transmission path is determined by the timing devices in the effective working state connected to the two ends of the connection structure 10 and is adapted to the timing requirement.

[0032] In the chip system 1 provided in the embodiment of the present invention, when data transmission is required, the data will be transmitted through the connection structure 10 and the configurable timing device 11 correspondingly connected at both ends thereof. Therefore, whether the configurable timing device 11 can transmit data according to the timing requirements of the chip system 1 determines whether the chip system 1 can work normally according to its timing requirements.

[0033] The timing device in the effective working state is a timing device that can perform data transmission normally.

[0034] The connection structure 10 is a physical structure for transmitting data. During the design stage of the chip system 1 , the simulation model of the connection structure 10 has an expected delay, that is, the time required for data transmitted in the chip system 1 to pass through the connection structure 10 .

[0035] When the timing device is in an effective working state, the output at any time depends not only on the input at that time, but also on the input at each past time. For example, the timing device can be a trigger. In the chip system 1, the timing device includes a configurable timing device 11 whose working state is configurable, and one configurable timing device 11 is connected to each end of the connection structure 10. In some specific embodiments, the configurable timing device 11 includes at least one of a trigger, a register or a counter.

[0036] The design files that have passed the test in the design stage of the chip system may be delivered to the wafer foundry for manufacturing. Due to the complexity of the manufacturing process, in the actual product, the electrical characteristics of the connection structure 10 may be significantly different from the simulation model used in the design stage, which may cause the transmission delay of the signal in the connection structure 10 to be too large or too small, or the signal delay distribution to be very discrete, thereby causing the chip system 1 to be unable to work normally according to its timing requirements.

[0037] Therefore, in the chip system provided by the embodiment of the present invention, one configurable timing device 11 is correspondingly connected at both ends of the connection structure 10, so that when the chip system 1 is working, if the data transmission requirement of the chip system 1 is data transmission, the working state of the configurable timing device 11 is configured according to the timing requirement of the chip system 1 to change the effective transmission path of the chip system 1, so that when the chip system 1 transmits data using the changed effective transmission path, the timing requirement of the chip system 1 can be met, thereby avoiding incorrect timing in the chip system 1 affecting the chip system performance and reducing the chip failure rate.

[0038] In some implementations, the working state of the configurable sequential device 11 includes: an enabled state and / or a disabled state.

[0039] Among them, when it is determined that the data transmission requirement of the chip system 1 is data transmission, when the state of the configurable timing device 11 is configured to be an enabled state, the configurable timing device 11 is a timing device in a valid working state; when the state of the configurable timing device 11 is configured to be a disabled state, the configurable timing device 11 is a timing device in an invalid working state, so as to transmit data according to the valid transmission path determined corresponding to the configurable timing device 11 after the working state is configured.

[0040] In some implementations, the sequential device further includes an original sequential device 12 whose working state is maintained in a valid working state. Different from the configurable sequential device 11, the working state of the original sequential device is always maintained in a valid working state.

[0041] In some embodiments, when it is determined that the data transmission demand is for data transmission, the effective transmission path determined corresponding to the configurable timing device 11 after the working state is configured is: the path between the configurable timing device 11 connected to one end of the connection structure 10 and configured to be in a valid working state, to the original timing device 12 connected to the other end of the connection structure 10; or, to the path between the original timing device 12 connected to both ends of the connection structure 10; or, to the path between the configurable timing devices 11 connected to both ends of the connection structure 10 and configured to be in a valid working state.

[0042] For example, refer to Figure 1In some embodiments, the configurable timing device 11 includes a first configurable timing device 111 and a second configurable timing device 112, the first configurable timing device 111 is connected to the front stage of the connection structure 10, and the second configurable timing device 112 is connected to the rear stage of the connection structure 10; the original timing device includes a first original timing device 121 and a second original timing device 122, the first original timing device 121 is connected to the front stage of the connection structure 10, and the second original timing device 122 is connected to the rear stage of the connection structure 10.

[0043] In the above embodiment, the path between the configurable timing device 11 connected to one end of the connection structure 10 and configured as a valid working state to the original timing device connected to the other end of the connection structure 10 is specifically: the path of the first configurable timing device 111 configured as a valid working state-connection structure 10-second original timing device 122, or the first original timing device 121-connection structure 10-second configurable timing device 112 configured as a valid working state.

[0044] The path between the original sequential devices 12 connected to the two ends of the connection structure 10 is specifically: a path of the first original sequential device 121 - the connection structure 10 - the second original sequential device 122 .

[0045] The path between the configurable timing devices 11 connected to both ends of the connection structure 10 and configured as a valid working state is specifically: the path of the first configurable timing device 111 configured as a valid working state-the connection structure 10-the second configurable timing device 112 configured as a valid working state.

[0046] Figure 2 is another schematic diagram of a chip system provided by an embodiment of the present invention, with reference to Figure 2 In some embodiments, the connection structure is: a through silicon via structure 101; the chip system 1 includes an upper chip 102 and a lower chip 103 connected by the through silicon via structure; the configurable timing device 11 includes: a first configurable timing device 111 located in the upper chip 102 and connected to one end of the through silicon via structure 101, and a second configurable timing device 112 located in the lower chip 103 and connected to the other end of the through silicon via structure 101.

[0047] Due to the complexity of the manufacturing process of the through silicon via structure 101, the electrical characteristics of the TSV are quite different from the TSV simulation model used in the chip design stage, resulting in a higher probability of chip failure than conventional interconnect structures (such as through holes). Therefore, a configurable timing device 11 is connected to each end of the through silicon via structure 101, so that the configuration of the working state of the configurable timing device 11 can be more effectively used to change the effective transmission path of the chip system 1, so that the chip system 1 meets its timing requirements.

[0048] In some embodiments, the working state of the configurable timing device 11 also includes: a closed state; if it is determined that the data transmission requirement of the chip system 1 is no data transmission, the working state of the configurable timing device 11 is configured to be a closed state so that there is no data transmission on the effective transmission path.

[0049] It is understandable that in Figure 2 In the chip system 1 shown, when the chip system 1 does not need to transmit data under the current timing requirements, the working state of any one of the first configurable timing device 111 and the second configurable timing device 112 is configured to be off, so that the effective transmission path does not transmit data, thereby reducing the power consumption of the chip system 1 and avoiding interference with other signal processing in the circuit downstream of the configurable timing device 11.

[0050] Figure 3 This is another schematic diagram of the chip system provided by an embodiment of the present invention.

[0051] refer to Figure 3 In some embodiments, the connection structure is: a connecting wire 104 on each layer of chip; the configurable timing device 11 includes: a third configurable timing device 113 located on each layer of chip and connected to one end of the connecting wire 104, and a fourth configurable timing device 114 located on each layer of chip and connected to the other end of the connecting wire 104.

[0052] Since in the design of some chip systems 1, some connecting wires 104 have a longer length (for example, the chip area is large and a plurality of internal devices need to be connected by longer wires), in actual chip products, these longer connecting wires have greater resistance and parasitic inductance than other connecting wires. Since the processes of semiconductor chip manufacturers may be different, when the connecting wire 104 is long, its resistance and parasitic inductance may be significantly different from the simulation model used in the chip design stage, resulting in the chip system 1 not meeting its timing requirements, leading to chip failure. Therefore, by correspondingly connecting one of the configurable timing devices 11 at both ends of the connecting wire 104, the configuration of the working state of the configurable timing logic device 11 can be more effectively utilized to change the effective transmission path of the chip system 1, so that the chip system 1 meets its timing requirements.

[0053] It is understandable that, in some embodiments, the connection structure may also be a cross-chip connection wire, and the chip system includes an upper chip and a lower chip connected by the cross-chip connection wire. Since in some packaging structures, a longer cross-chip connection wire is required between chips of different layers, the cross-chip connection wire connecting the upper chip and the lower chip may face the same problem as the connection wire 104 on each layer of chip, so it is necessary to connect a configurable timing device at both ends of the cross-chip connection wire, so as to more effectively use the configurable timing logic device to change the effective transmission path of the chip system 1 so that the chip system meets its timing requirements.

[0054] In some embodiments, the chip system 1 further includes a gating unit; the gating unit is connected to a clock input port and a data input port of the configurable sequential device 11 to configure a working state of the configurable sequential device 11 based on the gating unit.

[0055] It can be understood that by applying a gating configuration signal to the gating unit, the working state of the configurable timing device 11 can be configured to an enabled state, a disabled state or a closed state, so as to change the effective transmission path of the chip system 1 according to the timing requirements of the chip system 1 under different data transmission requirements.

[0056] by Figure 2 Taking a chip system shown as an example, in some specific embodiments, the gating unit includes a first gating unit 151 and a second gating unit 152, the first gating unit 151 is used to configure the working state of the first configurable timing device 111, and the second gating unit 152 is used to configure the working state of the second configurable timing device 112, so that the effective transmission path of the chip system 1 can be changed according to the timing requirements of the chip system 1.

[0057] An embodiment of the present invention further provides a working state configuration method, which is applied to the chip system described in the above embodiment to ensure the correct timing in the chip system and reduce the failure rate of the chip system.

[0058] For ease of understanding, a working state configuration method provided by an embodiment of the present invention is described in detail below in conjunction with a chip system provided by an embodiment of the present invention.

[0059] Figure 4 is a flow chart of a working status configuration method provided by an embodiment of the present invention. Figure 4 , a working state configuration method provided by an embodiment of the present invention includes:

[0060] Step S100: Determine the data transmission requirements of the chip system when it is working.

[0061] The data transmission requirement is a requirement for whether the chip system needs to perform data transmission. In some cases, the chip system does not need to perform data transmission, and the purpose of reducing power consumption can be achieved by configuring the working state of the configurable timing device.

[0062] After executing step S100, continue to execute step S200.

[0063] Step S200: Determine whether the data transmission requirement is data transmission.

[0064] If it is determined that the data transmission requirement is data transmission, step S300 is executed.

[0065] Step S300: Based on the timing requirements of the chip system, the working state of the configurable timing device in the chip system is configured to change the effective transmission path of the chip system.

[0066] The effective transmission path is determined by timing devices in an effective working state connected to both ends of the connection structure, and is adapted to the timing requirements of the chip system.

[0067] When the chip system needs to transmit data through the connection structure, the chip system needs to meet its timing requirements to ensure the correct transmission of data. Therefore, it is necessary to configure the working state of the configurable timing device in the chip system based on the timing requirements of the chip system to change the effective transmission path of the chip system so that the changed effective transmission path can meet the timing requirements of the chip system when transmitting data, so as to ensure that data can be correctly transmitted in the effective transmission path of the chip system.

[0068] To accurately configure the working state, in one implementation, step S300 may include:

[0069] Based on the determination condition of the timing requirement of the chip system, obtaining a corresponding working state configuration mode defined under the determination condition;

[0070] The working state of the configurable timing device in the chip system is configured using the acquired working state configuration mode.

[0071] The timing requirements in the chip system can be determined based on different determination conditions. Therefore, the corresponding defined working state configuration method can be selected according to the specific determination conditions to accurately configure the working state of the configurable timing device.

[0072] In some embodiments, reference Figure 5 , the determination condition may include: a timing constraint condition; the determination condition based on the timing requirement of the chip system, obtaining the corresponding working state configuration mode defined under the determination condition, including:

[0073] Step S310: Based on the timing constraint condition, obtain the corresponding definition of the first working state configuration method, the first working state configuration method is: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as a valid working state, and the working state of the configurable timing device connected to the other end of the connection structure is configured as an invalid working state.

[0074] Timing requirements refer to the time constraints that must be met by digital circuits, systems or devices during normal operation. In order for the chip system to work properly, all levels of timing devices in the chip system, including the configurable timing device, must meet the timing requirements. Therefore, when the timing requirements are determined based on the timing constraints, the working state of the configurable timing device is configured using the first working state configuration method defined accordingly, thereby changing the effective transmission path so that the chip system can meet the timing constraints for normal operation.

[0075] In some specific implementations, the timing constraints may include: a timing constraint formed based on a setup time constraint and a timing constraint formed based on a hold time constraint.

[0076] After defining the first working state configuration mode, continue to execute step S311.

[0077] Step S311: configuring the working state of the configurable sequential device using the first working state configuration method.

[0078] The effective transmission path in the chip system configured according to step S311 is changed, so that the chip system can meet the timing requirement determined based on the timing constraint condition.

[0079] The following is combined with Figure 2 A chip system is shown, which describes in detail step S300 in a working state configuration method provided by an embodiment of the present invention.

[0080] refer to Figure 2 , let the clock cycle of the chip system 1 be T_Cyc, and the timing constraint condition of the first timing requirement includes a timing constraint condition formed based on the setup time constraint: T_Setup>0.3*T_Cyc.

[0081] The setup time requirement refers to the minimum time that the input signal of the sequential device must remain stable before the effective edge of the clock signal. In other words, the input signal must remain stable before the effective edge of the clock signal arrives, so that the sequential element (such as a trigger) can correctly sample the input signal.

[0082] In such Figure 2 In a chip system shown, the original timing device 12 includes a first original timing device 121 and a second original timing device 122. For data transmitted by the chip system 1 under current data transmission requirements, the total transmission delay of the through silicon via structure 101, the combinational logic Logic2 and the combinational logic Logic3 is T_tsv=0.6*T_cyc, the delay of the combinational logic Logic1 is T_1=0.2*T_cyc, and the delay of the combinational logic Logic4 is T_4=0.5*T_cyc; the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 are all D flip-flops (Data Flip-Flop, DFF), and the transmission delays of the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 are negligible.

[0083] Execute step S310, that is, based on the timing constraint condition, use the corresponding defined first working state configuration method to configure the working state of the configurable timing device 11 connected to one end of the through silicon via structure 101 to a valid working state, and configure the working state of the configurable timing device 11 connected to the other end of the through silicon via structure 101 to an invalid working state.

[0084] For example, the original working state of the configurable sequential logic device 11 (i.e., the working state of the chip system 1 that does not meet the setup time requirement) is: the working state of the first configurable sequential device 111 is an enabled state, and the working state of the second configurable sequential device 112 is a disabled state. When the chip system 1 does not meet the setup time requirement, step S311 is executed: the working state of the configurable sequential device 11 is configured according to the first working state configuration mode, thereby changing the effective transmission path of the chip system 1, so that the effective transmission path is adapted to the timing constraint condition of the chip system 1.

[0085] Specifically, since in the original working state, the working state of the first configurable timing device 111 is an enabled state, according to the first working state configuration method, it is necessary to configure the working state of the second configurable timing device 112 connected to one end of the through silicon via structure 101 to a valid working state, and configure the working state of the second configurable timing device 111 connected to the other end of the connection structure to an invalid working state, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the timing constraints of the chip system 1.

[0086] In the original working state, the effective transmission path in the chip system 1 is: the first original timing device 121-the first configurable timing device 111-the silicon through via structure 101-the second original timing device 122, wherein the signal output by the first configurable timing device 111 is received and sampled by the second original timing device 122 after passing through T_tsv+T_4=1.1*Tcyc; however, for the timing device connected to the silicon through via structure 101, the setup time requirement is T_Setup>0.3*T_Cyc, and T_Setup of the second original timing device 122 is the part of T_real+T_4 that exceeds the integer multiple of the clock cycle, that is, T_Setup=(T_real+T_4)modT_cyc=0.1*T_Cyc<0.3*T_Cyc.

[0087] The reason for the above problem is that in the simulation model used in the design stage of the chip system 1, the expected total transmission delay of the through silicon via structure 101, the combinational logic Logic2 and the combinational logic Logic3 is T_design=0.2*T_cyc, however, in the actual product, the transmission delay of the through silicon via structure 101 increases, resulting in the total transmission delay T_tsv>T_design of the through silicon via structure 101, the combinational logic Logic2 and the combinational logic Logic3, which ultimately results in the second original timing device 122 in the chip system 1 not meeting the setup time requirement.

[0088] According to the first working state configuration mode, after the working state of the configurable timing device 11 is configured by the first gating unit 151 and the second gating unit 152, the effective transmission path in the chip system 1 is changed, and the changed effective transmission path is: the first original timing device 121-silicon through hole structure 101-the second configurable timing device 112-the second original timing device 122; it can be seen that for the timing device in the effective working state connected to the silicon through hole structure 101, the establishment time of the second configurable timing logic device 112 is T_Setup=T_1+T_tsv=0.8T_Cyc>0.3*T_Cyc, which meets the establishment time requirement. In addition, the number of pipeline stages of the effective transmission path before and after the change does not change, so that the chip system 1 can meet the timing constraint conditions formed by its establishment time constraint without introducing additional pipeline stages and avoiding the increase of the delay of the chip system 1, thereby ensuring the normal operation of the chip system and reducing the failure rate of the chip system.

[0089] In some other implementations, the timing constraint condition includes a timing constraint condition formed based on a hold time constraint: T_Setup>0.3*T_Cyc.

[0090] The Hold Time Requirement refers to the minimum time that the input signal must remain stable after the effective edge of the clock signal. That is to say, for a sequential logic element, the input signal cannot change immediately after the clock edge arrives, and must remain in the current state for a period of time to ensure that the sequential logic element can correctly sample the input signal.

[0091] Continue to refer Figure 2 , for the signal transmitted by the chip system 1 under the current data transmission requirement, the total transmission delay of the through silicon via structure 101, the combinational logic Logic2 and the combinational logic Logic3 is T_tsv=0.1*T_cyc, the delay of the combinational logic Logic1 is T_1=0.5*T_cyc, and the delay of the combinational logic Logic4 is T_4=0.1*T_cyc; the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 are all D flip-flops, and the transmission delays of the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 are negligible.

[0092] Execute step S310, that is, based on the timing constraint condition, define the first working state configuration mode as: configuring the working state of the configurable timing device 11 connected to one end of the through silicon via structure 101 to a valid working state, and configuring the working state of the configurable timing device 11 connected to the other end of the through silicon via structure 101 to an invalid working state.

[0093] For example, the original working state of the configurable sequential logic device 11 (i.e., the working state of the chip system 1 that does not meet the hold time requirement) is: the working state of the first configurable sequential device 111 is an enabled state, and the working state of the second configurable sequential device 112 is a disabled state. When the chip system 1 does not meet the timing constraint condition formed by the hold time constraint, step S311 is executed: the working state of the configurable sequential device 11 is configured according to the first working state configuration mode, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the timing requirement of the chip system 1 (i.e., the timing constraint condition established by the hold time constraint).

[0094] Specifically, since in the original working state, the working state of the first configurable timing device 111 is enabled, according to the first working state configuration method, it is necessary to configure the working state of the second configurable timing device 112 connected to one end of the through silicon via structure 101 to a valid working state, and configure the working state of the second configurable timing device 111 connected to the other end of the connection structure to an invalid working state, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is consistent with the timing requirements of the chip system 1.

[0095] In the original working state, the effective transmission path in the chip system 1 is: the first original sequential device 121 - the first configurable sequential device 111 - the through silicon via structure 101 - the second original sequential device 122 .

[0096] Among them, the data output by the first configurable timing device 111 is received and sampled by the second original timing device 122 after T_tsv + T_4 = 0.2 * Tcyc; however, for the timing devices in the active working state connected by the through-silicon via structure 101, the hold time requirement is T_Hold > 0.3 * T_Cyc, and the hold time T_Hold of the second original timing device 122 is 0.2 * T_Cyc < 0.3 * T_Cyc. The reason for this problem is that in the simulation model used in the design stage of the chip system 1, the expected total transmission delay of the through-silicon via structure 101, combinational logic Logic2, and combinational logic Logic3 is T_design = 0.5 * T_cyc. However, in the actual product, the transmission delay of the through-silicon via structure 101 is reduced, resulting in the total transmission delay T_tsv of the through-silicon via structure 101, combinational logic Logic2, and combinational logic Logic3 being less than T_design. Eventually, in the chip system 1, the second original timing device 122 does not meet the timing constraint conditions formed by the hold time constraint.

[0097] According to the first working state configuration method, after configuring the working state of the configurable timing device 11 through the first gating unit 151 and the second gating unit 152, the effective transmission path in the chip system 1 changes. The changed effective transmission path is: the first original timing device 121 - through-silicon via structure 101 - second configurable timing device 112 - second original timing device 122; it can be seen that for the timing devices in the active working state connected by the through-silicon via structure 101, the hold time of the second configurable timing logic device 112 is: T_Hold = T_1 + T_tsv = 0.8T_Cyc > 0.3 * T_Cyc, which meets the timing constraint conditions formed based on the hold time constraint. Moreover, the number of pipeline stages of the effective transmission path does not change before and after the change, so that the chip system 1 can meet its timing requirements without introducing additional pipeline stages and avoiding an increase in the delay of the chip system 1, ensuring the normal operation of the chip system and reducing the failure rate of the chip system.

[0098] According to the above implementation mode, the working state configuration method provided by the embodiment of the present invention determines that when the data transmission requirement of the chip system during operation is data transmission, based on the timing requirement determined by the timing constraint condition in the chip system, a first working state configuration method is defined as: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as a valid working state, and the working state of the configurable timing device connected to the other end of the connection structure is configured as an invalid working state, and the working state of the configurable timing device is configured according to the first working state configuration method to change the effective transmission path of the chip system; wherein the effective transmission path is determined by the timing devices in the effective working state connected to both ends of the connection structure, and is adapted to the timing requirement of the chip system.

[0099] It can be seen that the working state configuration method provided by the embodiment of the present invention, when the chip system does not meet the timing constraint conditions formed based on establishing time constraints and maintaining time constraints, configures the working state of the configurable timing device connected to one end of the connection structure of the chip system to a valid working state, and configures the working state of the configurable timing device connected to the other end of the connection structure to an invalid working state in a first working state configuration mode, thereby changing the effective transmission path of the chip system, and enabling the chip system to meet its timing requirements, ensure the normal operation of the chip system, and reduce the failure rate of the chip system without introducing additional pipeline stages and avoiding an increase in the delay of the chip system.

[0100] In some embodiments, reference Figure 6 and Figure 7 , the determination condition includes: a design clock frequency condition; the determination condition based on the timing requirement of the chip system, obtaining a corresponding working state configuration mode defined under the determination condition, including:

[0101] Step S320: Based on the design clock frequency condition, obtain a corresponding defined second working state configuration method, wherein the second working state configuration method is: configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system to a valid working state, and configuring the working state of the configurable timing device connected to the other end of the connection structure to an invalid working state.

[0102] or, as Figure 7 Step S321 shown: based on the design clock frequency of the second timing requirement, define the second working state configuration method as: configuring the working state of the configurable timing device connected to the two ends of the connection structure of the chip system to a valid working state.

[0103] In some embodiments, it is necessary to increase or temporarily increase the clock frequency of the chip system 1 to the design clock frequency to optimize the performance of the chip system 1, for example, to increase the data throughput of the chip system 1, or to increase the response speed of the chip system 1. The design clock frequency is the clock frequency that enables the chip system 1 to work as designed. It can be seen that under the timing requirements determined based on the design clock frequency conditions, the chip system can work as designed.

[0104] After the defined configuration mode of the second working state is acquired, step S322 is continued.

[0105] Step S322: configuring the working state of the configurable sequential device using the second working state configuration method.

[0106] The effective transmission path in the chip system after configuration in step S322 is changed, so that the chip system can meet the design clock frequency condition.

[0107] The following is combined with Figure 2 A chip system is shown, which describes in detail step S300 in a working state configuration method provided by an embodiment of the present invention.

[0108] refer to Figure 2 , the clock cycle of the chip system 1 is T_Cyc=600ps, that is, the clock frequency of the current state of the timing circuit is f_0=1.67GHz. For the data transmitted by the chip system 1 under the current data transmission requirement, the total transmission delay of the silicon through hole structure 101, the combinational logic Logic2 and the combinational logic Logic3 is T_tsv=200ps, the delay of the combinational logic Logic1 is T_1=200ps, and the delay of the combinational logic Logic4 is T_4=200ps; the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 are all D flip-flops (Data Flip-Flop, DFF), and the transmission delays of the first original timing device 121, the second original timing device 122, the first configurable timing device 111 and the second configurable timing device 112 can be ignored.

[0109] Execute step S320, that is, based on the design clock frequency condition, obtain the corresponding defined second working state configuration mode, configure the working state of the configurable timing device 11 connected to one end of the through silicon via structure 101 to a valid working state, and configure the working state of the configurable timing device 11 connected to the other end of the through silicon via structure 101 to an invalid working state.

[0110] For example, the original working state of the configurable sequential logic device 11 (i.e., the working state of the chip system 1 not meeting the design clock frequency requirement) is: the working states of the first configurable sequential logic device 111 and the second configurable sequential logic device 112 are both in a disabled state. When the chip system 1 does not meet the design clock frequency condition, step S322 is executed: the working state of the configurable sequential device 11 is configured according to the second working state configuration mode, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the timing requirement of the chip system 1 (i.e., the second timing requirement).

[0111] Specifically, since in the original working state, the working states of the first configurable timing device 111 and the second configurable timing logic device 112 are both in the disabled state, according to the second working state configuration method, it is necessary to configure the working state of the first configurable timing device 111 connected to one end of the through silicon via structure 101 to a valid working state, and configure the working state of the second configurable timing device 112 connected to the other end of the connection structure to an invalid working state, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to the design clock frequency condition of the chip system 1.

[0112] In the original working state, the effective transmission path in the chip system 1 is: the first original timing device 121-silicon through-via structure 101-the second original timing device 122, wherein the signal output by the first original timing device 121 is received and sampled by the second original timing device 122 after T_1+T_tsv+T_4=600ps; however, in one embodiment, the design clock frequency condition is f≥2GHz, that is, the transmission delay T≤500ps between any two levels of timing devices in the chip system 1.

[0113] According to the second working state configuration method defined in step S320, after the working state of the configurable timing device 11 is configured by the first gating unit 151 and the second gating unit 152, the effective transmission path in the chip system 1 is changed, and the changed effective transmission path is: the first original timing device 121-the first configurable timing device 111-the through silicon via structure 101-the second original timing device 122; it can be seen that for the timing devices in the effective working state connected to the through silicon via structure 101, the maximum transmission delay between any two levels of timing devices is T_tsv+T_4=400ps≤500ps, which can meet the design clock frequency condition.

[0114] In another embodiment, the design clock frequency condition is f≥4GHz, that is, the transmission delay T≤250ps between any two stages of sequential devices in the chip system 1. The second working state configuration method defined in step S320 cannot meet the design clock frequency requirement, so it is necessary to define the second working state configuration method in step S321 as follows: the working state of the configurable sequential device connected to both ends of the connection structure of the chip system is configured as a valid working state.

[0115] The effective transmission path after the change is: the first original timing device 121-the first configurable timing device 111-the through silicon via structure 101-the second configurable timing device 112-the second original timing device 122; it can be seen that for the timing devices connected to the through silicon via structure 101, the maximum transmission delay between any two levels of timing devices is T_1=T_tsv=T_4=200ps≤250ps, which can meet the design clock frequency condition.

[0116] According to the above implementation mode, the working state configuration method provided by the embodiment of the present invention determines that when the data transmission requirement of the chip system during operation is data transmission, based on the timing requirement determined by the design clock frequency condition in the chip system, the second working state configuration method is defined as: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as a valid working state, and the working state of the configurable timing device connected to the other end of the connection structure is configured as an invalid working state; or, the second working state configuration method is defined as: the working state of the configurable timing device connected to both ends of the connection structure of the chip system is configured as a valid working state; and according to the first working state configuration method, the working state of the configurable timing device is configured to change the effective transmission path of the chip system; wherein, the effective transmission path is determined by the timing devices in the effective working state connected to both ends of the connection structure, and is adapted to the timing requirements of the chip system.

[0117] It can be seen that the working state configuration method provided by the embodiment of the present invention, when the chip system does not meet the design clock frequency requirement, changes the effective transmission path of the chip system, so that the clock frequency of the chip system is increased to the design clock frequency, meets the design clock frequency, and optimizes the performance of the chip system by configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system as a valid working state and configuring the working state of the configurable timing device connected to the other end of the connection structure as an invalid working state in the second working state configuration mode, or configuring the working state of the configurable timing device connected to both ends of the connection structure of the chip system as a valid working state in the second working state configuration mode.

[0118] Continue to refer Figure 4 If it is determined that the data transmission requirement is no data transmission, execute step S400.

[0119] Step S400: Based on the timing requirements of the chip system, the working state of the configurable timing device in the chip system is configured so that there is no data transmission on the effective transmission path of the chip system.

[0120] When the chip system does not need to transmit data through the connection structure, that is, when there is no data transmission demand, the working state of the configurable timing device in the chip system is configured based on the timing requirements of the chip system so that the effective transmission path of the chip system does not transmit data, thereby reducing the power consumption of the chip system.

[0121] refer to Figure 8 , when the data transmission requirement is no data transmission, the determination condition further includes: low power data transmission condition; the determination condition based on the timing requirement of the chip system, obtaining the corresponding working state configuration mode defined under the determination condition, including:

[0122] Step S410: Based on the low-power data transmission condition, obtain a correspondingly defined third working state configuration method, wherein the third working state configuration method is: configuring the working state of any configurable timing device connected to both ends of the connection structure of the chip system to a closed working state.

[0123] In some implementations, it is necessary to reduce the power consumption of the chip system 1 to avoid additional energy consumption. It can be seen that after configuring the working state of the configurable timing device based on the timing requirements determined based on the low power data transmission condition, the chip system can meet the low power data transmission condition.

[0124] After the corresponding defined configuration mode of the third working state is acquired, step S411 is continued.

[0125] Step S411: configuring the working state of the configurable sequential device using the third working state configuration method.

[0126] The effective transmission path in the chip system after configuration in step S411 is changed, so that the chip system can meet the low-power data transmission condition.

[0127] Step S411 may include: using the third working state configuration mode to configure the working state of the configurable timing device connected to any end of the connection structure to a closed state; wherein, in the closed state, the output port of the configurable timing device outputs a fixed value.

[0128] The fixed value (Sig_1) may be 0, and power consumption is saved by reducing the toggle mode of useless data transmission.

[0129] The working state of the configurable timing device is configured to be off, so that there is no data transmission, the power consumption of the chip system is reduced, and the low-power data transmission condition is met.

[0130] The following is combined with Figure 2 A chip system is shown, which describes in detail step S400 in a working state configuration method provided by an embodiment of the present invention.

[0131] refer to Figure 2 When the data transmission requirement is no data transmission, step S410 is executed, that is, the working state of the configurable timing device is configured based on the third working state configuration method corresponding to the low-power data transmission condition, and the third working state configuration method is: the working state of the configurable timing device 11 connected to one end of the through silicon via structure 101 is configured to be a closed working state.

[0132] For example, the original working state of the configurable sequential logic device 11 (i.e., the working state of the chip system 1 that does not meet the design clock frequency requirement) is: the working state of the first configurable sequential logic device 111 is an enabled state, and the working states of the second configurable sequential logic device 112 are all disabled states. When the chip system 1 does not need to transmit data through the through silicon via structure 101, step S411 is executed: the working state of the configurable sequential device 11 is configured using the third working state configuration method, thereby changing the effective transmission path of the chip system 1, so that the effective transmission path is adapted to the low-power data transmission condition of the chip system 1.

[0133] Specifically, according to the third working state configuration mode, the working state of the second configurable timing device 112 connected to one end of the through silicon via structure 101 is configured to be a closed working state, thereby changing the effective transmission path of the chip system 1 so that the effective transmission path is adapted to low-power data transmission conditions.

[0134] According to the third working state configuration method defined in step S410, after the working state of the configurable timing device 11 is configured by the second gating unit 152, the effective transmission path in the chip system 1 is changed, and the changed effective transmission path is: the first original timing device 121-the first configurable timing device 111-the through silicon via structure 101-the second configurable timing device 112; it can be seen that the second original timing device 122 and other downstream timing devices thereof do not perform data transmission, thereby satisfying the low-power data transmission condition.

[0135] According to the above implementation mode, the working state configuration method provided by the embodiment of the present invention determines that when the data transmission demand of the chip system during operation is no data transmission, based on the low-power data transmission condition in the chip system, a correspondingly defined third working state configuration method is obtained, and the third working state configuration method is: the working state of the configurable timing device connected to one end of the connection structure of the chip system is configured as a valid working state, and the working state of the configurable timing device connected to the other end of the connection structure is configured as an invalid working state; or, the second working state configuration method is defined as: the working state of any configurable timing device connected to both ends of the connection structure of the chip system is configured as a closed working state; wherein the effective transmission path is determined by the timing devices in the effective working state connected to both ends of the connection structure, and is adapted to the low-power data transmission condition.

[0136] It can be seen that the working state configuration method provided by the embodiment of the present invention, when the chip system does not meet the low-power data transmission conditions, configures the working state of the configurable timing device connected to one end of the connection structure of the chip system to a closed working state, thereby changing the effective transmission path of the chip system and reducing the power consumption of the chip system.

[0137] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A chip system, characterized in that: include: At least one layer of chips, each layer of chips is provided with at least one timing device, and the timing device includes a configurable timing device whose working state is configurable; A connection structure, with two ends correspondingly connected to one of the configurable timing devices; When the chip system is working, if it is determined that the data transmission requirement of the chip system is data transmission, the working state of the configurable timing device is configured according to the timing requirement of the chip system to change the effective transmission path of the chip system; The effective transmission path is determined by timing devices in an effective working state connected to both ends of the connection structure and is adapted to the timing requirement.

2. The chip system according to claim 1, characterized in that: The sequential device also includes an original sequential device whose working state is maintained as a valid working state; the working state of the configurable sequential device includes an enabled state and / or a disabled state; When it is determined that the data transmission requirement of the chip system is data transmission, when the state of the configurable timing device is configured to be an enabled state, the configurable timing device is a timing device in a valid working state; when the state of the configurable timing device is configured to be a disabled state, the configurable timing device is a timing device in an invalid working state, so as to transmit data according to the valid transmission path determined corresponding to the configurable timing device after the working state is configured.

3. The chip system according to claim 2, characterized in that: According to the configured working state, the corresponding valid transmission path of the configurable timing device is: A path between a configurable sequential device connected to one end of the connection structure and configured as a valid working state, and the original sequential device connected to the other end of the connection structure; or, a path between the original sequential devices connected to both ends of the connection structure; Or, a path between configurable sequential devices connected to both ends of the connection structure and whose working state is configured as a valid working state.

4. The chip system according to claim 1, characterized in that: The working state of the configurable timing device also includes: a closed state; if it is determined that the data transmission requirement of the chip system is no data transmission, the working state of the configurable timing device is configured to be a closed state, so that there is no data transmission on the effective transmission path.

5. The chip system according to any one of claims 1 to 4, characterized in that: The connection structure is: a through silicon via structure; the chip system includes an upper chip and a lower chip connected by the through silicon via structure; the configurable timing device includes: a first configurable timing device located in the upper chip and connected to one end of the through silicon via structure, and a second configurable timing device located in the lower chip and connected to the other end of the through silicon via structure.

6. The chip system according to any one of claims 1 to 4, characterized in that: The connection structure is: a connecting wire on each layer of chips; the configurable timing device includes: a third configurable timing device located on each layer of chips and connected to one end of the connecting wire, and a fourth configurable timing device located on each layer of chips and connected to the other end of the connecting wire.

7. The chip system according to any one of claims 1 to 4, characterized in that: The configurable timing device includes at least one of a trigger, a register or a counter.

8. The chip system according to any one of claims 1 to 4, characterized in that: Also includes: Door control unit; The gating unit is connected to the clock input port and the data input port of the configurable sequential device, so as to configure the working state of the configurable sequential device based on the gating unit.

9. A working status configuration method, characterized in that: Applied to the chip system according to any one of claims 1 to 8, the method comprising: Determining the data transmission requirements of the chip system when in operation; If it is determined that the data transmission requirement is data transmission, based on the timing requirement of the chip system, configuring the working state of the configurable timing device in the chip system to change the effective transmission path of the chip system; The effective transmission path is determined by timing devices in an effective working state connected to both ends of the connection structure, and is adapted to the timing requirements of the chip system.

10. The working status configuration method according to claim 9, characterized in that: The configuring the working state of the configurable timing device in the chip system based on the timing requirement of the chip system includes: Based on the determination condition of the timing requirement of the chip system, obtaining a corresponding working state configuration mode defined under the determination condition; The working state of the configurable timing device in the chip system is configured using the acquired working state configuration mode.

11. The working status configuration method according to claim 10, characterized in that: The determination condition includes: a timing constraint condition; the determination condition based on the timing requirement of the chip system, and obtaining a corresponding working state configuration mode defined under the determination condition, including: Based on the timing constraint condition, a corresponding first working state configuration mode is obtained, wherein the first working state configuration mode is: configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system to a valid working state, and configuring the working state of the configurable timing device connected to the other end of the connection structure to an invalid working state; The step of configuring the working state of the configurable timing device in the chip system by using the acquired working state configuration mode includes: The working state of the configurable sequential device is configured using the first working state configuration method.

12. The working status configuration method according to claim 11, characterized in that: The configuring the working state of the configurable sequential device by using the first working state configuration method includes: Using the first working state configuration mode, the working state of the configurable sequential device connected to one end of the connection structure is configured to be an enabled state, so that the working state of the configurable sequential device is a valid working state; The working state of the configurable sequential device connected to the other end of the connection structure is configured as a disabled state, so that the working state of the configurable sequential device is an invalid working state.

13. The working status configuration method according to claim 12, characterized in that: The timing constraints include: timing constraints formed based on setup time constraints and timing constraints formed based on hold time constraints.

14. The working status configuration method according to claim 10, characterized in that: The determination condition includes: a design clock frequency condition; the determination condition based on the timing requirement of the chip system, and obtaining a corresponding working state configuration mode defined under the determination condition, including: Based on the design clock frequency condition, a corresponding defined second working state configuration mode is obtained, wherein the second working state configuration mode is: configuring the working state of the configurable timing device connected to one end of the connection structure of the chip system to a valid working state, and configuring the working state of the configurable timing device connected to the other end of the connection structure to an invalid working state; Or, the second working state configuration mode is defined as: configuring the working state of the configurable timing device connected to both ends of the connection structure of the chip system to a valid working state; The step of configuring the working state of the configurable timing device in the chip system by using the acquired working state configuration mode includes: The working state of the configurable sequential device is configured using the second working state configuration method.

15. The working status configuration method according to claim 14, characterized in that: The configuring the working state of the configurable sequential device by using the second working state configuration method includes: By using the second working state configuration mode, the working state of the configurable sequential device connected to one end of the connection structure is configured to be an enabled state, so that the working state of the configurable sequential device is a valid working state; Configuring the working state of the configurable sequential device connected to the other end of the connection structure to be a disabled state, so that the working state of the configurable sequential device is an invalid working state; Or, the working states of the configurable sequential devices connected to both ends of the connection structure are configured as enabled states by using the second working state configuration method, so that the working state of the configurable sequential devices is a valid working state.

16. The working status configuration method according to claim 15, characterized in that: Also includes: If it is determined that the data transmission requirement is no data transmission, based on the timing requirement of the chip system, the working state of the configurable timing device in the chip system is configured so that there is no data transmission on the effective transmission path of the chip system.

17. The working status configuration method according to claim 16, characterized in that: The determination condition further includes: a low power data transmission condition; the determination condition based on the timing requirement of the chip system, obtaining a corresponding working state configuration mode defined under the determination condition, including: Based on the low-power data transmission condition, a correspondingly defined third working state configuration mode is obtained, wherein the third working state configuration mode is: configuring the working state of any configurable timing device connected to both ends of the connection structure of the chip system to a closed working state; The step of configuring the working state of the configurable timing device in the chip system by using the acquired working state configuration mode includes: The working state of the configurable sequential device is configured using the third working state configuration method.

18. The working status configuration method according to claim 17, characterized in that: The step of configuring the working state of the configurable sequential device by using the third working state configuration method includes: By using the third working state configuration mode, the working state of the configurable timing device connected to any end of the connection structure is configured to be a closed state; Wherein, in the closed state, the output port of the configurable timing device outputs a fixed value.

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