Digital model of FPGA (Field Programmable Gate Array) configuration circuit, FPGA data configuration method, equipment and medium

Abstract

The invention provides a digital model of an FPGA configuration circuit, an FPGA data configuration method, equipment and a medium. The digital model comprises a parameter configuration module, a read-write processing module and a configuration state determination module. According to the digital model provided by the invention, the configuration of the digital model is realized through the parameter configuration module, so that the digital model can adapt to FPGA chips of different models, an FPGA configuration circuit does not need to be greatly modified, and the universality is high; the configuration of the FPGA chip and the configuration state detection are realized through the read-write processing module and the configuration state determination module, so that the configuration of the FPGA chip can be effectively completed; and the digital model adopts a partitioning design, so that a user can efficiently maintain and upgrade each module, and can expand on the basis of functional modules to support more types of FPGA chips and meet more configuration scene requirements.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a digital model of an FPGA configuration circuit, an FPGA data configuration method, a device and a medium. Background Art

[0002] With the rapid development of electronic technology, FPGA is increasingly used in digital circuit design. FPGA has the characteristics of programmability, reconfigurability, and high integration, which makes it of great value in many fields. However, the configuration process of FPGA is a complex and error-prone process, especially different models of FPGA have different configuration methods and interfaces, which brings great troubles to circuit design and circuit verification.

[0003] The FPGA configuration circuit is responsible for loading the configuration data into the programmable logic resources of the FPGA so that the FPGA can be programmed to implement specific digital circuit functions. In related technologies, the design of the FPGA configuration circuit is usually carried out for a specific model of FPGA, that is, when different models of FPGA need to be configured, the configuration circuit model needs to be redesigned for each model, which lacks versatility and scalability. This not only increases the design workload and prolongs the time to market, but may also lead to waste of resources and design redundancy.

[0004] Therefore, it is necessary to improve the FPGA configuration circuit model. Summary of the invention

[0005] The main purpose of this application is to provide a digital model of an FPGA configuration circuit, an FPGA data configuration method, a device and a medium, which can at least solve the problem of poor versatility and scalability of FPGA configuration circuit models in related technologies.

[0006] To achieve the above-mentioned purpose, the first aspect of the present application provides a digital model of an FPGA configuration circuit, which includes: a parameter configuration module, a read-write processing module and a configuration status determination module; the parameter configuration module is configured to: configure the digital model according to the input FPGA configuration parameters; wherein the FPGA configuration parameters include the FPGA model and the FPGA working mode; the read-write processing module is configured to: after the configuration of the digital model is completed, write the input target FPGA configuration data to an external FPGA chip, or read the target FPGA configuration data from an external FPGA chip, verify the target FPGA configuration data, and obtain a verification result; the configuration status determination module is configured to: determine the configuration status of the FPGA chip according to the verification result and the level type of the status pin of the FPGA chip.

[0007] A second aspect of the present application provides an FPGA data configuration method, which is applied to a digital model of an FPGA configuration circuit, the method comprising: configuring the digital model according to input FPGA configuration parameters; wherein the FPGA configuration parameters include an FPGA model and an FPGA operating mode; after the digital model configuration is completed, writing the input target FPGA configuration data to an external FPGA chip, or reading the target FPGA configuration data from an external FPGA chip, verifying the target FPGA configuration data to obtain a verification result; determining the configuration state of the FPGA chip according to the verification result and the level type of the status pin of the FPGA chip.

[0008] The third aspect of the present application provides an electronic device, comprising: a memory and a processor, wherein the processor is used to execute a computer program stored in the memory, and when the processor executes the computer program, it implements the steps of the FPGA data configuration method provided in the second aspect of the present application.

[0009] The fourth aspect of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, each step of the FPGA data configuration method provided in the second aspect of the present application is implemented.

[0010] As can be seen from the above, the digital model of the FPGA configuration circuit of the present application scheme realizes the configuration of the digital model through the parameter configuration module, so that the digital model can adapt to different types of FPGA chips, without the need to significantly modify the FPGA configuration circuit, and has strong versatility; the configuration and configuration status detection of the FPGA chip are realized through the read-write processing module and the configuration status determination module, so that the configuration of the FPGA chip can be effectively completed; and the digital model adopts a block design, users can efficiently maintain and upgrade each module, and can also be expanded on the basis of the functional module to support more types of FPGA chips and meet the needs of more configuration scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 A schematic diagram of the structure of a digital model of an FPGA configuration circuit provided in an embodiment of the present application;

[0013] Figure 2A flowchart of an FPGA data configuration method provided in one embodiment of the present application;

[0014] Figure 3 A schematic diagram of the workflow of a digital model provided in one embodiment of the present application;

[0015] Figure 4 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0017] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0018] In order to solve the problem of poor versatility and scalability of FPGA configuration circuit models in related technologies, an embodiment of the present application provides a digital model of an FPGA configuration circuit, such as Figure 1 As shown, the digital model of the FPGA configuration circuit mainly includes: a parameter configuration module, a read-write processing module and a configuration status determination module; the parameter configuration module is configured to: configure the digital model according to the input FPGA configuration parameters; wherein the FPGA configuration parameters include the FPGA model and the FPGA working mode; the read-write processing module is configured to: after the digital model configuration is completed, write the input target FPGA configuration data to the external FPGA chip, or read the target FPGA configuration data from the external FPGA chip, verify the target FPGA configuration data, and obtain the verification result; the configuration status determination module is configured to: determine the configuration status of the FPGA chip according to the verification result and the level type of the status pin of the FPGA chip.

[0019] Specifically, in this embodiment, the digital model realizes the configuration of the digital model through the parameter configuration module, so that the digital model can adapt to different types of FPGA chips, so that in the configuration scenarios of various types of FPGA, there is no need to significantly modify the FPGA configuration circuit, and the versatility is strong; the configuration and configuration status detection of the FPGA chip are realized through the read-write processing module and the configuration status determination module, so that the configuration of the FPGA chip can be effectively completed; and the digital model adopts a block design, and the user can efficiently maintain and upgrade each module, and can also be expanded on the basis of the functional module to support more types of FPGA chips and meet more configuration scenario requirements. In addition, the digital model in this embodiment is a SystemVerilog model. The System Verilog language has the characteristics of higher level and high flexibility, which makes the implementation of the model more readable than the implementation of hardware description languages ​​such as Verilog.

[0020] Furthermore, in some implementations of the present embodiment, the parameter configuration module includes a parameter configuration unit and a parameter initialization unit; the parameter configuration unit is configured to: configure the target model parameters of the digital model according to the input FPGA model; wherein the target model parameters include: an identifier, a register address list, a register domain, a configuration package format and a frame length; the parameter initialization unit is configured to: initialize the corresponding registers in the digital model according to the FPGA model and the FPGA working mode.

[0021] Specifically, in this embodiment, when the parameter configuration module receives the FPGA configuration parameters from the outside, it will perform parameter configuration on the digital model according to the FPGA configuration parameters to ensure that the digital model can accurately complete the FPGA configuration task. The FPGA configuration parameters can be FPGA models, FPGA working modes such as serial mode and parallel mode; wherein, according to the FPGA model, the unique identifier of the corresponding FPGA chip can be matched, and the associated register address list, register domain, configuration package format, frame length and other parameter values ​​can be matched, and the matched parameter values ​​are used to configure the corresponding parameters of the digital model; the register address list can include CRC register, frame address register, frame data input register, frame data output register, status register, control mask register, command register, device identification register, and the configuration package format includes header type, operation code, register address, and word number. After that, the corresponding registers (such as control registers and status registers) in the digital model will be initialized according to the FPGA model and FPGA working mode. After the digital model is parameterized and initialized, the digital model can realize the function of the FPGA configuration circuit applicable to the FPGA model. Thus, the digital model can be adapted to the configuration requirements of different scenarios through parameter configuration, which improves the flexibility of configuration.

[0022] Furthermore, in some implementations of the present embodiment, the digital model also includes a configuration interface and a bitstream instruction parsing module. The configuration interface is used to connect to the FPGA chip and receive the FPGA configuration bitstream file. The bitstream instruction parsing module is configured to: parse the FPGA configuration bitstream file to obtain a configuration package and configuration instructions; convert the configuration package and configuration instructions to obtain corresponding operation signals; wherein the operation signal is used to instruct the read-write processing module to write the input target FPGA configuration data into an external FPGA chip; or, to instruct the read-write processing module to read the target FPGA configuration data from an external FPGA chip.

[0023] Specifically, in this embodiment, after the parameter configuration module completes the processing, the bitstream instruction parsing module receives the FPGA configuration bitstream file from the configuration interface, and obtains the configuration package and configuration instructions by parsing the FPGA configuration bitstream file. Through the header type, operation code, register address, word count and other fields in the configuration package, the type of the configuration package, the operation to be performed on the device to be configured (such as read, write operation), the register address to be configured, the number of words to be written or read and other information can be understood. The configuration instruction can be a bus width detection instruction, a bus width synchronization instruction, a CRC configuration and readback instruction, a frame address control instruction, a frame data configuration instruction, a frame data readback instruction, a control shield instruction, a status readback instruction, a command configuration instruction, a device identification configuration instruction, a startup instruction, etc. The parsed configuration package and configuration instruction are converted into an operation signal that can be recognized by the digital model, and the operation signal is used to instruct the read-write processing module to perform a read-write operation.

[0024] Furthermore, in some implementations of the present embodiment, the read-write processing module includes a format conversion unit, a data writing unit, a data reading unit and a data verification unit; the format conversion unit is configured to: perform format conversion on the FPGA configuration data in the configuration package to obtain target FPGA configuration data; the data writing unit is configured to: write the target FPGA configuration data into the storage unit of the external FPGA chip according to the operation signal; the data verification unit is configured to: perform CRC verification on the target FPGA configuration data written into the storage unit to obtain a verification result; or, the data reading unit is configured to: read the target storage unit address in the configuration package, and read the FPGA configuration data corresponding to the target storage unit address from the storage unit of the external FPGA chip according to the operation signal; the format conversion unit is configured to: perform format conversion on the FPGA configuration data to obtain the target FPGA configuration data; the data verification unit is configured to: perform CRC verification on the read target FPGA configuration data to obtain a verification result.

[0025] Specifically, in this embodiment, the read-write processing module will perform read-write operations on the storage unit of the FPGA chip according to the operation signal transmitted by the bit stream instruction parsing module, and will perform data format conversion when performing read-write operations, such as converting data in a standard format into a format dedicated to the FPGA chip so that the data can be compatible with the storage unit of the FPGA chip, or converting data in a proprietary format into a readable format for use by external devices; and performing checks on the configuration data, such as CRC (cyclic redundancy check), to ensure that the data written to the storage unit of the FPGA chip, or to ensure that the data read from the storage unit of the FPGA chip is correct.

[0026] Furthermore, in some implementations of the present embodiment, the read-write processing module also includes a timing generation unit; the timing generation unit is configured to: generate a storage unit write timing or a storage unit read timing according to the FPGA model and the FPGA working mode; the data write unit is configured to: write the target FPGA configuration data into the storage unit of an external FPGA chip according to the operation signal and the storage unit write timing; or, the data read unit is configured to: read the FPGA configuration data corresponding to the target storage unit address from the storage unit of an external FPGA chip according to the operation signal and the storage unit read timing.

[0027] Specifically, in this embodiment, the storage unit of the FPGA chip includes registers and memories, and the read processing module will also establish a register write timing or a register read timing or a memory write timing or a register read timing according to the FPGA model and the FPGA working mode, so as to write the target configuration data into the storage unit of the FPGA chip according to the write timing and the operation signal, or read the configuration data from the storage unit of the FPGA chip according to the read timing and the operation signal.

[0028] Furthermore, in some other implementations of the present embodiment, the storage unit includes a register or a memory, and the read-write processing module also includes a first judgment unit and a second judgment unit; the first judgment unit is configured to: when reading the FPGA configuration data from the register, determine whether to perform byte swapping and bit reverse order on the FPGA configuration data according to the FPGA model; or, the second judgment unit is configured to: when reading the FPGA configuration data from the memory, determine whether to perform byte swapping and bit reverse order on the FPGA configuration data according to the FPGA model, and determine whether to add an empty frame to the data frame according to the unit read frame number.

[0029] Specifically, in this embodiment, the read-write processing module can verify the accuracy of data processing when performing a read-back operation. The storage unit of the FPGA chip includes a register and a memory. When performing a read operation on the configuration data in the register of the FPGA chip, it may be necessary to perform byte swapping and bit reversal on the configuration data read. For example, the bit order in the register of the FPGA chip is the most significant bit first and the least significant bit last, and the processor requires the least significant bit first and the most significant bit last, so it is necessary to perform bit reversal when reading back the register data. Whether byte swapping and bit reversal are required when reading back the register data depends on the specific characteristics of the device. When performing a read operation on the configuration data in the register of the FPGA chip, in addition to the need for byte swapping and bit reversal, it is also necessary to select whether to add an empty frame when reading back the memory data to complete a single-frame readback or multi-frame readback operation. In a single-frame readback operation, the controller reads one data frame from the memory at a time. In a multi-frame readback operation, the controller reads multiple data frames from the memory at a time. If multi-frame readback is required, the controller needs to add an empty frame between each data frame. A null frame is a special frame that does not contain any data and can be used to synchronize the communication between the controller and the memory. Adding a null frame can be used to ensure that the controller and the memory operate at the same speed and prevent data frames from being lost or corrupted.

[0030] Furthermore, in some implementations of the present embodiment, the status pin includes an initialization pin and a configuration completion pin, and the configuration status determination module is configured as follows: if the level types of the initialization pin and the configuration completion pin are both target levels, and the verification result is a successful verification, then it is determined that the FPGA chip configuration is completed; wherein, the target level is used to indicate that the FPGA configuration is completed.

[0031] Specifically, in the present embodiment, the status pin (i.e., the configuration status pin) can determine the FPGA configuration state according to the CRC check result obtained during the data configuration process and the level state of the configuration status pin. When the check results are all successful, and the level states of the configuration status pins are all target level states, it can be determined that the FPGA configuration is complete. Among them, the configuration status pin includes an initialization pin INIT and a configuration completion DONE pin. When the INIT pin is at a low level and the DONE pin is at a low level, it can be indicated that the FPGA is being configured. When the INIT pin is at a high level and the DONE pin is at a high level, it can be indicated that the FPGA has completed the configuration. In addition, the configuration status determination module is also used to update the level state of the configuration status pin in the status register in real time, so that when the configuration status pin fails, its pin level state can still be obtained.

[0032] Furthermore, in some implementations of the present embodiment, the digital model also includes a timing detection module, and the timing detection module is configured to: perform pulse width detection on the reset signal of the FPGA chip; perform clock cycle detection on the clock signal of the FPGA chip; perform establishment and hold time detection on the configuration data signal of the FPGA chip; wherein the configuration data signal includes a serial data interface signal, a parallel data interface signal, a chip select interface signal, and a read-write enable interface signal; if there is a timing abnormality signal, an abnormality detection report is generated; wherein the abnormality detection report is used to indicate that the digital model is in an abnormal configuration state.

[0033] Specifically, in this embodiment, the digital model also includes a timing detection module, which monitors the timing of the reset signal, clock signal and configuration data signal of the FPGA chip to ensure that the configuration data can be transmitted stably and accurately. In the case of timing violations, classified printing and reporting will be performed to help users quickly understand the operating status of the model and discover abnormalities in the configuration process.

[0034] Therefore, the scheme of the present application has the following beneficial effects: strong versatility and scalability. The SystemVerilog model of the present application takes into account the configuration requirements of various FPGA models. By adopting a block-based and parameterized design method, the model can adapt to different models of FPGA without major modifications; users can also expand on the basis of the implementation of the original functional module to support more FPGA models, so that design engineers and verification engineers can quickly match new FPGA models. The model allows engineers to adapt to the specific requirements of different scenarios through parameter configuration, such as different working modes and device models. This flexible configuration enables the model to adapt to various complex configuration scenarios. Through the higher-level and highly flexible characteristics of the System Verilog language, the implementation of the model has better readability than the implementation of hardware description languages ​​such as Verilog. The model provides a reporting mechanism to help engineers quickly understand the operating status of the model and discover abnormal situations during the configuration process. Due to the block-based design of the model and the clear structure, users can easily maintain and upgrade each functional module without affecting other parts. This design method greatly reduces the difficulty of maintenance and upgrade, and effectively improves the design and verification efficiency of FPGA configuration circuits.

[0035] Figure 2 An FPGA data configuration method provided in an embodiment of the present application can be applied to the aforementioned digital model. Figure 2 As shown, the FPGA data configuration method includes the following steps:

[0036] Step 201: configuring the digital model according to the input FPGA configuration parameters;

[0037] Step 202: after the digital model configuration is completed, the input target FPGA configuration data is written into the external FPGA chip, or the target FPGA configuration data is read from the external FPGA chip, and the target FPGA configuration data is verified to obtain a verification result;

[0038] Step 203: Determine the configuration state of the FPGA chip according to the verification result and the level type of the status pin of the FPGA chip.

[0039] Furthermore, in some implementations of this embodiment, the digital model also includes a configuration interface, which is used to connect to the FPGA chip and receive the FPGA configuration bitstream file; the method also includes: parsing the FPGA configuration bitstream file to obtain a configuration package and configuration instructions; converting the configuration package and the configuration instructions to obtain corresponding operation signals; wherein the operation signal is used to indicate that the input target FPGA configuration data is written to an external FPGA chip; or, to indicate that the target FPGA configuration data is read from an external FPGA chip.

[0040] Furthermore, in some implementations of the present embodiment, the method also includes: performing pulse width detection on the reset signal of the FPGA chip; performing clock cycle detection on the clock signal of the FPGA chip; performing establishment and hold time detection on the configuration data signal of the FPGA chip; wherein the configuration data signal includes a serial data interface signal, a parallel data interface signal, a chip select interface signal and a read-write enable interface signal; if there is a timing abnormality signal, an abnormality detection report is generated; wherein the abnormality detection report is used to indicate that the digital model is in an abnormal configuration state.

[0041] Specifically, in this embodiment, the FPGA data configuration method is applied to the aforementioned digital model, and the workflow diagram of the digital model is as follows: Figure 3As shown, the parameter configuration module configures the digital model according to the input FPGA configuration parameters, for example, the parameters of the model are configured according to the FPGA model, so that the device identification, register address list, register domain, configuration package format, and frame length in the model match the FPGA model, ensuring that the model can accurately simulate the configuration behavior of the FPGA configuration circuit of the model, and initialize the corresponding registers (such as control registers and status registers) in the digital model according to the FPGA model and the FPGA working mode. After the digital model is processed by parameter configuration and initialization, the digital model can realize the function of the FPGA configuration circuit applicable to the FPGA model. When the parameter configuration module is processed, the bitstream instruction parsing module receives the FPGA configuration bitstream file from the configuration interface, parses the FPGA configuration bitstream file, obtains the configuration package and configuration instructions, and converts the parsed configuration package and configuration instructions into an operation signal that can be recognized by the digital model, and the operation signal is used to instruct the read-write processing module to perform read-write operations. At the same time, the timing detection module monitors the timing of the reset signal, clock signal, and configuration data signal of the FPGA chip to ensure that the configuration data can be transmitted stably and accurately. For situations where there are timing violations, classified printing and reporting will be performed to help users quickly understand the operating status of the model and discover abnormalities during the configuration process. The read-write processing module will establish register write timing or register read timing according to the FPGA model and FPGA operating mode to write the target configuration data into the storage unit of the FPGA chip according to the write timing and operation signal, or read the configuration data from the storage unit of the FPGA chip according to the read timing and operation signal. The configuration status pin can judge the FPGA configuration status based on the CRC check result obtained during the data configuration process and the level status of the configuration status pin. When the check results are all successful and the level status of the configuration status pin is the target level state, it can be determined that the FPGA configuration is complete.

[0042] Therefore, by configuring the digital model, data configuration can be performed on FPGA chips of different models based on the read and write processing module of the digital model, and then the configuration completion status can be judged based on the level status of the FPGA configuration status pin of the digital model and the verification results during the data configuration process, thereby efficiently completing the data configuration of FPGA chips of different models.

[0043] Figure 4 An electronic device provided in an embodiment of the present application can be used to implement the FPGA data configuration method in the aforementioned embodiment, mainly including:

[0044] The memory 401, the processor 402, and the computer program 403 stored in the memory 401 and executable on the processor 402 are connected to the memory 401 and the processor 402 are connected via communication. When the processor 402 executes the computer program 403, the method in the above-mentioned embodiment is implemented. The number of processors can be one or more.

[0045] The memory 401 may be a high-speed random access memory (RAM) memory, or a non-volatile memory, such as a disk memory. The memory 401 is used to store executable program codes, and the processor 402 is coupled to the memory 401 .

[0046] Furthermore, the embodiment of the present application also provides a computer-readable storage medium, which may be disposed in the above-mentioned electronic device. The computer-readable storage medium may be the above-mentioned Figure 4 Memory in the illustrated embodiment.

[0047] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the FPGA data configuration method in the aforementioned embodiment is implemented. Furthermore, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0048] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0049] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0050] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0051] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a readable storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned readable storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0052] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0053] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0054] The above is a description of the digital model of the FPGA configuration circuit, the FPGA data configuration method, the device and the medium provided in the present application. For technicians in this field, according to the ideas of the embodiments of the present application, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A digital model of an FPGA configuration circuit, characterized in that: It includes a parameter configuration module, a read-write processing module and a configuration status determination module; The parameter configuration module is configured to: configure the digital model according to the input FPGA configuration parameters; wherein the FPGA configuration parameters include FPGA model and FPGA working mode; The read / write processing module is configured to: after the digital model configuration is completed, write the input target FPGA configuration data into an external FPGA chip, or read the target FPGA configuration data from an external FPGA chip, verify the target FPGA configuration data, and obtain a verification result; The configuration status determination module is configured to determine the configuration status of the FPGA chip according to the verification result and the level type of the status pin of the FPGA chip.

2. The digital model according to claim 1, characterized in that: The parameter configuration module includes a parameter configuration unit and a parameter initialization unit; The parameter configuration unit is configured to: configure the target model parameters of the digital model according to the input FPGA model; wherein the target model parameters include: identification, register address list, register domain, configuration package format and frame length; The parameter initialization unit is configured to initialize corresponding registers in the digital model according to the FPGA model and the FPGA working mode.

3. The digital model according to claim 1, characterized in that: It also includes a configuration interface and a bitstream instruction parsing module, wherein the configuration interface is used to connect to the FPGA chip and receive the FPGA configuration bitstream file, and the bitstream instruction parsing module is configured as follows: Parsing the FPGA configuration bitstream file to obtain a configuration package and configuration instructions; The configuration package and the configuration instruction are converted to obtain a corresponding operation signal; wherein the operation signal is used to instruct the read-write processing module to write the input target FPGA configuration data into an external FPGA chip; or, to instruct the read-write processing module to read the target FPGA configuration data from an external FPGA chip.

4. The digital model according to claim 3, characterized in that: The read-write processing module includes a format conversion unit, a data writing unit, a data reading unit and a data verification unit; The format conversion unit is configured to: perform format conversion on the FPGA configuration data in the configuration package to obtain target FPGA configuration data; the data writing unit is configured to: write the target FPGA configuration data into a storage unit of an external FPGA chip according to the operation signal; the data verification unit is configured to: perform CRC verification on the target FPGA configuration data written into the storage unit to obtain a verification result; Alternatively, the data reading unit is configured to: read the target storage unit address in the configuration package, and read the FPGA configuration data corresponding to the target storage unit address from the storage unit of the external FPGA chip according to the operation signal; the format conversion unit is configured to: perform format conversion on the FPGA configuration data to obtain the target FPGA configuration data; the data verification unit is configured to: perform CRC verification on the read target FPGA configuration data to obtain a verification result.

5. The digital model according to claim 4, characterized in that: The read-write processing module also includes a timing generation unit; The timing generation unit is configured to: generate a storage unit write timing or a storage unit read timing according to the FPGA model and the FPGA working mode; The data writing unit is configured to: write the target FPGA configuration data into the storage unit of the external FPGA chip according to the operation signal and the storage unit writing timing; Alternatively, the data reading unit is configured to read the FPGA configuration data corresponding to the target storage unit address from the storage unit of the external FPGA chip according to the operation signal and the storage unit reading timing.

6. The digital model according to claim 4, characterized in that: The storage unit includes a register or a memory, and the read-write processing module also includes a first judgment unit and a second judgment unit; The first determination unit is configured to: when reading the FPGA configuration data from the register, determine whether to perform byte swapping and bit reversal on the FPGA configuration data according to the FPGA model; Or, the second judgment unit is configured to: when reading the FPGA configuration data from the memory, determine whether to perform byte swapping and bit reversal on the FPGA configuration data according to the FPGA model, and determine whether to add an empty frame to the data frame according to the unit reading frame number.

7. The digital model according to claim 1, characterized in that: The status pins include an initialization pin and a configuration completion pin, and the configuration status determination module is configured as follows: If the level types of the initialization pin and the configuration completion pin are both target levels, and the verification result is a successful verification, it is determined that the configuration of the FPGA chip is completed; wherein the target level is used to indicate that the FPGA configuration is completed.

8. The digital model according to claim 1, characterized in that: It also includes a timing detection module, which is configured to: Performing pulse width detection on a reset signal of the FPGA chip; Performing clock cycle detection on the clock signal of the FPGA chip; Performing establishment and holding time detection on the configuration data signal of the FPGA chip; wherein the configuration data signal includes a serial data interface signal, a parallel data interface signal, a chip select interface signal and a read / write enable interface signal; If there is a timing abnormality signal, an abnormality detection report is generated; wherein the abnormality detection report is used to indicate that the digital model is in an abnormal configuration state.

9. The digital model according to any one of claims 1 to 8, characterized in that: The digital model is a SystemVerilog model.

10. A FPGA data configuration method, characterized in that: A digital model applied to an FPGA configuration circuit, wherein the FPGA data configuration method comprises: The digital model is configured according to the input FPGA configuration parameters; wherein the FPGA configuration parameters include the FPGA model and the FPGA working mode; After the digital model configuration is completed, the input target FPGA configuration data is written into an external FPGA chip, or the target FPGA configuration data is read from an external FPGA chip, and the target FPGA configuration data is verified to obtain a verification result; The configuration state of the FPGA chip is determined according to the verification result and the level type of the status pin of the FPGA chip.

11. An electronic device, characterized in that: The device comprises a memory and a processor, wherein: The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the steps in the FPGA data configuration method as described in claim 10 are implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the FPGA data configuration method as claimed in claim 10 are implemented.

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