Data transmission array and generation method thereof, chip and data transmission method thereof

Abstract

The embodiment of the invention provides a data transmission array and a generation method thereof, and a chip and a data transmission method thereof. The data transmission array comprises a plurality of data transmission modules; the data transmission module has first preset performance; the plurality of data transmission modules are spliced according to a preset arrangement mode; and the data transmission array is used for forming a signal channel in the chip. According to the scheme of the embodiment, a technical basis is provided for circuit performance adjustability, and a technical basis is provided for quickly responding, meeting a layout setting scene with multiple performance requirements and improving the setting efficiency of a circuit layout and a chip.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design, and particularly to a data transmission array and its generation method, and a chip and its data transmission method. Background Technology

[0002] With the advent of the data-driven era, the demands on data transmission are increasing, making the design of data transmission modules crucial. Furthermore, as chips become larger, data transmission requirements are becoming more diverse. Data transmission, especially large-scale data transmission, involves a vast number of signal lines. Summary of the Invention

[0003] This disclosure provides a data transmission array and a method for generating the same, as well as a chip and a data transmission method thereof.

[0004] In a first aspect, embodiments of this disclosure provide a data transmission array, including multiple data transmission modules; the data transmission modules have a first preset performance.

[0005] Multiple data transmission modules are spliced ​​together according to a preset arrangement; the data transmission array is used to form the signal channel in the chip.

[0006] Secondly, embodiments of this disclosure provide a chip including a signal channel; the signal channel is configured based on the data transmission array.

[0007] Thirdly, embodiments of this disclosure provide a method for generating a data transmission array, the method including:

[0008] Multiple data transmission modules are acquired; each data transmission module has a first preset performance.

[0009] The data transmission modules are spliced ​​together in a preset arrangement to generate the data transmission array; the data transmission array is used to form the signal channel in the chip.

[0010] Fourthly, embodiments of this disclosure provide a data transmission method for a chip, wherein the chip is the aforementioned chip, and the method includes:

[0011] Data transmission is performed between two functional modules of the chip based on the signal channels within the chip; the signal channels are constructed based on the data transmission array.

[0012] Fifthly, embodiments of this disclosure provide an electronic device, the electronic device comprising: a multi-core processor;

[0013] The multi-core processor includes multiple cores, each core including a control unit, an arithmetic logic unit, and registers;

[0014] The multiple cores are connected to each other via the data transmission array, wherein each data transmission array is connected to the core via a register in the core.

[0015] In a sixth aspect, embodiments of this disclosure provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements: the method for generating the data transmission array and / or the data transmission method of the chip.

[0016] The data transmission array of this embodiment includes multiple data transmission modules, which are spliced ​​together in a preset arrangement to form signal channels in the chip. This modularizes the data transmission lines, accelerates routing speed in layout setup, and improves work efficiency. Furthermore, each data transmission module has a certain first preset performance (e.g., delay performance), allowing direct access to a data transmission module with that performance (i.e., the first preset performance matching that performance) when a specific performance requirement is needed during circuit design. This avoids the complex manual operations introduced by having to redesign the circuit if performance adjustments are needed after placement and routing. This provides a technical foundation for adjustable and rapid circuit performance, enabling rapid response to and fulfillment of layout setup scenarios with multiple performance requirements. It also provides a technical basis for improving the data transmission performance and design efficiency of circuit layouts and chips. Attached Figure Description

[0017] In the accompanying drawings of the embodiments disclosed herein:

[0018] Figure 1 This is a schematic diagram of a data transmission array provided in an embodiment of the present disclosure;

[0019] Figure 2 A schematic diagram of a data transmission module provided in an embodiment of this disclosure;

[0020] Figure 3 This is a schematic diagram of a data transmission array obtained by horizontal splicing, as provided in an embodiment of the present disclosure.

[0021] Figure 4 This is a schematic diagram of a data transmission array obtained by splicing data in the vertical direction, as provided in an embodiment of this disclosure.

[0022] Figure 5 A block diagram of chip composition provided in the embodiments of this disclosure;

[0023] Figure 6 A flowchart illustrating the method for generating a data transmission array according to an embodiment of this disclosure;

[0024] Figure 7A flowchart of a method for generating a data transmission module provided in this embodiment of the disclosure;

[0025] Figure 8 A flowchart illustrating a method for acquiring multiple data transmission modules provided in this embodiment of the disclosure;

[0026] Figure 9 A flowchart illustrating the data transmission method of a chip provided in this embodiment of the disclosure;

[0027] Figure 10 A block diagram of an electronic device provided in the embodiments of this disclosure;

[0028] Figure 11 A block diagram of a computer-readable storage medium provided in an embodiment of this disclosure. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions of this disclosure, the communication-sensing data processing method and computer-readable storage medium provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0030] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0031] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0032] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0033] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0034] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0035] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0036] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0037] With the advent of the data-driven era, the demands on data transmission are increasing, making the design of data transmission modules crucial. As chips become larger, data transmission requirements are becoming more diverse. In data transmission, especially large-scale transmission, the number of signal lines involved in the transmission module is enormous. Efficiently planning the layout of the data transmission module to meet diverse data transmission needs presents a challenge for chip designers.

[0038] Many related technologies are based on preset scripts (i.e., programs) to directly connect the input and output ports of specific cells through automated P&R (placement and routing, one of the main processes of circuit layout design, which plans the spatial distribution and routing of the circuit structure with the help of software, which can be abbreviated as PR). This is convenient and fast. However, since P&R connections are random, the delay of each connection may be different. When data transmission involves thousands of signal lines, the corresponding timing structure will be quite complex, and the delay accuracy of data transmission will be difficult to guarantee.

[0039] Furthermore, since the spatial layout of signal lines is automatically planned by software, modifications to the Placement and Rectification (P&R) process are extremely complex when the design changes and transmission performance needs adjustment. This is equivalent to repeating the routing process, and adding additional routing may introduce additional Design Rule Check (DRC) errors (a crucial step in circuit layout checking to ensure the distance between lines meets the manufacturer's design rules and prevent potential short circuits and open circuits). In contrast, manually creating long-distance transmission layouts for hundreds or thousands of signal lines is extremely labor-intensive and time-consuming. Moreover, completing the layout with a large number of signals increases the difficulty of K-library (cell characterization, a key process in standard library design, where tools extract key information from standard cells and generate library files recognizable by the backend design), consuming significant amounts of CPU (central processing unit) memory and processing space. If a modular set of manual layout drawing rules can be developed, simplifying the timing analysis and K-library process of the transmission path without introducing overly complex manual operations, accurately determining the delay of each data path, and enabling flexible adjustment of the number of channels and timing performance through the addition, deletion, and splicing of modules, then the data transmission performance and design efficiency of the chip can be directly improved, meeting the needs of a variety of application scenarios.

[0040] This disclosure provides a data transmission module comprising at least one signal line and a circuit structure formed by the signal line. The data transmission module can be used as a signal channel in the circuit layout, achieving modularization of the data transmission line, accelerating routing speed in layout setup, and improving work efficiency. Furthermore, each data transmission module has a certain first preset performance (e.g., delay performance), allowing direct use of a data transmission module with that performance (i.e., the first preset performance matching that performance) when a line with a specific performance requirement is needed during circuit design. This avoids the complex manual operations introduced by redesigning the circuit after layout and routing if performance adjustments or data line additions / reductions are needed. This provides a technical foundation for adjustable circuit performance, data line additions / reductions, and rapid adjustment, enabling rapid response to and satisfaction of layout setup scenarios with multiple performance requirements. It provides a technical foundation for improving the data transmission performance and design efficiency of circuit layouts and chips.

[0041] The data transmission module and array of this disclosure can be set in a standard cell library and can be applied to any circuit layout with various performance requirements for the data transmission module in long-distance data transmission, any circuit layout that requires precise control of the performance of each signal channel in the data transmission line, and any circuit layout that wants to adjust the number of channels, transmission performance (such as timing performance), and improve design efficiency. The method for generating the data transmission module can be applied to any standard cell design software and tools, and the method for generating the data transmission array can be applied to any circuit layout design software and tools. These methods can be implemented by the processor calling computer-readable program instructions stored in memory. The data transmission module and array of this disclosure can be applied to any circuit layout drawing process and to any chip design. For example, it can include, but is not limited to, CPUs (Central Processing Processor), GPUs (Graphics Processing Units), DPUs (Data Processing Units), etc., which have various requirements for data transmission latency, and is especially suitable for multi-core chips. The data transmission method of this disclosure can be applied to data transmission scenarios of any circuit or chip, as well as data transmission scenarios between cores in any multi-core chip.

[0042] The embodiments of this disclosure will be described in detail below.

[0043] This disclosure provides a data transmission array 200, such as Figure 1 As shown, it includes multiple data transmission modules 100; each data transmission module 100 has a first preset performance.

[0044] Multiple data transmission modules 100 are spliced ​​together according to a preset arrangement; the data transmission array 200 is used to form the signal channel in the chip 300.

[0045] In this embodiment of the disclosure, the data transmission module 100, as... Figure 2 As shown, the data transmission module 100 can be set in the standard cell library and has a first preset performance, which is used to be called into the circuit layout as a signal channel.

[0046] In the embodiments of this disclosure, the first preset performance may include, but is not limited to, delay performance, impedance performance, etc. For example, the first preset performance may be delay performance.

[0047] In this embodiment of the disclosure, the data transmission module 100 may include at least one signal line and a line structure formed by the at least one signal line.

[0048] In this embodiment of the disclosure, in order to solve the problem that the performance of the PR generated by the script in the current solution cannot be adjusted arbitrarily and the number of transmission data lines can not be increased or decreased, so that the layout must be redesigned when different performance requirements (such as delay requirements) are met or when the number of transmission data lines is increased or decreased, the solution of this embodiment of the disclosure can pre-customize various types of data transmission modules 100. When customizing the data transmission module 100, based on the signal lines and line structure in the data transmission module 100, the data transmission module 100 can have a certain first preset performance, such as having a certain delay performance, such as being able to meet a delay of 0.2 nanoseconds.

[0049] In this embodiment of the disclosure, the data transmission module 100 may include various types;

[0050] Data transmission modules of the same type have the same initial preset performance;

[0051] Different types of data transmission modules have different initial preset performance characteristics.

[0052] In this embodiment of the disclosure, different numbers of data transmission modules have different first preset performance.

[0053] In this embodiment of the disclosure, various types of data transmission modules 100 can be pre-customized and these data transmission modules 100 can be stored as a whole in the form of modules, so that these modules can be called as a whole.

[0054] In this embodiment of the disclosure, the pre-customized data transmission module 100 may include, but is not limited to, a data transmission module with common performance. For example, if the delay that often needs to be adjusted in the circuit meets 0.2 nanoseconds and 0.4 nanoseconds, then the pre-customized data transmission module 100 may be a data transmission module that meets the 0.2 nanosecond delay performance and the 0.4 nanosecond delay performance; the pre-customized data transmission module 100 may also be a data transmission module with specific performance.

[0055] In this embodiment of the disclosure, each data transmission module 100 may include at least one data input terminal and at least one data output terminal.

[0056] In this embodiment of the disclosure, since each data transmission module 100 has a certain first preset performance, according to the required first preset performance, at least one signal line in each data transmission module 100 may be configured to include, but is not limited to, one or more interconnected preset elements, and the data transmission module 100 may have the first preset performance based on the preset elements contained in the signal line.

[0057] In this embodiment of the disclosure, the preset element may include, but is not limited to, a buffer (a logic forward drive unit in a circuit), a logic element, an impedance element, etc.

[0058] In this embodiment of the disclosure, when the first preset performance is a delay performance, the preset element may include a buffer.

[0059] In this embodiment of the disclosure, different types of data transmission modules 100 can be distinguished by different identifiers, such as: data transmission module A, data transmission module B, data transmission module C, data transmission module D, ..., data transmission module M, data transmission module N, ...

[0060] In this embodiment of the disclosure, data transmission modules 100 of the same type have the same first parameters and line structure based on the included signal lines, and have the same first preset performance;

[0061] Different types of data transmission modules 100 have different first preset performance based on the different first parameters of the included signal lines and / or different line structures.

[0062] In this embodiment of the disclosure, the first parameter may include any one or more of the following:

[0063] The second preset performance of each signal line, the arrangement order and number of signal lines with different second preset performance, and the total number of signal lines.

[0064] In this embodiment of the disclosure, for the same type of data transmission module 100, the number of selected signal lines, the second preset performance (e.g., delay performance) of the signal lines, the arrangement order of each signal line, and the line structure formed by all selected signal lines are completely identical, which facilitates the standardized setting of the same type of data transmission module 100.

[0065] In this embodiment of the disclosure, for example, for data transmission module A, if the first preset performance of data transmission module A satisfies a delay of 0.2 nanoseconds, then all data transmission modules 100 of this type can be configured to include 80 signal lines, of which 40 signal lines have a delay of 200 picoseconds (second preset performance), 20 signal lines have a delay of 150 picoseconds (second preset performance), 10 signal lines have a delay of 100 picoseconds (second preset performance), and 10 signal lines have a delay of 50 picoseconds (second preset performance); the 80 signal lines are connected according to a preset first line structure (the detailed connection method is not limited here).

[0066] In this embodiment of the disclosure, the delay of multiple signal lines in the data transmission module 100 does not refer to the individual delay of each signal line, but rather to the overall delay effect. For example, "100 signal lines satisfy 400 picoseconds, 50 signal lines satisfy 300 picoseconds" means that the delay of each of the 100 signal lines is less than or equal to 400 picoseconds, and 400 picoseconds is the overall delay effect of the 100 signal lines; similarly, the delay of each of the 50 signal lines is less than or equal to 300 picoseconds, and 300 picoseconds is the overall delay effect of the 50 signal lines.

[0067] In this embodiment of the disclosure, for different types of data transmission modules 100, at least one of the following is different: the number of selected signal lines, the second preset performance (e.g., delay performance) of the signal lines, the arrangement order of each signal line, and the line structure formed by all selected signal lines. Based on this difference, different types of data transmission modules 100 have different first preset performance.

[0068] In this embodiment of the disclosure, for example, for a data transmission module B of a different type than the aforementioned data transmission module A, if the first preset performance of data transmission module B satisfies a delay of 0.4 nanoseconds, then all data transmission modules 100 of this type can be configured to include 70 signal lines, wherein 20 signal lines have a delay of 400 picoseconds (second preset performance), 20 signal lines have a delay of 200 picoseconds (second preset performance), 15 signal lines have a delay of 100 picoseconds (second preset performance), and 15 signal lines have a delay of 50 picoseconds (second preset performance); the 70 signal lines are connected according to a preset second line structure (the detailed connection method is not limited here).

[0069] In this embodiment of the disclosure, the at least one signal line is divided into multiple groups, and at least two groups of signal lines have the same first parameter and line structure.

[0070] In this embodiment of the disclosure, multiple sets of identical signal lines can be set in a data transmission module 100. The number of signal lines in each set, the second preset performance (e.g., delay performance) of the signal lines, the arrangement order, and the circuit structure formed by the signal lines are all the same, so that each set of signal lines is completely identical. The data transmission module 100 can be set up by copying a set of signal lines.

[0071] In the embodiments of this disclosure, the arrangement (e.g., position, direction, etc.) of multiple identical signal lines (which may be referred to as multiple identical signal line groups) can be the same or different.

[0072] In this embodiment of the disclosure, a data transmission module 100 may include multiple signal line groups of different types, such as signal line group 1, signal line group 2, signal line group 3, ..., wherein the number of signal line group 1, signal line group 2, and signal line group 3 can be one or more.

[0073] In this embodiment of the disclosure, the boundary of the line structure constitutes the boundary of the data transmission module 100, such as Figure 2 The boundary is shown by the dashed line in the diagram. Figure 2 The width (W) direction and length (L) direction of the data transmission module 100 are also indicated.

[0074] In this embodiment of the disclosure, when splicing multiple data transmission modules 100, the length of the multiple data transmission modules 100 can be unified to ensure the regularity of the splicing.

[0075] In this embodiment of the disclosure, Figure 2 The virtual borders indicated by solid lines and the boundaries indicated by dashed lines are not actual existing structures. The boundary indicated by the dashed lines not only does not exist in reality, but also does not exist in the design; it represents the boundary of the internal wiring structure of the data transmission module 100. It is drawn here for the purpose of... Figure 1 The splicing method shown will be explained more intuitively. The virtual border indicated by the solid line is called the prboundary (i.e., the boundary of PR, which is the outermost boundary of the data transmission module 100, i.e., the maximum outer width of all graphics inside the data transmission module 100). This prboundary does not actually exist, but it exists in the design software and is the reference used for splicing in the design. Because of the existence of this prboundary, the data transmission modules 100 can be directly called and spliced ​​when splicing, and the prboundaries of adjacent data transmission modules 100 overlap during splicing.

[0076] In this embodiment of the disclosure, the boundary of the data transmission module 100 is determined here so that the distance between any two adjacent data transmission modules 100 can be determined based on the boundary of the data transmission module 100 when splicing the data transmission modules 100 in the future.

[0077] In the embodiments disclosed herein, such as Figure 1 , Figure 3 , Figure 4 As shown, a data transmission array 200 is obtained by directly splicing multiple data transmission modules 100 according to specific distance requirements in a specific way and arranging them sequentially in a preset arrangement.

[0078] In this embodiment of the disclosure, the above-mentioned splicing method refers to the following: each data transmission module 100 is also provided with a virtual border (prboundary) around its perimeter. When splicing the data transmission modules 100, the edges of the virtual borders (prboundaries) of adjacent data transmission modules 100 can be overlapped and spliced, so that the distance between any two adjacent data transmission modules 100 meets the preset distance requirement.

[0079] In the embodiments disclosed herein, such as Figure 2 As shown, the above distance requirements include: the distance d (d = 2d0) between the internal line structure boundaries of any two adjacent data transmission modules must be greater than or equal to the minimum distance between modules or units specified by DRC, so as to ensure that no new DRC errors are introduced after splicing.

[0080] In this embodiment of the disclosure, the preset arrangement may include: arranging the data transmission modules horizontally or vertically.

[0081] In the embodiments disclosed herein, such as Figure 3 The diagram shown illustrates a horizontal arrangement of multiple data transmission modules 100 (including data transmission module 100-1, data transmission module 100-2, ..., data transmission module 100-10, ..., data transmission module 100-n, ..., where n is a positive integer). Figure 4 The diagram shown is a schematic diagram of multiple data transmission modules 100 (including data transmission module 100-1, data transmission module 100-2, ..., data transmission module 100-10, ..., data transmission module 100-m, ..., where m is a positive integer) arranged vertically.

[0082] In this embodiment of the disclosure, the multiple data transmission modules 100 spliced ​​together may include at least two data transmission modules of the exact same type; or, the multiple data transmission modules 100 spliced ​​together may be of different types.

[0083] In this embodiment of the disclosure, the multiple data transmission modules 100 participating in the splicing can be multiple data transmission modules 100 of the same type or multiple data transmission modules 100 of different types. They can be flexibly adjusted according to project requirements and are not limited here.

[0084] In this embodiment of the disclosure, the data transmission array 200 may include various types, and different types of data transmission arrays may have different third preset performance.

[0085] In this embodiment of the disclosure, the spliced ​​data transmission array 200 may have a commonly used third preset performance (e.g., a commonly used delay performance). For example, if the delay that often needs to be adjusted in the circuit meets 0.2 nanoseconds and 0.4 nanoseconds, then the spliced ​​data transmission array 200 may be a data transmission array 200 with a delay performance of 0.2 nanoseconds and a delay performance of 0.4 nanoseconds; the spliced ​​data transmission array 200 may also be a data transmission array 200 with a specific third preset performance.

[0086] In this embodiment of the disclosure, different types of data transmission arrays 200 have different third preset performance based on the different second parameters of the included data transmission modules 100.

[0087] In this embodiment of the disclosure, the second parameter may include any one or more of the following:

[0088] The first preset performance of each data transmission module 100, the arrangement order and number of data transmission modules 100 with different first preset performance, and the total number of data transmission modules 100.

[0089] In this embodiment of the disclosure, for the same type of data transmission array 200, the number of data transmission modules 100 selected for splicing, the first preset performance (e.g., delay performance) of the data transmission modules 100, and the arrangement order of each data transmission module 100 are all exactly the same, so that the same type of data transmission array 200 has the same third preset performance (e.g., delay performance).

[0090] In this embodiment of the disclosure, for example, for the data transmission array 200-1, if the third preset performance of the data transmission array 200-1 is a delay of 0.6 nanoseconds, then all data transmission arrays 200-1 of this type can be configured to include 200 data transmission modules 100, wherein the delay of 100 data transmission modules A is 0.6 nanoseconds (first preset performance), and the delay of 100 data transmission modules B is 0.3 nanoseconds (first preset performance); the 100 data transmission modules A and 100 data transmission modules B are spliced ​​horizontally according to a preset first interval to obtain the data transmission array 200-1.

[0091] In this embodiment of the disclosure, for different types of data transmission arrays 200, at least one of the following is different: the number of data transmission modules 100 selected for splicing, the first preset performance (e.g., delay performance) of the data transmission modules 100, and the arrangement order of each data transmission module 100. Based on this difference, different types of data transmission arrays 200 have different third preset performance.

[0092] In this embodiment of the disclosure, for example, for a data transmission array 200-2 of a different type than the data transmission array 200-1 described above, if the third preset performance of the data transmission array 200-2 is a delay of 0.5 nanoseconds, then all data transmission arrays 200-2 of this type can be configured as follows: containing 500 data transmission modules 100, wherein the delay of 200 data transmission modules A is 0.5 nanoseconds (first preset performance), the delay of 200 data transmission modules B is 0.2 nanoseconds (first preset performance), and the delay of 100 data transmission modules C is 0.1 nanoseconds (first preset performance); the 200 data transmission modules A, 200 data transmission modules B, and 100 data transmission modules C are spliced ​​vertically according to a preset second interval to obtain the data transmission array 200-2.

[0093] In this embodiment of the disclosure, the above scheme can quickly obtain the transmission timing relationship of a data transmission array 200, which greatly improves the timing calculation efficiency of the data transmission array 200, the efficiency of the K library, and the delay accuracy of the data transmission array 200.

[0094] In this embodiment of the disclosure, for example, a horizontally transmitted data transmission array 200 contains 2000 signal lines and is composed of 100 data transmission modules D, each containing 20 signal lines. When performing timing analysis on this data transmission array 200, it is only necessary to analyze the timing structure of the data transmission modules D containing 20 signal lines. The timing of all 100 data transmission modules D can be obtained. By repeating the combination 100 times, the complete transmission timing relationship of the 2000 signal lines can be obtained, which greatly improves the timing calculation efficiency, K-library efficiency, and delay accuracy of the data transmission array 200.

[0095] In this embodiment, for example, when project requirements are adjusted to require the data transmission array 200 to contain 2040 channels, adding two data transmission modules D can easily meet the project requirements. Furthermore, when the project needs to adjust the timing of some channels of the data transmission array 200, for example, if the delay requirement for some channels is adjusted from the original requirement to 0.2 nanoseconds, the data transmission module 100 corresponding to these channels can be replaced with the data transmission module A mentioned above. Since different types of data transmission modules can be directly spliced, this replacement can be easily performed, thereby realizing the timing function adjustment of the data transmission array.

[0096] In this embodiment of the disclosure, when drawing the circuit layout, the aforementioned data transmission module 100 can be invoked to set up a data transmission array 200 in the circuit board diagram, and the data transmission module 100 in the data transmission array 200 can be connected between any required functional modules in the circuit layout to realize the data transmission function; in addition, based on the first preset performance of each data transmission module 100, the data transmission array 200 is made to have a certain third preset performance, so that the circuit layout meets the performance requirements.

[0097] In this embodiment of the disclosure, any data transmission module 100 in the circuit layout has the attributes of being replaceable and removable. When the performance requirements of the circuit layout change, the purpose of circuit layout performance simulation can be achieved by adjusting the second parameter of any one or more data transmission modules 100 in the circuit layout, thereby improving the efficiency of the K library, the performance accuracy of the circuit layout, and the drawing efficiency of the circuit layout.

[0098] This disclosure also provides a chip 300, such as Figure 5 As shown, it includes a signal channel 301; the signal channel is constructed based on the data transmission array 200.

[0099] In this embodiment of the disclosure, chip 300 includes at least two functional modules (e.g. Figure 5 Functional modules 302-1 and 302-2 are shown;

[0100] The signal channel 301 between the two functional modules is constructed based on the data transmission array 200.

[0101] In this embodiment of the disclosure, the signal channel 301 may be specifically configured based on the line structure of the signal lines in at least one data transmission module 100 included in the data transmission array 200.

[0102] In the embodiments of this disclosure, when the data transmission array 200 includes at least two data transmission modules 100 of the same type and / or the data transmission module 100 contains at least two identical signal line groups, the signal channel 402 between the at least two functional modules has a duplicate channel structure.

[0103] In this embodiment of the disclosure, during the circuit layout drawing process of the chip, there may be multiple duplicate data transmission modules 100 of the same type spliced ​​together in one or more data transmission arrays 200, or there may be one or more identical signal line groups in one or more data transmission modules 100. These situations will result in duplicate line structures in the circuit layout of the chip 300. Accordingly, after the chip 300 is manufactured, there will be duplicate channel structures of signal channels 301 in the structure of the chip 300.

[0104] In the embodiments of this disclosure, the repeating channel structure greatly simplifies the chip manufacturing process, reduces mold making, accelerates production, and thus saves costs.

[0105] This disclosure also provides a method for generating a data transmission array, such as... Figure 6 As shown, the method may include steps S11-S12:

[0106] S11. Obtain multiple data transmission modules; the data transmission modules have a first preset performance;

[0107] S12. Multiple data transmission modules are spliced ​​together according to a preset arrangement to generate the data transmission array; the data transmission array is used to form the signal channel in the chip.

[0108] In this embodiment of the disclosure, before acquiring multiple data transmission modules, the method may further include: generating data transmission modules; as shown below. Figure 7 As shown, the data transmission generation module may include steps S21-S23:

[0109] S21. Determine the first preset performance required by the data transmission module;

[0110] In this embodiment of the disclosure, a third preset performance of the data transmission array required for circuit layout can be determined according to the actual performance requirements of the chip, and then a first preset performance of the required data transmission module can be determined based on the third performance.

[0111] In this embodiment of the disclosure, the first preset performance can be determined by comprehensively considering various conditions such as the structure, area, and manufacturing process conditions of the circuit layout. The first preset performance can be determined based on the experience of the staff or based on a preset algorithm. Here, no specific method is limited for determining the first preset performance.

[0112] S22. Determine the first parameters of the signal lines constituting the data transmission module based on the first preset performance.

[0113] In this embodiment of the disclosure, based on the determined first preset performance, a first parameter that the selected signal line needs to satisfy in order to achieve the first preset performance can be further determined.

[0114] In this embodiment of the disclosure, the first parameter may include, but is not limited to, any one or more of the following:

[0115] The second preset performance of each signal line, the arrangement order and number of signal lines with different second preset performance, and the total number of signal lines.

[0116] In this embodiment of the disclosure, for example, if a data transmission module with a delay of 0.2 nanoseconds is required, the existing customized signal lines have the following second preset performance: meeting a delay performance of 150 picoseconds, meeting a delay performance of 100 picoseconds, and meeting a delay performance of 50 picoseconds, etc. Based on the delay requirement of meeting 0.2 nanoseconds, the signal lines that meet one or more of the delay performances of 150 picoseconds, 100 picoseconds, and 50 picoseconds are configured to combine the configured signal lines to meet the delay of 0.2 nanoseconds, thereby obtaining the required data transmission module.

[0117] In this embodiment of the disclosure, when configuring the signal lines, it is also necessary to consider whether the signal lines need to be grouped, and to set up the data transmission module through multiple signal line groups.

[0118] S23. Call the corresponding signal line according to the first parameter, and construct the corresponding line structure based on the called signal line to generate the data transmission module.

[0119] In this embodiment of the disclosure, since the circuit structure of the signal line also affects the final first preset performance of the data transmission module, the circuit structure can be planned based on the signal line configured in the above steps so that the final data transmission module meets the required first preset performance.

[0120] In this embodiment of the disclosure, the detailed layout of the line structure is not limited. As long as the preset specifications are met, the first preset performance required by the data transmission module can be satisfied.

[0121] In this embodiment of the disclosure, the method further includes:

[0122] By adjusting the line structure in any of the first data transmission modules, and / or any one or more of the first parameters corresponding to the first data transmission module, a second data transmission module with different first preset performance from the first data transmission module can be obtained.

[0123] In this embodiment of the disclosure, each signal line included in the data transmission module may have replaceable and removable features, so that incorrectly configured signal lines can be adjusted when the data transmission module is generated, and when another data transmission module with different first preset performance is needed, the signal lines can be simply adjusted based on the existing data transmission module to obtain the data transmission module with different first preset performance, such as the second data transmission module described above.

[0124] In this embodiment, for example, if the current first data transmission module has a first preset performance, such as satisfying a 0.2 nanosecond latency performance, and if a data transmission module that satisfies a 0.4 nanosecond latency performance is required, one or more of the following can be adjusted based on the first data transmission module that satisfies the 0.2 nanosecond latency performance: the number of signal lines, the type of signal lines (the second preset performance), the number and arrangement order of each type of signal lines, the total number of signal lines, the grouping of signal lines, the line structure of signal lines, etc., to obtain a second data transmission module that satisfies the 0.4 nanosecond latency performance. This embodiment can save the design and generation time of the second data transmission module and improve work efficiency.

[0125] In the embodiments disclosed herein, such as Figure 8 As shown, steps S31-S33 are used to obtain multiple data transmission modules:

[0126] S31. Determine the third preset performance required for the data transmission array.

[0127] In this embodiment of the disclosure, the third preset performance of the data transmission array required for fabricating the circuit layout can be determined according to the actual performance requirements of the chip.

[0128] In this embodiment of the disclosure, the third preset performance can be determined by comprehensively considering various conditions such as the structure, area, and manufacturing process conditions of the circuit layout. The third preset performance can be determined based on the experience of the staff or based on a preset performance algorithm. Here, no specific method is limited for determining the third preset performance.

[0129] S32. Determine the second parameters of the data transmission module constituting the data transmission array based on the third preset performance.

[0130] In this embodiment of the disclosure, based on the determined third preset performance, a second parameter that the selected data transmission module needs to satisfy in order to achieve the third preset performance can be further determined.

[0131] In this embodiment of the disclosure, the second parameter may include any one or more of the following:

[0132] The first preset performance of each data transmission module, the arrangement order and number of data transmission modules with different first preset performance, and the total number of data transmission modules.

[0133] In this embodiment of the disclosure, for example, if a data transmission array with a delay of 0.5 nanoseconds is required, the existing data transmission modules have the following first preset performance: meeting the delay performance of 0.3 nanoseconds, 0.2 nanoseconds, and 0.1 nanoseconds, etc. Based on the requirement of meeting the delay of 0.5 nanoseconds, data transmission modules that meet one or more of the delay performances of 0.3 nanoseconds, 0.2 nanoseconds, and 0.1 nanoseconds are configured, and the configured data transmission modules are spliced ​​together to obtain a data transmission array that meets the delay performance of 0.5 nanoseconds.

[0134] S33. Call the corresponding multiple data transmission modules according to the second parameter, and splice the multiple data transmission modules according to the preset arrangement to generate a data transmission array.

[0135] In this embodiment of the disclosure, the preset arrangement may include: arranging the data transmission modules horizontally or vertically.

[0136] In the embodiments disclosed herein, such as Figure 3 The diagram shown illustrates a horizontal arrangement of multiple data transmission modules. Figure 4 The diagram shown is a schematic of multiple data transmission modules arranged vertically.

[0137] In this embodiment of the disclosure, when splicing multiple data transmission modules, the length of the multiple data transmission modules 100 can be unified to ensure the regularity of the splicing.

[0138] In this embodiment of the disclosure, when splicing multiple data transmission modules, the length or width of each data transmission module 100 can be aligned.

[0139] In this embodiment of the disclosure, when multiple data transmission modules are spliced ​​together, the distance d between any adjacent data transmission modules needs to satisfy the following: d is greater than or equal to the minimum distance between modules or units specified by DRC, so as to ensure that no new DRC errors are introduced after splicing.

[0140] In this embodiment of the disclosure, the multiple data transmission modules 100 spliced ​​together may include at least two data transmission modules of the exact same type; or, the multiple data transmission modules 100 spliced ​​together may be of different types.

[0141] In this embodiment of the disclosure, the multiple data transmission modules 100 participating in the splicing can be multiple data transmission modules 100 of the same type or multiple data transmission modules 100 of different types. They can be flexibly adjusted according to project requirements and are not limited here.

[0142] In this embodiment of the disclosure, the method may further include: obtaining a second data transmission array with different third preset performance from the first data transmission array by adjusting any one or more of the second parameters corresponding to any first data transmission array.

[0143] In this embodiment of the disclosure, each data transmission module included in the data transmission array may have replaceable and removable features, so that data transmission modules with incorrect settings can be adjusted when splicing data transmission arrays, and when another data transmission array with different third preset performance is needed, the data transmission modules can be simply adjusted based on the existing data transmission array to obtain the data transmission array with different first preset performance, such as the second data transmission array described above.

[0144] In this embodiment of the disclosure, after splicing the data transmission modules to obtain the data transmission array, the layout inspection stage needs to comprehensively inspect the spliced ​​layout to confirm that the layout's DRC, LVS (layout vesus schematics, layout netlist comparison, another important step in circuit layout inspection, checking whether the designed layout is consistent with the initial netlist), EM (electro migration, electromigration check, the calculation of electromigration effect of the layout structure, used to evaluate whether the lifetime of the circuit structure meets the design requirements), and other indicators meet the design requirements.

[0145] In this embodiment of the disclosure, the netlist can be extracted based on the layout results during the simulation stage. The simulation results are used to determine whether the third preset performance (e.g., delay performance) of the data transmission array can meet the project requirements, thereby determining the final circuit layout structure.

[0146] In this embodiment, during the K-library step, the post-simulation netlists of several data transmission modules can be extracted first, and the K-library is performed only on these data transmission modules. Subsequently, based on the repetition and splicing of the data transmission modules, the corresponding data information is synchronized to the corresponding signals, thereby obtaining the final lib file.

[0147] This disclosure also provides a data transmission method for a chip, such as... Figure 9 As shown, the chip is the chip described above, and the method may include step S31:

[0148] S31. Data transmission is performed between two functional modules of the chip based on the signal channel within the chip; the signal channel is constructed based on a data transmission array.

[0149] In this embodiment of the disclosure, when the data transmission array includes at least two data transmission modules of the same type, data transmission between two functional modules of the chip is performed based on the signal channel within the chip, including:

[0150] For signal channels with repetitive channel structures, the same signal information is used for data transmission.

[0151] In the embodiments of this disclosure, when the data transmission array comprises multiple data transmission modules of the same type spliced ​​together, since the internal circuit structure of the same data transmission modules is necessarily identical, the signal channels in the chip manufactured based on these circuit structures will necessarily have multiple identical channel structures. When using signal channels with the same channel structure for data transmission, the same signal information can be transmitted.

[0152] In this embodiment of the disclosure, the solution includes at least the following advantages:

[0153] 1. The present invention provides a modular layout solution that splits all signal lines into groups of multiple signal lines (or data lines, transmission lines) to form a data transmission module. By repeatedly splicing the data transmission modules in batches, the data transmission lines in the circuit layout are set up, which greatly simplifies the process of manual layout drawing and improves the efficiency of layout design.

[0154] 2. The solution of this disclosure simplifies the timing analysis involving thousands of signal lines to a limited number of data transmission modules, which greatly reduces the complexity of timing analysis of data transmission lines. While simplifying the K-library process of data transmission lines, it also improves the delay accuracy of data transmission.

[0155] 3. When it is necessary to adjust the number of channels of the data transmission line, the layout engineer does not need to redraw the layout. Instead, he can simply add or remove the number of data transmission modules, which is convenient and quick.

[0156] 4. When it is necessary to adjust the timing performance of the data transmission module, it can also be achieved by adding, deleting or splicing different types of data transmission modules, making the data transmission line more flexible and adjustable, and more efficient in meeting a variety of chip design requirements, thereby improving design efficiency and flexibility and accelerating project progress.

[0157] 5. In chips with multiple cores such as CPUs, DPUs, and GPUs, the modular layout setting method of this disclosure can optimize data transmission and reduce system-level delays.

[0158] This disclosure also provides an electronic device 400, such as... Figure 10 As shown, the electronic device may include:

[0159] Multi-core processor 401;

[0160] The multi-core processor 401 includes multiple cores 402, and each core 402 includes a control unit 4021, an arithmetic logic unit 4022, and a register 4023.

[0161] The multiple cores 402 are connected to each other via a data transmission array 200, wherein the data transmission array 200 is connected to the core 402 via a register 4023 in the core 402.

[0162] Among them, the multi-core processor 401 is a device with data processing capabilities, including but not limited to a central processing unit (CPU).

[0163] In this embodiment of the disclosure, the core 402 can be arranged in multiple rows and columns, and the rows and columns can be connected by a data transmission array 200 for data transmission.

[0164] This disclosure also provides a computer-readable storage medium 500, such as... Figure 11 As shown, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements any one or more of the following methods: the method for generating the data transmission module, the method for generating the data transmission array, and the data transmission method.

[0165] Those skilled in the art will understand that all or some of the functional modules / units disclosed above can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0166] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0167] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0168] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A data transmission array, characterized in that: It includes a plurality of data transmission modules; the data transmission modules have a first preset performance; A plurality of the data transmission modules are spliced ​​in a preset arrangement; the data transmission array is used to form a signal channel in a chip.

2. The data transmission array according to claim 1, characterized in that: The data transmission module includes multiple types; The data transmission modules of the same type have the same first preset performance; Different types of data transmission modules have different first preset performances.

3. The data transmission array according to claim 2, characterized in that: A circuit structure comprising at least one signal line and the at least one signal line; The data transmission modules of the same type have the same first preset performance based on the same first parameters of the signal lines and the same line structures; Different types of data transmission modules have different first preset performances based on different first parameters of the signal lines included therein and / or different line structures.

4. The data transmission array according to claim 3, characterized in that: The first parameter includes any one or more of the following: The second preset performance of each signal line, the arrangement order and quantity of the signal lines with different second preset performances, and the total quantity of the signal lines.

5. The data transmission array according to claim 3, characterized in that: The at least one signal line is divided into a plurality of groups, and the first parameter and the line structure of at least two groups of signal lines in the plurality of groups of signal lines are the same.

6. The data transmission array according to claim 3, characterized in that: The boundary of the line structure constitutes the boundary of the data transmission module.

7. The data transmission array according to claim 1, characterized in that: The preset arrangement includes: arranging the data transmission modules horizontally or vertically.

8. The data transmission array according to claim 1, characterized in that: The plurality of data transmission modules include at least two data transmission modules of exactly the same type; or, The types of the multiple data transmission modules are all different.

9. The data transmission array according to claim 1, characterized in that: The data transmission arrays may be of multiple types, and different types of data transmission arrays may have different third preset performances.

10. The data transmission array according to claim 9, characterized in that: Different types of data transmission arrays have different third preset performances based on different second parameters of the data transmission modules included therein.

11. The data transmission array according to claim 10, characterized in that: The second parameter includes any one or more of the following: The first preset performance of each of the data transmission modules, the arrangement order and quantity of the data transmission modules with different first preset performances, and the total quantity of the data transmission modules.

12. A chip, characterized in that: It comprises a signal channel; the signal channel is formed based on the data transmission array described in any one of claims 1-11.

13. The chip according to claim 12, characterized in that: The chip includes at least two functional modules; The signal channel is located between the two functional modules.

14. The chip according to claim 12, characterized in that: In the case where the data transmission array includes at least two data transmission modules of completely identical types and / or the data transmission module includes at least two completely identical signal line groups, the signal channel has a repeated channel structure.

15. A method for generating a data transmission array, characterized in that: The method comprises: Acquire multiple data transmission modules; the data transmission modules have a first preset performance; The data transmission array is generated by splicing a plurality of the data transmission modules in a preset arrangement; the data transmission array is used to form a signal channel in a chip.

16. The method for generating a data transmission array according to claim 15, characterized in that: The obtaining of multiple data transmission modules includes: Determining a third preset performance that the data transmission array needs to have; Determining a second parameter of a data transmission module constituting the data transmission array according to the third preset performance; The corresponding plurality of data transmission modules are called according to the second parameter.

17. The method for generating a data transmission array according to claim 16, characterized in that: The second parameter includes any one or more of the following: The first preset performance of each of the data transmission modules, the arrangement order and quantity of the data transmission modules with different first preset performances, and the total quantity of the data transmission modules.

18. The method for generating a data transmission array according to claim 17, characterized in that: The method further includes: obtaining a second data transmission array having a third preset performance different from that of the first data transmission array by adjusting any one or more of the second parameters corresponding to any first data transmission array.

19. The method for generating a data transmission array according to claim 15, characterized in that: Before acquiring a plurality of data transmission modules, the method further comprises: generating the data transmission modules; The generating the data transmission module comprises: Determining a first preset performance that the data transmission module needs to have; Determining a first parameter of a signal line constituting the data transmission module according to the first preset performance; The corresponding signal line is acquired according to the first parameter, and the corresponding line structure is constructed based on the acquired signal line to generate the data transmission module.

20. The method for generating a data transmission array according to claim 19, characterized in that: The first parameter includes any one or more of the following: The second preset performance of each signal line, the arrangement order and quantity of the signal lines with different second preset performances, and the total quantity of the signal lines.

21. The method for generating a data transmission array according to claim 20, characterized in that: The method also includes: obtaining a second data transmission module having a first preset performance different from that of the first data transmission module by adjusting the line structure in any first data transmission module and / or any one or more of the first parameters corresponding to the first data transmission module.

22. A chip data transmission method, characterized in that: The chip is the chip according to any one of claims 12 to 14, and the method comprises: Data is transmitted between two functional modules of the chip based on a signal channel within the chip; the signal channel is formed based on a data transmission array.

23. The chip data transmission method according to claim 22, characterized in that: In the case where the data transmission array includes at least two data transmission modules of the same type, the data transmission between the two functional modules of the chip based on the signal channel in the chip includes: For signal channels with repeated channel structures, the same signal information is used for data transmission.

24. An electronic device, characterized in that: The electronic device comprises: a multi-core processor; The multi-core processor includes a plurality of cores, each core includes a control unit, an arithmetic logic unit and a register; The plurality of cores are connected via a data transmission array as described in any one of claims 1 to 11, wherein the data transmission arrays are connected to the cores via registers in the cores.

25. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the computer program implements: the method for generating a data transmission array as described in any one of claims 15 to 21 and / or the data transmission method for a chip as described in claim 22 or 23.

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