Data transmission unit, circuit layout setting method, data transmission method and chip

Abstract

The embodiment of the invention provides a data transmission unit, a circuit layout setting method, a data transmission method and a chip, the data transmission unit has first performance, and the data transmission unit comprises at least one type of data transmission chain; wherein the different types of data transmission chains respectively have different second performance; the performance type of the second performance is the same as that of the first performance; the at least one data transmission chain is arranged according to a preset layout mode. According to the scheme of the embodiment, a technical basis is provided for circuit performance adjustability, and a technical basis is provided for quickly responding, meeting a layout setting scene with multiple performance requirements and improving the setting efficiency of a circuit layout and a chip.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of integrated circuit design, and in particular to a data transmission unit and a circuit layout setting method, a data transmission method and a chip. Background Art

[0002] With the advent of the digital age, the requirements for data transmission are getting higher and higher, so the design for data transmission has become crucial for chip designers. As the times develops, the scale of chips is getting larger and larger, so the requirements for data transmission are more diverse and the transmission distance is longer. Summary of the invention

[0003] The embodiments of the present disclosure provide a data transmission unit and a circuit layout setting method, a data transmission method and a chip.

[0004] In a first aspect, an embodiment of the present disclosure provides a data transmission unit that can be arranged in a standard cell library, the data transmission unit having a first performance, the data transmission unit comprising: at least one type of data transmission chain;

[0005] Among them, different types of data transmission chains have different second performances respectively; the second performance is the same performance type as the first performance; and the at least one data transmission chain is arranged according to a preset layout.

[0006] In a second aspect, an embodiment of the present disclosure provides a method for setting a data transmission unit, and the method may include:

[0007] Determining a first performance that a data transmission unit needs to have;

[0008] At least one type of customized data transmission link is retrieved according to the first performance; different types of data transmission links have different second performances respectively; the second performance is the same as the performance type of the first performance;

[0009] Arrange the at least one data transmission chain according to a preset layout to obtain a layout of a data transmission unit having the first performance.

[0010] In a third aspect, an embodiment of the present disclosure provides a circuit layout setting method, which may include:

[0011] Retrieve a data transmission unit; the data transmission unit is the data transmission unit mentioned above;

[0012] The layout of the data transmission unit is set in the circuit layout so that the circuit corresponding to the circuit layout has a preset third performance; the third performance is the same as the performance type of the first performance of the data transmission unit.

[0013] In a fourth aspect, an embodiment of the present disclosure provides a data transmission method, which may include:

[0014] Data transmission is performed through a preset data transmission unit; the data transmission unit is the above-mentioned data transmission unit.

[0015] In a fifth aspect, an embodiment of the present disclosure provides a chip comprising the data transmission unit.

[0016] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, the electronic device comprising: a multi-core processor;

[0017] The multi-core processor includes a plurality of cores, each core includes a control unit, an arithmetic logic unit and a register;

[0018] The multiple cores are connected via the data transmission unit, wherein the data transmission units are connected to the core via registers in the core.

[0019] In the seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements any one or more of the following methods: the data transmission unit setting method, the circuit layout setting method, and the data transmission method.

[0020] The data transmission unit of the embodiment of the present disclosure includes at least one type of data transmission chain. Different types of data transmission chains are pre-customized and belong to fully customized data transmission chains. Different types of data transmission chains have different second performances (for example, delay performance), thereby realizing modular setting of the data transmission chain. Based on the second performance of at least one type of data transmission chain, the data transmission unit has a first performance (for example, delay performance), so that data transmission units with different first performances can be obtained based on the modular data transmission chain. Accordingly, the modularization of the data transmission unit is realized, so that when the third performance (for example, delay performance) needs to be implemented in the circuit layout, the data transmission unit with the first performance can be directly called and set in the circuit layout, which provides a technical basis for adjustable circuit performance, and can accurately control the performance of each data transmission chain, and can quickly respond to and meet the layout setting scenarios with multiple performance requirements, thereby providing a technical basis for improving the setting efficiency of circuit layout and chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In the accompanying drawings of the embodiments of the present disclosure:

[0022] Figure 1 A schematic diagram of a data transmission unit for horizontal transmission provided in an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of a data transmission unit for vertical transmission provided by an embodiment of the present disclosure;

[0024] Figure 3 A flow chart of a method for setting a data transmission unit provided in an embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of a data transmission unit 100-1 provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of a data transmission unit 100-2 provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of a data transmission unit 100-3 provided in an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of a data transmission unit 100-4 provided in an embodiment of the present disclosure;

[0029] Figure 8 A flow chart of a circuit layout setting method provided in an embodiment of the present disclosure;

[0030] Fig. 9 A flow chart of a data transmission method provided by an embodiment of the present disclosure;

[0031] Fig.10 A block diagram of the chip composition provided in the embodiment of the present disclosure;

[0032] Fig.11 A block diagram of the electronic device provided in the embodiment of the present disclosure;

[0033] Fig.12 A block diagram of the computer-readable storage medium provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the communication perception data processing method and computer-readable storage medium provided by the embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0035] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0036] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0037] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0038] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0039] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0041] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0042] With the advent of the digital age, the requirements for data transmission are getting higher and higher, so the design for data transmission has become crucial for chip designers. With the development of the times, the scale of chips is getting larger and larger, so the demand for data transmission is more diverse and the transmission distance is longer. In data transmission, especially when long-distance data transmission is required, the transmission chain involves many types and levels of standard units. It is a challenge for chip designers to efficiently meet various performance requirements.

[0043] Most existing technologies use specific cells in the standard cell library provided by the Foundry (wafer manufacturer) to automatically complete Place & Route (PR for short, i.e. layout and routing) based on scripts. Therefore, in order to efficiently meet the diverse performance requirements during long-distance data transmission, it is necessary to repeatedly go through a complex design process, which is time-consuming and labor-intensive.

[0044] In addition, the current PR schemes for realizing data transmission in integrated circuits all automatically generate PR through scripts (i.e., programs), that is, realize the automatic generation of PR. However, when the data transmission line generated by automatic PR involves more ports, it is impossible to accurately control the performance of each signal channel (such as delay performance), so it has great limitations in practical application. The performance of the data transmission line (such as delay performance) cannot be adjusted, and the delay of each signal channel cannot be accurately controlled, so that the layout of the designed data transmission method cannot meet various application scenarios.

[0045] The embodiment of the present disclosure provides a data transmission unit, which is composed of at least one data transmission chain. Different types of data transmission chains are pre-customized, and different types of data transmission chains have different second performances (for example, delay performance), so that modular setting of the data transmission chain is realized, and based on the second performance of at least one type of data transmission chain, the data transmission unit has a first performance (for example, delay performance), so that data transmission units with different first performances can be obtained based on the modular data transmission chain, so that when data transmission units with different first performances are needed, the corresponding type of data transmission chain can be directly called to set the data transmission unit, so that data transmission units with different first performances (for example, delay performance) can be quickly combined through modular data transmission chains, and based on the setting of data transmission units with different first performances, the modularization of the data transmission unit is correspondingly realized, so that when the third performance (for example, delay performance) needs to be realized in the circuit layout, the data transmission unit with the first performance can be directly called and set in the circuit layout, so that the performance of the data transmission line can be adjusted very easily, and the performance (such as delay) of each signal channel can be accurately controlled, which provides a technical basis for improving the chip setting efficiency. The embodiment of the present disclosure can quickly respond to and meet the layout setting scenarios with multiple performance requirements.

[0046] The data transmission unit of the embodiment of the present disclosure can be set in the standard cell library, and can be applied to any circuit layout with multiple performance requirements for the data transmission chain in long-distance data transmission, and can be applied to any circuit layout in which the performance of each signal channel in the data transmission line needs to be accurately controlled in the data transmission chain. The setting method of the data transmission unit can be applied to any standard cell design software and tools, and the circuit layout setting method can be applied to any circuit layout design software and tools. These methods can be implemented by the processor calling the computer-readable program instructions stored in the memory. The data transmission unit of the embodiment of the present disclosure can be applied to the drawing process of any circuit layout, and can be applied to any chip design. For example, it can include but is not limited to CPU (Central Processing Processor, central processing unit), GPU (Graphics Processing Unit, graphics processor), DPU (Data Processing Unit, data processing unit) and other chips with various requirements for data transmission delay, and is particularly suitable for multi-core chips. The data transmission method of the embodiment of the present disclosure can be applied to the data transmission scenario of any circuit and chip, and the data transmission scenario between cores in any multi-core chip.

[0047] The following is a detailed introduction to the embodiments of the present disclosure.

[0048] The present disclosure provides a data transmission unit 100, such as Figure 1 As shown, it can be set in a standard cell library, the data transmission unit 100 has a first performance, and the data transmission unit 100 can include but is not limited to: at least one type of data transmission link 101;

[0049] Different types of data transmission links 101 have different second performances respectively; the second performance is the same as the performance type of the first performance; and the at least one data transmission link 101 is arranged according to a preset layout.

[0050] In the embodiments of the present disclosure, the first performance and the second performance may include but are not limited to delay performance, impedance performance, etc., and the first performance and the second performance may both be delay performance.

[0051] In the embodiments of the present disclosure, in order to solve the problem that the PR generated by the current solution based on the script cannot be adjusted at will, so that the layout and circuit must be redesigned when there are different performance requirements (such as delay requirements), the embodiments of the present disclosure can pre-customize multiple types of data transmission chains 101, and different data transmission chains 101 have different second performances (such as delay performance), so that the data transmission chains 101 with different second performances are modularized, so that the corresponding modules of the data transmission chains 101 with different performances can be directly called, and the data transmission unit 100 with preset performance requirements (that is, the first performance requirements, such as delay requirements) can be quickly set.

[0052] In the disclosed embodiment, various types of data transmission chains 101 may be pre-drawn, and these data transmission chains 101 may be stored as a whole in the form of modules, and these modules may be called, thereby implementing pre-customization of different types of data transmission chains 101 .

[0053] In the embodiment of the present disclosure, the pre-customized modular data transmission chain 101 may include but is not limited to a data transmission chain with commonly used performance. For example, if the delay duration that often needs to be adjusted in the circuit is 0.2 microseconds or 0.4 microseconds, the pre-customized data transmission chain may be a data transmission chain with 0.2 microsecond delay performance and 0.4 microsecond delay performance). The pre-customized modular data transmission chain 101 may also be a data transmission chain with specific performance.

[0054] In the embodiment of the present disclosure, one end of each data transmission chain 101 serves as a data input end, and the other end serves as a data output end; and / or,

[0055] Each data transmission chain 101 may include but is not limited to one or more connected preset elements, and the one or more connected preset elements enable the data transmission chain 101 to have a second performance.

[0056] In the embodiment of the present disclosure, the preset element may include but is not limited to a buffer (a logical forward driving unit in a circuit), a logic element, an impedance element, and the like.

[0057] In the embodiment of the present disclosure, when the second performance is a delay performance, the preset element may include a buffer, and based on the buffer having a certain delay performance, the data transmission chain 101 may be a buffer-like chain. A buffer-like chain is a data transmission chain with adjustable performance and a forward driving function.

[0058] In the embodiments of the present disclosure, different types of data transmission chains can be distinguished by different identifiers, for example: data transmission chain A, data transmission chain B, data transmission chain C, data transmission chain D, ..., data transmission chain M, data transmission chain, etc. If each data transmission chain can be used as a class buffer chain, different types of data transmission chains can also be called: class buffer chain A, class buffer chain B, class buffer chain C, class buffer chain D, ..., class buffer chain M, class buffer chain N, etc.

[0059] In the embodiments of the present disclosure, the layout may include horizontal arrangement or vertical arrangement, such as Figure 1 and Figure 2 shown.

[0060] In the embodiment of the present disclosure, when horizontal arrangement or vertical arrangement is performed, multiple data transmission chains can be arranged in parallel.

[0061] In the embodiment of the present disclosure, the data transmission unit 100 can perform horizontal data transmission when arranged horizontally, and can perform vertical data transmission when arranged vertically.

[0062] The present disclosure also provides a method for setting a data transmission unit. Figure 3 As shown, the method may include steps S11-S13:

[0063] S11, determining a first performance that a data transmission unit needs to have;

[0064] S12, calling at least one type of customized data transmission link according to the first performance; different types of data transmission links have different second performances respectively; the second performance is the same as the performance type of the first performance;

[0065] S13: Arrange the at least one data transmission chain according to a preset layout to obtain a data transmission unit with a first performance.

[0066] In the embodiment of the present disclosure, at least one type of customized data transmission chain is retrieved according to the first performance, including:

[0067] Parameters of the data transmission link required by the first performance configuration;

[0068] At least one data transmission chain matching the parameters is called from the customized multiple data transmission chains.

[0069] In the embodiment of the present disclosure, the parameter may include but is not limited to: the type of data transmission link to be selected, the number of each type of data transmission link selected, and the metal layer that can be set for each type of data transmission link selected.

[0070] In the disclosed embodiment, the data transmission unit includes multiple data transmission chains, with multiple inputs and multiple outputs, and each data transmission chain exists independently. The delay of the data transmission unit required by the project is not the overall average delay, for example, x 150 picoseconds, y 200 picoseconds, z 300 picoseconds, ..., where x, y, and z are all positive integers, and it is only necessary to combine these data transmission chains as required to achieve the delay performance requirements of the data transmission unit.

[0071] In the embodiment of the present disclosure, the layout includes horizontal arrangement or vertical arrangement.

[0072] In the embodiment of the present disclosure, after the required data transmission links are selected according to the first performance, the data transmission links may be arranged horizontally or vertically to obtain a data transmission unit with the first performance.

[0073] In the embodiment of the present disclosure, when horizontal arrangement or vertical arrangement is performed, multiple data transmission chains can be arranged in parallel.

[0074] In the embodiment of the present disclosure, when arranged horizontally, the data transmission unit 100 can transmit data horizontally, and when arranged vertically, the data transmission unit 100 can transmit data vertically.

[0075] In the embodiment of the present disclosure, each data transmission chain included in the data transmission unit is replaceable.

[0076] In the embodiment of the present disclosure, the method may further include:

[0077] By adjusting any one or more of the number, type and setting level of the data transmission chains in the data transmission unit, a data transmission unit with different first performances is obtained.

[0078] In an embodiment of the present disclosure, after selecting and configuring different types of data transmission chains, a data transmission unit with a first performance can be obtained. The data transmission unit includes multiple data transmission chains with multiple inputs and multiple outputs, and each data transmission chain exists independently. The delay of the data transmission unit required by the project is not the overall average delay, for example, x 150 picoseconds, y 200 picoseconds, z 300 picoseconds, ..., where x, y, and z are all positive integers. It is only necessary to combine these data transmission chains as required to achieve the delay performance requirements of the data transmission unit. This embodiment scheme can save the generation process of the data transmission unit and improve efficiency.

[0079] In the embodiments of the present disclosure, Figure 4 , Figure 5 As shown, there are two horizontally arranged data transmission units, wherein Figure 4The data transmission unit 100-1 is shown, which is provided with a plurality of data transmission chains, such as a data transmission chain A, a data transmission chain B, a data transmission chain C, and a data transmission chain M. Figure 5 The data transmission unit 100-2 is shown. By replacing the data transmission chain C in the data transmission unit 1 with the data transmission chain D, and replacing the data transmission chain M with the data transmission chain N, a data transmission unit 100-2 having different performance (such as delay performance) from the data transmission unit 100-1 is obtained. At this time, the data transmission unit 100-2 is provided with multiple data transmission chains such as the data transmission chain A, the data transmission chain B, the data transmission chain D, and the data transmission chain N.

[0080] In the embodiments of the present disclosure, Figure 6 , Figure 7 As shown, there are two vertically arranged data transmission units, wherein Figure 6 The data transmission unit 100-3 is shown, which is provided with a plurality of data transmission chains, such as a data transmission chain A, a data transmission chain B, a data transmission chain C, and a data transmission chain M. Figure 7 The data transmission unit 100-4 is shown. By replacing the data transmission chain C in the data transmission unit 100-3 with the data transmission chain D, and replacing the data transmission chain M with the data transmission chain N, a data transmission unit 100-4 having performance (such as delay performance) different from that of the data transmission unit 100-3 is obtained. At this time, the data transmission unit 100-4 is provided with multiple data transmission chains such as data transmission chain A, data transmission chain B, data transmission chain D, and data transmission chain N.

[0081] In the embodiments of the present disclosure, it can be seen from the above examples that by setting each data transmission chain to have replaceable performance, when generating a new data transmission unit, only part of the data transmission chains of the existing data transmission unit need to be adjusted to obtain the new data transmission unit, which greatly improves work efficiency, especially for application scenarios with a large number of data transmission chains.

[0082] The present disclosure also provides a circuit layout setting method, such as Figure 8 As shown, steps S21-S22 may be included:

[0083] S21, retrieve a data transmission unit; the data transmission unit is the above-mentioned data transmission unit;

[0084] S22. Setting the layout of the data transmission unit in the circuit layout so that the circuit corresponding to the circuit layout has a preset third performance; the third performance is the same as the performance type of the first performance of the data transmission unit.

[0085] In the disclosed embodiment, when drawing a circuit layout, the above-mentioned data transmission unit can be called, and the data transmission chain in the data transmission unit can be connected to any required line in the circuit layout, so that the circuit layout meets the performance requirements.

[0086] In the embodiment of the present disclosure, the third performance may include but is not limited to delay performance, impedance performance, etc. For example, the third performance may be delay performance.

[0087] In the disclosed embodiment, when any line in the circuit layout needs to have a certain delay performance, a data transmission unit with the delay performance can be directly set in the circuit layout to achieve the corresponding delay performance through the data transmission chain in the data transmission unit.

[0088] In the disclosed embodiment, when designing a circuit, a post-simulation netlist of the circuit can be extracted, and the delay of the circuit under different load requirements (i.e., the third performance mentioned above) can be simulated based on the post-simulation netlist. Based on the third performance, a corresponding data transmission unit can be given and called into the circuit layout of the circuit.

[0089] In the embodiment of the present disclosure, the data transmission unit is replaceable.

[0090] In an embodiment of the present disclosure, the method may further include: when the required third performance changes, replacing one or more data transmission units in the circuit layout with data transmission units with different first performance, so that the circuit corresponding to the circuit layout has the required third performance.

[0091] In the disclosed embodiment, for example, the project requires a data transmission unit 100-5 with horizontal transmission having 2000 data transmission chains, of which 1000 data transmission chains A have a delay of 400 picoseconds, 500 data transmission chains B have a delay of 350 picoseconds, 300 data transmission chains C have a delay of 300 picoseconds, and 200 data transmission chains M have a delay of 200 picoseconds; later, due to project adjustments, the project requires a data transmission unit 100-6 with horizontal transmission having 1500 data transmission chains, of which 300 data transmission chains A have a delay of 400 picoseconds, 400 data transmission chains B have a delay of 350 picoseconds; 400 data transmission chains D have a delay of 250 picoseconds; and 400 data transmission chains N have a delay of 150 picoseconds. Compared with the data transmission unit 100 - 5 , the data transmission chain type, quantity and metal layer used in the data transmission unit 100 - 6 are different. By directly replacing the data transmission unit 100 - 5 with the data transmission unit 100 - 6 , the data transmission delay can be adjusted.

[0092] In the embodiment of the present disclosure, the purpose of adjusting the performance of data transmission can be achieved by replacing data transmission units with different delays, and various performance requirements can be easily met.

[0093] In the disclosed embodiment, the layout of the data transmission unit before and after replacement can have different widths, or keep the width unchanged, so the area and the overall shape can be the same or different, and the increase or decrease of the area meets the final area requirements of the project. If there is no change, it can be easily replaced during the back-end implementation process to reduce additional layout and wiring changes and reduce the risk of design rule violations.

[0094] In the embodiment of the present disclosure, the performance adjustable mechanism of the data transmission unit for longitudinal transmission is the same as the performance adjustable mechanism of the data transmission unit for transverse transmission.

[0095] The present disclosure also provides a data transmission method. Fig. 9 As shown, the method may include step S31:

[0096] S31. Perform data transmission through a preset data transmission unit; the data transmission unit is the above-mentioned data transmission unit.

[0097] In the embodiments of the present disclosure, the data transmission method of the embodiments of the present disclosure can be applicable to data transmission scenarios of any circuits and chips, and data transmission scenarios between cores in any multi-core chip.

[0098] In the embodiments of the present disclosure, at least the following advantages are included:

[0099] 1. By replacing the data transmission unit with different first performance, the data transmission performance of the circuit can be adjusted, which can easily meet the different needs of the project.

[0100] 2. Each data transmission chain in the data transmission unit can be easily adjusted, so the performance (such as delay) of each data transmission chain can be accurately controlled to achieve the purpose of accurately controlling data transmission performance, which can efficiently meet a variety of chip application scenarios.

[0101] 3. In multi-core chips such as CPU, DPU and GPU, the data transmission unit of the embodiment of the present disclosure is used to optimize the data transmission method (for example, reduce system-level delay) and improve signal transmission quality.

[0102] The present disclosure also provides a chip 300, such as Fig.10 As shown, it is generated based on a preset circuit layout, and the preset circuit layout is obtained according to the circuit layout setting method.

[0103] The present disclosure also provides an electronic device 400, such as Fig.11 As shown, the electronic device 400 may include: a multi-core processor 401;

[0104] The multi-core processor 401 includes a plurality of cores 402 , each core 402 includes a control unit 4021 , an arithmetic logic unit 4022 and a register 4023 ;

[0105] The multiple cores 402 are connected via a data transmission unit 100 , wherein the data transmission units 100 are connected to the core 402 via a register 4023 in the core 402 .

[0106] The multi-core processor 401 is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like.

[0107] In the embodiment of the present disclosure, the cores 402 may be arranged in multiple rows and columns, and the rows and columns may be connected by data transmission units 100 for data transmission.

[0108] The present disclosure also provides a computer-readable storage medium 500. Fig.12 As shown, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by the processor, any one or more of the following methods are implemented: the data transmission unit setting method, the circuit layout setting method and the data transmission method.

[0109] Those skilled in the art will appreciate that all or some of the functional modules / units disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0110] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0111] Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-temporary medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0112] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data transmission unit, characterized in that: The data transmission unit has a first performance, and the data transmission unit includes: at least one type of data transmission link; Among them, different types of data transmission chains have different second performances respectively; the second performance is the same performance type as the first performance; and the at least one data transmission chain is arranged according to a preset layout.

2. The data transmission unit according to claim 1, characterized in that: One end of each of the data transmission chains serves as a data input end and the other end serves as a data output end; and / or, Each of the data transmission chains comprises one or more connected preset elements, and the one or more connected preset elements enable the data transmission chain to have the second performance.

3. A method for setting a data transmission unit, characterized in that: The method comprises: Determining a first performance that a data transmission unit needs to have; At least one type of customized data transmission link is retrieved according to the first performance; different types of data transmission links have different second performances respectively; the second performance is the same as the performance type of the first performance; Arrange the at least one data transmission chain according to a preset layout to obtain a layout of a data transmission unit having the first performance.

4. The method for setting up a data transmission unit according to claim 3, characterized in that: The at least one type of data transmission chain customized according to the first performance call includes: Parameters of the data transmission link required by the first performance configuration; At least one data transmission chain matching the parameters is retrieved from the customized multiple data transmission chains.

5. The method for setting up a data transmission unit according to claim 4, characterized in that: The parameters include: the type of data transmission link to be selected, the number of each type of data transmission link selected, and the setting level of each type of data transmission link selected.

6. The method for setting up a data transmission unit according to claim 3, characterized in that: Each of the data transmission chains included in the data transmission unit is replaceable.

7. The method for setting up a data transmission unit according to claim 6, characterized in that: The method further comprises: By adjusting any one or more of the number, type and setting level of the data transmission chains in the data transmission unit, a data transmission unit with different first performance is obtained.

8. A circuit layout setting method, characterized in that: The method comprises: Retrieve a data transmission unit; the data transmission unit is the data transmission unit according to claim 1 or 2; The layout of the data transmission unit is set in the circuit layout so that the circuit corresponding to the circuit layout has a preset third performance; the third performance is the same as the performance type of the first performance of the data transmission unit.

9. The circuit layout setting method according to claim 8, characterized in that: The data transmission unit is replaceable.

10. The circuit layout setting method according to claim 9, characterized in that: The method further comprises: In the case where the required third performance changes, the data transmission unit in the circuit layout is replaced with a data transmission unit with a different first performance, so that the circuit corresponding to the circuit layout has the required third performance.

11. A data transmission method, characterized in that: The method comprises: Data transmission is performed through a preset data transmission unit; the data transmission unit is the data transmission unit according to claim 1 or 2.

12. A chip, characterized in that: A data transmission unit comprising the data transmission unit according to claim 1 or 2.

13. An electronic device, characterized in that: The electronic device comprises: a multi-core processor; The multi-core processor includes a plurality of cores, each core includes a control unit, an arithmetic logic unit and a register; The multiple cores are connected via the data transmission unit described in claim 1 or 2, wherein the data transmission units are connected to the core via registers in the core.

14. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any one or more of the following methods: the method for setting a data transmission unit as described in any one of claims 3 to 7, the method for setting a circuit layout as described in any one of claims 8 to 10, and the data transmission method as described in claim 11.

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