Semiconductor integrated circuit, method of manufacturing same, and semiconductor device

Abstract

The invention provides a semiconductor integrated circuit, a manufacturing method thereof and a semiconductor device. The semiconductor integrated circuit includes a first region and a remaining region other than the first region. The manufacturing method includes: arranging standard cells in the remaining area; generating a wiring structure connecting the standard cells; arranging the sub-power tap units in the first region based on a predefined design rule; and verifying whether the sub-power tap unit and the standard unit conform to a predefined design rule.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0156358 filed in the Korean Intellectual Property Office on November 13, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor integrated circuit and a method for designing the semiconductor integrated circuit. Background Art

[0003] By arranging a semiconductor device (such as an integrated circuit) including a signal line for signal routing and an active device on the front side of the wafer, and arranging a power distribution network (PDN) for power supply on the back side of the wafer, a back side power distribution network (BSPDN) semiconductor structure separates the signal line from the power distribution network arranged on the wafer. Such a BSPDN semiconductor structure can minimize routing congestion and reduce the area of ​​the semiconductor structure.

[0004] Integrated circuits that process digital signals can be designed based on standard cells. Functional circuits can be formed by placing and routing standard cells so that the integrated circuits can achieve the desired functions.

[0005] As the demand for high performance, higher speed and / or multifunctionality of semiconductor devices increases, the integration of semiconductor devices is increasing. Under the trend of semiconductor devices toward higher integration, the number of design rules that need to be considered during layout design is increasing. These design rules need to be considered during the layout of standard cells. Summary of the invention

[0006] One or more embodiments provide a design method of a semiconductor integrated circuit in which a power tap cell is laid out after a standard cell is laid out.

[0007] One or more embodiments provide a design method for a semiconductor integrated circuit, the design method reducing design rule constraints on a standard cell during a layout process of the standard cell.

[0008] One or more embodiments provide a design method for a semiconductor integrated circuit to reduce the number of cells stored in a cell library.

[0009] One or more embodiments provide a semiconductor integrated circuit having a backside power distribution network semiconductor structure designed using the integrated circuit design method.

[0010] According to one aspect of an embodiment, a method for manufacturing a semiconductor integrated circuit including a first region and a remaining region other than the first region includes: placing standard cells in the remaining region; generating a wiring structure connecting the standard cells; placing sub-power tap cells in the first region based on predefined design rules; and verifying whether the sub-power tap cells and the standard cells comply with the predefined design rules.

[0011] According to another aspect of the embodiment, a semiconductor integrated circuit includes: a first power rail extending in a first direction; a second power rail extending in the first direction and spaced apart from the first power rail in a second direction intersecting the first direction; a first standard cell located between the first power rail and the second power rail; and a first power tap cell adjacent to the first standard cell in the first direction and including a first region and a second region, the first region including a first via electrically connecting an external power line and the first power rail, and the second region including a second via electrically connecting the external power line and the second power rail, a first active layer having a first width in the second direction, and a second active layer having a second width different from the first width in the second direction.

[0012] According to another aspect of the embodiment, a semiconductor device includes: a substrate; a first layer located on a first side of the substrate and including a power distribution network; and a second layer located on a second side of the substrate and including a first power rail, a first through-silicon via, and a second through-silicon via, the first power rail extending in a first direction, the first through-silicon via extending from the power distribution network through the substrate to the first power rail in a second direction and having a first length in the first direction, the second direction intersecting the first direction, the second through-silicon via contacting the first through-silicon via, being adjacent to the first through-silicon via in the first direction, extending from the power distribution network through the substrate to the first power rail in the second direction, and having a first length in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects will become more apparent from the following description of embodiments in conjunction with the accompanying drawings.

[0014] Figure 1 2 is a perspective view of a front side power distribution network (FSPDN) semiconductor structure and a back side power distribution network (BSPDN) semiconductor structure according to an embodiment.

[0015] Figure 2 A BSPDN semiconductor structure according to an embodiment is shown.

[0016] Figure 3 A BSPDN semiconductor structure according to an embodiment is shown.

[0017] Figure 4A portion of an integrated circuit formed in a signal line layer according to an embodiment is schematically shown.

[0018] Figure 5 is a flowchart provided for describing a design method of a semiconductor device according to a comparative example.

[0019] Figure 6 is a top plan view of a power tap unit according to a comparative example and a standard unit.

[0020] Figure 7 is a diagram for describing a design rule for a power tap unit.

[0021] Figure 8 is a flowchart for describing a design method of a semiconductor device according to an embodiment.

[0022] Fig. 9 A portion of an integrated circuit formed in a signal line layer according to an embodiment is schematically shown.

[0023] Fig.10 is a top plan view of a sub-power tap unit provided by a unit library according to an embodiment.

[0024] Fig.11 A portion of an integrated circuit formed in a signal line layer according to an embodiment is schematically shown.

[0025] Fig.12 is a flowchart of a layout method of sub-power tap units according to an embodiment.

[0026] Fig.13 is a flowchart of a layout method of sub-power tap units according to an embodiment.

[0027] Fig.14 A portion of an integrated circuit according to an embodiment is schematically shown to describe Fig.13 A layout method of a sub-power tap unit.

[0028] Fig.15 is a flowchart of a layout method of sub-power tap units according to an embodiment.

[0029] Fig.16 A portion of an integrated circuit according to an embodiment is schematically shown to describe Fig.15 A layout method of a sub-power tap unit.

[0030] Fig.17 A design system for a semiconductor device according to an embodiment is schematically shown. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The same reference numerals are assigned to the same components in the accompanying drawings, and repeated description of the same components is omitted.

[0032] The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, but may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, the size of the component is not limited to the disclosed range or value, but may vary according to process conditions and / or desired device properties. In addition, in the following description, forming a first structure on or above a second structure may include an embodiment in which the first structure and the second structure are formed by direct contact, and may also include an embodiment in which an additional structure is formed between the first structure and the second structure so that the first structure and the second structure are not in direct contact. For simplicity and clarity, various structures may be arbitrarily drawn in different proportions. Expressions such as "at least one (kind / person) of ..." modify the entire column of elements rather than modifying individual elements in the column when they are attached to (before) a column of elements. For example, the expression "at least one (kind / person) of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0033] In addition, in order to facilitate the description of the relationship of elements or structures shown in the drawings relative to other elements or structures, terms with spatial relationships may be used, such as "below", "lower", "under", "above" and "top".

[0034] Therefore, the drawings and descriptions are to be considered as illustrative in nature and not restrictive, and like reference numerals denote like elements throughout the specification. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, some operations may be split, and some operations may not be performed.

[0035] Figure 1 2 is a perspective view of a front side power distribution network (FSPDN) semiconductor structure and a back side power distribution network (BSPDN) semiconductor structure according to an embodiment.

[0036] Reference Figure 1 , a front side power distribution network (FSPDN) semiconductor structure 110 includes a power distribution network (PDN) and a signal line layer 113 disposed on one side of a wafer 111. The power distribution network and signal line layer 113 may include power rails and signal lines. However, the FSPDN semiconductor structure 110 may cause wiring congestion in the lines of the power distribution network and signal line layer 113, and may increase the size of the semiconductor structure 110.

[0037] The backside power distribution network (BSPDN) semiconductor structure 120 according to the embodiment may include a signal line layer 125 provided to a first side (e.g., front side) of a wafer 123 and a PDN layer 121 provided in a second side (e.g., back side) opposite to the first side of the wafer 123, the signal line layer 125 provides a signal line, and the PDN layer 121 includes a power rail metal layer. The wafer 123 may include, for example, a silicon (Si) substrate, a glass substrate, a sapphire substrate, etc., but this is not restrictive.

[0038] like Figure 1 As shown in FIG. 1 , the signal line layer 125 and the PDN layer 121 are separated from each other by a wafer 123 disposed therebetween. At least one of the signal line layer 125 and the PDN layer 121 may be bonded (bonded) to or integrated with the wafer 123 according to an embodiment. Optionally, one or more intermediate layers may be disposed between at least one of the signal line layer 125 and the PDN layer 121 and the wafer 123.

[0039] The BSPDN semiconductor structure 120 may prevent (or reduce) wiring congestion in a signal line by removing the PDN layer 121 from the signal line layer 125 and reduce the size of the semiconductor structure 120 , and thus, may improve current-resistance (IR) drop.

[0040] Figure 2 and Figure 3 FIG. 1 shows a BSPDN semiconductor structure according to an embodiment. Specifically, Figure 2 is a vertical cross-sectional view of the BSPDN semiconductor structure. Figure 3 A three-dimensional (3D) perspective view of a BSPDN semiconductor structure is shown.

[0041] Reference Figure 2 , the BSPDN semiconductor structure 200 may include a wafer 210, a signal line layer 220 on a first side of the wafer 210, and a PDN layer 230 on a second side of the wafer 210 opposite to the first side. The signal line layer 220 may be, for example, an integrated circuit including constituent elements such as active devices (e.g., transistors) or signal lines for signal routing. For example, the active device may include an active pattern 227 on an active area and a source / drain pattern 225 disposed on the active pattern 227. In addition, the signal line layer 220 may include an active contact 223 extending in a horizontal direction parallel to the front side of the wafer 210 while contacting the source / drain pattern 225. The signal line layer 220 may include a power rail 222 for supplying power to the active device. The via 221 may be disposed between the power rail 222 and the active contact 223 for electrical connection between the power rail 222 and the active contact 223 .

[0042] The PDN layer 230 may include a power rail metal layer 233 on the second side of the wafer 210. The PDN layer 230 may include vias 231 disposed between the power rail metal layers 233. In addition, through silicon vias (TSVs, or “through silicon vias”) 211 penetrate the wafer 210 and extend from the PDN layer 230 to the power rail 222. The TSVs 211 may extend into the PDN layer 230.

[0043] The components included in each layer are not limited to the described components, but additional components may be included, or some components may be omitted, and the structure of the components included in each layer may be variously modified.

[0044] Figure 3 is provided to describe the power supply voltage supplied from the power rail metal layer 311 of the PDN layer 310. Figure 3 In the BSPDN semiconductor structure 300, the power rail 331 on the signal line layer 330 can be supplied with a power supply voltage from the power rail metal layer 311 of the PDN layer 310 through the TSV 321 penetrating the wafer 320. The power supply voltage provided from the power rail metal layer 311 of the PDN layer 310 along the arrow direction 340 can be used to drive the active devices in the signal line layer 330.

[0045] Figure 4 A portion of an integrated circuit formed in a signal line layer is schematically shown. Specifically, Figure 4 yes Figure 3 FIG. 4 is a top plan view of a signal line layer 330 , and also shows a layout of an integrated circuit 400 including a plurality of standard cells.

[0046] Reference Figure 4 , the integrated circuit 400 may include a plurality of power rails M1_R1, M1_R2, M1_R3, and M1_R4 extending in the X-axis direction. Each of the power rails M1_R1, M1_R2, M1_R3, and M1_R4 may be applied with a power supply voltage (e.g., VDD) or a ground voltage (e.g., VSS). For example, the power rails M1_R1 and M1_R3 may be applied with a power supply voltage VDD, and the power rails M1_R2 and M1_R4 may be applied with a ground voltage VSS.

[0047] The standard cell SC may be arranged between power rails M1_R1, M1_R2, M1_R3, and M1_R4 to which a power supply voltage and a ground voltage are applied. The standard cell may include a logic cell, a filler cell, and the like. Here, a logic cell may refer to a logic device that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.), and a filler cell may be a cell for maintaining well continuity between adjacent cells. A logic cell may include a circuit configured to perform a logic function.

[0048] The integrated circuit 400 may further include a power tap unit PTC. The power tap unit PTC may be a circuit for transferring a voltage (eg, a power supply voltage or a ground voltage) from the PDN layer 310 (see Figure 3 ) of the power rail metal layer 311 (refer to Figure 3 ) is a unit that supplies power to at least one of the power rails M1_R1, M1_R2, M1_R3, and M1_R4. Unlike the logic cell of the standard cell SC, the power tap cell PTC may not include a logic device. That is, the power tap cell PTC may be a dummy cell that performs a function of applying power to the power rails M1_R1, M1_R2, M1_R3, and M1_R4 without performing a logic function.

[0049] The power tap cell PTC may include a through silicon via region 411, which includes a through silicon via extending from the power rail metal layer 311 of the PDN layer 310 to the power rails M1_R1, M1_R2, M1_R3, and M1_R4. The through silicon via may have a column shape extending in the Z-axis direction. The power rail metal layer 311 and the power rails M1_R1, M1_R2, M1_R3, and M1_R4 may be electrically connected to each other through the through silicon via. That is, a voltage may be applied from the power rail metal layer 311 to the power rails M1_R1, M1_R2, M1_R3, and M1_R4 through the through silicon via. The power rails M1_R1, M1_R2, M1_R3, and M1_R4 may supply the voltage applied through the through silicon via to the standard cell SC.

[0050] The power tap cells PTC may be continuously laid out in the Y-axis direction and spaced apart in the X-axis direction at a regular interval D. The interval D may be predetermined to prevent power problems such as current-resistance (IR) drop from occurring in the integrated circuit 400 . Figure 4 The layout relationship between the power tap cell PTC and the standard cell SC shown in FIG. 1 is provided as an example, and the layout between the power tap cell PTC and the standard cell SC may be changed in various ways.

[0051] Figure 51 is a flowchart provided for describing a design method of a semiconductor device according to a comparative example. Specifically, Figure 5 is provided to describe a layout method of a power tap unit according to a comparative example.

[0052] The design method 500 of a semiconductor device may include a floorplan operation (S510), a placement operation (S520), a clock tree synthesis (CTS) operation (S530), a routing operation (S540), and an analysis and verification operation (S550). Figure 5 Each operation is an operation for designing a layout of a circuit and may be performed by a semiconductor design tool for designing and verifying an integrated circuit.

[0053] To briefly explain each operation, in the layout planning operation (S510), the principle circuit of the logic design may be physically designed by cutting and moving the principle circuit of the logic design. In S510, the memory or the functional block may be laid out. For example, in S510, the functional blocks that should be laid out adjacently may be identified, and the space for the functional blocks and the memory may be allocated while considering the available space and the required performance.

[0054] The layout operation (S520) according to the comparative example may include an operation for laying out the power tap cells PTC and the standard cells SC. In S520, the semiconductor design tool may lay out the power tap cells PTC at a predetermined spacing, and may lay out the standard cells SC in the remaining space after the power tap cells PTC are laid out. The semiconductor design tool may lay out the power tap cells PTC and the standard cells SC using information about the power tap cells PTC and the standard cells SC stored in the cell library 521. The information about the power tap cells PTC and the standard cells SC may include functional information, characteristic information, layout information, and the like. The semiconductor design tool may lay out the standard cells SC in consideration of the interfaces between the constituent elements in the semiconductor device. When laying out the standard cells CS, the semiconductor design tool may further consider whether the predefined design rules 551 in the relationship with the power tap cells PTC are satisfied. This will be referred to later. Figure 7 Describe in detail.

[0055] The CTS operation ( S530 ) may be an operation for generating a clock distribution network for distributing a clock signal to a group of consecutive circuit elements of a semiconductor device.

[0056] The wiring operation ( S540 ) may be an operation for generating a wiring structure including a plurality of line routes and a plurality of vias connecting the laid out standard cells SC and macros.

[0057] The analysis and verification operation (S550) may be an operation for verifying and modifying the generated layout. The verification project may include a design rule check (DRC) that verifies whether the layout satisfies the design rules 551 that may be defined by semiconductor process requirements.

[0058] Figure 6 is a top plan view of a power tap unit PTC and a standard unit SC according to a comparative example. Specifically, Figure 6 An enlarged view of a portion of a standard cell SC disposed adjacent to the power tap cell PTC after the power tap cell PTC is laid out is shown.

[0059] As previously described, according to the comparative example, the semiconductor design tool may place the standard cell SC in the space remaining after the power tap cell PTC is placed.

[0060] The power tap unit 610 and the standard unit 620 may each include first active layers 621 and 625 and second active layers 623 and 627, the first active layers 621 and 625 and the second active layers 623 and 627 corresponding to active regions, respectively. For example, the first active layers 621 and 625 may be p-type metal oxide semiconductor (PMOS) transistor (e.g., field effect transistor) regions, and the second active layers 623 and 627 may be n-type metal oxide semiconductor (NMOS) transistor (e.g., field effect transistor) regions. The first active layers 621 and 625 may be adjacent to the first power rail 641, and the second active layers 623 and 627 may be adjacent to the second power rail 643. However, compared to the active layers 625 and 627 of the standard unit 620, the active layers 621 and 623 of the power tap unit 610 may not be implemented as logic circuits. The active layers 621 and 623 of the power tap unit 610 may be used as buffers between standard cells adjacent to the power tap unit 610. The power tap unit 610 may reduce the film effect of the power tap unit 610 on the surrounding standard cells 620 through the active layers 621 and 623. The width W of the active layers 621, 623, 625, and 627 in the Y-axis direction may vary according to the channel resistance of the transistor inside the cell and the current driving capability of the cell. In this regard, the width W of the active layer may vary according to the cell characteristics.

[0061] The power tap unit 610 and the standard unit 620 may include injection layers 631 and 633. The injection layers 631 and 633 represent ion implantation regions, and the threshold voltage (Vt) of the transistor inside the unit may depend on the depth of the well formed by ion implantation or the impurity concentration of the injection layers 631 and 633. According to the threshold voltage of the internal transistor, the unit may be classified into a high voltage transistor (HVT) unit, a conventional voltage transistor (RVT) unit, and a low voltage transistor (LVT) unit, but this is not restrictive. That is, the impurity concentration or impurity type of the injection layers 631 and 633 may be different according to the unit type according to the threshold voltage of the internal transistor.

[0062] The power tap cell PTC may include through silicon via regions (Vtsv) 611 and 613 including through silicon vias overlapping power rails 641 and 643. The power rails 641 and 643 may provide a voltage applied through the through silicon vias in the through silicon via regions 611 and 613 to the standard cell 620.

[0063] According to the predefined design rules, the lengths of the through silicon via regions 611 and 613 of the power tap unit 610 in the X-axis direction need to meet a predetermined length. That is, the design rules define a minimum length rule for the through silicon via regions 611 and 613.

[0064] According to the minimum length rule for through-silicon via regions 611 and 613, the power tap unit 610 according to the comparative example may be fixed to a size of 2Ncpp (i.e., 2×N×cpp), where cpp is a contacted poly pitch and N is an integer greater than 1. The cpp unit refers to the center-to-center distance between two gates 651 and 653 that are adjacent along the X-axis. Because the size of the power tap unit 610 according to the comparative example is fixed to 2Ncpp, the lengths of the active layers 621 and 623 and the injection layer 631 in the power tap unit 610 are fixed to 2Ncpp.

[0065] According to a predetermined design rule, the length of the active layers 621, 623, 625 and 627 and the injection layers 631 and 633 needs to meet a predetermined length. That is, the design rule defines a minimum length rule for the active layers 621, 623, 625 and 627 and the injection layers 631 and 633. The minimum length of the active layers 621, 623, 625 and 627 and the injection layers 631 and 633 defined by the design rule may be Mcpp (i.e., M×cpp). Here, M may be an integer greater than 2N, but this is not restrictive. In the following, it will be assumed that M is an integer greater than 2N.

[0066] According to the cell library 521 of the comparative example (refer to Figure 5 ) can provide a power tap cell 610 of 2Ncpp size according to the minimum length rule for the length of the through silicon via regions 611 and 613. However, the minimum length according to the minimum length rule for the active layers 621 and 623 and the injection layer 631 of the power tap cell 610 is Mcpp. Therefore, in order to meet this point, the standard cell 620 arranged adjacent to the power tap cell 610 needs to include the same active layers 625 and 627 and the injection layer 633 as the active layers 621 and 623 and the injection layer 631 of the power tap cell 610.

[0067] Figure 7 is provided to describe the design rules for the power tap unit. Specifically, Figure 7 Provided to describe minimum length rules for active and injection layers in relation to standard cells placed adjacent to power tap cells.

[0068] For better understanding and ease of description, it is assumed that each power tap unit 710, 730 and 750 is adjacent to only one standard unit 720, 740 and 760, and the size of each standard unit 720, 740 and 760 is Ncpp, and the minimum length Mcpp according to the minimum length rule for the active layer and the injection layer is assumed to be 3Ncpp, but this is not restrictive.

[0069] Reference Figure 7 In part (a), the power tap unit 710 may include through-silicon via regions 712 and 714 overlapping the power rails 717 and 719, a first active layer 711 and a second active layer 713 having a first width W1 and adjacent to the power rails 717 and 719, and an injection layer 715 according to a first threshold voltage Vt1 of the internal transistor.

[0070] The standard cell 720 may be disposed adjacent to the power tap cell 710. The standard cell 720 may include first and second active layers 721 and 723 having a first width W1 and an injection layer 725 according to a first threshold voltage Vt1.

[0071] according to Figure 7 In part (a), since the power tap unit 710 and the standard unit 720 include an active layer of the same width W1 and an injection layer according to the same threshold voltage Vt1, the length (3Ncpp) of the active layer of the same width W1 and the injection layer according to the same threshold voltage Vt1 satisfies the minimum length (Mcpp) according to the minimum length rule. Therefore, the problem of design rule violation does not occur.

[0072] Reference Figure 7In part (b), compared with part (a), the standard cell 740 adjacent to the power tap unit 730 may include a first active layer 741 and a second active layer 743 of a second width W2, and the second width W2 is different from the first width W1 of the first active layer 731 and the second active layer 733. Therefore, the length (2Ncpp) of the active layers 731 and 733 of the same width W1 of the power tap unit 730 does not satisfy the minimum length (Mcpp) according to the minimum length rule, and therefore, a design rule violation occurs. Mcpp, which is the minimum length according to the minimum length rule for the active layer, is assumed to be 3Ncpp, but this is not restrictive.

[0073] The cell library needs to provide another standard cell having the same function and size as the standard cell 740 and including an active layer of the first width W1 , so that the standard cell 740 can be replaced by another standard cell having an active layer of the first width W1 .

[0074] Reference Figure 7 In part (c), compared with part (a), the standard cell 760 adjacent to the power tap unit 750 may include an injection layer 765 according to a second threshold voltage Vt2, which is different from the first threshold voltage Vt1. Therefore, the length (2Ncpp) of the injection layer 755 according to the same threshold voltage Vt1 of the power tap unit 750 does not satisfy the minimum length (Mcpp) according to the minimum length rule, and therefore, a design rule violation may occur. Mcpp, which is the minimum length according to the minimum length rule for the injection layer, is assumed to be 3Ncpp, but this is not restrictive.

[0075] The cell library needs to provide another standard cell having the same function and size as the standard cell 760 and including an implantation layer according to the first threshold voltage Vt1 , so that the standard cell 760 can be replaced by another standard cell including an implantation layer according to the first threshold voltage Vt1 .

[0076] As described above, the cell library according to the comparative example provides a power tap cell having a fixed size and a fixed layer, and the semiconductor design tool according to the comparative example lays out the standard cell after laying out the power tap cell, and therefore, there may be many restrictions on the standard cell adjacent to the power tap cell. For example, in order to meet the design rules, the standard cell adjacent to the power tap cell needs to include an active layer and an injection layer that are the same as the active layer and the injection layer of the power tap cell. In addition, the cell library needs to provide an excessive number of cell types including various active layers and various injection layers while having the same function and size for multiple standard cells.

[0077] Figure 8 1 is a flowchart for describing a design method of a semiconductor device according to an embodiment. Specifically, Figure 8 The present invention is provided to describe a layout method of a power tap unit according to an embodiment. Figure 8 Each operation in Figure 5 Descriptions that are the same or similar to those described in .

[0078] The design method 800 of the semiconductor device according to the embodiment may include a layout planning operation (S810), a layout operation (S820), a clock tree synthesis (CTS) operation (S830), a routing operation (S840), and an analysis and verification operation (S860), and may also include a sub-power tap cell (S_PTC) layout operation (S850). The sub-power tap cell S_PTC refers to a cell separated from the power tap cell of the 2Ncpp size according to the comparative example in the size of Ncpp, and the sub-power tap cell S_PTC will be referred to later. Fig.10 Describe in detail.

[0079] In the design method 800 of the semiconductor device according to the embodiment, the S_PTC layout operation (S850) can be performed separately from the layout operation (S820) of laying out the standard cells SC. For example, after all the standard cells SC are laid out, the S_PTC layout operation (S850) can be performed. Therefore, the semiconductor design tool does not need to consider the predefined design rules about the relationship between the sub-power tap unit S_PTC and the standard cell SC in the layout operation (S820) for laying out the standard cell SC.

[0080] Although it is shown in the drawing that the S_PTC layout operation (S850) is performed after the routing operation (S840), additional operations may be performed before the S_PTC layout operation (S850) is performed.

[0081] Fig. 9 Schematically shows a portion of an integrated circuit formed in a signal line layer according to an embodiment. Specifically, Fig. 9 The signal line layer 330 according to the embodiment (see Figure 3 ) is a top plan view, and is a layout operation (S820) for laying out a plurality of standard cells SC (refer to Figure 8 ) is a top plan view of the layout of the integrated circuit 900 after.

[0082] Reference Fig. 9, the integrated circuit 900 according to the embodiment may include a plurality of power rails M1_R1, M1_R2, M1_R3, and M1_R4 extending in the X-axis direction. Each of the power rails M1_R1, M1_R2, M1_R3, and M1_R4 may be applied with a positive power supply voltage (e.g., VDD) or a ground voltage (e.g., VSS). For example, the power rails M1_R1 and M1_R3 may be applied with a power supply voltage VDD, and the power rails M1_R2 and M1_R4 may be applied with a ground voltage VSS.

[0083] In the layout operation ( S820 ) according to an embodiment, the standard cell SC may be laid out between the power rails M1_R1 , M1_R2 , M1_R3 , and M1_R4 to which the positive power supply voltage and the ground voltage are applied. The standard cell may include a logic cell, a filler cell, and the like.

[0084] The integrated circuit 900 according to the embodiment may include blocking areas 921 and 923 for laying out the sub-power tap unit. The blocking areas 921 and 923 may prohibit the layout of the standard cell SC. In an embodiment, the blocking areas 921 and 923 may extend in the Y-axis direction across all rows separated by a plurality of power rails M1_R1, M1_R2, M1_R3, and M1_R4. The blocking areas 921 and 923 may be separated from each other at regular intervals D in the X-axis direction. The interval D may be a predetermined interval to prevent power problems (such as current-resistance (IR) drop) from occurring in the integrated circuit 900. The blocking areas 921 and 923 may have a size of 2Ncpp in the X-axis direction. This may be a size according to a minimum length rule for a through-silicon via region included in a power tap unit formed by a sub-power tap unit.

[0085] In the design method according to the embodiment, the sub power tap cells are laid out after the standard cells SC are laid out, so restrictions on the standard cells SC that need to be considered in relation to the power tap cells PTC when laying out the standard cells SC according to the comparative example can be reduced.

[0086] Fig.10 is a top plan view of a sub-power tap unit provided by a unit library according to an embodiment. Specifically, Fig.10 The type of sub-power tap cells provided by the cell library 1000 to satisfy the design rules associated with adjacent standard cells is shown. According to an embodiment, a power tap cell with a size of 2Ncpp can be formed by placing two sub-power tap cells with a size of Ncpp together.

[0087] Fig.10Part (a) in the figure shows sub-power tap units of Ncpp size with active layers of different widths provided by the cell library. Each sub-power tap unit may include through-silicon via regions 1011 and 1013 and active layers 1012 and 1014. The cell library 1000 may provide a sub-power tap unit including an active layer 1012 having a first width W1 and a sub-power tap unit including an active layer 1014 having a second width W2 different from the first width W1. The semiconductor design tool may select and layout sub-power tap units including active layers of the same width based on the width of the active layers of adjacent standard cells. Here, it is shown that there are two types of sub-power tap units of Ncpp size provided by the cell library according to the width of the active layer, but it is not limited thereto, but there are more types of sub-power tap units that can be stored in the cell library according to the width of the active layer of the standard cell.

[0088] Fig.10 Part (b) in the figure shows sub-power tap units of Ncpp size each including different injection layers according to the threshold voltage of the cell. Each sub-power tap unit may include through-silicon via regions 1021 and 1023 and injection layers 1022, 1032 and 1042. The cell library 1000 may provide a sub-power tap unit including a first injection layer 1022, a sub-power tap unit including a second injection layer 1032, and a sub-power tap unit including a third injection layer 1042 according to the threshold voltage of the cell. The semiconductor design tool may select and layout sub-power tap units including the same injection layer based on the injection layers of adjacent standard cells. Here, it is shown that there are three sub-power tap units of Ncpp size provided by the cell library according to the different injection layers, but it is not limited thereto, but more types of sub-power tap units may be stored in the cell library according to the different injection layers of the standard cells.

[0089] As described above, since the sub-power tap unit includes an active layer and an injection layer, the sub-power tap unit provided by the cell library 1000 may be a sub-power tap unit according to Fig.10 The active layer of part (a) and Fig.10 Combinations of various types of injection layers in part (b).

[0090] In addition, according to the minimum length rule for the length of the through-silicon via region of the power tap unit, the semiconductor design tool considers the direction (orientation) of each sub-power tap unit and lays out the sub-power tap units so that the through-silicon vias in the through-silicon via regions 1011, 1013, 1021, and 1023 contact each other. In this regard, the through-silicon via regions 1011, 1013, 1021, and 1023 of the sub-power tap units may contact each other. Through such a layout, a power tap unit of 2Ncpp size may be formed.

[0091] The cell library provides 2Ncpp-sized power tap cells with separate Ncpp-sized sub-power tap cells, thereby reducing the burden of providing too many cell types for multiple standard cells.

[0092] Fig.11 Schematically shows a portion of an integrated circuit formed in a signal line layer according to an embodiment. Specifically, Fig.11 The signal circuit layer 330 (refer to Figure 3 ) is a top plan view showing a layout of an integrated circuit 1100 in which a plurality of standard cells and a plurality of sub-power tap cells according to an embodiment are arranged.

[0093] according to Figure 8 According to the design method, after laying out a plurality of standard cells SC1 , . . . , and SC6 , the sub-power tap cells S_PTC1 , . . . , and S_PTC6 of a size of Ncpp may be laid out in a predetermined blocking area 1120 . Fig.11 An integrated circuit 1100 is shown in which a sub-power tap unit is laid out after a plurality of standard cells SC1, ..., and SC6 are laid out, and it is assumed that the plurality of standard cells SC1, ..., and SC6 all have a size of 2Ncpp, and the minimum length Mcpp according to the minimum length rule for the active layer and the injection layer is 3Ncpp, but is not limited thereto.

[0094] In the layout operation according to the embodiment ( Figure 8 In S820), a plurality of standard cells SC1, ..., and SC6 may be laid out. In order to meet the predefined design rules for the active layer and the injection layer of the sub-power tap cell S_PTC, the semiconductor design tool needs to select and lay out the sub-power tap cell S_PTC corresponding to the active layer and the injection layer of the standard cells SC1, ..., and SC6 laid out adjacent to the pre-assigned blocking area 1120.

[0095] In the first row R1, the first standard cell SC1 includes an active layer of (1111) a first width W1 and an injection layer according to a first threshold voltage Vt1, and the second standard cell SC2 may include an active layer of (1112) a first width W1 and an injection layer according to a first threshold voltage Vt1. In an embodiment, the semiconductor design tool may select a sub-power tap cell of an Ncpp size to be laid out in the blocking area 1120 based on the standard cell adjacent to the blocking area 1120. The semiconductor design tool may select the sub-power tap cell based on the width of the active layer of the standard cell adjacent to the blocking area 1120 and the injection layer according to the threshold voltage. For example, because the first standard cell SC1 includes an active layer of the first width W1 and an injection layer according to the first threshold voltage Vt1, the semiconductor design tool may select a first sub-power tap cell S_PTC1 including an active layer of the first width W1 and an injection layer according to the first threshold voltage Vt1 from among a plurality of sub-power tap cells stored in the cell library, and lay out the selected cell to be adjacent to the first standard cell SC1. In addition, because the second standard cell SC2 also includes an active layer of the first width W1 and an injection layer according to the first threshold voltage Vt1, the semiconductor design tool can select a second sub-power tap cell S_PTC2 including an active layer of the first width W1 and an injection layer according to the first threshold voltage Vt1 from among a plurality of sub-power tap cells stored in the cell library, and layout the selected cell to be adjacent to the second standard cell SC2. When the first sub-power tap cell S_PTC1 and the second sub-power tap cell S_PTC2 are laid out, the semiconductor design tool can adjust the orientation of the sub-power tap cells so that the through-silicon vias in the through-silicon via region 1110 can contact each other. Through such a layout, the sub-power tap cells S_PTC1 and S_PTC2 in the first row R1 can meet the minimum length (Mcpp) according to the minimum length rules 1151 and 1152 for the length of the active layer and the injection layer in the relationship with the adjacent standard cells SC1 and SC2. Mcpp, which is the minimum length according to the minimum length rule for the active layer and the injection layer, is assumed to be 3Ncpp, but this is not restrictive.

[0096] In the second row R2, the third standard cell SC3 includes (1113) an active layer of a first width W1 and an injection layer according to a first threshold voltage Vt1, and the fourth standard cell SC4 includes (1114) an active layer of a second width W2 different from the first width W1 and an injection layer according to the first threshold voltage Vt1. In an embodiment, the semiconductor design tool may select a sub-power tap cell of an Ncpp size to be laid out in the blocking area 1120 based on the standard cells adjacent to the blocking area 1120. The semiconductor design tool may select the sub-power tap cell based on the width of the active layer of the standard cells adjacent to the blocking area 1120 and the injection layer according to the threshold voltage. For example, because the third standard cell SC3 includes an active layer of a first width W1 and an injection layer according to a first threshold voltage Vt1, the semiconductor design tool can select a third sub-power tap cell S_PTC3 including an active layer of a first width W1 and an injection layer according to a first threshold voltage Vt1 from among a plurality of sub-power tap cells stored in the cell library, and layout the selected cell adjacent to the third standard cell SC3. In addition, because the fourth standard cell SC4 includes an active layer of a second width W2 different from the first width W1 and an injection layer according to a first threshold voltage Vt1, the semiconductor design tool can select a fourth sub-power tap cell S_PTC4 including an active layer of a second width W2 and an injection layer according to a first threshold voltage Vt1 from among a plurality of sub-power tap cells stored in the cell library, and layout the selected cell adjacent to the fourth standard cell SC4. By such a layout, the sub-power tap cells S_PTC3 and S_PTC4 in the second row R2 can satisfy the minimum length (Mcpp) according to the minimum length rules 1153 and 1154 for the active layer and the injection layer in the relationship with the adjacent standard cells SC3 and SC4. The Mcpp as the minimum length according to the minimum length rule for the active layer and the injection layer is assumed to be 3Ncpp, but this is not restrictive.

[0097] In the third row R3, the fifth standard cell SC5 may include an active layer of a second width W2 and an injection layer according to a first threshold voltage Vt1, and the sixth standard cell SC6 may include an active layer of a second width W2 and an injection layer according to a second threshold voltage Vt2 different from the first threshold voltage Vt1. In an embodiment, the semiconductor design tool may select a sub-power tap cell of Ncpp size to be laid out in the blocking area 1120 based on the standard cell adjacent to the blocking area 1120. The semiconductor design tool may select a sub-power tap cell based on the width of the active layer of the standard cell adjacent to the blocking area 1120 and the injection layer according to the threshold voltage. For example, the fifth standard cell SC5 includes (1115) an active layer of a second width W2 and an injection layer according to a first threshold voltage Vt1, and therefore, the semiconductor design tool may select a fifth sub-power tap cell S_PTC5 including an active layer of a second width W2 and an injection layer according to a first threshold voltage Vt1 from among a plurality of sub-power tap cells stored in the cell library, and lay out the selected cell to be adjacent to the fifth standard cell SC5. In addition, the sixth standard cell SC6 includes an active layer of (1116) a second width W2 and an injection layer according to a second threshold voltage Vt2 different from the first threshold voltage Vt1, and therefore, the semiconductor design tool can select a sixth sub-power tap cell S_PTC6 including an active layer of the second width W2 and an injection layer according to the second threshold voltage Vt2 from among a plurality of sub-power tap cells stored in the cell library, and layout the selected cell to be adjacent to the sixth standard cell SC6. By such a layout, the sub-power tap cells S_PTC5 and S_PTC6 in the third row R3 can satisfy the minimum length (Mcpp) according to the minimum length rules 1155 and 1156 for the active layer and the injection layer in a relationship with the adjacent standard cells SC5 and SC6. The Mcpp as the minimum length according to the minimum length rule for the active layer and the injection layer is assumed to be 3Ncpp, but this is not restrictive.

[0098] As described, the semiconductor design tool places together two sub-power tap cells of Ncpp size selected based on the standard cells adjacent to the blocking area 1120 so as to satisfy the minimum length rules for the active layer and the injection layer in relationship to the adjacent standard cells and to satisfy the minimum length rules for the through-silicon via area for the power tap cells.

[0099] The above description has been made under the assumption that all standard cells adjacent to the power tap cell are cells of 2Ncpp size. However, the standard cell may have various sizes other than 2Ncpp, and considerations when laying out the sub-power tap cells may differ depending on the size of the standard cell. Hereinafter, a case where the size of the standard cell adjacent to the power tap cell varies will be described.

[0100] Fig.12 FIG. 1 is a flow chart of a layout method 1200 of a sub-power tap unit according to an embodiment. Figure 8 , the layout of the sub-power tap cells may be performed after the layout of the standard cells is completed.

[0101] In an embodiment, the semiconductor design tool may identify adjacent standard cells on both sides of a predetermined blocking area for layout of a sub-power tap unit, and may obtain (acquire) size information of the adjacent standard cells and active layer information and injection layer information of the adjacent standard cells (S1210). As previously described, the standard cells may be laid out in an area other than the predetermined blocking area for layout of the sub-power tap unit, and the semiconductor design tool may identify the standard cells adjacent to the blocking area based on the coordinate information of the blocking area and the standard cells. The semiconductor design tool may identify the standard cells adjacent to the blocking area, and obtain (acquire) size information of the identified standard cells and information about the active layer and injection layer of the standard cells. For example, information about whether the size of the standard cells adjacent to the blocking area is greater than or equal to Mcpp, the width of the active layer of the standard cells, and the injection layer information of the standard cells according to the threshold voltage may be collected.

[0102] In an embodiment, the semiconductor design tool may select a sub-power tap cell S_PTC to be laid out in a blocking area from among a plurality of sub-power tap cells S_PTC stored in the cell library 1221 based on the collected information, and lay out the selected sub-power tap cell S_PTC (S1220). As described above with reference to the accompanying drawings, the semiconductor design tool may select a sub-power tap cell of Ncpp size from among a plurality of sub-power tap cells S_PTC stored in the cell library 1221 based on size information of adjacent standard cells and information about an active layer and an injection layer.

[0103] Fig.13 is a flowchart of a layout method 1300 of a sub-power tap unit according to an embodiment, Fig.14 Schematically shows the use of Fig.13 A layout method of a sub-power tap cell is provided to design a portion of an integrated circuit. Specifically, the drawings are provided to describe the layout method of the sub-power tap cell when at least one of the standard cells on both sides adjacent to the blocking area is greater than or equal to the Mcpp size.

[0104] In an embodiment, the semiconductor design tool may determine whether the standard cells placed on both sides adjacent to the blocking area where the sub-power tap cells are to be placed are greater than or equal to a first size (eg, Mcpp size) (S1310). Fig.14, the first row R1 of the integrated circuit 1400 may include a blocking region 1420 in which the sub-power tap cells are to be laid out and standard cells SC1 and SC2 adjacent to the blocking region 1420. The semiconductor design tool may determine whether the sizes of the standard cells SC1 and SC2 adjacent to the blocking region 1420 of the first row R1 are greater than or equal to Mcpp.

[0105] In an embodiment, based on the fact that the sizes of the standard cells SC1 and SC2 adjacent to the blocking region 1420 are both greater than or equal to Mcpp, the semiconductor design tool may select a sub-power tap cell including the same active layer and injection layer as each adjacent standard cell from among the sub-power tap cells of the Ncpp size stored in the cell library (S1320). Fig.14 , in the first row R1, when the size of the standard cells SC1 and SC2 is greater than or equal to Mcpp, the standard cell itself can meet the minimum length rule for the active layer and the injection layer. Therefore, the semiconductor design tool can select a sub-power tap cell S_PTC1 including the same layer as the active layer and the injection layer of the first standard cell SC1 and a sub-power tap cell S_PTC2 including the same layer as the active layer and the injection layer of the second standard cell SC2 from the cell library, and layout the selected cells in the blocking area 1420 to comply with the design rules for the active layer and the injection layer of the sub-power tap cells S_PTC1 and S_PTC2. Because the sub-power tap cells S_PTC1 and S_PTC2 of Ncpp size are laid out together, a power tap cell of 2Ncpp size can be formed. The lengths of the active layers and the injection layers of the sub-power tap cells S_PTC1 and S_PTC2 can meet the minimum length rule.

[0106] In an embodiment, when one of the standard cells arranged on both sides adjacent to the blocking area is smaller than the first size (e.g., Mcpp size) (i.e., smaller than the Mcpp size), the semiconductor design tool may select a sub-power tap cell including the same active layer and injection layer as the standard cell smaller than the Mcpp size (S1330). Fig.14, the second row R2 of the integrated circuit 1400 may include a blocking region 1420 in which a sub-power tap cell is to be laid out, and standard cells SC3 and SC4 adjacent to the blocking region 1420. When one standard cell SC3 among the standard cells SC3 and SC4 adjacent to the blocking region 1420 has a size smaller than the Mcpp size, the semiconductor design tool may select the sub-power tap cell to comply with the minimum length rule for the active layer and the injection layer. Therefore, the semiconductor design tool selects a sub-power tap cell S_PTC3 including a layer having the same active layer and injection layer as the standard cell SC3 having a size smaller than the Mcpp size from the cell library, and continuously lays out the selected cell in the blocking region 1420. A power tap cell of 2Ncpp size may be formed by laying out two sub-power tap cells S_PTC3 of size Ncpp together. The length of the active layer and the injection layer of the sub-power tap cell S_PTC3 may satisfy the minimum length rule, and at the same time, the length of the active layer and the injection layer of the standard cell SC3 may satisfy the minimum length rule.

[0107] Fig.15 is a flowchart of a layout method 1500 of a sub-power tap unit according to an embodiment, Fig.16 Schematically shows the use of Fig.15 A layout method of a sub-power tap cell is provided to design a portion of an integrated circuit. Specifically, the drawings are provided to describe a layout method of a sub-power tap cell when all standard cells on both sides adjacent to a blocking area where the sub-power tap cell is laid out are smaller than the Mcpp size.

[0108] In an embodiment, when all standard cells arranged on both sides adjacent to a blocking area where a sub-power tap unit is to be arranged are smaller than the Mcpp size, the semiconductor design tool may determine whether the active layers and injection layers of the standard cells arranged on both sides of the blocking area are identical to each other (S1510). In an embodiment, based on determining that the active layers and injection layers of the standard cells arranged on both sides of the blocking area are identical to each other, the semiconductor design tool may select a sub-power tap unit whose active layer and injection layer are identical to the active layer and injection layer of an adjacent standard cell from among the sub-power tap units of the Ncpp size stored in the cell library (S1520). Refer to Fig.16, the first row R1 of the integrated circuit 1600 may include a blocking region 1620 in which a sub-power tap unit is to be laid out and standard cells SC1 and SC2 disposed adjacent to the blocking region 1620. The semiconductor design tool may determine whether the active layers and injection layers of the standard cells SC1 and SC2 adjacent to the blocking region 1620 of the first row R1 are identical to each other. When the active layers and injection layers of the standard cells SC1 and SC2 adjacent to the blocking region 1620 are identical to each other, the semiconductor design tool may select a sub-power tap unit S_PTC1 whose active layers and injection layers are identical to those of the adjacent standard cells SC1 and SC2, and continuously lay out the selected unit in the blocking region 1620. A power tap unit of 2Ncpp size may be formed by laying out two sub-power tap units S_PTC1 of Ncpp size. The lengths of the active layers and injection layers of the sub-power tap unit S_PTC1 may satisfy the minimum length rule.

[0109] In an embodiment, based on determining that the active layers and injection layers of the standard cells SC1 and SC2 adjacent to the blocking area 1620 are different from each other, the semiconductor design tool may determine whether the size of the standard cells arranged on both sides exceeds Ncpp (S1530). In an embodiment, based on determining that the size of the standard cells arranged on both sides of the blocking area exceeds Ncpp, the semiconductor design tool may select a sub-power tap cell whose active layer and injection layer are the same as the active layer and injection layer of the adjacent standard cell from the sub-power tap cells of the Ncpp size stored in the cell library (S1520). Fig.16 , when it is determined that the active layers and / or injection layers of the standard cells SC3 and SC4 adjacent to the blocking region 1620 of the second row R2 of the integrated circuit 1600 are different from each other, and the sizes of the standard cells SC3 and SC4 are a second size different from the first size (for example, the size is a 2Ncpp size; that is, the sizes of the standard cells SC3 and SC4 each exceed Ncpp), the semiconductor design tool may select and layout sub-power tap cells S_PTC3 and S_PTC4 having the same active layer and injection layer as the respective adjacent standard cells. For example, the semiconductor design tool may select a sub-power tap cell S_PTC3 including a layer identical to that of the third standard cell SC3 and a sub-power tap cell S_PTC4 including a layer identical to that of the fourth standard cell SC4 from the cell library, and layout the selected cells in the blocking region 1620. A power tap cell of 2Ncpp size may be formed by laying out the sub-power tap cells S_PTC3 and S_PTC4 of Ncpp size together. The lengths of the active layers and the injection layers of the sub-power tap units S_PTC3 and S_PTC4 may satisfy the minimum length rule.

[0110] In an embodiment, when at least one of the standard cells adjacent to the blocking area has a third size (e.g., Ncpp size) different from the second size, the semiconductor design tool may determine whether the standard cell adjacent to the blocking area violates the design rules for the active layer and the injection layer in a relationship with the standard cells arranged adjacent to the blocking area in the opposite direction (e.g., the standard cells arranged adjacent to the standard cells in a direction opposite to the blocking area) (S1540). In an embodiment, based on determining that the standard cell adjacent to the blocking area satisfies the design rules for the active layer and the injection layer in a relationship with the standard cells arranged adjacent to the blocking area in the opposite direction, the semiconductor design tool may select a sub-power tap cell having the same active layer and injection layer as those of each adjacent standard cell (S1520). In an embodiment, based on determining that one of the standard cells adjacent to the blocking area violates the design rules for the active layer and the injection layer in a relationship with the standard cells arranged adjacent to the blocking area in the opposite direction, the semiconductor design tool may select a sub-power tap cell containing the same layer as the layer of the standard cell that violates the design rule (S1550). Refer to Fig.16 , in the third row R3, one standard cell SC5 among the standard cells SC5 and SC6 adjacent to the blocking region 1620 may have an Ncpp size. In this case, the semiconductor design tool may determine whether the standard cells SC5 and SC6 adjacent to the blocking region 1620 violate the design rules for the active layer and the injection layer in the relationship with the standard cells SC7 and SC8 disposed adjacent to the blocking region 1620 in the opposite direction. When one standard cell SC5 among the standard cells SC5 and SC6 adjacent to the blocking region 1620 violates the design rules in the relationship with the other adjacent standard cell SC7, the semiconductor design tool may select a sub-power tap cell S_PTC5 containing the same layer as the active layer and the injection layer of the standard cell SC5 from the cell library, and continuously layout the selected cell in the blocking region 1620. A power tap cell of 2Ncpp size may be formed by laying out two sub-power tap cells S_PTC5 of Ncpp size. The lengths of the active layer and the injection layer of the standard cell SC5 and the sub-power tap cell S_PTC3 may satisfy the minimum length rule.

[0111] Fig.17 A design system for a semiconductor device according to an embodiment is schematically shown.

[0112] The design system 1700 may include a storage device 1710 , a design module 1730 , a processor 1750 , and an analysis module 1770 . Fig.17 The design system 1700 can perform reference Figures 8 to 16The design method of a semiconductor device describes at least a portion of the design operation of the semiconductor device. The design system 1700 may be implemented as an integrated device and may therefore be referred to as a design device. The design system 1700 may be configured as a dedicated device for designing an integrated circuit of a semiconductor device, but may also be a computer for running various simulation tools or design tools.

[0113] The storage device 1710 according to an embodiment may include a standard cell library 1711, a sub-power tap cell library 1713, and a design rule 1715. In an embodiment, the sub-power tap cell library 1713 may store information about a sub-power tap cell of an Ncpp size. In an embodiment, the sub-power tap cell library 1713 may store sub-power tap cells including active layers of various widths and various injection layers. The standard cell library 1711, the sub-power tap cell library 1713, and the design rule 1715 may be provided from the storage device 1710 to the design module 1730 and the analysis module 1770. The number of cell libraries included in the storage device 1710 may be changed in various ways.

[0114] The design module 1730 according to the embodiment may receive the standard cell library 1711, the sub-power tap cell library 1713, and the design rule 1715 from the storage device 1710, and perform the above-mentioned Figures 8 to 16 In an embodiment, the design module 1730 may perform batch operations for standard cells using the standard cell library 1711, and then perform batch operations for sub-power tap cells using the sub-power tap cell library 1713. Here, the term "module" may refer to hardware, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or a combination thereof.

[0115] The processor 1750 may be used by the design module 1730 and the analysis module 1770 to perform calculations. For example, the processor 1750 may include a microprocessor, an application processor (AP), a digital signal processor (DSP), a graphics processing unit (GPU), etc. Fig.17 In the embodiment, only one processor 1750 is shown, but according to an embodiment, the design system 1700 may include a plurality of processors. The processor 1750 may include a cache memory for improving computing performance.

[0116] In execution Figures 8 to 16 During or after a design operation of a semiconductor device of the present invention, an analysis module (i.e., analyzer) 1770 may perform analysis and verification of a layout generated by the design module 1730. In an embodiment, the analysis module 1770 may analyze and verify whether a layer included in a standard cell and a power tap cell satisfies a design rule based on a design rule 1715 received from the storage device 1710.

[0117] While aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor integrated circuit, the semiconductor integrated circuit comprising a first region and a remaining region other than the first region, the method for manufacturing the semiconductor integrated circuit comprising the following steps: Place standard cells in the remaining area; generating a wiring structure connecting the standard cells; placing the sub-power tap units in the first region based on predefined design rules; as well as Verify that sub-power tap cells and standard cells comply with predefined design rules.

2. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein: The step of placing the sub-power tap units in the first area includes: identifying a first standard cell and a second standard cell arranged adjacent to a first region in a first row among a plurality of rows of the semiconductor integrated circuit; Acquire first layer information and second layer information of the first standard unit and the second standard unit; The sub-power tap cells stored in the cell library are selected and arranged based on the first layer information and the second layer information.

3. The method for manufacturing a semiconductor integrated circuit according to claim 2, wherein: The steps of selecting and arranging the sub-power tap units stored in the unit library based on the first layer information and the second layer information include: Among the sub-power tap cells stored in the cell library, selecting a first sub-power tap cell including a first layer corresponding to the first layer of the first standard cell and a second layer corresponding to the second layer of the first standard cell; selecting a second sub-power tap cell including a first layer corresponding to the first layer of the second standard cell and a second layer corresponding to the second layer of the second standard cell; and A first sub power tap cell is arranged in the first region adjacent to the first standard cell, and a second sub power tap cell is arranged in the first region adjacent to the second standard cell.

4. The method for manufacturing a semiconductor integrated circuit according to claim 3, wherein: The first sub-power tap unit and the second sub-power tap unit each further include a via region, the via region including a through-silicon via, and Among them, the steps of placing the first sub-power tap unit adjacent to the first standard unit in the first area and placing the second sub-power tap unit adjacent to the second standard unit in the first area include: controlling the orientation of the first sub-power tap unit and the second sub-power tap unit so that the corresponding via areas of the first sub-power tap unit and the second sub-power tap unit are in contact with each other.

5. The method for manufacturing a semiconductor integrated circuit according to claim 3, wherein: The first sub power tap unit and the second sub power tap unit form one power tap unit.

6. The method for manufacturing a semiconductor integrated circuit according to claim 2, wherein: The predefined design rule is a minimum length rule for the length of the first layer and the length of the second layer.

7. The method for manufacturing a semiconductor integrated circuit according to claim 2, wherein: The step of identifying the first standard cell and the second standard cell arranged adjacent to the first region includes obtaining size information of the first standard cell and size information of the second standard cell.

8. The method for manufacturing a semiconductor integrated circuit according to claim 7, further comprising: On the basis that the first standard cell and the second standard cell are both smaller than the first size along the first direction, determining whether a first layer of the first standard cell and a first layer of the second standard cell are identical to each other and whether a second layer of the first standard cell and a second layer of the second standard cell are identical to each other; Determining whether a size of one of the first standard cell and the second standard cell is a second size different from the first size along the first direction, based on the first layer of the first standard cell and the first layer of the second standard cell being different from each other and the second layer of the first standard cell and the second layer of the second standard cell being different from each other; as well as On the basis that the first standard cell has a second size along the first direction, it is determined whether the first standard cell and the third standard cell meet the predefined design rule, the third standard cell being adjacent to the first standard cell in a direction facing away from the first region.

9. The method for manufacturing a semiconductor integrated circuit according to claim 8, further comprising: On the basis that the first layer of the first standard cell and the first layer of the second standard cell are identical to each other and the second layer of the first standard cell and the second layer of the second standard cell are identical to each other, a sub-power tap cell including a layer corresponding to the layer of the first layer of the first standard cell and the second standard cell and a layer corresponding to the layer of the second layer of the first standard cell and the second standard cell is selected from the sub-power tap cells stored in the cell library.

10. The method for manufacturing a semiconductor integrated circuit according to claim 9, further comprising: The selected sub-power tap cells are continuously laid out in a first area corresponding to a first row.

11. The method for manufacturing a semiconductor integrated circuit according to claim 8, further comprising: On the basis that the first layer of the first standard cell is different from the first layer of the second standard cell, the second layer of the first standard cell is different from the second layer of the second standard cell, and the first standard cell and the second standard cell both have a third size different from the second size along the first direction, Among the sub-power tap cells stored in the cell library, selecting a first sub-power tap cell including a first layer corresponding to the first layer of the first standard cell and a second layer corresponding to the second layer of the first standard cell; selecting a second sub-power tap cell including a first layer corresponding to the second layer of the second standard cell and a second layer corresponding to the first layer of the second standard cell; and The first sub power tap cell is arranged in the first region adjacent to the first standard cell, and the second sub power tap cell is arranged in the first region adjacent to the second standard cell.

12. The method for manufacturing a semiconductor integrated circuit according to claim 8, further comprising: On the basis that the first standard cell and the third standard cell violate the predefined design rule, a sub power tap cell including layers corresponding to the first and second layers of the first standard cell is selected from among the sub power tap cells stored in the cell library.

13. The method for manufacturing a semiconductor integrated circuit according to any one of claims 1 to 12, wherein: The sub-power tap unit has a size of 1 contact poly pitch.

14. A semiconductor integrated circuit, comprising: a first power rail extending in a first direction; a second power rail extending in the first direction and spaced apart from the first power rail in a second direction intersecting the first direction; A first standard cell is located between the first power rail and the second power rail; as well as A first power tap unit is adjacent to the first standard unit in a first direction and includes a first region and a second region, the first region includes a first via hole electrically connecting the external power line and the first power rail and a first active layer having a first width in the second direction, and the second region includes a second via hole electrically connecting the external power line and the second power rail and a second active layer having a second width different from the first width in the second direction.

15. The semiconductor integrated circuit according to claim 14, wherein: The first active layer and the second active layer have the same length in the first direction.

16. The semiconductor integrated circuit according to claim 14, wherein: The first standard cell includes an active layer having a first width in a second direction. 17 . The semiconductor integrated circuit of claim 16 , further comprising a second standard cell located between the first power rail and the second power rail, the second standard cell including an active layer having a second width in the second direction and adjacent to the first power tap cell in the first direction.

18. The semiconductor integrated circuit according to claim 14, wherein: A length of the first region in the first direction and a length of the second region in the first direction satisfy a minimum length rule according to a predefined design rule. 19 . The semiconductor integrated circuit according to claim 14 , further comprising a second power tapping unit spaced apart from the first power tapping unit by a predetermined distance in the first direction.

20. A semiconductor device, comprising: substrate; a first layer located on a first side of the substrate and comprising a power distribution network; as well as A second layer is located on a second side of the substrate and includes: a first power rail extending in a first direction; a first through-silicon via extending in a second direction from a power distribution network through the substrate to the first power rail and having a first length in the first direction, the second direction intersecting the first direction; and a second through-silicon via contacting the first through-silicon via, being adjacent to the first through-silicon via in the first direction, extending in a second direction from the power distribution network through the substrate to the first power rail, and having a first length in the first direction.

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