Verification method of data extraction module, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a verification method of a data extraction module, electronic equipment and a medium, and the method comprises the following steps: S1, reading to-be-tested chip data output by the data extraction module from a memory, and generating first chip text data according to a preset data structure; s2, acquiring standard chip data output by a checker corresponding to the read data extraction module, and generating second chip text data according to a preset data structure; s3, executing one or more of comparison of different domain segments in the EAim, comparison of different EAim in the LAm and comparison of different LAm, if all the comparison passes, executing the step S4, otherwise, determining that verification is not passed, and ending the process; and S4, comparing the first chip text data with the second chip text data, if the comparison is passed, determining that the verification is passed, otherwise, determining that the verification is not passed, and ending the process. According to the invention, the data extraction module can be accurately verified.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a verification method, electronic equipment and medium for a data extraction module. Background Art

[0002] Existing post-silicon performance test analysis usually obtains chip data by reading chip registers, which has the disadvantages of long reading time and few types of information obtained. Therefore, a data extraction module can be set up to extract performance parameters of the chip in real time during operation, and write them into the memory in a preset format. The preset format is set as a key (token), for example. The software directly reads the memory, and a large amount of chip performance data can be read out simply and efficiently, greatly improving the efficiency of post-silicon performance testing. Setting up the data extraction module also requires verification of the data extraction module.

[0003] However, the existing verification method is to directly compare the result of the design under test (DUT) with the expected result of the checker (model), while the data extraction module outputs data in a preset format, and the timing of the checker cannot strictly correspond to the timing of the data extraction module, so it is impossible to achieve a bit-by-bit comparison between the data output by the data extraction module and the data output by the checker. It can be seen that the existing verification method cannot check the correctness of the data output by the data extraction module, and thus cannot achieve verification of the data extraction module. It can be seen that how to provide a technology that can accurately verify the data extraction module has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The object of the present invention is to provide a data extraction module verification method, electronic equipment and medium, which can realize accurate verification of the data extraction module.

[0005] According to a first aspect of the present invention, a verification method for a data extraction module is provided, comprising: Step S1: read the chip data to be tested output by the data extraction module from the memory, and generate the first chip text data {LA 1 ,LA 2 ,...,LA m ,...,LA M}, L.A. m is the data list of the mth type of chip to be tested, the value range of m is 1 to M, M is the total number of chip data types to be tested, LA m ={EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m},EAi m For LA m The i-th text data to be tested in EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m Arranged in the order of generation, the value range of i is 1 to f(m), f(m) is LA m The total number of text data to be tested in EA i m ={HA 1 im ,HA 2 im ,....,HA j im ,...,HA g(m) im}, HA j im For EA i m The jth domain in the , j ranges from 1 to g(m), g(m) is LA m The total number of domain segments into which the text data to be tested is divided; Step S2, obtain the standard chip data output by the checker corresponding to the read data extraction module, and generate the second chip text data {LB 1 ,LB 2 ,...,LB n ,...,LB N}, LB n is the data list of the nth type of standard chip, the value range of n is 1 to N, N is the total number of standard chip data types, LB n ={EB 1 n ,EB 2 n ,...,EB k n ,...,EB p(n) n}, EB k n For LB n The kth standard text data in the , k ranges from 1 to p(n), p(n) is LB m Total number of standard text data in EB 1 n ,EB 2 n ,...,EBk n ,...,EB p(n) n Arranged in the order of generation, EB k n ={HB 1 kn ,HB 2 kn ,....,HB r kn ,...,HB q(n) kn}, HB r kn EB k n The rth domain in the , r ranges from 1 to q(n), q(n) is LB m The total number of domain segments divided by the standard text data in the test data and the standard text data have the same length; Step S3: 1 ,LA 2 ,...,LA m ,...,LA M}Execute EA i m Comparison of different domains in LA m Different EAs in i m Comparison and Different LA m If all the comparisons are passed, step S4 is executed; otherwise, it is determined that the data extraction module verification fails and the process ends; Step S4: Compare {LA 1 ,LA 2 ,...,LA m ,...,LA M} and {LB 1 ,LB 2 ,...,LB n ,...,LB N}, if the comparison passes, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has failed and the process ends.

[0006] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions to be executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0007] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0008] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the verification method, electronic device and medium of a data extraction module provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects: The present invention first stores the chip data to be tested output by the data extraction module into the memory, then generates the first chip text data according to the preset data structure, and generates the second chip text data with the same data structure, and then performs the comparison of different domain segments in the same text data to be tested, the comparison of different text data to be tested, the comparison of different chip data lists to be tested, and the overall comparison of the first chip text data and the second chip text data on the first chip text data, thereby realizing the bit-by-bit comparison of the data output by the data extraction module and the data output by the checker, thereby realizing the accurate verification of the data extraction module. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 A flow chart of a verification method for a data extraction module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0012] The embodiment of the present invention provides a verification method for a data extraction module, such as Figure 1 As shown, including: Step S1: read the chip data to be tested output by the data extraction module from the memory, and generate the first chip text data {LA 1 ,LA 2 ,...,LA m ,...,LA M}, L.A. mis the data list of the mth type of chip to be tested, the value range of m is 1 to M, M is the total number of chip data types to be tested, LA m ={EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m},EA i m For LA m The i-th text data to be tested in EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m Arranged in the order of generation, the value range of i is 1 to f(m), f(m) is LA m The total number of text data to be tested in EA i m ={HA 1 im ,HA 2 im ,....,HA j im ,...,HA g(m) im}, HA j im For EA i m The jth domain in the , j ranges from 1 to g(m), g(m) is LA m The total number of domain segments into which the text data to be tested is divided.

[0013] The data extraction module is used to extract the chip data to be tested from the chip. For example, the chip may be a GPU chip, and the chip data to be tested may be performance parameters during the operation of the chip. The preset data structure divides the chip data to be tested into different hierarchical structures for storage.

[0014] Step S2, obtain the standard chip data output by the checker corresponding to the read data extraction module, and generate the second chip text data {LB 1 ,LB 2 ,...,LB n ,...,LB N}, LB nis the data list of the nth type of standard chip, the value range of n is 1 to N, N is the total number of standard chip data types, LB n ={EB 1 n ,EB 2 n ,...,EB k n ,...,EB p(n) n}, EB k n For LB n The kth standard text data in the , k ranges from 1 to p(n), p(n) is LB m Total number of standard text data in EB 1 n ,EB 2 n ,...,EB k n ,...,EB p(n) n Arranged in the order of generation, EB k n ={HB 1 kn ,HB 2 kn ,....,HB r kn ,...,HB q(n) kn}, HB r kn EB k n The rth domain in the , r ranges from 1 to q(n), q(n) is LB m The total number of domain segments divided by the standard text data in the test data and the length of the standard text data are the same.

[0015] It should be noted that the checker can be specifically set as a model generated based on a high-level language, and the data output by the checker is standard chip data. The standard chip data is also stored in the same preset data structure as the chip data to be tested, and is also divided into different hierarchical structures for subsequent comparison.

[0016] Step S3: 1 ,LA 2 ,...,LA m ,...,LA M}Execute EA i m Comparison of different domains in LA m Different EAs in im Comparison and Different LA m If all the comparisons are passed, step S4 is executed; otherwise, it is determined that the data extraction module verification fails and the process ends.

[0017] It should be noted that based on different hierarchical structures, by executing EA i m Comparison of different domains in LA m Different EAs in i m Comparison and Different LA m One or more of the comparisons can achieve bit-by-bit comparison to verify the data extraction module.

[0018] Step S4: Compare {LA 1 ,LA 2 ,...,LA m ,...,LA M} and {LB 1 ,LB 2 ,...,LB n ,...,LB N}, if the comparison passes, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has failed and the process ends.

[0019] As an embodiment, the step S1 includes: Step S11: Obtain the chip data to be tested through the data extraction module and store it in the memory.

[0020] Step S12: reading the chip data to be tested from the starting address of the chip data to be tested in the memory, and storing it in the form of an X-bit array.

[0021] Step S13: Combine Y arrays to generate EA i m , and store them in the corresponding LA in the order of generation m In the final generation, {LA 1 ,LA 2 ,...,LA m ,...,LA M}.

[0022] Among them, X can be set to 32 bits, Y can be set to 2, then EA i m The corresponding length is 64 bits. However, it is understandable that the specific data of X and Y can be adjusted according to application requirements.

[0023] As an embodiment, in step S3, {LA 1,LA 2 ,...,LA m ,...,LA M}Execute EA i m The method comprises comparing different domain segments in the embodiment of the present invention, comprising at least one of step S31 and step S32: Step S31, determine EA i m HA e im The corresponding designated bit and HA d im Whether the corresponding designated bit meets the consistency matching condition. The value range of e is 1 to g(m), the value range of d is 1 to g(m), and e≠g.

[0024] It should be noted that the consistency matching condition can be specifically set to: HA e im When the corresponding designated bit is 1, HA d im The corresponding designated bit is also 1, or is set to: HA e im When the corresponding designated bit is 0, HA d im The corresponding designated bit is also 0.

[0025] Step S32: Determine EA i m HA s im The corresponding designated bit and HA v im Whether the corresponding specified bit meets the mutually exclusive matching condition. The value range of s is 1 to g(m), the value range of v is 1 to g(m), s≠v.

[0026] It should be noted that the mutually exclusive matching condition can be specifically set to: HA e im When the corresponding designated bit is 1, HA d im The corresponding designated bit is also 0, or is set to: HA e im When the corresponding designated bit is 0, HA d im The corresponding designated bit is also 1.

[0027] Among them, HA e im The corresponding designated bit can be one or more bits, HA d im The corresponding designated bit can be one or more bits, HA eim The corresponding designated bit and HA d im The number of corresponding designated bits can be the same or different, and can be flexibly set according to application requirements. e im and HA d im Can be used for EA i m The adjacent domain segment can also be EA i m Non-adjacent domain segments.

[0028] As an embodiment, in step S3, {LA 1 ,LA 2 ,...,LA m ,...,LA M}Execute LA m Different EAs in i m Comparisons include: Step S33: Determine EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m Each EA in i m Is the axth field segment in accordance with EA 1 m ,EA 2 m ,...,EA i m ,...,EA f(m) m The order of increasing, decreasing, remaining consistent, or wrapping back is as follows, and ax is a value between 1 and g(m).

[0029] It should be noted that one or more LAs can be m Step S33 is executed and set according to specific application requirements. Rollback refers to rolling back when increasing to a certain value, or rolling back when decreasing to a certain value.

[0030] As an embodiment, in step S3, {LA 1 ,LA 2 ,...,LA m ,...,LA M}Execute different LA m Comparisons include: Step S34: Determine LAu and LA z Whether there is data with a preset mapping relationship and the same number.

[0031] It should be noted that the preset mapping relationship and corresponding data are set according to specific application requirements.

[0032] As an embodiment, step S4 includes: Step S41: Determine {LA 1 ,LA 2 ,...,LA m ,...,LA M The total number of text data to be tested in {LB 1 ,LB 2 ,...,LB n ,...,LB N} is consistent, if so, execute step S42, otherwise, determine that the data extraction module verification fails and end the process.

[0033] It should be noted that due to {LA 1 ,LA 2 ,...,LA m ,...,LA M} and {LB 1 ,LB 2 ,...,LB n ,...,LB N} is generated based on the same preset data structure, so {LA 1 ,LA 2 ,...,LA m ,...,LA M The total number of text data to be tested in {LB 1 ,LB 2 ,...,LB n ,...,LB N In some application scenarios, the generation order of the text data to be tested needs to be strictly consistent with the generation order of the standard text data, and in some application scenarios, the generation order of the text data to be tested does not need to be strictly consistent with the generation order of the standard text data, so it is necessary to continue to further judge according to the situation in step S42.

[0034] Step S42: If the verification requirement of the data extraction module is sequential consistency, execute step S43; if the verification requirement of the data extraction module is random consistency, execute step S44.

[0035] Step S43, determine {LA 1 ,LA 2,...,LA m ,...,LA M} in the text data to be tested and {LB 1 ,LB 2 ,...,LB n ,...,LB N} to determine whether the order of the text data to be tested is consistent. If so, it is determined that the data extraction module verification has passed. Otherwise, it is determined that the data extraction module verification has failed and the process ends.

[0036] It should be noted that step S43 can be specifically performed by sequentially determining each EB k n and every EB k n Whether the corresponding information is consistent to determine {LA 1 ,LA 2 ,...,LA m ,...,LA M} in the text data to be tested and {LB 1 ,LB 2 ,...,LB n ,...,LB N} to check whether the sorting of the text data to be tested is consistent.

[0037] Step S44, {LB 1 ,LB 2 ,...,LB n ,...,LB N} whether each EA in the judgment exists i m Corresponding EB k n If both exist, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has failed and the process ends.

[0038] It should be noted that step S44 can specifically determine each EA in turn. i m In {LB 1 ,LB 2 ,...,LB n ,...,LB N} whether there is a corresponding EB k n , it only needs to exist, and there is no need to ensure the order consistency.

[0039] During the information comparison process, some fields contain information that does not need to be compared. In order to improve the comparison efficiency and reduce errors during the comparison process, the corresponding bits may be masked before the comparison. As an embodiment, the steps S2 and S3 further include: Step S10: In EA i m Set the mask on the preset mask position of EA i m Corresponding EB k n A mask is set on the preset mask bit, and the bit of the mask is set to 0 during the comparison process of step S3 and step S4.

[0040] It should be noted that some domains are used to represent timestamps, but due to the limitation of the checker timing when comparing with the checker, it is impossible to compare based on timing, so the bit corresponding to the timestamp can be directly masked, so the preset masking bit can be set to the bit corresponding to the timestamp. In addition, some identifiers are randomly generated, and there will be inconsistencies when comparing, but it is not an abnormal situation. Therefore, such identifiers can be set as preset identifiers, and then the bits corresponding to the preset identifier information can be set as masking bits.

[0041] It should be noted that, in order to realize the reuse of the comparison strategy, the relevant bits can also be masked in step S10 to realize the reuse of the comparison strategy. The comparison strategy is a comparison process determined based on step S3 and step S4.

[0042] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0043] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0044] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0045] The embodiment of the present invention first stores the chip data to be tested output by the data extraction module into the memory, then generates the first chip text data according to the preset data structure, and generates the second chip text data with the same data structure, and then performs the comparison of different domain segments in the same text data to be tested, the comparison of different text data to be tested, the comparison of different chip data lists to be tested, and the overall comparison of the first chip text data and the second chip text data on the first chip text data, thereby realizing the bit-by-bit comparison of the data output by the data extraction module and the data output by the checker, thereby realizing the accurate verification of the data extraction module.

[0046] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A verification method for a data extraction module, characterized in that: include: Step S1, read the chip data to be tested output by the data extraction module from the memory, and generate the first chip text data {LA1, LA2, ..., LA m ,...,LA M }, L.A. m is the data list of the mth type of chip to be tested, the value range of m is 1 to M, M is the total number of chip data types to be tested, LA m ={EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m },EA i m For LA m The i-th text data to be tested in EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m Arranged in the order of generation, the value range of i is 1 to f(m), f(m) is LA m The total number of text data to be tested in EA i m ={HA1 im ,HA2 im ,....,HA j im ,...,HA g(m) im }, HA j im For EA i m The jth domain in the , j ranges from 1 to g(m), g(m) is LA m The total number of domain segments into which the text data to be tested is divided; Step S2, obtain the standard chip data output by the checker corresponding to the read data extraction module, and generate the second chip text data {LB1, LB2, ..., LB n ,...,LB N }, LB n is the data list of the nth type of standard chip, the value range of n is 1 to N, N is the total number of standard chip data types, LB n ={EB1 n ,EB2 n ,...,EB k n ,...,EB p(n) n }, EB k n For LB n The kth standard text data in the , k ranges from 1 to p(n), p(n) is LB m Total number of standard text data in EB1 n ,EB2 n ,...,EB k n ,...,EB p(n) n Arranged in the order of generation, EB k n ={HB1 kn ,HB2 kn ,....,HB r kn ,...,HB q(n) kn }, HB r kn EB k n The rth domain in the , r ranges from 1 to q(n), q(n) is LB m The total number of domain segments divided by the standard text data in the test data and the standard text data have the same length; Step S3: {LA1, LA2, ..., LA m ,...,LA M }Execute EA i m Comparison of different domains in LA m Different EAs in i m Comparison and Different LA m If all the comparisons are passed, step S4 is executed; otherwise, it is determined that the data extraction module verification fails and the process ends; Step S4: Compare {LA1, LA2, ..., LA m ,...,LA M } and {LB1,LB2,...,LB n ,...,LB N }, if the comparison passes, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has failed and the process ends.

2. The method according to claim 1, characterized in that The step S1 comprises: Step S11, obtaining the chip data to be tested through the data extraction module and storing it in the memory; Step S12, reading the chip data to be tested from the starting address of the chip data to be tested in the memory, and storing it in the form of an X-bit array; Step S13: Combine Y arrays to generate EA i m , and store them in the corresponding LA in the order of generation m In the final generation, {LA1,LA2,...,LA m ,...,LA M }.

3. The method according to claim 1, characterized in that In step S3, {LA1, LA2, ..., LA m ,...,LA M }Execute EA i m The method comprises comparing different domain segments in the embodiment of the present invention, comprising at least one of step S31 and step S32: Step S31, determine EA i m HA e im The corresponding designated bit and HA d im Whether the corresponding designated bit meets the consistency matching condition, the value range of e is 1 to g(m), the value range of d is 1 to g(m), e≠g; Step S32: Determine EA i m HA s im The corresponding designated bit and HA v im Whether the corresponding specified bit meets the mutually exclusive matching condition. The value range of s is 1 to g(m), the value range of v is 1 to g(m), s≠v.

4. The method according to claim 1, characterized in that: In step S3, {LA1, LA2, ..., LA m ,...,LA M }Execute LA m Different EAs in i m Comparisons include: Step S33, determine EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m Each EA in i m Is the axth field segment in accordance with EA1 m ,EA2 m ,...,EA i m ,...,EA f(m) m The order of increasing, decreasing, remaining consistent, or wrapping back is as follows, and ax is a value between 1 and g(m).

5. The method according to claim 1, characterized in that In step S3, {LA1, LA2, ..., LA m ,...,LA M }Execute different LA m Comparisons include: Step S34: Determine LA u and LA z Whether there is data with a preset mapping relationship and the same number.

6. The method according to claim 1, characterized in that The step S4 comprises: Step S41: Determine {LA1, LA2, ..., LA m ,...,LA M } and the total number of text data to be tested in {LB1,LB2,...,LB n ,...,LB N } is consistent, if it is consistent, then execute step S42, otherwise, determine that the data extraction module verification fails, and end the process; Step S42: If the verification requirement of the data extraction module is sequential consistency, then execute step S43; if the verification requirement of the data extraction module is random consistency, then execute step S44; Step S43: Determine {LA1, LA2, ..., LA m ,...,LA M } and the order of the text data to be tested in {LB1,LB2,...,LB n ,...,LB N } whether the order of the text data to be tested is consistent, if it is consistent, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has not passed, and the process ends; Step S44, {LB1, LB2, ..., LB n ,...,LB N } whether each EA in the judgment exists i m Corresponding EB k n If both exist, it is determined that the data extraction module verification has passed, otherwise, it is determined that the data extraction module verification has failed and the process ends.

7. The method according to claim 1, characterized in that The steps S2 and S3 also include: Step S10: In EA i m Set the mask on the preset mask position of EA i m Corresponding EB k n A mask is set on the preset mask bit, and the bit of the mask is set to 0 during the comparison process of step S3 and step S4.

8. The method according to claim 1, characterized in that The preset masking bit is a bit corresponding to the timestamp or a bit corresponding to the preset identification information.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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