Multi-die test method based on simulation platform, electronic equipment and storage medium

Abstract

The invention relates to the technical field of chip design, in particular to a multi-die test method based on a simulation platform, electronic equipment and a storage medium, and the method comprises the steps: obtaining a test template which comprises a basic template with interconnection ports between dies configured to be fully interconnected and a topological structure table; each topological structure in the topological structure table is configured with an identity identifier topoid, and a plurality of interconnection structures in each topological structure are respectively configured with a corresponding identity identifier socket; a compiler compiles the test template to obtain a template database; and the user specifies a target interconnection structure to be tested according to the topoid and the socket, and the simulator tests the interconnection relationship in the target interconnection structure. Compared with the prior art, the scheme provided by the invention only needs to generate the template database through the compiling step, does not need to compile when testing various different interconnection structures, and greatly shortens the verification period.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a multi-die testing method based on a simulation platform, an electronic device and a storage medium. Background Art

[0002] In the complex process of chip design and verification, it is crucial to ensure that the connection relationship between all dies (bare chips) in the topology is fully verified. However, the current simulation platform can only test the interface connectivity between two dies at a time. In order to fully verify the entire topology, multiple compilation and testing cycles must be performed.

[0003] In this process, different parts of the tool chain have specific tasks: The synthesis tool is used to convert the hardware description language code into a netlist. The compiler is used to compile the netlist and other design files into a database (DB) that can run on the simulation platform. The emulator is used to apply stimulus signals using the compiled database, simulate actual working conditions, and collect test data for analysis. Due to the diversity of interfaces between different dies, recompilation is indeed required when the test object is changed, which may cause each compilation to take up to dozens of hours or even longer, significantly extending the overall verification cycle. Therefore, there is an urgent need for a test method that can reduce the compilation time. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: a multi-die testing method based on a simulation platform, the method comprising the following steps: A test template is obtained, wherein the test template includes a basic template and template configuration information of a single interconnection structure composed of N interconnected dies; all interfaces between any two of the dies in the basic template are configured as full interconnection; the target configuration information includes a topology structure table, each topology structure in the topology structure table includes an identity identifier topo_id of the current topology structure and all interconnection structures; each interconnection structure includes an identity identifier socket_id of the interconnection structure and an interconnection relationship between interconnection interfaces of the N dies.

[0005] The test template is compiled by a compiler to generate a template database.

[0006] Obtain a target topology structure to be tested, wherein the target topology structure includes M target interconnect structures to be tested, and when simulating the i-th target interconnect structure, configure the topo_id of the target topology structure for the template databasei and the socket_id of the i-th target interconnect structure i The template database is based on topo_id i and socket_id i The target database is obtained by the interconnection relationship bound thereto, and the value range of i is 1 to M.

[0007] The emulator is used to identify the socket_id in the target database i All the interconnections of the binding are tested.

[0008] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0009] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0010] The present invention has at least the following beneficial effects: The present invention provides a multi-die test method, electronic device and storage medium based on a simulation platform, which configure the interconnection interface between dies included in a test template as full interconnection, and configure template configuration information; compile the test template into a template database; when a user tests a target interconnection structure, the target interconnection structure can be obtained by only specifying the topology structure and the identity information of the interconnection structure, thereby achieving the purpose of testing the interconnection relationship in the target interconnection structure. Compared with the prior art, the time-consuming compilation step only needs to be executed when generating the template database, and when testing various interconnection structures, the compilation step does not need to be executed, which greatly shortens the verification cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A flow chart of a multi-die testing method based on a simulation platform provided by an embodiment of the present invention; Figure 2 A schematic diagram for visualizing the contents stored in a test template provided by an embodiment of the present invention; Figure 3 A schematic diagram of a topological structure. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0014] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0015] See also Figure 1 , which shows a multi-die testing method based on a simulation platform, the method comprising the following steps: S100, obtaining a test template, wherein the test template includes a basic template and template configuration information of a single interconnection structure composed of N interconnected dies; all interfaces between any two of the dies in the basic template are configured as fully interconnected; the target configuration information includes a topology structure table, each topology structure in the topology structure table includes an identity identifier topo_id of the current topology structure and all interconnection structures; each interconnection structure includes an identity identifier socket_id of the interconnection structure and an interconnection relationship between interconnection interfaces of the N dies.

[0016] Among them, the simulation platform (emulation) includes a compiler and an emulator.

[0017] The basic template is a netlist of N interconnected dies, and all interfaces between any two of the dies in the netlist are fully interconnected.

[0018] In one implementation, the value of N is equal to the maximum number of single simulations of the simulation platform. Configuring N to be the maximum number of single simulations can fully utilize the resources of the simulation platform and can save the time of a single simulation test to the maximum extent.

[0019] In one implementation, N is equal to 2. When the maximum number of single simulations of the simulation platform is 2, N is equal to 2. Alternatively, when the minimum test unit specified by the user is 2, the flexibility is better, and the test template of the interconnection between two dies can be more flexibly adapted to all different types of interconnection topologies, whether symmetrical or asymmetrical.

[0020] The topo_id bound to each topology structure is unique. The number of dies included in each interconnect structure is equal to the number of dies in the basic template.

[0021] In one implementation, there are no identical interconnection paths between two dies in different topologies. By properly allocating them, the number of compilations and verification cycles can be reduced. If the same path is allocated to different interconnection structures, the same path will be repeatedly compiled and tested, increasing the compilation time and verification cycle. As an example, please refer to Figure 3 , taking N=2 as an example, the interconnect topology includes 4 dies: die 0 、die 1 、die 2 and die 3 , where die 0 Respectively with die 1 、die 2 and die 3 Interconnection, then get die 0 and die 1 The interconnect structure and die 0 and die 2 The interconnect structure and die 0 and die 3 The interconnect structure composed of die 1 Also respectively with die 2 and die 3 Interconnection, then get die 1 and die 2 The interconnect structure and die 1 and die 3 The interconnect structure composed of die 2 and die 3 Also interconnected, we get die 2 and die 3 A total of 6 interconnection structures are obtained, and there are no two identical interconnection paths between these interconnection structures. Similarly, when N=3 or N=4, or N takes other values, there are no two identical interconnection paths in the two interconnection structures.

[0022] In one implementation, the interface connection between the two dies is a point-to-point interconnection between the two interfaces.

[0023] In one embodiment, the full interconnection includes all interconnection relationships of all interconnection structures in all target topology structures to be tested.

[0024] As an example, for ease of understanding, see Figure 2 , Figure 2 A visual diagram of the contents saved in the test template is provided to help understand the contents. For example, N=2, and each die includes M1-M3 and E0 interfaces. In the test template, the die xIncluding M1-M3 interface and E0 interface, similarly, die y Also includes M1-M3 interface and E0 interface, die x and die y The corresponding interfaces are interconnected to achieve full interconnection. Among them, M1-M3 are high-speed interconnection interfaces, and E0 is a network interface. In the actual topology, for example, Figure 3 In the topological structure of die 0 and die 1 The die are interconnected through M3. 0 and die 2 The die are interconnected through M1. 0 and die 3 The test template also includes the interconnection relationship of other topological structures. That is, the test template includes the interconnection relationship of all interconnection structures in the target topological structure to be tested.

[0025] It should be noted that the dies in the test template, the interfaces of each die, and the connection relationship between the interfaces of the dies are all saved in the netlist. The template configuration information includes all the topological structures to be tested and all the interconnection structures included in each topological structure. Each topological structure has a unique topo_id, and the interconnection structure in each topological structure has a unique socket_id. Users can uniquely determine the interconnection structure to be tested by specifying topo_id and socket_id.

[0026] In one embodiment, the identity of each topological structure in the topological structure table is globally unique, and the identity of each interconnected structure is locally unique in the current topological structure. The local uniqueness of the identity of the interconnected structure can significantly reduce the amount of data.

[0027] In another embodiment, the identity of each topological structure in the topological structure table is globally unique, and the identity of each interconnection structure is globally unique in the topological structure table. The global uniqueness of the identity of the interconnection structure can eliminate the need to search according to the hierarchical structure during the configuration search process, greatly improving the search speed.

[0028] S200, compiling the test template by a compiler to generate a template database.

[0029] It should be noted that since all interfaces between the N interconnected dies in the test template are configured as fully interconnected, the compiler obtains a template database storing the fully interconnected relationships between these dies after compilation. The template database describes how the interfaces between the dies are interconnected at the logical level, including the connection mapping between the ports of each die, providing basic information for subsequent simulation based on this, and facilitating further simulation of these interconnected relationships.

[0030] S300, obtaining a target topology structure to be tested, wherein the target topology structure includes M target interconnect structures to be tested, and when simulating the i-th target interconnect structure, configuring the topo_id of the target topology structure for the template database i and the socket_id of the i-th target interconnect structure i The template database is based on topo_id i and socket_id i The target database is obtained by the interconnection relationship bound thereto, and the value range of i is 1 to M.

[0031] After compilation, the template database has been generated, and the user can obtain the target interconnection structure to be tested by configuring the corresponding topo_id and socket_id.

[0032] In one embodiment, the step of acquiring the target database includes: the template database includes a target selection interface, when the target selection interface receives the topo_id i and socket_id i When the target selection interface looks for the topo_id i The same topo_id gets the target topology structure, and searches for the socket_id in the target topology structure. i The same socket_id obtains the target interconnection structure and the interconnection relationship bound thereto.

[0033] In one embodiment, the template database is configured with the topo_id of the target topology structure. i and the socket_id of the i-th target interconnect structure i The method is: obtain the configuration file to be tested, the configuration file to be tested includes the topo_id of the target topology structure i and the socket_id of the i-th target interconnect structure i ; Parse the configuration file to be tested, use the topo_id in the configuration file to be tested i and socket_id i Establish a database connection.

[0034] In another embodiment, the topo_id can be configured directly through the simulator. i and socket_id i .

[0035] S400, using an emulator to identify the socket_id in the target database i All the interconnections of the binding are tested.

[0036] It should be noted that even if the user's interconnection structure to be tested includes interconnections between multiple different dies, the user can obtain various interconnection structures to be tested by configuring the corresponding topo_id and socket_id and then directly simulate. Before simulation, it is only necessary to write the hardware description language code of the test template, synthesize the test template, and then compile the test template to obtain the template database, that is, the code writing, synthesis and compilation process only needs to be performed once. The traditional simulation method requires writing hardware description language code, synthesis, compilation and simulation for each different interconnection structure to be tested. For example Figure 3 The topological structure shown, using the traditional method, needs to compile and simulate the netlists of the 6 interconnection structures in the topological structure respectively. However, using the present invention for simulation only requires compiling once to generate a template database, and then obtaining the 6 interconnection structures to be tested by sequentially configuring topo_id and socket_id, and testing each interconnection structure separately. Compared with the traditional solution, the method provided by the embodiment of the present invention greatly reduces the time spent on compilation and greatly compresses the verification cycle. In addition, since the present invention only needs to compile the test template, and does not need to compile each interconnection structure separately, the present invention also greatly reduces the time spent on collecting verification coverage compared to the traditional method.

[0037] In one embodiment, the interconnection relationship includes an interconnection relationship interconnected through a high-speed interconnection interface and an interconnection relationship interconnected through a network interface. Other types of interconnection relationships also fall within the protection scope of the present invention.

[0038] In one embodiment, the high-speed interconnect interface uses a bus interconnect that complies with the MetaX Link, NVLink, InfinityFabric, or UCIe standards.

[0039] In summary, the present invention provides a multi-die testing method based on a simulation platform, which configures the interconnection interface between the dies included in the test template as full interconnection, and configures the template configuration information; compiles the test template into a template database; when the user tests the target interconnection structure, only the topology structure and the identity information of the interconnection structure need to be specified to obtain the target interconnection structure, thereby achieving the purpose of testing the interconnection relationship in the target interconnection structure. Compared with the prior art, the time-consuming compilation step only needs to be executed when the template database is generated. When testing various different interconnection structures, there is no need to execute the compilation step, which greatly shortens the verification cycle.

[0040] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0041] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0042] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0043] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0044] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A multi-die testing method based on a simulation platform, characterized in that: The method comprises the following steps: Acquire a test template, wherein the test template includes a basic template and template configuration information of a single interconnection structure composed of N interconnected dies; all interfaces between any two of the dies in the basic template are configured as full interconnection; the target configuration information includes a topology structure table, each topology structure in the topology structure table includes an identity identifier topo_id of the current topology structure and all interconnection structures; each interconnection structure includes an identity identifier socket_id of the interconnection structure and an interconnection relationship between interconnection interfaces of the N dies; Compiling the test template by a compiler to generate a template database; Obtain a target topology structure to be tested, wherein the target topology structure includes M target interconnect structures to be tested, and when simulating the i-th target interconnect structure, configure the topo_id of the target topology structure for the template database i and the socket_id of the i-th target interconnect structure i The template database is based on topo_id i and socket_id i and the interconnected relationship bound thereto to obtain a target database, wherein the value of i ranges from 1 to M; The emulator is used to identify the socket_id in the target database i All the interconnections of the binding are tested.

2. The method according to claim 1, characterized in that The value of N is equal to the maximum number of single simulations of the simulation platform.

3. The method according to claim 1, characterized in that The N is equal to 2.

4. The method according to claim 1, characterized in that The target database acquisition step includes: the template database includes a target selection interface, when the target selection interface receives the topo_id i and socket_id i When the target selection interface looks for the topo_id i The same topo_id gets the target topology structure, and searches for the socket_id in the target topology structure. i The same socket_id obtains the target interconnection structure and the interconnection relationship bound thereto.

5. The method according to claim 1, characterized in that The topo_id of the target topology structure is configured for the template database i and the socket_id of the i-th target interconnect structure i The method is: obtain the configuration file to be tested, the configuration file to be tested includes the topo_id of the target topology structure i and the socket_id of the i-th target interconnect structure i ; Parse the configuration file to be tested, use the topo_id in the configuration file to be tested i and socket_id i Establish a database connection.

6. The method according to claim 1, characterized in that The interconnection relationship includes an interconnection relationship through a high-speed interconnection interface and an interconnection relationship through a network interface.

7. The method according to claim 1, characterized in that The identity of each topological structure in the topological structure table is globally unique, and the identity of each interconnected structure is locally unique in the current topological structure.

8. The method according to claim 1, characterized in that The identity of each topological structure in the topological structure table is globally unique, and the identity of each interconnection structure in the topological structure table is globally unique.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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