Microchip high-precision defect detection system and method based on efficient activation

Abstract

The invention is suitable for the technical field of chip manufacturing, and provides a microchip high-precision defect detection system and method based on efficient activation, and the method comprises the following steps: Step 1, obtaining a high-resolution image; step 2, constructing a sample data set; step 3, carrying out sample pretreatment; step 4, applying the optimized FReLU activation function, the SE module and the Transform module to enhance the expressive force of the model and increase the training speed; step 5, performing model training; step 6, acquiring a chip image; step 7, defect detection: inputting a to-be-detected image into the trained model, and identifying and outputting a corresponding chip defect type; and step 8, guiding wafer transplanting equipment to take away chips without defects from the processed wafer disc to carry out packaging processing operation. The system can be used for defect detection of chips with the size of 2 mm or below, tiny defects can be accurately detected through the system, the efficiency and precision of defect recognition are improved, and therefore the overall operation speed and quality control capacity of a production line are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip manufacturing, and in particular to a high-precision defect detection system and method for microchips based on efficient activation. Background Art

[0002] With the development of miniaturization technology, chips of 2mm and below are widely used in consumer electronics, medical devices, sensors and other fields. As the chip size decreases, tiny defects in the manufacturing process have an increasingly significant impact on chip performance. Existing defect detection methods mostly rely on optical microscopes or machine vision systems. These systems can usually only detect larger defects, or the detection accuracy is insufficient, making it difficult to accurately identify tiny defects on the chip surface such as cracks, scratches, foreign matter, etc.

[0003] Existing defect detection technologies mainly face the following problems:

[0004] 1. Insufficient detection accuracy: Traditional optical systems are limited by resolution and it is difficult to ensure high-precision detection without increasing production costs;

[0005] 2. Slow detection speed: The detection process usually requires scanning piece by piece, which leads to low efficiency and is difficult to meet the needs of large-scale production;

[0006] 3. Limited defect recognition capabilities: Existing systems have poor defect recognition capabilities in complex backgrounds and are prone to mistaking noise and other surface features for defects.

[0007] In view of the above problems, the present invention provides a microchip high-precision defect detection system and method based on efficient activation. Summary of the invention

[0008] The purpose of the present invention is to provide a high-precision defect detection system and method for microchips based on efficient activation, so as to solve the problems of insufficient detection accuracy, slow detection speed and limited defect recognition ability faced by defect detection technology in the prior art.

[0009] To achieve the above object, the present invention provides the following technical solution: In a first aspect, the present invention provides a high-precision defect detection method for a microchip based on efficient activation, comprising the following steps:

[0010] Step 1, high-resolution image acquisition;

[0011] Step 2, sample data set construction:

[0012] Create a sample dataset containing multiple chip defect types;

[0013] Step 3, sample preprocessing:

[0014] Process the data set, including noise injection and sample weighting, to ensure that the sample weights of different defect types are reasonably distributed;

[0015] Step 4: Apply the optimized FReLU activation function, SE module, and Transformer module to enhance the model’s expressiveness and improve training speed.

[0016] Step 5, model training:

[0017] Use the processed data set as a training set to train the improved network;

[0018] Step 6, chip image acquisition:

[0019] Acquire the chip image to be detected;

[0020] Step 7, defect detection:

[0021] Input the image to be inspected into the trained model to identify and output the corresponding chip defect type;

[0022] Step 8, instruct the wafer transfer equipment to take out the non-defective chips from the processed wafer tray for packaging processing operations.

[0023] Preferably, the chip image acquisition steps of Step 1 and Step 6 are as follows:

[0024] A high-resolution industrial camera with a high-precision optical lens is used to shoot the chip at multiple angles, and multi-spectral imaging technology is used to illuminate the chip surface with light sources of different bands and display it in grayscale. The resulting image is then input into the image for preprocessing.

[0025] Preferably, the specific operations of the noise injection and sample weighting are as follows:

[0026] Noise injection: simulate various possible noise interferences to enhance the model’s robustness to noise;

[0027] Sample weighting: According to the distribution of different types of chip defects, the weight of each sample is adjusted to reduce the impact of data imbalance.

[0028] Preferably, the Step 4 combines the improvement of the FReLU activation function, the introduction of the SE module and the Transformer module to construct a deep learning network model for defect detection, as follows:

[0029] Improvement of FReLU activation function: An optimized FReLU activation function is introduced after each convolutional layer and residual block, which improves the model's ability to handle negative features;

[0030] Introduction of SE module: Through the adaptive channel attention mechanism, each feature channel is given a weight, which further improves the classification accuracy;

[0031] Combination of Transformer modules: Through the self-attention mechanism, long-distance dependencies are captured, improving the generalization ability of the model.

[0032] Preferably, the deep learning network model image processing algorithm used for defect detection in Step 4 is as follows:

[0033] 4.1, Input layer:

[0034] Takes in and normalizes an input image:

[0035]

[0036] 4.2, Convolutional layer:

[0037] For feature extraction, standard convolution and pooling operations are used. The convolution operation can be expressed as:

[0038] Z = W*X+b;

[0039] Among them, Z is the output, W is the convolution kernel, X is the input feature map, and b is the bias term;

[0040] 4.3, Maximum Pooling Layer:

[0041] Pooling operation:

[0042] Z pool =max(Z);

[0043] 4.4, residual block:

[0044] By introducing short-circuit connections, the gradient vanishing problem in deep networks is effectively solved. Each residual block can be expressed as:

[0045] Y=F(X,W)+X;

[0046] Among them, Y is the output, F is the residual function, X is the input feature map, and W is the weight in the residual block;

[0047] 4.5, Optimize FReLU activation function:

[0048]

[0049] Among them, α i and β i is a learnable parameter, γ is a smoothing factor; H(x) is the Heaviside step function, which is used to distinguish positive and negative inputs;

[0050] 4.6, SE module:

[0051] Attention Mechanism:

[0052] S=σ(W 2 ·δ(W 1 ·X));

[0053] Among them, W 1 and W 2 is the learnable weight, δ is the FReLU activation function, and S is the weight calculated by the sigmoid function;

[0054] 4.7, Transformer module:

[0055] Self-Attention Mechanism:

[0056]

[0057] Where Q, K, and V are query, key, and value respectively. k is the dimension of the key;

[0058] 4.8, global average pooling layer:

[0059] The feature map is pooled to reduce the number of parameters and prevent overfitting, and its output can be expressed as:

[0060]

[0061] Among them, H and W are the height and width of the feature map respectively;

[0062] 4.9, fully connected layer:

[0063] Output defect classification results. Assuming the input feature is V and the output is O, then:

[0064] O=W·V+b;

[0065] Among them, W is the weight matrix and b is the bias term;

[0066] 4.10, Softmax layer:

[0067] Output classification probability:

[0068]

[0069] Among them, P(y i ) is the probability of category i, O i is the output of category i, and C is the total number of categories.

[0070] Preferably, the Step 5 model training method is as follows:

[0071] Use the labeled data set to train the model and optimize the loss function, which can be expressed as:

[0072]

[0073] Among them, y i is the true label, is the predicted probability.

[0074] Preferably, the specific steps of Step 7 are as follows:

[0075] The image to be detected is input into the model, and reasoning is performed through the feature layer processed by the improved FReLU activation function, and finally the classification result is output; for defect detection tasks, the output category is normal or defective.

[0076] Preferably, in the Step 5, according to the production test requirements, when the ratio of the training false detection image to the correct recognition image is less than 0.1, the training result is better.

[0077] The second aspect of the present invention provides a system using the method described in the first aspect of the present invention, the system comprising a high-resolution image acquisition module, an intelligent image processing module, and a defect classification and feedback module;

[0078] The high-resolution image acquisition module is used to operate Step 1 and Step 6;

[0079] The intelligent image processing module is used to operate Step 2-Step 5;

[0080] The defect classification and feedback module is used to operate Step 6-Step 8.

[0081] The third aspect of the present invention provides an application of the system described in the second aspect of the present invention, and the application fields of the system include but are not limited to chip manufacturing, electronic component production, scientific research institutions and laboratories.

[0082] The present invention has at least the following beneficial effects:

[0083] (1) The present invention provides a high-precision microchip defect detection system and method based on efficient activation, which uses multispectral imaging technology to obtain subtle differences on the chip surface in different bands, thereby improving the detection accuracy, especially for micro cracks and surface scratches.

[0084] (2) The present invention provides a microchip high-precision defect detection system and method based on efficient activation. By introducing the optimized FReLU activation function, SE module and Transformer module, the accuracy and robustness of chip defect detection are significantly improved, and the system has a faster convergence speed and a lower loss value. The residual block and FReLU activation function in the network structure effectively prevent the gradient vanishing problem, further improving the deep learning ability of the network.

[0085] (3) The present invention provides a microchip high-precision defect detection system and method based on efficient activation, which can automatically classify and generate feedback reports according to the type and severity of defects, thereby reducing human intervention and improving detection efficiency; through continuous model training, the system can self-optimize detection capabilities;

[0086] (4) The present invention provides a high-precision microchip defect detection system and method based on efficient activation. The system supports seamless integration with existing production lines, has a high degree of automation, and can improve the work efficiency of the entire production line. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Figure 1 It is a flow chart of the high-precision defect detection method of microchips of the present invention;

[0088] Figure 2 This is the SE-FReLU ResNet model diagram of the present invention;

[0089] Figure 3 This is a comparison chart of the accuracy of the improved activation function of the present invention;

[0090] Figure 4 This is a comparison chart of the accuracy of the improved network of the present invention;

[0091] Figure 5 It is the 2mm IC scratch training recognition diagram of the present invention;

[0092] Figure 6 It is the 2mm IC foreign body training identification diagram of the present invention;

[0093] Figure 7 It is the 2mm IC crack training identification diagram of the present invention;

[0094] Figure 8 It is the 2mm IC normal training recognition diagram of the present invention;

[0095] Fig. 9 This is a diagram of the 2mm IC plate of the present invention before taking out the material;

[0096] Fig.10 This is a diagram of the 2mm IC disc after taking out the material of the present invention;

[0097] Fig.11 This is a diagram showing the completion of the 2mm IC material placement process of the present invention. DETAILED DESCRIPTION

[0098] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0099] like Figure 1 As shown, the present invention provides a high-precision defect detection method for microchips based on efficient activation, comprising the following steps:

[0100] Step 1, high-resolution image acquisition;

[0101] Step 2, sample data set construction:

[0102] Create a sample dataset containing multiple chip defect types;

[0103] Step 3, sample preprocessing:

[0104] Process the data set, including noise injection and sample weighting, to ensure that the sample weights of different defect types are reasonably distributed;

[0105] Step 4: Apply the optimized FReLU activation function, SE module, and Transformer module to enhance the model’s expressiveness and improve training speed.

[0106] Step 5, model training:

[0107] Use the processed data set as a training set to train the improved network;

[0108] Step 6, chip image acquisition:

[0109] Acquire the chip image to be detected;

[0110] Step 7, defect detection:

[0111] Input the image to be inspected into the trained model to identify and output the corresponding chip defect type;

[0112] Step 8, instruct the wafer transfer equipment to take out the non-defective chips from the processed wafer tray for packaging processing operations.

[0113] The present invention also provides a system applying the above method, comprising a high-resolution image acquisition module, an intelligent image processing module, and a defect classification and feedback module;

[0114] The high-resolution image acquisition module is used to operate Step 1 and Step 6; the intelligent image processing module is used to operate Step 2-Step 5; and the defect classification and feedback module is used to operate Step 6-Step 8.

[0115] The technical solution provided by the present invention can be used for defect detection of chips with a size of 2 mm or less. Through this system, tiny defects can be accurately detected, and the efficiency and accuracy of defect identification can be improved, thereby improving the overall operating speed and quality control capabilities of the production line.

[0116] Based on the above technical solution, the present invention provides the following partial embodiments:

[0117] Example 1

[0118] This embodiment provides a 2 mm chip defect detection method, including:

[0119] Step 1: Collect chip images. The present invention uses IC transplantation equipment to collect images of the surface of a 2 mm microchip.

[0120] Step 2: Label the defect area and category information of the training 2mm microchip image, where the defect area is the minimum circumscribed polygon box selected manually;

[0121] Step 3: Expand the manually annotated chip image and use the data enhancement algorithm to highlight the image information features to obtain the initial training data set;

[0122] Step 4: Construct a deep learning network model for defect detection based on the Proposed Network (FReLU+SE+Transformer) network;

[0123] Step 5: Use the pre-trained parameters as the initial weights to train the deep learning network, and apply the confusion matrix to finally determine the training results. According to production test requirements, when the ratio of training false positive images to correctly identified images is less than 0.1, the training results are good.

[0124] Step 6: Obtain the chip image to be tested;

[0125] Step 7: Input the image to be tested into the trained model to identify and output the corresponding chip defect type;

[0126] Step 8: Based on the image detection results, the chips without defects are finally removed from the processed IC tray through the IC transfer equipment to complete the sorting of microchips.

[0127] 1. Operations of Step 1 and Step 6 through the high-resolution image acquisition module are as follows:

[0128] The system uses a high-resolution industrial camera with a high-precision optical lens to shoot 2mm chips from multiple angles. Using multispectral imaging technology, the chip surface is illuminated by light sources of different bands. The image of each band can be processed separately and displayed in grayscale, emphasizing the structure, texture and other physical characteristics of the object without being disturbed by color. It can clearly present the tiny details on the chip surface, especially the tiny cracks, scratches or foreign objects that are difficult to capture with conventional optical detection, while simplifying the subsequent analysis and processing process. The obtained image is then input into the image for preprocessing, including image normalization, image enhancement and other operations to improve the robustness of the model.

[0129] 2. Operations of Step 2-Step 5 through the intelligent image processing module are as follows:

[0130] (1) Data preprocessing

[0131] Performing data enhancement and preprocessing on the sample data set includes:

[0132] Noise injection: simulate various possible noise interferences to enhance the model’s robustness to noise;

[0133] Sample weighting: According to the distribution of different types of chip defects, the weight of each sample is adjusted to reduce the impact of data imbalance.

[0134] (2) Constructing an improved neural network model

[0135] Using the deep learning network model image processing algorithm based on the Proposed Network (FReLU+SE+Transformer) network, the system can quickly process and analyze the collected images. First, the algorithm removes background noise and irrelevant surface features. Then, the system automatically annotates defects such as scratches, foreign matter, microcracks, etc., and classifies and prioritizes defects based on parameters such as size, shape, and location.

[0136] Improvement of FReLU activation function: An optimized FReLU activation function is introduced after each convolutional layer and residual block to improve the model's ability to handle negative features.

[0137] Introduction of SE module: Through the adaptive channel attention mechanism, each feature channel is given a weight, which further improves the classification accuracy.

[0138] Combination of Transformer modules: Through the self-attention mechanism, long-distance dependencies are captured, improving the generalization ability of the model.

[0139] like Figure 2 As shown, the deep learning network model image processing algorithm for defect detection is constructed based on the Proposed Network (FReLU+SE+Transformer) network:

[0140] 1. Input layer:

[0141] Takes in and normalizes an input image:

[0142]

[0143] 2. Convolutional layer:

[0144] For feature extraction, standard convolution and pooling operations are used. The convolution operation can be expressed as:

[0145] Z = W*X+b;

[0146] Among them, Z is the output, W is the convolution kernel, X is the input feature map, and b is the bias term;

[0147] 3. Max pooling layer:

[0148] Pooling operation:

[0149] Z pool =max(Z);

[0150] 4. Residual Block:

[0151] By introducing short-circuit connections, the gradient vanishing problem in deep networks is effectively solved. Each residual block can be expressed as:

[0152] Y=F(X,W)+X;

[0153] Among them, Y is the output, F is the residual function, X is the input feature map, and W is the weight in the residual block;

[0154] 5. Optimize FReLU activation function:

[0155] The traditional ResNet network model uses the ReLU activation function, which has a simple calculation model and small amount of computation. It has achieved good results in image classification and defect detection, but there are still problems such as activation function saturation and gradient disappearance.

[0156] To solve the above problems, the present invention introduces an optimized FReLU activation function to replace the ReLU activation function.

[0157] Advantages of the optimized FReLU activation function:

[0158] Multi-channel support: Different feature channels can be learned independently, making the model more flexible and adaptable when processing complex data.

[0159] Dynamic adjustment capability: Using additional network layers to learn the parameters of the activation function enables the model to dynamically optimize its behavior based on the input data.

[0160] Reduce the risk of gradient vanishing: By introducing the gradient adjustment mechanism and adaptive regularization, the optimized FReLU can maintain good gradient flow during training and improve the training effect of deep networks.

[0161] Improve model performance: By optimizing the response mechanism for negative inputs, the expressiveness of the activation function is enhanced, ultimately improving the performance of the model on various tasks.

[0162] The new activation function can be specifically defined as:

[0163]

[0164] Optimization parameters:

[0165] Multi-channel dynamic learnable parameters:

[0166] Multiple channel support: introduce different learnable parameters α for each input feature channel i and β i , so that different channels can learn specific response mechanisms.

[0167] Dynamic adjustment mechanism: Use additional network layers (such as small neural networks or convolutional layers) to learn α i and β i , enabling it to be dynamically updated based on input data, enhancing the flexibility of the model.

[0168] Gradient adjustment mechanism:

[0169] A smoothing factor γ is introduced to control the gradient flow in the negative area to avoid the gradient vanishing phenomenon. For negative input, its expression can be adjusted as follows:

[0170]

[0171] Adaptive Regularization:

[0172] During the training process, an adaptive regularization mechanism is used to make the learnable parameter α i and β i The update of is restricted to avoid overfitting. The regularization term can be defined as:

[0173]

[0174] The optimized FReLU activation function can be expressed as:

[0175]

[0176] Where H(x) is the Heaviside step function, which is used to distinguish between positive and negative inputs;

[0177] 6.SE module:

[0178] Attention Mechanism:

[0179] S=σ(W 2 ·δ(W 1 ·X));

[0180] Among them, W 1 and W 2 is the learnable weight, δ is the FReLU activation function, and S is the weight calculated by the sigmoid function;

[0181] 7. Transformer module:

[0182] Self-Attention Mechanism:

[0183]

[0184] Where Q, K, and V are query, key, and value respectively. k is the dimension of the key;

[0185] 8. Global average pooling layer:

[0186] The feature map is pooled to reduce the number of parameters and prevent overfitting, and its output can be expressed as:

[0187]

[0188] Among them, H and W are the height and width of the feature map respectively;

[0189] 9. Fully connected layer:

[0190] Output defect classification results. Assuming the input feature is V and the output is O, then:

[0191] O=W·V+b;

[0192] Among them, W is the weight matrix and b is the bias term;

[0193] 10.Softmax layer:

[0194] Output classification probability:

[0195]

[0196] Among them, P(y i ) is the probability of category i, O i is the output of category i, and C is the total number of categories.

[0197] Defect detection process:

[0198] 1. Data preprocessing: The obtained image is input into the image for image preprocessing, including image normalization, image enhancement and other operations to improve the robustness of the model.

[0199] 2. Model training: Use the labeled data set to train the model (improved ResNet-152 model) and optimize the loss function. The loss function can be expressed as:

[0200]

[0201] Among them, y i is the true label, is the predicted probability.

[0202] 3. During the inference process, the image to be detected is input into the ResNet-152 model, and the feature layer processed by the improved FReLU activation function is used for inference, and the classification result is finally output. For defect detection tasks, the output category is normal or defective.

[0203] (III) Operations through the defect classification and feedback module Step 6-Step 8

[0204] The system has a built-in intelligent classifier, combined with a machine learning model, which can continuously optimize the defect recognition and classification capabilities based on historical data and training sets. For the detected defects, the system will classify them according to the severity of the defects, and automatically generate a test report to guide the production line to screen, repair or scrap the chips. The system supports seamless integration with existing chip production lines, and automatically transfers the chips to be inspected to the inspection platform through an automatic conveyor. The inspection process is fully automated, and the system independently completes everything from image acquisition to analysis and feedback to ensure efficient inspection. Finally, the classification results of real-time detection guide the wafer transfer equipment to remove the defect-free chips from the processed wafer tray for packaging and processing operations.

[0205] The above embodiments were tested and the results are as follows:

[0206] 1. Figure 3 This is a comparison chart of the accuracy of the improved activation function, such as Figure 3As shown in the figure, the optimized FReLU activation function achieves 94% accuracy in the defect detection task, which is 6%, 4%, 1%, 3% and 2% higher than the traditional ReLU (88%), LeakyReLU (90%), SReLU (93%), ELU (91%) and Swish (92%) respectively. This result not only highlights its advantage in accuracy, but also shows that FReLU demonstrates faster convergence speed and lower loss value, further proving its excellent performance in stability and generalization ability.

[0207] 2. Figure 4 This is a comparison chart of the improved network accuracy, such as Figure 4 As shown in the figure, the new network combining the optimized FReLU activation function, SE module and Transformer module shows excellent performance in defect detection tasks, with an accuracy of 96%, significantly better than other comparison networks, such as VisionTransformer's 94%, EffICientNet's 93%, ResNet's 92% and DenseNet's 90%. This innovative network architecture effectively improves the expressiveness and robustness of the model, fully demonstrating the potential of new technologies in the field of deep learning, and indicating that in complex image analysis tasks, integrating different modules can significantly improve the detection accuracy and reliability of the model.

[0208] 3. Figure 5-8 Training recognition graphs for IC; Figure 9-10 This is the before and after picture of taking material from 2mm IC disc; Fig.11 This is the completed picture of 2mm IC material placement. At the same time, the percentage of good 2mm IC material is statistically shown in Table 1:

[0209] Table 1 Proportion of good quality 2mm IC materials

[0210] Processing quantity Good product Proportion of good products determination 1728 1728 100％ OK

[0211] In summary, the 2mm chip defect detection system and method of this embodiment can achieve efficient and accurate detection of the chip surface, greatly improving the speed and accuracy of defect identification. The system can automatically adapt to different defect types and continuously optimize based on historical data, thereby effectively improving the overall production qualification rate of chips and reducing production costs and waste.

[0212] The detection system and method provided by the present invention can be extended to the following application scenarios:

[0213] 1. Chip manufacturing plant:

[0214] Quality control testing is performed at the final stage of chip manufacturing to ensure that each chip is accurately inspected for defects before leaving the factory.

[0215] 2. Electronic component manufacturers:

[0216] Used to detect defects in small electronic components (such as sensors, microcontrollers, etc.) to improve product quality.

[0217] 3. Scientific research institutions and laboratories:

[0218] The system can also be used in scientific research institutions or laboratories to conduct defect research and process optimization in the chip manufacturing process.

[0219] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention.

[0220] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-precision defect detection method for microchips based on efficient activation, characterized in that: The following steps are involved: Step 1, high-resolution image acquisition; Step 2, sample data set construction: Create a sample dataset containing multiple chip defect types; Step 3, sample preprocessing: Process the data set, including noise injection and sample weighting, to ensure that the sample weights of different defect types are reasonably distributed; Step 4: Apply the optimized FReLU activation function, SE module, and Transformer module to enhance the model’s expressiveness and improve training speed. Step 5, model training: Use the processed data set as a training set to train the improved network; Step 6, chip image acquisition: Acquire the chip image to be detected; Step 7, defect detection: Input the image to be inspected into the trained model to identify and output the corresponding chip defect type; Step 8, instruct the wafer transfer equipment to take out the non-defective chips from the processed wafer tray for packaging processing operations.

2. A high-precision defect detection method for microchips based on efficient activation according to claim 1, characterized in that: The chip image acquisition steps of Step 1 and Step 6 are as follows: A high-resolution industrial camera with a high-precision optical lens is used to shoot the chip at multiple angles, and multi-spectral imaging technology is used to illuminate the chip surface with light sources of different bands and display it in grayscale. The resulting image is then input into the image for preprocessing.

3. A high-precision defect detection method for microchips based on efficient activation according to claim 1, characterized in that: The specific operations of the noise injection and sample weighting are as follows: Noise injection: simulate various possible noise interferences to enhance the model’s robustness to noise; Sample weighting: According to the distribution of different types of chip defects, the weight of each sample is adjusted to reduce the impact of data imbalance.

4. A high-precision defect detection method for microchips based on efficient activation according to claim 1, characterized in that: Step 4 combines the improvement of the FReLU activation function, the introduction of the SE module and the Transformer module to construct a deep learning network model for defect detection, as follows: Improvement of FReLU activation function: An optimized FReLU activation function is introduced after each convolutional layer and residual block, which improves the model's ability to handle negative features; Introduction of SE module: Through the adaptive channel attention mechanism, each feature channel is given a weight, which further improves the classification accuracy; Combination of Transformer modules: Through the self-attention mechanism, long-distance dependencies are captured, improving the generalization ability of the model.

5. A high-precision microchip defect detection method based on efficient activation according to claim 4, characterized in that: The image processing algorithm of the deep learning network model used for defect detection in Step 4 is as follows: 4.1, Input layer: Takes in and normalizes an input image: 4.2, Convolutional layer: For feature extraction, standard convolution and pooling operations are used. The convolution operation can be expressed as: Z = W*X+b; Among them, Z is the output, W is the convolution kernel, X is the input feature map, and b is the bias term; 4.3, Maximum Pooling Layer: Pooling operation: WITH pool =max(Z); 4.4, residual block: By introducing short-circuit connections, the gradient vanishing problem in deep networks is effectively solved. Each residual block can be expressed as: Y=F(X,W)+X; Among them, Y is the output, F is the residual function, X is the input feature map, and W is the weight in the residual block; 4.5, Optimize FReLU activation function: Among them, α i and β i is a learnable parameter, γ is a smoothing factor; H(x) is the Heaviside step function, which is used to distinguish positive and negative inputs; 4.6, SE module: Attention Mechanism: S = σ(W2·δ(W1·X)); Among them, W1 and W2 are learnable weights, δ is the FReLU activation function, and S is the weight calculated by the sigmoid function; 4.7, Transformer module: Self-Attention Mechanism: Where Q, K, and V are query, key, and value respectively. k is the dimension of the key; 4.8, global average pooling layer: The feature map is pooled to reduce the number of parameters and prevent overfitting, and its output can be expressed as: Among them, H and W are the height and width of the feature map respectively; 4.9, fully connected layer: Output defect classification results. Assuming the input feature is V and the output is O, then: O = W·V + b; Among them, W is the weight matrix and b is the bias term; 4.10, Softmax layer: Output classification probability: Among them, P(y i ) is the probability of category i, O i is the output of category i, and C is the total number of categories.

6. A high-precision microchip defect detection method based on efficient activation according to claim 5, characterized in that: The Step 5 model training method is as follows: Use the labeled data set to train the model and optimize the loss function, which can be expressed as: Among them, y i is the true label, is the predicted probability.

7. A high-precision microchip defect detection method based on efficient activation according to claim 6, characterized in that: The specific steps of Step 7 are as follows: The image to be detected is input into the model, and the feature layer processed by the improved FReLU activation function is used for inference, and the classification result is finally output; for defect detection tasks, the output category is normal or defective.

8. A high-precision microchip defect detection method based on efficient activation according to claim 1, characterized in that: In the Step 5, according to the production test requirements, when the ratio of the training misdetected image to the correctly identified image is less than 0.1, the training result is good.

9. A system using the method according to any one of claims 1 to 8, characterized in that: The system includes a high-resolution image acquisition module, an intelligent image processing module, and a defect classification and feedback module; The high-resolution image acquisition module is used to operate Step 1 and Step 6; The intelligent image processing module is used to operate Step 2-Step 5; The defect classification and feedback module is used to operate Step 6-Step 8.

10. An application of the system according to claim 9, characterized in that: The application fields of the system include but are not limited to chip manufacturing, electronic component production, scientific research institutions and laboratories.

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