Gate drive unit and display panel

Abstract

The present invention provides a gate drive unit and a display panel. By electrically connecting at least one of a first node control module and an output control module in a current-stage gate drive circuit to a second node of a previous-stage gate drive circuit, at least one of the first node control module and the output control module in the current-stage gate drive circuit is no longer electrically connected to the first output end of a different previous-stage gate drive circuit, thereby reducing the number of gate drive circuits controlled by a first gate control signal output from the first output end of the previous-stage gate drive circuit, reducing the load carried by the previous-stage gate drive circuit, and further improving the problem of a large voltage drop of the first gate control signal output by the gate drive circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving unit and a display panel. Background Art

[0002] In the gate drive circuit, transistors using CMOS (Complementary Metal Oxide Semiconductor) design technology have severe coupling when outputting high and low levels, resulting in a larger voltage drop of the gate control signal output by the gate drive circuit for driving the oxide transistor. Summary of the Invention

[0003] Embodiments of the present invention provide a gate driving unit and a display panel, which can improve the problem of increased voltage drop of a gate control signal output by a gate driving circuit.

[0004] An embodiment of the present invention provides a gate drive unit comprising a plurality of gate drive circuits, at least one of which comprises a first node control module, a first output module, an output control module, and a second output module. The first node control module is electrically connected to a first node and a second node of the gate drive circuit at the same level, and is configured to transmit a first power signal to the first node based on the potential of the second node and a corresponding first clock signal, or to transmit a second power signal to the first node based on the potential of the second node. The first output module is electrically connected to the first node of the gate drive circuit at the same level and a first output terminal of the gate drive circuit at the same level, and is configured to output the second power signal or a third power signal to the first output terminal based on the potential of the first node. The output control module is electrically connected to the first node and a third node of the gate drive circuit at the same level, and is configured to electrically connect the first node and the third node, or to disconnect the first node from the third node. The second output module is electrically connected to the second node of the gate driver circuit of the current stage, the third node of the gate driver circuit of the current stage, and the second output terminal of the gate driver circuit of the current stage, and is configured to output the corresponding second clock signal or the first power supply signal to the second output terminal based on the potential of the second node and the potential of the third node. At least one of the first node control module and the output control module is electrically connected to the second node of the gate driver circuit of the previous stage.

[0005] An embodiment of the present invention further provides a display panel, comprising any of the above-mentioned gate drive units; and a plurality of sub-pixels. At least one of the sub-pixels comprises a light-emitting device and a pixel drive circuit for driving the light-emitting device to emit light, the pixel drive circuit comprising a drive transistor, a compensation transistor, and a data transistor, the input end of the compensation transistor and the output end of the compensation transistor being electrically connected between the control end of the drive transistor and the output end of the drive transistor, the input end of the data transistor being configured to receive a corresponding data signal, and the output end of the data transistor being electrically connected to the input end of the drive transistor. The first output ends of the plurality of gate drive circuits are electrically connected to the control ends of the compensation transistors of the plurality of sub-pixels, and the second output ends of the plurality of gate drive circuits are electrically connected to the control ends of the data transistors of the plurality of sub-pixels.

[0006] The gate drive unit and display panel provided by the embodiments of the present invention electrically connect at least one of the first node control module and the output control module in the current-stage gate drive circuit to the second node of the previous-stage gate drive circuit, so that at least one of the first node control module and the output control module in the current-stage gate drive circuit is no longer electrically connected to the first output end of a different previous-stage gate drive circuit, thereby reducing the number of gate drive circuits controlled by the first gate control signal output from the first output end of the previous-stage gate drive circuit, reducing the load carried by the previous-stage gate drive circuit, and then improving the problem of a large voltage drop of the first gate control signal output by the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0008] Figures 1A to 1C 1 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present invention;

[0009] Figure 2 yes Figure 1C The timing diagram corresponding to the gate drive circuit shown;

[0010] Figures 3A to 3H is a structural diagram of a gate driving unit provided by an embodiment of the present invention;

[0011] Figure 4 1 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present invention;

[0012] Figures 5A to 5D yes Figure 4 The timing diagram corresponding to the gate drive circuit shown;

[0013] Figure 6 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0014] Figure 7 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0015] Figure 8 yes Figure 7 The timing diagram corresponding to the pixel driving circuit shown;

[0016] Figure 9 is a cross-sectional view of a multi-layer routing provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0018] Specifically, Figures 1A to 1C is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present invention, Figure 2 yes Figure 1C The gate drive circuit shown corresponds to the timing diagram. Figure 1A The gate driver circuit (i.e., CMOS GOA) shown in FIG. transmits a first gate control signal Nscan via a first output terminal Nout to the display panel to assist the display panel in achieving its display function. The stability of the first gate control signal Nscan has a significant causal relationship with certain optical performance indicators of the display panel, significantly impacting the optical performance of the display panel.

[0019] The existing simulation model confirms that the first gate control signal Nscan has severe coupling when outputting high level and low level. And, through comparative experiments, it is found that Figure 1A The first gate control signal Nscan output by the gate drive circuit shown in FIG. 1 has a relatively high coupling condition when outputting a high level and a low level. Figures 1B to 1CThe gate drive circuit shown is serious.

[0020] Taking the first gate control signal Nscan outputting a high level as an example, Figures 1B to 1C The voltage drop of the power signal VGH used in the gate drive circuit shown is about 0.7V. Figure 1A The voltage drop of the first gate control signal Nscan of the gate drive circuit shown is about 2V. The main reason is that Figure 1A The gate drive circuit shown is determined by the design. Figures 1B to 1C The gate drive circuit shown in the figure corresponds to the upper and lower transmission relationship. Figure 1A The gate drive circuit shown corresponds to a larger number of stages. The first gate control signal Nscan(n) output by the n-th stage gate drive circuit needs to be transmitted to the n+10-th stage gate drive circuit, the n+2-th stage gate drive circuit, and the n-1-th stage gate drive circuit. As a result, the n-th stage gate drive circuit needs to take into account the load of the 4-stage gate drive circuit, which causes the first gate control signal Nscan to generate too much load when controlled by the power supply signal (NVGH / NVGL) output, resulting in a large voltage drop at the moment when the transistor T9 / T10 is turned on, and then the first gate control signal Nscan generates a high and low level voltage drop, as shown in FIG. Figure 2 shown.

[0021] Moreover, corresponding Figure 1A In the gate drive circuit shown, each stage of the gate drive circuit is generated by a pair of NVGH / NVGL. This means that the load generated by the first gate control signal Nscan is entirely borne by NVGH / NVGL. When multiple gate drive circuits generate current draw during the stage transmission process, the resulting voltage drop is also borne by NVGH / NVGL. This draw not only causes a voltage drop between the high and low levels of the first gate control signal Nscan, but the load capacitance also causes a longer recovery time.

[0022] For display panels using gate drive circuits, a high-level voltage drop in the first gate control signal Nscan can cause horizontal crosstalk and deterioration of dense horizontal stripes on the display panel. A low-level voltage drop in the first gate control signal Nscan can worsen the display panel's display in variable refresh rate mode. Furthermore, a voltage drop occurs at the matching point between the high-level first gate control signal Nscan output by the current gate drive circuit and the second gate control signal Pscan output by the current gate drive circuit, exacerbating the display unevenness problem on the display panel.

[0023] In order to improve the voltage drop problem of the first gate control signal Nscan, the present application provides a gate driving unit and a display panel. Figures 3A to 3H is a structural diagram of a gate driving unit provided by an embodiment of the present invention, Figure 410 is a structural diagram of a gate drive circuit provided in an embodiment of the present invention. An embodiment of the present invention provides a gate drive unit, including multiple gate drive circuits GDC, at least one of the gate drive circuits GDC includes a first node control module 101, a first output module 102, an output control module 103 and a second output module 104.

[0024] The first node control module 101 is electrically connected to the first node K of the gate drive circuit at this level and the second node P of the gate drive circuit at this level. The first node control module 101 is configured to transmit the first power signal PVGH to the first node K according to the potential of the second node P and the corresponding first clock signal XCK, or to transmit the second power signal NVGL to the first node K according to the potential of the second node P.

[0025] The first output module 102 is electrically connected to the first node K of the gate drive circuit at this level and the first output terminal Nout of the gate drive circuit at this level. The first output module 102 is configured to output the second power signal NVGL or the third power signal NVGH to the first output terminal Nout according to the potential of the first node K.

[0026] The output control module 103 is electrically connected to the first node K of the gate drive circuit at this level and the third node Q of the gate drive circuit at this level. The output control module 103 is configured to electrically connect the first node K and the third node Q, or disconnect the electrical connection between the first node K and the third node Q.

[0027] The second output module 104 is electrically connected to the second node P of the gate drive circuit at this level, the third node Q of the gate drive circuit at this level, and the second output end Pout(n) of the gate drive circuit at this level. The second output module 104 is configured to output the corresponding second clock signal CK or the first power supply signal PVGH to the second output end Pout(n) according to the potential of the second node P and the potential of the third node Q.

[0028] Among them, at least one of the first node control module 101 and the output control module 103 is electrically connected to the second node P of the previous gate drive circuit, so that at least one of the first node control module 101 and the output control module 103 in the current gate drive circuit is no longer electrically connected to the first output terminal Nout of a different previous gate drive circuit, thereby distinguishing Figure 1AThe design of the gate drive circuit shown reduces the number of gate drive circuits controlled by the first gate control signal Nscan output from the first output terminal Nout of the previous gate drive circuit, reduces the load carried by the previous gate drive circuit, and then improves the problem of a large voltage drop of the first gate control signal Nscan output by the gate drive circuit.

[0029] Optionally, the first node control module 101 of the n-th stage gate driver circuit GDC(n) is electrically connected to the second node P(nA) of the nA-th stage gate driver circuit GDC(nA), such that the first node control module 101 of the n-th stage gate driver circuit GDC(n) is configured to transmit the first power signal PVGH or the fourth power signal PVGL to the first node K based on the potential of the second node P(nA) of the nA-th stage gate driver circuit GDC(nA) and the corresponding first clock signal XCK. By controlling the first node control module 101 of the n-th stage gate driver circuit GDC(n) by the second node P(nA) of the nA-th stage gate driver circuit GDC(nA) instead of the first gate control signal Nscan(nA) output by the nA-th stage gate driver circuit GDC(nA), the control of the first gate control signal Nscan(nA) output by the nA-th stage gate driver circuit GDC(nA) on other stages of gate driver circuits is reduced. Where A ≥ 1.

[0030] Optionally, the first node control module 101 of the n-th level gate driving circuit GDC(n) is electrically connected to the second node P(n-1) of the n-1-th level gate driving circuit GDC(n-1), and the first node control module 101 of the n-th level gate driving circuit GDC(n) is configured to transmit the first power signal PVGH or the fourth power signal PVGL to the first node K according to the potential of the second node P(n-1) of the n-1-th level gate driving circuit GDC(n-1) and the corresponding first clock signal XCK.

[0031] Optionally, continue Figure 4 The first node control module 101 includes a first transistor T1, a second transistor T2 and a third transistor T3.

[0032] An input terminal of the first transistor T1 is configured to receive a first power signal PVGH.

[0033] The first control terminal and the second control terminal of the second transistor T2 are electrically connected to the control terminal of the first transistor T1. The input terminal of the second transistor T2 is configured to receive the fourth power signal PVGL. The output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1.

[0034] The control end of the third transistor T3 is configured to receive the corresponding first clock signal XCK, the input end of the third transistor T3 is electrically connected to the output end of the first transistor T1 , and the output end of the third transistor T3 is electrically connected to the first node K.

[0035] In which, the control end of the first transistor T1 of the n-th level gate driving circuit GDC(n) is electrically connected to the second node P(nA) of the nA-th level gate driving circuit GDC(nA), so that the first transistor T1 and the second transistor T2 are controlled by the second node P(nA) of the nA-th level gate driving circuit GDC(nA).

[0036] Optionally, the control end of the first transistor T1 of the n-th level gate drive circuit GDC(n) is electrically connected to the second node P(n-1) of the n-1-th level gate drive circuit GDC(n-1), so that the first transistor T1 and the second transistor T2 are turned on or off according to the potential of the second node P(n-1) of the n-1-th level gate drive circuit GDC(n-1).

[0037] Please continue reading Figure 4 The output control module 103 includes a fourth transistor T4, a fifth transistor T5 and a first capacitor C1.

[0038] An input terminal of the fourth transistor T4 is electrically connected to the first node K of the gate driving circuit at this stage.

[0039] The input end of the fifth transistor T5 is electrically connected to the output end of the fourth transistor T4 , and the output end of the fifth transistor T5 is electrically connected to the third node Q of the current-stage gate driving circuit.

[0040] A first end of the first capacitor C1 is electrically connected to the control end of the fourth transistor T4 , and a second end of the first capacitor C1 is electrically connected to the output end of the fourth transistor T4 .

[0041] Among them, the control end of at least one of the fourth transistor T4 and the fifth transistor T5 is electrically connected to the second node P of the previous gate driving circuit, so that at least one of the fourth transistor T4 and the fifth transistor T5 is no longer controlled by the first gate control signal Nscan output by the previous gate driving circuit, thereby reducing the number of gate driving circuits controlled by the first gate control signal Nscan output from the first output end Nout of the previous gate driving circuit, and improving the problem of a large voltage drop of the first gate control signal Nscan output by the gate driving circuit.

[0042] Optionally, the control terminal of the fourth transistor T4 of the n-th stage gate driver circuit GDC(n) is electrically connected to the second node P(nB) of the nB-th stage gate driver circuit GDC(nB), so that the fourth transistor T4 of the n-th stage gate driver circuit GDC(n) is no longer controlled by the first gate control signal Nscan(nB) output by the nB-th stage gate driver circuit GDC(nB), thereby reducing the control of the first gate control signal Nscan(nB) output by the nB-th stage gate driver circuit GDC(nB) on other stages of gate driver circuits. Wherein, B≥1.

[0043] Optionally, in order to enable the gate drive circuit of this stage to output normally, A can be made less than B.

[0044] Optionally, the control end of the fourth transistor T4 of the n-th level gate driving circuit GDC(n) is electrically connected to the second node P(n-10) of the n-10th level gate driving circuit GDC(n-10) so that the fourth transistor T4 is turned on or off according to the potential of the second node P(n-10) of the n-10th level gate driving circuit GDC(n-10).

[0045] Please continue reading Figure 4 The control terminal of the fifth transistor T5 of the n-th stage gate driver circuit GDC(n) is electrically connected to the second node P(nC) of the nC-th stage gate driver circuit GDC(nC), so that the fifth transistor T5 of the n-th stage gate driver circuit GDC(n) is no longer controlled by the first gate control signal Nscan(nC) output by the nC-th stage gate driver circuit GDC(nC), thereby reducing the control of the first gate control signal Nscan(nC) output by the nC-th stage gate driver circuit GDC(nC) on other stages of gate driver circuits. Where C ≥ 1.

[0046] Optionally, in order to make the pulse width of the effective pulse of the second gate control signal Pscan output by the current gate drive circuit smaller than the pulse width of the effective pulse of the first gate control signal Nscan output by the current gate drive circuit, A <C<B。

[0047] Optionally, the control end of the fifth transistor T5 of the n-th level gate drive circuit GDC(n) is electrically connected to the second node P(n-2) of the n-2-th level gate drive circuit GDC(n-2), so that the fifth transistor T5 is turned on or off according to the potential of the second node P(n-2) of the n-2-th level gate drive circuit GDC(n-2).

[0048] Please continue reading Figure 4 , the first output module 102 includes a first output transistor To1 and a second output transistor To2.

[0049] The control end of the first output transistor To1 is electrically connected to the first node K of the gate driving circuit at this stage, and the input end of the first output transistor To1 is configured to receive the second power signal NVGL.

[0050] The control end of the second output transistor To2 is electrically connected to the first node K of the gate drive circuit of this stage, the input end of the second output transistor To2 is configured to receive the third power supply signal NVGH, and the output end of the second output transistor To2 and the output end of the first output transistor To1 are electrically connected to the first output end Nout of the gate drive circuit of this stage.

[0051] Please continue reading Figure 4 , the first node control module 101 includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0052] The first control terminal and the second control terminal of the sixth transistor T6 are configured to receive the corresponding first clock signal XCK, and the input terminal of the sixth transistor T6 is electrically connected to the first node K.

[0053] The control end of the seventh transistor T7 is electrically connected to the second node P of the current gate driving circuit. The input end of the seventh transistor T7 is configured to receive the first power signal PVGH. The output end of the seventh transistor T7 is electrically connected to the output end of the sixth transistor T6.

[0054] The control end of the eighth transistor T8 is electrically connected to the second node P of the gate drive circuit of this stage, the input end of the eighth transistor T8 is configured to be electrically connected to receive the second power signal NVGL, and the output end of the eighth transistor T8 is electrically connected to the first node K of the gate drive circuit of this stage.

[0055] Please continue reading Figure 4 The second output module 104 includes a third output transistor To3, a fourth output transistor To4 and a second capacitor C2.

[0056] The control end of the third output transistor To3 is electrically connected to the third node Q of the gate driving circuit at this stage, and the input end of the third output transistor To3 is configured to receive the corresponding second clock signal CK.

[0057] The control terminal of the fourth output transistor To4 is electrically connected to the second node P of the gate drive circuit of this stage. The input terminal of the fourth output transistor To4 is configured to receive the first power signal PVGH. The output terminal of the third output transistor To3 and the output terminal of the fourth output transistor To4 are electrically connected to the second output terminal Pout(n) of the gate drive circuit of this stage.

[0058] A first end of the second capacitor C2 is electrically connected to the control end of the third output transistor To3 , and a second end of the second capacitor C2 is electrically connected to the output end of the third output transistor To3 .

[0059] Please continue reading Figure 4 At least one gate driving circuit GDC further includes a second node control module 105 , and the second node control module 105 includes a ninth transistor T9 and a tenth transistor T10 .

[0060] The control end of the ninth transistor T9 is electrically connected to the first node K of the current gate driving circuit, the input end of the ninth transistor T9 is configured to receive the first power signal PVGH, and the output end of the ninth transistor T9 is electrically connected to the second node P of the current gate driving circuit.

[0061] The control end of the tenth transistor T10 is electrically connected to the first node K of the current gate driving circuit, the input end of the tenth transistor T10 is configured to receive the fourth power signal PVGL, and the output end of the tenth transistor T10 is electrically connected to the second node P of the current gate driving circuit.

[0062] It can be understood that the control terminal of the first transistor of the first-stage gate driving circuit in the multi-stage gate driving unit is configured to receive the start signal stv, the control terminal of the fourth transistor is configured to receive the corresponding control signal to keep it turned on (such as if the fourth transistor is a P-type transistor, it receives the low-level signal VGL), and the control terminal of the fifth transistor is configured to receive the corresponding control signal to keep it turned on. Figure 3B to Figure 3H STV corresponds to the control terminal of the first transistor, RST1 corresponds to the control terminal of the fourth transistor, and RST2 corresponds to the control terminal of the fifth transistor.

[0063] Since the potentials of the first gate control signal Nscan and the second node P are both generated by the potential of the first node K through the inverter (i.e., the ninth transistor T9 and the tenth transistor T10, the first output transistor To1 and the second output transistor To2), the potential change of the second node P is the same as the first gate control signal Nscan. Therefore, the potential of the second node P(nA) of the nA-th level gate drive circuit GDC(nA) can be used to replace the first gate control signal Nscan(nA) output by the nA-th level gate drive circuit GDC(nA) to control the conduction or cutoff of the first transistor T1 and the second transistor T2 of the n-th level gate drive circuit GDC(n); the potential of the second node P(nB) of the nB-th level gate drive circuit GDC(nB) can be used to replace the first gate control signal Nscan(nB) output by the nB-th level gate drive circuit GDC(nB) to control the conduction or cutoff of the n-th level gate drive circuit GDC (n) is turned on or off; the potential of the second node P(nC) of the nC-th gate driving circuit GDC(nC) can be used to replace the first gate control signal Nscan(nC) output by the nC-th gate driving circuit GDC(nC) to control the conduction or cutoff of the fifth transistor T5 of the n-th gate driving circuit GDC(n), so as to reduce the control of the first gate control signal Nscan output by each stage of gate driving circuit on the remaining stages of gate driving circuits without changing the output principle of the gate driving circuit, thereby improving the problem of voltage drop of the first gate control signal Nscan.

[0064] Since the high level output by the first gate control signal Nscan is generated by the third power supply signal NVGH, in the application Figure 1A In the gate drive unit of the gate drive circuit shown, during the stage transmission process of the multi-stage gate drive circuit, the third power supply signal NVGH needs to participate in the operation of the three-stage gate drive circuit at the same time. Therefore, the voltage drop generated by the third power supply signal NVGH is large, resulting in a large voltage drop of the first gate control signal Nscan. Therefore, it is also possible to increase the transmission path for transmitting the second power supply signal NVGL and the third power supply signal NVGH so that the first output module 102 of the multi-stage gate drive circuit receives the corresponding second power supply signal NVGL and the third power supply signal NVGH through different power lines (such as Figure 3B to Figure 3H As shown), instead of the first output module 102 of the multi-stage gate drive circuit receiving the corresponding second power signal NVGL through the same power line, receiving the corresponding third power signal NVGH through the same power line (as shown), Figure 3H(as shown in the figure) to reduce the load carried by the second power signal NVGL or the third power signal NVGH transmitted on a power line, thereby improving the voltage drop problem of the first gate control signal Nscan. At the same time, the pull-down coupling period of the first gate control signal Nscan can be lengthened to reduce the matching effect between the first gate control signal Nscan and the second gate control signal Pscan.

[0065] Please continue reading Figure 3B to Figure 3D The input end of the first output transistor To1 of the odd-numbered gate driving circuit (such as GDC (1), GDC (3), ...) is electrically connected to the first sub-power line NLL1 transmitting the second power signal NVGL, and the input end of the second output transistor To2 of the odd-numbered gate driving circuit is electrically connected to the second sub-power line NHL1 transmitting the third power signal NVGH; the input end of the first output transistor To1 of the even-numbered gate driving circuit (such as GDC (2), GDC (4), ...) is electrically connected to the third sub-power line NLL2 transmitting the second power signal NVGL, and the input end of the second output transistor To2 of the even-numbered gate driving circuit is electrically connected to the second sub-power line NHL1 transmitting the third power signal NVGH. The fourth sub-power line NHL2 of the third power signal NVGH is electrically connected so that the two adjacent gate drive circuits receive the corresponding second power signal NVGL and third power signal NVGH through different power lines, thereby lengthening the period in which the voltage drop problem of the first gate control signal Nscan occurs, and then making the part of the first gate control signal Nscan without the voltage drop problem overlap with the second gate control signal Pscan, so that the display panel using the gate drive unit can realize the normal writing of the data signal when receiving the corresponding first gate control signal Nscan and the second gate control signal Pscan, thereby improving the problem of uneven display on the display panel.

[0066] in, Figure 3B A plurality of gate drive circuits are cascaded when the first gate control signal Nscan(n-1) output by the corresponding n-1th-level gate drive circuit GDC(n-1) is output to the control end of the first transistor T1 of the n-level gate drive circuit GDC(n), the second node P(n-10) of the n-10th-level gate drive circuit GDC(n-10) is electrically connected to the control end of the fourth transistor T4 of the n-level gate drive circuit GDC(n), and the second node P(n-2) of the n-2nd-level gate drive circuit GDC(n-2) is electrically connected to the control end of the fifth transistor T5 of the n-level gate drive circuit GDC(n).

[0067] Figure 3CThe second node P(n-1) of the corresponding n-1th-level gate driving circuit GDC(n-1) is electrically connected to the control end of the first transistor T1 of the n-level gate driving circuit GDC(n), the first gate control signal Nscan(n-10) output by the n-10th-level gate driving circuit GDC(n-10) is output to the control end of the fourth transistor T4 of the n-level gate driving circuit GDC(n), and the second node P(n-2) of the n-2nd-level gate driving circuit GDC(n-2) is electrically connected to the control end of the fifth transistor T5 of the n-level gate driving circuit GDC(n). In this case, a plurality of gate driving circuits are cascaded.

[0068] Figure 3D The second node P(n-1) of the corresponding n-1th-level gate driving circuit GDC(n-1) is electrically connected to the control end of the first transistor T1 of the n-level gate driving circuit GDC(n), the second node P(n-10) of the n-10th-level gate driving circuit GDC(n-10) is electrically connected to the control end of the fourth transistor T4 of the n-level gate driving circuit GDC(n), and the first gate control signal Nscan(n-2) output by the n-2nd-level gate driving circuit GDC(n-2) is output to the control end of the fifth transistor T5 of the n-level gate driving circuit GDC(n). In this case, a plurality of gate driving circuits are cascaded.

[0069] Optionally, if the first gate control signal Nscan output by each gate driving circuit is only received by one gate driving circuit (eg Figure 3B to Figure 3D Any of the cascade forms shown), then, a first sub-power line NLL1 to a fourth sub-power line NHL2 can be set, so that the two adjacent gate drive circuits receive the corresponding second power signal NVGL and the third power signal NVGH through different power lines through the first sub-power line NLL1 to the fourth sub-power line NHL2, which can improve the voltage drop problem of the first gate control signal Nscan while making the load regularity of the multi-stage gate drive circuit more uniform without long-period regular changes.

[0070] Optionally, see Figure 3H The first sub-power line NLL1 and the third sub-power line NLL2 are electrically connected to the first power bus NLB so that the second power signal NVGL is generated through the same power management chip and other devices, thereby reducing the control complexity while keeping the second power signal NVGL received by the gate driving circuits at all levels synchronized.

[0071] Optionally, the second sub-power line NHL1 and the fourth sub-power line NHL2 are electrically connected to the second power bus NHB so that the third power signal NVGH can be generated through the same power management chip or other devices, so as to reduce the control complexity while keeping the third power signal NVGH received by the gate drive circuits at each level synchronized.

[0072] Optionally, the adjacent three-stage gate drive circuits can receive the corresponding second power signal NVGL and third power signal NVGH through different power lines to improve the voltage drop problem of the first gate control signal Nscan while making the load pattern of the multi-stage gate drive circuit uniform.

[0073] Please continue reading Figure 3E to Figure 3G , the input end of the first output transistor To1 of the (1+3m)-stage gate driving circuit is electrically connected to the first sub-power line NLL1 transmitting the second power signal NVGL, and the input end of the second output transistor To2 of the (1+3m)-stage gate driving circuit is electrically connected to the second sub-power line NHL1 transmitting the third power signal NVGH; the input end of the first output transistor To1 of the (2+3m)-stage gate driving circuit is electrically connected to the third sub-power line NLL2 transmitting the second power signal NVGL, and the input end of the second output transistor To2 of the (2+3m)-stage gate driving circuit is electrically connected to the fourth sub-power line NHL2 transmitting the third power signal NVGH The input end of the first output transistor To1 of the (3+3m)-stage gate drive circuit is electrically connected to the fifth sub-power line NLL3 transmitting the second power signal NVGL, and the input end of the second output transistor To2 of the (3+3m)-stage gate drive circuit is electrically connected to the sixth sub-power line NHL3 transmitting the third power signal NVGH, so that the three adjacent stages of the gate drive circuit receive the corresponding second power signal NVGL and third power signal NVGH through different power lines, thereby causing the portion of the first gate control signal Nscan without a voltage drop problem to overlap with the second gate control signal Pscan, thereby improving the display unevenness problem that occurs in a display panel using the gate drive unit. Wherein, m≥0.

[0074] Optionally, the first gate control signal Nscan output by each stage of the gate driving circuit is only received by one stage of the gate driving circuit (eg Figure 3E to Figure 3G Any of the cascade methods shown), then, a first sub-power line NLL1 to a sixth sub-power line NHL3 can be set to enable the adjacent three-stage gate driving circuits to receive the corresponding second power signal NVGL and third power signal NVGH through different power lines through the first sub-power line NLL1 to the sixth sub-power line NHL3.

[0075] Optionally, the first gate control signal Nscan output by each stage of the gate driving circuit is received by only two stages of the gate driving circuits (e.g., the first gate control signal Nscan(nA) output by the nA-th stage gate driving circuit GDC(nA) is output to the control end of the first transistor T1 of the n-th stage gate driving circuit GDC(n), the first gate control signal Nscan(nB) output by the nB-th stage gate driving circuit GDC(nB) is output to the control end of the fourth transistor T4 of the n-th stage gate driving circuit GDC(n), and the first gate control signal Nscan(nB) output by the nC-th stage gate driving circuit is output to the control end of the fourth transistor T5 of the n-th stage gate driving circuit GDC(n). The second node P(nC) of the gate driver circuit GDC(nC) is electrically connected to the control terminal of the fifth transistor T5 of the n-th gate driver circuit GDC(n); or, the first gate control signal Nscan(nA) output by the nA-th gate driver circuit GDC(nA) is output to the control terminal of the first transistor T1 of the n-th gate driver circuit GDC(n), and the first gate control signal Nscan(nB) output by the nB-th gate driver circuit GDC(nB) is output to the control terminal of the fourth transistor T4 of the n-th gate driver circuit GDC(n). The first gate control signal Nscan(nC) output by the nC-th gate driving circuit GDC(nC) is output to the control terminal of the fifth transistor T5 of the n-th gate driving circuit GDC(n); or, the second node P(nA) of the nA-th gate driving circuit GDC(nA) is electrically connected to the control terminal of the first transistor T1 of the n-th gate driving circuit GDC(n), and the first gate control signal Nscan(nB) output by the nB-th gate driving circuit GDC(nB) is output to the control terminal of the n-th gate driving circuit GDC(n); DC(n), and the first gate control signal Nscan(nC) output by the nC-th level gate driving circuit GDC(nC) is output to the control terminal of the fifth transistor T5 of the n-th level gate driving circuit GDC(n)). Then, a first sub-power line NLL1 to a sixth sub-power line NHL3 can be set to enable the adjacent three-level gate driving circuits to receive the corresponding second power signal NVGL and third power signal NVGH through different power lines through the first sub-power line NLL1 to the sixth sub-power line NHL3.

[0076] Optionally, see Figure 3H The first sub-power line NLL1, the third sub-power line NLL2 and the fifth sub-power line NLL3 are electrically connected to the first power bus NLB; the second sub-power line NHL1, the fourth sub-power line NHL2 and the sixth sub-power line NHL3 are electrically connected to the second power bus NHB.

[0077] Optionally, the voltage drop of the second power signal NVGL and the third power signal NVGH may be reduced by reducing the wiring resistance for transmitting the second power signal NVGL and the third power signal NVGH, thereby improving the voltage drop problem of the first gate control signal Nscan.

[0078] For example, the square resistance of the first power bus NLB is smaller than the square resistance of the first sub power line NLL1 , and the square resistance of the first power bus NLB is smaller than the square resistance of the third sub power line NLL2 .

[0079] Similarly, the square resistance of the second power bus NHB is smaller than the square resistance of the second sub-power line NHL1 , and the square resistance of the second power bus NHB is smaller than the square resistance of the fourth sub-power line NHL2 .

[0080] Optionally, the square resistance of the first power bus NLB can be made smaller than the square resistance of the first sub-power line NLL1 and the third sub-power line NLL2 by making the routing width of the first power bus NLB larger than that of the first sub-power line NLL1 and the third sub-power line NLL2; the square resistance of the first power bus NLB can also be adjusted by setting the first power bus NLB as a multi-layer routing so that the square resistance of the first power bus NLB is smaller than that of the first sub-power line NLL1 and the third sub-power line NLL2.

[0081] Similarly, the square resistance of the second power bus NHB can be made smaller than the square resistances of the second sub-power line NHL1 and the fourth sub-power line NHL2 by making the routing width of the second power bus NHB larger than that of the second sub-power line NHL1 and the fourth sub-power line NHL2; the square resistance of the second power bus NHB can also be adjusted by setting the second power bus NHB as a multi-layer routing line, so that the square resistance of the second power bus NHB is smaller than that of the second sub-power line NHL1 and the fourth sub-power line NHL2.

[0082] Since the voltage drops of the second power signal NVGL and the third power signal NVGH are not only related to the driving capability but also to the parasitic capacitance of the first output transistor To1 and the second output transistor To2, the pull-down effect on the first gate control signal Nscan can be reduced by adjusting the parameters of the first output transistor To1 and the second output transistor To2.

[0083] Optionally, the channel width of the first output transistor To1 can be reduced to reduce the pull-down effect of the second power signal NVGL on the first gate control signal Nscan; the channel width of the second output transistor To2 can be reduced to reduce the pull-down effect of the voltage drop of the third power signal NVGH on the first gate control signal Nscan.

[0084] Optionally, the channel width of the first output transistor To1 is less than 288 microns, and the channel width of the second output transistor To2 is less than 186 microns, so that the channel widths of the first output transistor To1 and the second output transistor To2 are smaller than those of the existing design, thereby reducing the pull-down effect of the voltage drop of the second power supply signal NVGL and the third power supply signal NVGH on the first gate control signal Nscan.

[0085] It is understandable that for display panels of different sizes and performances, the channel widths of the first output transistor To1 and the second output transistor To2 may be different. Therefore, the channel widths of the first output transistor To1 and the second output transistor To2 may be adjusted according to actual needs.

[0086] Please continue reading Figure 3B to Figure 3H Multi-stage gate drive circuits can share four clock signals (i.e., CK1, CK2, CK3, and CK4). Each gate drive circuit uses two of the four clock signals as the first clock signal XCK and the second clock signal CK, respectively. Two adjacent gate drive units share a clock signal, and this shared clock signal serves as the second clock signal CK for the subsequent-stage gate drive circuit and the first clock signal XCK for the preceding-stage gate drive circuit. Taking the 1st to 5th level gate drive circuits as an example, the first clock signal CK1 serves as the second clock signal CK of the 1st level gate drive circuit, the second clock signal CK2 serves as the first clock signal XCK of the 1st level gate drive circuit, and the second clock signal CK2 serves as the second clock signal CK of the 2nd level gate drive circuit; the third clock signal CK3 serves as the first clock signal XCK of the 2nd level gate drive circuit, and the third clock signal CK3 serves as the second clock signal CK of the 3rd level gate drive circuit; the fourth clock signal CK4 serves as the first clock signal XCK of the 3rd level gate drive circuit, and the fourth clock signal CK4 serves as the second clock signal CK of the 4th level gate drive circuit; the first clock signal CK1 serves as the first clock signal XCK of the 4th level gate drive circuit, and the first clock signal CK1 serves as the second clock signal CK of the 5th level gate drive circuit, and the second clock signal CK2 serves as the first clock signal XCK of the 5th level gate drive circuit, so that the 1st level gate drive circuit and the 5th level gate drive circuit apply the same clock signal, and so on, thereby obtaining the clock signals corresponding to the remaining levels of gate drive circuits.

[0087] Figures 5A to 5D yes Figure 4In the timing diagram corresponding to the gate drive circuit shown, the first transistor T1 to the tenth transistor T10 and the first output transistor To1 to the fourth output transistor To4 are N-type transistors. The control end of the first transistor T1 of the n-stage gate drive circuit GDC(n) is controlled by the first gate control signal Nscan(n-1) output by the n-1-stage gate drive circuit GDC(n-1), the control end of the fourth transistor T4 of the n-stage gate drive circuit GDC(n) is controlled by the second node P(n-10) of the n-10-stage gate drive circuit GDC(n-10), and the control end of the fifth transistor T5 of the n-stage gate drive circuit GDC(n) is controlled by the second node P(n-2) of the n-2-stage gate drive circuit GDC(n-2). The n-stage gate drive circuit GDC(n) corresponds to the first clock signal CK1 as the second clock signal CK, and the n-stage gate drive circuit GDC(n) corresponds to the second clock signal CK1 as the first clock signal XCK. The working principle of the n-stage gate drive circuit GDC(n) is briefly described.

[0088] In the first stage t1, the first clock signal XCK is at a low level, the second clock signal CK is at a high level, the second node P(n-10) of the n-10th-level gate drive circuit GDC(n-10) is at a high level, the potential of the second node P(n-2) of the n-2nd-level gate drive circuit GDC(n-2) is at a low level, and the first gate control signal Nscan(n-1) output by the n-1st-level gate drive circuit GDC(n-1) is at a low level.

[0089] The first transistor T1, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 of the n-th stage gate drive circuit GDC(n) are turned on, the first power signal PVGH is transmitted to the first node K(n), the tenth transistor T10 and the first output transistor To1 are turned on, the second power signal NVGL is transmitted to the first output terminal Nout(n), the fourth power signal PVGL is transmitted to the second node P(n), the seventh transistor T7 and the fourth output transistor To4 are turned on, and the first power signal PVGH is transmitted to the second output terminal Pout(n).

[0090] In the second stage t2, the first clock signal XCK is at a high level, the second clock signal CK is at a low level, the second node P(n-10) of the n-10th-level gate drive circuit GDC(n-10) is at a low level, the potential of the second node P(n-2) of the n-2nd-level gate drive circuit GDC(n-2) is at a high level, and the first gate control signal Nscan(n-1) output by the n-1st-level gate drive circuit GDC(n-1) is at a high level.

[0091] The second transistor T2 of the n-th stage gate drive circuit GDC(n) is turned on, and the fourth power signal PVGL is transmitted to the output end of the first transistor T1 (i.e., point O). However, since the third transistor T3 is turned off, the second power signal NVGL is still transmitted to the first output end Nout(n), and the first power signal PVGH is still transmitted to the second output end Pout(n).

[0092] In the third stage t3, the first clock signal XCK is at a low level, the second clock signal CK is at a high level, the second node P(n-10) of the n-10th-level gate drive circuit GDC(n-10) is at a low level, the potential of the second node P(n-2) of the n-2nd-level gate drive circuit GDC(n-2) is at a high level, and the first gate control signal Nscan(n-1) output by the n-1st-level gate drive circuit GDC(n-1) is at a high level.

[0093] The second transistor T2, third transistor T3, fourth transistor T4, and sixth transistor T6 of the n-stage gate driver circuit GDC(n) are turned on, the fourth power signal PVGL is transmitted to the first node K(n), the ninth transistor T9 and the second output transistor To2 are turned on, the first power signal PVGH is transmitted to the second node P(n), the eighth transistor T8 is turned on, the first output transistor To1 is turned off, and the third power signal NVGH is transmitted to the first output terminal Nout(n). Because the fifth transistor T5 is turned off, the output state of the second output terminal Pout(n) remains the same as in the previous stage.

[0094] In the fourth stage t4, the first clock signal XCK and the second clock signal CK are at a high level, the second node P(n-10) of the n-10th-level gate drive circuit GDC(n-10) is at a low level, the potential of the second node P(n-2) of the n-2nd-level gate drive circuit GDC(n-2) is at a low level, and the first gate control signal Nscan(n-1) output by the n-1st-level gate drive circuit GDC(n-1) is at a high level.

[0095] The fifth transistor T5 of the n-th stage gate driving circuit GDC(n) is turned on, the first node K(n) is electrically connected to the control end of the third transistor T3, the third transistor T3 is turned on, and the second clock signal CK is transmitted to the second output end Pout(n).

[0096] In the fifth stage t5, the first clock signal XCK is at a high level, the second clock signal CK is at a low level, the second node P(n-10) of the n-10th-level gate drive circuit GDC(n-10) is at a low level, the potential of the second node P(n-2) of the n-2nd-level gate drive circuit GDC(n-2) is at a low level, and the first gate control signal Nscan(n-1) output by the n-1st-level gate drive circuit GDC(n-1) is at a low level.

[0097] The first transistor T1 of the n-th stage gate driver circuit GDC(n) is turned on, and the first power signal PVGH is transmitted to the output terminal of the first transistor T1. Since the third transistor T3 is turned off, the second clock signal CK is still transmitted to the second output terminal Pout(n), so that the second gate control signal Pscan(n) output by the second output terminal Pout(n) is in a low state.

[0098] In the sixth stage t6, the first clock signal XCK is at a low level, the second clock signal CK is at a high level, the second node P(n-10) of the n-10th-level gate drive circuit GDC(n-10) is at a low level, the potential of the second node P(n-2) of the n-2nd-level gate drive circuit GDC(n-2) is at a low level, and the first gate control signal Nscan(n-1) output by the n-1st-level gate drive circuit GDC(n-1) is at a low level.

[0099] The first transistor T1, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 of the n-th stage gate drive circuit GDC(n) are turned on, the first power signal PVGH is transmitted to the first node K(n), the tenth transistor T10 and the first output transistor To1 are turned on, the second power signal NVGL is transmitted to the first output terminal Nout(n), the fourth power signal PVGL is transmitted to the second node P(n), the seventh transistor T7 and the fourth output transistor To4 are turned on, and the first power signal PVGH is transmitted to the second output terminal Pout(n).

[0100] Since reducing the channel width of the first output transistor To1 and the second output transistor To2 will lead to a decrease in the driving capability of the gate drive circuit, the delay of the first gate control signal Nscan will increase. Moreover, the output end of the first transistor T1 transmits the first power signal PVGH or the fourth power signal PVGL to the first node K through the third transistor T3 controlled by the first clock signal XCK. Therefore, when the first clock signal XCK simultaneously controls the first output transistor To1 to be turned on, the load corresponding to the output end of the first transistor T1 increases, resulting in the high level of the output end of the first transistor T1 (i.e., point O) cannot be maintained, and a "pit" appears (such as Figure 5BA shown in the figure), which affects the normal conduction of the first output transistor To1, so that the output capability of the first gate control signal Nscan is deteriorated.

[0101] Therefore, in order to improve the problem that the high level at the output end of the first transistor T1 cannot be maintained and a “pit” occurs, and to improve the change delay of the potential of the first node K, the channel width of the first transistor T1 can be adjusted.

[0102] Optionally, the writing capability of the first transistor T1 to the first power signal PVGH can be increased by increasing the channel width of the first transistor T1, so as to improve the pit problem occurring at the output end of the first transistor T1 and improve the change delay of the potential of the first node K corresponding to the pit problem occurring at the output end of the first transistor T1.

[0103] Optionally, the channel width of the first transistor T1 is greater than 4.95 microns, so that the channel width of the first transistor T1 is greater than that of existing designs. It is understood that the channel width of the first transistor T1 may vary for display panels of different sizes and performance. Therefore, the channel width of the first transistor T1 may be adjusted according to actual needs.

[0104] Please continue reading Figure 5C to Figure 5D The inventors conducted simulation verification on a design that reduces the channel width of the first output transistor To1 and the second output transistor To2, and increases the channel width of the first transistor T1. Where W represents the channel width; W / L represents the width-to-length ratio; L1 corresponds to a reduction in the channel width of the second output transistor To2; L2 corresponds to an increase in the channel width of the first transistor T1; and L3 corresponds to a reduction in the channel width of the second output transistor To2 and an increase in the channel width of the first transistor T1.

[0105] Figure 5C to Figure 5D The simulation results show that as the channel width of the first transistor T1 increases, the high-level output capability of the output end of the first transistor T1 increases, the pull-down effect of the first output transistor To1 becomes smaller, and the impact on the output of the first gate control signal Nscan becomes smaller. The delay of the first gate control signal Nscan changing from a high level to a low level (that is, the change range changes from 5% to 95%) is reduced from 1.05 microseconds to 0.66 microseconds.

[0106] The channel width of the second output transistor To2 is reduced, the output load of the output end of the first transistor T1 is reduced, and the high-level voltage drop of the first gate control signal Nscan is reduced by about 0.2V.

[0107] The channel width of the first transistor T1 increases, the channel width of the second output transistor To2 decreases, the delay of the first gate control signal Nscan is increased by about 0.4 μs, and the voltage drop of the first gate control signal Nscan is improved by about 0.2 V.

[0108] The simulation of reducing the low-level voltage drop of the first gate control signal Nscan by reducing the channel width of the first output transistor To1, thereby reducing the voltage drop of the first gate control signal Nscan, is similar to the simulation of reducing the high-level voltage drop of the first gate control signal Nscan by reducing the channel width of the second output transistor To2, thereby reducing the voltage drop of the first gate control signal Nscan. Therefore, the simulation of reducing the channel width of the first output transistor To1 to reduce the low-level voltage drop of the first gate control signal Nscan will not be repeated.

[0109] Therefore, the design of reducing the channel width of the first output transistor To1 and the second output transistor To2 can be combined with the design of increasing the channel width of the first transistor T1 to achieve a reduction in the low-level voltage drop and the high-level voltage drop of the first gate control signal Nscan, and will not significantly worsen the delay of the first gate control signal Nscan during the period when it changes from a high level to a low level (i.e., the corresponding change amplitude is in the range of 5% to 95%).

[0110] The inventors conducted simulation verification on the gate drive circuit in which the control end of the fifth transistor T5 is electrically connected to the second node P(n-2) of the n-2-level gate drive circuit GDC(n-2). The simulation results show that when the control end of the fifth transistor T5 is converted from being controlled by the first gate control signal Nscan(n-2) output by the n-2-level gate drive circuit GDC(n-2) to being controlled by the second node P(n-2) of the n-2-level gate drive circuit GDC(n-2), the output load of the third power supply signal NVGH is reduced, and the voltage drop problem of the first gate control signal Nscan is improved, and the improvement is about 0.1V.

[0111] The inventors conducted simulation verification on the design of reducing the channel width of the first output transistor To1 and the second output transistor To2. According to the simulation results, when the channel width of the first output transistor To1 and the second output transistor To2 is reduced, the pull-down voltage drop of the first gate control signal Nscan can be reduced.

[0112] like Figure 6 is a structural diagram of a display panel provided by an embodiment of the present invention. The present invention further provides a display panel comprising any of the above-mentioned gate driving units.

[0113] Optionally, the display panel includes a display area 10 a and a non-display area 10 b located outside the display area 10 a , and the gate driving unit is located in the non-display area 10 b .

[0114] The display panel includes a plurality of sub-pixels Spi, at least one of which includes a light-emitting device Di and a pixel driving circuit for driving the light-emitting device Di to emit light.

[0115] Figure 7 : This is a structural diagram of a pixel driving circuit provided by an embodiment of the present invention. The pixel driving circuit includes a driving transistor Tdr, a compensation transistor Tc, a data transistor Tda, a first reset transistor Ti1, a second reset transistor Ti2, a first switching transistor Ts1, a second switching transistor Ts2, a first capacitor C1 and a light-emitting device.

[0116] The control end of the driving transistor Tdr is electrically connected to the output end of the first reset transistor Ti1 , the input end of the driving transistor Tdr is electrically connected to the output end of the first switch transistor Ts1 , and the output end of the driving transistor Tdr is electrically connected to the input end of the second switch transistor Ts2 .

[0117] The control terminal of the compensation transistor Tc is configured to receive a corresponding gate control signal. The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr. The output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.

[0118] The control end of the data transistor Tda is configured to receive a corresponding gate control signal, the input end of the data transistor Tda is configured to receive a corresponding data signal Data, and the output end of the data transistor Tda is electrically connected to the input end of the driving transistor Tdr.

[0119] The control terminal of the first reset transistor Ti1 is configured to receive a corresponding gate control signal, and the input terminal of the first reset transistor Ti1 is configured to receive a first reset signal Vi1.

[0120] The control terminal of the second reset transistor Ti2 is configured to receive a corresponding gate control signal, the input terminal of the second reset transistor Ti2 is configured to receive a second reset signal Vi2, and the output terminal of the second reset transistor Ti2 is electrically connected to the output terminal of the second switch transistor Ts2.

[0121] The control terminal of the first switch transistor Ts1 is configured to receive a corresponding light emitting control signal EM, and the input terminal of the first switch transistor Ts1 is electrically connected to the first voltage terminal VDD.

[0122] The control terminal of the second switch transistor Ts2 is configured to receive a corresponding light emitting control signal EM.

[0123] A first end of the first storage capacitor Cst1 is electrically connected to the first voltage end, and a second end of the first storage capacitor Cst1 is electrically connected to the control end of the driving transistor Tdr.

[0124] The anode of the light emitting device Di is electrically connected to the output terminal of the second switch transistor Ts2 , and the cathode of the light emitting device Di is electrically connected to the second voltage terminal VSS.

[0125] Optionally, the light emitting device Di includes at least one type of an organic light emitting diode, a sub-millimeter light emitting diode, and a micro light emitting diode.

[0126] Optionally, the control end of the compensation transistor Tc is configured to receive a first gate control signal Nscan, the control end of the data transistor Tda is configured to receive a second gate control signal Pscan, the first reset transistor Ti1 is configured to receive a third gate control signal Nscan_T4, and the control end of the second reset transistor Ti2 is configured to receive a fourth gate control signal Pscan2.

[0127] Optionally, the first gate control signal Nscan and the fourth gate control signal Pscan2 may be generated by the same gate driving unit or by different gate driving units.

[0128] Optionally, the second gate control signal Pscan and the fourth gate control signal Pscan2 may be generated by gate driving circuits of different stages of the same gate driving unit, or may be generated by different gate driving units.

[0129] Optionally, the control terminals of the first switching transistor Ts1 and the second switching transistor Ts2 may share the same light emitting control signal EM, or may use different light emitting control signals EM.

[0130] Optionally, the pixel driving circuit further includes a third reset transistor Ti3, wherein an input terminal of the third reset transistor Ti3 is configured to receive a third reset signal Vi3, an output terminal of the third reset transistor Ti3 is electrically connected to an input terminal of the driving transistor Tdr, and a control terminal of the third reset transistor Ti3 is electrically connected to a control terminal of the second reset transistor Ti2.

[0131] Optionally, the pixel driving circuit further includes a second storage capacitor Cst2, a first end of the second storage capacitor Cst2 is electrically connected to the control end of the data transistor Tda, and a second end of the second storage capacitor Cst2 is electrically connected to the control end of the driving transistor Tdr.

[0132] Optionally, at least one of the compensation transistor Tc and the first reset transistor Ti1 is an oxide transistor.

[0133] Optionally, at least one of the compensation transistor Tc and the first reset transistor Ti1 is an N-type transistor.

[0134] Optionally, the first output terminals Nout of the multiple gate driving circuits are electrically connected to the control terminals of the compensation transistors Tc of the multiple sub-pixels, and the second output terminals Pout(n) of the multiple gate driving circuits are electrically connected to the control terminals of the data transistors Tda of the multiple sub-pixels, so that the data transistors Tda and the compensation transistors Tc of the multiple sub-pixels are controlled by the gate driving unit, thereby realizing the writing of the data signal Data and the compensation function of the threshold voltage of the driving transistor Tdr.

[0135] like Figure 8 yes Figure 7 The timing diagram corresponding to the pixel driving circuit shown is taken as an example in which the data transistor Tda and the first reset transistor Ti1 included in the pixel driving circuit are N-type transistors, and the driving transistor Tdr, the third reset transistor Ti3, the second reset transistor Ti2, the first switch transistor Ts1, and the second switch transistor Ts2 are all P-type transistors, to briefly describe the working principle of the pixel driving circuit.

[0136] In the first reset phase tp1, the compensation transistor Tc, the second reset transistor Ti2 and the third reset transistor Ti3 are turned on, the third reset signal Vi3 resets the potentials of the input, control and output ends of the driving transistor Tdr, and the second reset signal Vi2 resets the anode potential of the light-emitting device Di.

[0137] In the second reset phase tp2, the first reset transistor Ti1 is turned on, and the first reset signal Vi1 resets the potential of the control terminal of the driving transistor Tdr. The compensation transistor Tc is turned on, and the first reset signal Vi1 resets the potential of the output terminal of the driving transistor Tdr.

[0138] In the data writing phase tp3 , the data transistor Tda and the compensation transistor Tc are turned on, and the data signal Data is written into the control terminal of the driving transistor Tdr.

[0139] In the third reset phase tp4, the second reset transistor Ti2 and the third reset transistor Ti3 are turned on, the third reset signal Vi3 resets the potential of the input terminal of the driving transistor Tdr, and the second reset signal Vi2 resets the anode potential of the light emitting device Di.

[0140] In the light emitting stage tp5 , the first switch transistor Ts1 and the second switch transistor Ts2 are turned on, and the driving transistor Tdr generates a driving current to drive the light emitting device Di to emit light.

[0141] Optionally, the first output terminals Nout of the plurality of gate driving circuits may also be electrically connected to the control terminals of the first reset transistors Ti1 of the plurality of sub-pixels.

[0142] Please continue reading Figure 6 The non-display area 10b includes a fan-out area 10c, and the display panel includes a first power connection line NLC, a second power connection line NHC, a first pin Pin1, and a second pin Pin2 located in the fan-out area 10c.

[0143] Among them, the first power connection line NLC is electrically connected to the first pin Pin1, and is electrically connected to multiple gate drive circuits through the power sub-line that transmits the second power signal NVGL, so that the first power bus NLB, the first sub-power line NLL1, the third sub-power line NLL2, etc. are electrically connected to the power management chip through the first pin Pin1 and the first power connection line NLC, and the second power signal NVGL is generated through the power management chip.

[0144] The second power connection line NHC is electrically connected to the second pin Pin2, and is electrically connected to multiple gate drive circuits through a power sub-line that transmits a third power signal NVGH, so that the second power bus NHB, the second sub-power line NHL1, the fourth sub-power line NHL2, etc. are electrically connected to the power management chip through the second pin Pin2 and the second power connection line NHC, and the third power signal NVGH is generated by the power management chip.

[0145] Optionally, the square resistance of the first power connection line NLC is smaller than the square resistance of the sub-power line transmitting each first power signal PVGH, and the square resistance of the second power connection line NHC is smaller than the square resistance of the sub-power line transmitting each second power signal NVGL, so as to reduce the low-level voltage drop of the first gate control signal Nscan by reducing the wiring resistance of the second power signal NVGL; and reduce the high-level voltage drop of the first gate control signal Nscan by reducing the wiring resistance of the third power signal NVGH.

[0146] Optionally, the square resistance of the first power connection line NLC can be made smaller than the square resistance of the first sub-power line NLL1 and the third sub-power line NLL2 by making the routing width of the first power connection line NLC larger than that of the first sub-power line NLL1 and the third sub-power line NLL2; the square resistance of the first power connection line NLC can also be adjusted by setting the first power connection line NLC as a multi-layer routing line, so that the square resistance of the first power connection line NLC is smaller than the square resistance of the first sub-power line NLL1 and the third sub-power line NLL2.

[0147] like Figure 9: This is a cross-sectional view of a multi-layer wiring provided by an embodiment of the present invention. The first power bus NLB or the first power connection line NLC can be prepared using the first gate layer GE1, the second gate layer GE2, the third gate layer GE3, and the first source-drain layer SD1 in the display panel. The first sub-power line NLL1 or the third sub-power line NLL2 can be prepared using the second source-drain layer SD2 and the third source-drain layer SD3. A first insulating layer GI1 is provided between the first gate layer GE1 and the second gate layer GE2, a first insulating layer GI1 and a second insulating layer GI2 are provided between the third gate layer GE3 and the second gate layer GE2, and a planar layer PLN is provided between the second source-drain layer SD2 and the third source-drain layer SD3. Optionally, the first insulating layer GI1 is made of SiNx, and the second insulating layer GI2 is made of SiO2.

[0148] It is understandable that the display panel further includes a first active layer, a second active layer, and other parts not shown, wherein the first active layer includes a silicon semiconductor and the second active layer includes an oxide semiconductor.

[0149] Similarly, the square resistance of the second power connection line NHC can be made smaller than the square resistances of the second sub-power line NHL1 and the fourth sub-power line NHL2 by making the routing width of the second power connection line NHC larger than that of the second sub-power line NHL1 and the fourth sub-power line NHL2; the square resistance of the second power connection line NHC can also be adjusted by setting the second power connection line NHC as a multi-layer routing line, so that the square resistance of the second power connection line NHC is smaller than that of the second sub-power line NHL1 and the fourth sub-power line NHL2.

[0150]

[0151] The inventors conducted simulations to verify a design that reduces the wiring resistance of the power bus and power connection lines to improve the voltage drop of the first gate control signal Nscan. The simulation results are shown in Table 1. R-WOA represents the resistance of the power connection lines in the fan-out area of ​​the display panel; R-BUS represents the resistance of the power bus.

[0152] According to the simulation results in Table 1, when the resistance of the first power bus NLB is reduced to 0.5 times the original resistance (i.e., the resistance corresponding to the case where the width of the first power bus NLB is equal to that of the first sub-power line NLL1, and the routing film layer of the first power bus NLB and the first sub-power line NLL1 is the same), and the resistance of the first power connection line NLC is reduced to 0.5 times the original resistance (i.e., the resistance corresponding to the case where the width of the first power connection line NLC is equal to that of the first sub-power line NLL1, and the routing film layer of the first power connection line NLC and the first sub-power line NLL1 is the same), the maximum voltage drop of the first gate control signal Nscan can be reduced by approximately 0.5V.

[0153] Therefore, in order to improve the voltage drop problem of the first gate control signal Nscan, the solution provided by this application is summarized as follows:

[0154] 1. A solution in which the first transistor T1 of the n-th gate driving circuit GDC(n) is controlled by the potential of the second node P(nA) of the nA-th gate driving circuit GDC(nA).

[0155] 2. A solution in which the fourth transistor T4 of the n-th gate driving circuit GDC(n) is controlled by the potential of the second node P(nB) of the nB-th gate driving circuit GDC(nB).

[0156] 3. A solution in which the fifth transistor T5 of the n-th gate driving circuit GDC(n) is controlled by the potential of the second node P(nC) of the nC-th gate driving circuit GDC(nC).

[0157] 4. A solution in which two or three adjacent gate drive circuits are connected to different power lines and access the second power signal NVGL.

[0158] 5. A solution in which two or three adjacent gate drive circuits are connected to different power lines and access the third power signal NVGH.

[0159] 6. A solution for reducing the wiring resistance of a power bus transmitting the second power signal NVGL.

[0160] 7. A solution for reducing the wiring resistance of a power bus transmitting the third power signal NVGH.

[0161] 8. A solution for reducing the channel width of the first output transistor To1.

[0162] 9. A solution for reducing the channel width of the second output transistor To2.

[0163] 10. A solution for increasing the channel width of the first transistor T1.

[0164] 11. A solution for reducing the wiring resistance of a power connection line transmitting the second power signal NVGL.

[0165] 12. A solution for reducing the wiring resistance of a power connection line transmitting the third power signal NVGH.

[0166] Among them, the above twelve plans can be implemented separately or in combination.

[0167] Table 2 is a comparison table of simulation parameters obtained by the inventors by superimposing different schemes. The NVGH-GOA resistance represents the resistance of the sub-power line and power bus that transmit the third power signal NVGH; the NVGH-WOA resistance represents the resistance of the power connection line that transmits the third power signal NVGH and is located in the fan-out area of ​​the display panel; the NVGL-GOA resistance represents the resistance of the sub-power line and power bus that transmits the second power signal NVGL; and the NVGL-WOA resistance represents the resistance of the power connection line that transmits the second power signal NVGL and is located in the fan-out area of ​​the display panel.

[0168]

[0169] According to the data in Table 2, it can be analyzed that by superimposing the designs of Schemes 6 to 12, the high-level voltage drop of the first gate control signal Nscan can be reduced by 1.17V, which is 0.27V greater than the conventional gate drive circuit simulation using 8 transistors; the low-level voltage drop of the first gate control signal Nscan is reduced by 0.99V, which is 0.2V greater than the conventional gate drive circuit simulation using 8 transistors; and the delay during the period when the first gate control signal Nscan changes from a high level to a low level is reduced by 0.4 microseconds.

[0170] Moreover, the channel width of the first output transistor To1 and the second output transistor To2 is reduced, which can reduce the frame size of the display panel using the gate driving unit (the frame size that can be saved is in the range of 50 microns to 60 microns), so that Figure 4 The border size occupied by the gate driving unit of the gate driving circuit structure shown when applied to a display panel can be equal to the border size occupied by the gate driving unit of a conventional gate driving circuit structure including 8 transistors, which is beneficial to reducing the border size of the display panel.

[0171] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A gate drive unit, characterized in that: The invention comprises a plurality of gate drive circuits, at least one of which comprises: a first node control module, electrically connected to the first node of the gate drive circuit of the current stage and the second node of the gate drive circuit of the current stage, and configured to transmit a first power signal to the first node according to the potential of the second node and a corresponding first clock signal, or to transmit a second power signal to the first node according to the potential of the second node; a first output module, electrically connected to the first node of the gate driving circuit of this stage and the first output end of the gate driving circuit of this stage, and configured to output the second power signal or the third power signal to the first output end according to the potential of the first node; an output control module, electrically connected to the first node of the gate drive circuit of this stage and the third node of the gate drive circuit of this stage, and configured to electrically connect the first node and the third node, or disconnect the electrical connection between the first node and the third node; and a second output module, electrically connected to the second node of the gate driving circuit of this stage, the third node of the gate driving circuit of this stage, and the second output end of the gate driving circuit of this stage, and configured to output the corresponding second clock signal or the first power supply signal to the second output end according to the potential of the second node and the potential of the third node; Wherein, at least one of the first node control module and the output control module is electrically connected to the second node of the previous gate driving circuit.

2. The gate driving unit according to claim 1, wherein: The first node control module of the n-th level gate driving circuit is electrically connected to the second node of the n-1-th level gate driving circuit, and the first node control module of the n-th level gate driving circuit is configured to transmit the first power signal or the fourth power signal to the first node according to the potential of the second node of the n-1-th level gate driving circuit and the corresponding first clock signal.

3. The gate driving unit according to claim 2, wherein: The first node control module includes: a first transistor, wherein an input terminal of the first transistor is configured to receive the first power signal; a second transistor, wherein a first control terminal and a second control terminal of the second transistor are electrically connected to the control terminal of the first transistor, an input terminal of the second transistor is configured to receive the fourth power signal, and an output terminal of the second transistor is electrically connected to the output terminal of the first transistor; and a third transistor, wherein a control terminal of the third transistor is configured to receive the corresponding first clock signal, an input terminal of the third transistor is electrically connected to the output terminal of the first transistor, and an output terminal of the third transistor is electrically connected to the first node; The control terminal of the first transistor of the n-th stage gate driving circuit is electrically connected to the second node of the (n-1)-th stage gate driving circuit.

4. The gate driving unit according to any one of claims 1 to 3, characterized in that: The output control module includes: a fourth transistor, wherein an input terminal of the fourth transistor is electrically connected to the first node; a fifth transistor, wherein an input terminal of the fifth transistor is electrically connected to the output terminal of the fourth transistor, and an output terminal of the fifth transistor is electrically connected to the third node of the gate driving circuit of this stage; and a first capacitor, wherein a first end of the first capacitor is electrically connected to the control end of the fourth transistor, and a second end of the first capacitor is electrically connected to the output end of the fourth transistor; The control terminal of at least one of the fourth transistor and the fifth transistor is electrically connected to the second node of the previous gate driving circuit.

5. The gate driving unit according to claim 4, wherein: The control terminal of the fourth transistor of the n-th stage gate driving circuit is electrically connected to the second node of the (n-10)-th stage gate driving circuit.

6. The gate driving unit according to claim 4, wherein: The control terminal of the fifth transistor of the n-th stage gate driving circuit is electrically connected to the second node of the (n-2)-th stage gate driving circuit.

7. The gate driving unit according to claim 1, wherein: The first output module includes: a first output transistor, wherein a control terminal of the first output transistor is electrically connected to the first node of the gate driving circuit of the current stage, and an input terminal of the first output transistor is configured to receive a second power signal; a second output transistor, wherein the control end of the second output transistor is electrically connected to the first node of the gate drive circuit of this level, the input end of the second output transistor is configured to receive a third power supply signal, and the output end of the second output transistor and the output end of the first output transistor are electrically connected to the first output end of the gate drive circuit of this level.

8. The gate driving unit according to claim 7, wherein: The input end of the first output transistor of the odd-numbered gate drive circuit is electrically connected to the first sub-power line that transmits the second power signal, and the input end of the second output transistor of the odd-numbered gate drive circuit is electrically connected to the second sub-power line that transmits the third power signal; the input end of the first output transistor of the even-numbered gate drive circuit is electrically connected to the third sub-power line that transmits the second power signal, and the input end of the second output transistor of the even-numbered gate drive circuit is electrically connected to the fourth sub-power line that transmits the third power signal.

9. The gate driving unit according to claim 7, wherein: The input terminal of the first output transistor of the gate driving circuit of the (1+3m)th level is electrically connected to the first sub-power line transmitting the second power signal, and the input terminal of the second output transistor of the gate driving circuit of the (1+3m)th level is electrically connected to the second sub-power line transmitting the third power signal; wherein m≥0; The input end of the first output transistor of the gate driving circuit of the (2+3m)th stage is electrically connected to the third sub-power line transmitting the second power signal, and the input end of the second output transistor of the gate driving circuit of the (2+3m)th stage is electrically connected to the fourth sub-power line transmitting the third power signal; The input end of the first output transistor of the (3+3m)th level gate driving circuit is electrically connected to the fifth sub-power line that transmits the second power signal, and the input end of the second output transistor of the (3+3m)th level gate driving circuit is electrically connected to the sixth sub-power line that transmits the third power signal.

10. The gate driving unit according to claim 8, wherein: The first sub-power line and the third sub-power line are electrically connected to the first power bus; The square resistance of the first power bus is smaller than the square resistance of the first sub-power line, and the square resistance of the first power bus is smaller than the square resistance of the third sub-power line.

11. The gate driving unit according to claim 8, wherein: The second sub-power line and the fourth sub-power line are electrically connected to the second power bus; The square resistance of the second power bus is smaller than the square resistance of the second sub-power line, and the square resistance of the second power bus is smaller than the square resistance of the fourth sub-power line.

12. The gate driving unit according to claim 7, wherein: The channel width of the first output transistor is less than 288 micrometers, and the channel width of the second output transistor is less than 186 micrometers.

13. The gate driving unit according to claim 3, wherein: The channel width of the first transistor is greater than 4.95 microns.

14. The gate driving unit according to claim 1, wherein: The first node control module includes a sixth transistor, a seventh transistor, and an eighth transistor; the first control terminal and the second control terminal of the sixth transistor are configured to receive the corresponding first clock signal, and the input terminal of the sixth transistor is electrically connected to the first node; the control terminal of the seventh transistor is electrically connected to the second node of the gate drive circuit of the current level, the input terminal of the seventh transistor is configured to receive the first power supply signal, and the output terminal of the seventh transistor is electrically connected to the output terminal of the sixth transistor; The control terminal of the eighth transistor is electrically connected to the second node of the gate driving circuit of the current stage, the input terminal of the eighth transistor is configured to be electrically connected to receive the second power supply signal, and the output terminal of the eighth transistor is electrically connected to the first node of the gate driving circuit of the current stage; The second output module includes a third output transistor, a fourth output transistor, and a second capacitor, wherein the control terminal of the third output transistor is electrically connected to the third node of the gate drive circuit of the current stage, and the input terminal of the third output transistor is configured to receive the corresponding second clock signal; the control terminal of the fourth output transistor is electrically connected to the second node of the gate drive circuit of the current stage, and the input terminal of the fourth output transistor is configured to receive the first power supply signal, and the output terminal of the third output transistor and the output terminal of the fourth output transistor are electrically connected to the second output terminal of the gate drive circuit of the current stage; the first terminal of the second capacitor is electrically connected to the control terminal of the third output transistor, and the second terminal of the second capacitor is electrically connected to the output terminal of the third output transistor; At least one of the gate drive circuits further includes a second node control module, the second node control module includes a ninth transistor and a tenth transistor, the control end of the ninth transistor is electrically connected to the first node of the gate drive circuit at this level, the input end of the ninth transistor is configured to receive the first power supply signal, and the output end of the ninth transistor is electrically connected to the second node of the gate drive circuit at this level; the control end of the tenth transistor is electrically connected to the first node of the gate drive circuit at this level, the input end of the tenth transistor is configured to receive the fourth power supply signal, and the output end of the tenth transistor is electrically connected to the second node of the gate drive circuit at this level.

15. A display panel, characterized in that: include: The gate drive unit according to any one of claims 1 to 14; as well as a plurality of sub-pixels, at least one of the sub-pixels comprising a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light, the pixel driving circuit comprising a driving transistor, a compensation transistor, and a data transistor, the input terminal of the compensation transistor and the output terminal of the compensation transistor being electrically connected between the control terminal of the driving transistor and the output terminal of the driving transistor, the input terminal of the data transistor being configured to receive a corresponding data signal, and the output terminal of the data transistor being electrically connected to the input terminal of the driving transistor; Among them, the first output ends of the multiple gate driving circuits are electrically connected to the control ends of the compensation transistors of the multiple sub-pixels, and the second output ends of the multiple gate driving circuits are electrically connected to the control ends of the data transistors of the multiple sub-pixels.

16. The display panel according to claim 15, wherein: The display panel includes a display area and a non-display area located outside the display area, wherein the non-display area includes a fan-out area; The display panel includes a first power connection line, a second power connection line, a first pin, and a second pin located in the fan-out area; the first power connection line is electrically connected to the first pin and is electrically connected to the plurality of gate drive circuits via a power sub-line that transmits a second power signal; the second power connection line is electrically connected to the second pin and is electrically connected to the plurality of gate drive circuits via a power sub-line that transmits a third power signal; In which, the plurality of sub-pixels are located in the display area, the gate driving unit is located in the non-display area, the square resistance of the first power connection line is smaller than the square resistance of the sub-power line transmitting each of the first power signals, and the square resistance of the second power connection line is smaller than the square resistance of the sub-power line transmitting each of the second power signals.

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