Electronic device

Abstract

An electronic device according to an embodiment of the present disclosure includes a first substrate, a first conductive line, a second conductive line, and a metal oxide semiconductor. The first conductive line is disposed on the first substrate. The second conductive wire is disposed on the first conductive wire and is electrically connected with the first conductive wire through the through hole. The metal oxide semiconductor crosses the first conductive line and the second conductive line. The electronic device provided by the embodiment of the invention can have an ideal display effect.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201910776051.6 and invention name “Electronic Device”. The filing date of the original application is August 21, 2019. Technical Field

[0002] The present disclosure is directed to an electronic device. Background Art

[0003] Electronic devices are continuously developing towards higher resolution, higher quality, etc. In most electronic devices, a driving layer is used to control electronic units (such as pixels), so the electrical characteristics and layout of the driving layer still need to be improved. Summary of the invention

[0004] The electronic device according to an embodiment of the present disclosure has a better display effect.

[0005] According to an embodiment of the present disclosure, an electronic device includes a first substrate, a first conductive line, a second conductive line, and a metal oxide semiconductor. The first conductive line is disposed on the first substrate. The second conductive line is disposed on the first conductive line and is electrically connected to the first conductive line via a through hole. The metal oxide semiconductor spans the first conductive line and the second conductive line.

[0006] According to an embodiment of the present disclosure, an electronic device includes a first substrate, a first conductive line, a second conductive line, and an oxide semiconductor. The first conductive line is disposed on the first substrate, extends along a first direction, and has a protruding portion protruding along a second direction, and the first direction is different from the second direction. The second conductive line overlaps the first conductive line and extends along the first direction. The semiconductor overlaps the protruding portion of the first conductive line.

[0007] In summary, in the electronic device of the embodiment of the present disclosure, a portion of the scan line includes two branches electrically connected in parallel. The arrangement of these two branches helps to reduce the overall impedance of the scan line. In this way, the driving layer can provide ideal driving performance, thereby helping to improve the display effect of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the figures of the accompanying drawings, some aspects are illustrated by way of example and not by way of limitation;

[0009] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 2 for Figure 1 A partial top view schematic diagram of a driving layer in an electronic device;

[0011] Figure 3 for Figure 2A partial schematic diagram of region A in the middle driving layer;

[0012] Figure 4 for Figure 3 An enlarged schematic diagram of region B of the driving layer;

[0013] Figure 5 for Figure 3 A schematic diagram of an implementation of a cross-sectional structure of a driving layer along section line II;

[0014] Figure 6 It is a partial top view schematic diagram of a driving layer according to another embodiment of the present disclosure;

[0015] Figure 7 for Figure 6 A schematic diagram of an embodiment of a cross-sectional structure of a driving layer along a section line II-II;

[0016] Figure 8 It is a partial top view schematic diagram of a driving layer according to another embodiment of the present disclosure;

[0017] Fig. 9 for Figure 8 A schematic diagram of an embodiment of a cross-sectional structure of a driving layer along section line III-III. DETAILED DESCRIPTION

[0018] A structure (or layer, component, substrate) described in the present disclosure is located on another structure (or layer, component, substrate), which may refer to the two structures being adjacent and directly connected, or may refer to the two structures being adjacent but not directly connected, and the indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate interval) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure, and the intermediate structure may be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is arranged "on" another structure, it may refer to that the certain structure is "directly" on the other structure, or it may refer to that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0019] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, resistors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but it is not limited to these.

[0020] In the present disclosure, the length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but the method is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0021] In the present disclosure, the various embodiments described below may be mixed and matched without departing from the spirit and scope of the present disclosure. For example, some features of one embodiment may be combined with some features of another embodiment to form another embodiment.

[0022] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0023] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure, and Figure 2 for Figure 1 A partial top view of the driving layer in the electronic device. Figure 1 and Figure 2The electronic device 100 includes a first substrate 110, a second substrate 120, a driving layer 130 and a dielectric layer 140. The first substrate 110 and the second substrate 120 are disposed opposite to each other and face to face. In at least some embodiments, the first substrate 110 and the second substrate 120 can be a hard substrate or a soft substrate, such as a transparent plastic substrate or a glass substrate. For example, the materials of the first substrate 110 and the second substrate 120 include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), liquid crystal polymers (LCP), rubber, glass fiber, ceramic, other suitable substrate materials, or a combination of the foregoing, but not limited thereto. The driving layer 130 and the dielectric layer 140 are both disposed between the first substrate 110 and the second substrate 120. The driving layer 130 is, for example, disposed on the first substrate 110 and between the first substrate 110 and the dielectric layer 140. The driving layer 130 can be used to drive the dielectric layer 140. The material of the dielectric layer 140 includes a liquid crystal material, an electrowetting display material, an electrophoretic display material, an organic light-emitting material, an inorganic light-emitting material, a quantum dot (QD) material, a fluorescence material, a phosphor material, other suitable materials, or a combination of the above materials, but not limited thereto. In some embodiments, the dielectric layer 140 may be a display dielectric layer, but not limited thereto. The electronic device 100 may be a display device, a sensing device, a lighting device, an antenna device, a splicing device, other suitable devices, or a combination of the above devices, but not limited thereto.

[0024] like Figure 2As shown, the driving layer 130 may include a plurality of scan lines 132 and a plurality of data lines 134, and the scan lines 132 intersect with the data lines 134 to define a driving pixel PX. For example, two adjacent scan lines 132 and two adjacent data lines 134 may define a driving pixel PX. In some embodiments, the scan lines 132 extend, for example, along a first direction D1, and the data lines 134 extend, for example, along a second direction D2, and the first direction D1 is different from the second direction D2. In some embodiments, the first direction D1 and the second direction D2 may be orthogonal to each other, but are not limited thereto. In addition, in some embodiments, the scan lines 132 and the data lines 134 are respectively linear conductive lines, but the present disclosure is not limited thereto. In other embodiments, at least one of the scan lines 132 and the data lines 134 is a non-linear conductive line. For example, when the scan line 132 is a non-linear conductive line, the conductive line may be formed by connecting multiple segments along the first direction D1, and the extension direction of some of the segments may intersect with the first direction D1. In this way, although some segments of the scan line 132 may not extend along the first direction D1, the overall extension direction of the scan line 132 (such as the connection line at two opposite ends) is still the first direction D1. When the data line 134 is a non-linear conductive line, it can also be understood as a similar layout method.

[0025] Figure 3 for Figure 2 A partial enlarged schematic diagram of area A in the middle driving layer, and Figure 4 for Figure 3 Please refer to the enlarged schematic diagram of the driving layer area B. Figure 2 and Figure 3 , the scan line 132 of the driving layer 130 may include a first scan line segment 1321 and a second scan line segment 1322. The first scan line segment 1321 is connected to the second scan line segment 1322, and for example, Figure 2 A single scan line 132 may be formed by a plurality of first scan line segments 1321 and a plurality of second scan line segments 1322 alternately connected along the first direction D1. In this embodiment, the first scan line segment 1321 and the second scan line segment 1322 may have different pattern designs. For example, the first scan line segment 1321 has an opening OP and includes a first branch 1321A and a second branch 1321B. The first branch 1321A and the second branch 1321B are located on opposite sides of the opening OP and are electrically connected in parallel to each other. The second scan line segment 1322 may be a single line segment without a plurality of branches.

[0026] In this embodiment, the opening OP is, for example, a closed opening, and the first branch 1321A and the second branch 1321B are located at opposite sides of the opening OP, such that there is a spacing distance S between the first branch 1321A and the second branch 1321B. Although the first branch 1321A and the second branch 1321B are spaced apart from each other, the first branch 1321A and the second branch 1321B may be connected together at opposite ends via opposite connecting portions 1321C and 1321D to surround the opening OP. In some embodiments, the first branch 1321A may have a first branch line width W1A, the second branch 1321B may have a second branch line width W1B, and the sum of the first branch line width W1A, the second branch line width W1B and the spacing distance S may be regarded as the first scan line width W1 of the first scan line segment 1321. The second scan line segment 1322 has a second scan line width W2, and the first scan line width W1 may be greater than the second scan line width W2. That is, the first scan line segment 1321 is the segment with the largest line width in the entire scan line 132. In some embodiments, the second scan line segment 1322 may have different segments with different line widths, and some of the segments may have a second scan line width W2'. In a possible implementation, the second scan line width W2' may be less than or equal to the sum of the first branch line width W1A and the second branch line width W1B.

[0027] In some embodiments, the first branch line width W1A may be the maximum width of the first branch 1321A measured in a direction perpendicular to the first direction D1, the second branch line width W1B may be the maximum width of the second branch 1321B measured in a direction perpendicular to the first direction D1, and the second scan line widths W2 and W2' may be the maximum widths of the second scan line segment 1322 measured in a direction perpendicular to the first direction D1. In some embodiments, the spacing distance S may be the maximum distance between the first branch 1321A and the second branch 1321B measured in a direction perpendicular to the first direction D1.

[0028] In this embodiment, the first branch line width W1A and the second branch line width W1B may be the same, but not limited thereto. In addition, the first scan line width W1 may be, for example, less than or equal to the spacing PS between two adjacent scan lines 132 (marked at Figure 2), and the spacing distance S between the first branch 1321A and the second branch 1321B may be, for example, less than or equal to one-fifth of the spacing PS between two adjacent scan lines 132. The so-called spacing PS between two adjacent scan lines 132 may be regarded as the distance between the middle lines of two adjacent scan lines 1324 in the direction perpendicular to the first direction D1, the minimum distance between the upper boundary lines of two adjacent scan lines 132 in the direction perpendicular to the first direction D1, or the minimum distance between the lower boundary lines of two adjacent scan lines 132 in the direction perpendicular to the first direction D1. The spacing distance S between the first branch 1321A and the second branch 1321B may be used to separate the first branch 1321A from the second branch 1321B, so the minimum value of the spacing distance S may be determined, for example, based on the capability of the manufacturing process.

[0029] In the present embodiment, the data line 134 may intersect with the first branch 1321A and / or the second branch 1321B. That is, the data line 134 may overlap with the first branch 1321A and / or overlap with the second branch 1321B in the top-view direction. Since the first branch 1321A and the second branch 1321B are electrically connected in parallel with each other, the impedance caused by the data line 134 to the first branch 1321A and the impedance caused by the data line 134 to the second branch 1321B are also connected in parallel with each other. Such impedance parallel connection will reduce the equivalent impedance caused by the data line 134 to the scan line 132, which helps to reduce the load of the scan line 132, thereby reducing the resistance-capacitance delay effect of the scan line 132. In this way, the signal transmission performance and quality of the scan line 132 can be improved. However, the present disclosure is not limited to this. In other embodiments, the data line 134 may overlap with other parts of the scan line 132 in the top-view direction, but is not limited to this.

[0030] exist Figure 3In the embodiment, the driving layer 130 may further include a semiconductor layer 136. The semiconductor layer 136 may include at least a first section 136A, a second section 136B, and a third section 136C, and the extension direction of the first section 136A is different from the extension direction of the second section 136B, and the extension direction of the first section 136A is different from the extension direction of the third section 136C. Here, the turning point between the first section 136A and the second section 136B and the turning point between the first section 136A and the third section 136C may be a non-right angle (arc angle) turning point. The first section 136A may intersect with the scan line 132, and the extension direction of the first section 136A may be approximately the second direction D2. In other words, the first section 136A may be approximately parallel to the extension direction (second direction D2) of the data line 134, or may be approximately parallel to a portion of the data line 134. The second section 136B is a section extending from one end of the first section 136A away from the data line 134, and the third section 136C is a section extending from the other end of the first section 136A toward the data line 134. The end of the third section 136C can be electrically connected to the data line 134, and the end of the second section 136B can be used to electrically connect to a pixel electrode (not shown). In other alternative embodiments, the extension direction of the first section 136A can be different from the second direction D2.

[0031] In addition, by Figure 3 It can be seen that the driving layer 130 may further include a shared line 138, and the shared line 138 also extends substantially along the first direction D1, but is not limited thereto. The shared line 138 may be formed by the same film layer or the same process as the scan line 132, and the shared line 138 may be interlaced with the data line 134. The shared line 138 may be electrically independent of the scan line 132.

[0032] exist Figure 3 and Figure 4 In the embodiment, the first segment 136A may intersect the first branch 1321A, the opening OP and the second branch 1321B. In this way, the semiconductor layer 136 may include a first channel region 1361, a second channel region 1362 and a middle region 1363 located between the first channel region 1361 and the second channel region 1362. The first channel region 1361 overlaps the first branch 1321A (for the clarity of the drawings, Figure 4 Not indicated, but can be referred to Figure 3 ) and the second channel region 1362 overlaps the second branch 1321B (for the clarity of the drawings, Figure 4 Not indicated, but can be referred to Figure 3 The middle area 1363 is, for example, located in the opening OP and does not overlap the first branch 1321A or the second branch 1321B. In other words, the middle area 1363 is located between the first branch 1321A and the second branch 1321B in a top view direction.

[0033] In this embodiment, the portion of the first branch 1321A overlapping the first channel region 1361 can be regarded as the first gate G1, the portion of the second branch 1321B overlapping the second channel region 1362 can be regarded as the second gate G2, the second section 136B of the semiconductor layer 136 can be regarded as the drain, and the third section 136C of the semiconductor layer 136 can be regarded as the source. In this way, the semiconductor layer 136 can define an active component (such as a thin film transistor) with a double gate (the first gate G1 and the second gate G2). Specifically, the second section 136B of the semiconductor layer 136 can be the drain region 1365, the third section 136C of the semiconductor layer 136 can be the source region 1367, and the first section 136A of the semiconductor layer 136 can include a low-doped region 1364, a first channel region 1361, a middle region 1363, a second channel region 1362, and a low-doped region 1366. The doping concentration of the low-doped region 1364, the low-doped region 1366 and the middle region 1363 is lower than that of the drain region 1365 and the source region 1367, and the doping concentration of the first channel region 1361 and the second channel region 1362 is lower than that of the low-doped region 1364, the low-doped region 1366 and the middle region 1363. The first channel region 1361 and the second channel region 1362 may also be undoped and substantially consist of an intrinsic semiconductor.

[0034] In some embodiments, the maximum length of the low-doped region 1364 in the second direction D2 is approximately half of the maximum length of the middle region 1363 in the second direction D2. Similarly, the maximum length of the low-doped region 1366 in the second direction D2 is approximately half of the maximum length of the middle region 1363 in the second direction D2. That is, the maximum length of the middle region 1363 is approximately two to three times the maximum length of the low-doped region 1364 or the low-doped region 1366, wherein the maximum length of the middle region 1363 may be substantially equal to the spacing distance S between the first branch 1321A and the second branch 1321B. In some embodiments, the maximum length of the low-doped region 1364 or the low-doped region 1366 in the second direction D2 may be in the range of 0.5 microns to 3.0 microns (0.5 microns ≤ maximum length ≤ 3.0 microns), or in the range of 1 micron to 2.5 microns (1 micron ≤ maximum length ≤ 2.5 microns), for example, 1.9 microns, 2 microns, 1.5 microns, or any other value in the range. In addition, the second segment 136B of the semiconductor layer 136 may be spaced apart from the scan line 132. In some embodiments, the distance DS between the second segment 136B and the scan line 132 may be at least half of the spacing distance S to ensure that the second segment 136B and the scan line 132 do not overlap in the top view direction. In some embodiments, the distance DS may be the maximum distance between the second segment 136B and the scan line 132 in the second direction D2.

[0035] In this embodiment, the first channel region 1361 , the middle region 1363 and the second channel region 1362 in the first section 136A are arranged along an arrangement direction, which can be regarded as an extension direction of the first section 136A.

[0036] The first channel region 1361 and the second channel region 1362 have a width WS1 and a width WS2, respectively. The width WS1 is the maximum width of the first channel region 1361 in a direction perpendicular to the second direction D2, and the width WS2 is the maximum width of the second channel region 1362 in a direction perpendicular to the second direction D2. In some embodiments, the width WS1 and the width WS2 may be the same. In this way, the component channel length and the component channel width defined by the first channel region 1361 may be equal to the component channel length and the component channel width defined by the second channel region 1362. In other words, the first channel region 1361 and the second channel region 1362 may define channels with the same aspect ratio.

[0037] In the present embodiment, the first channel region 1361 is separated from the data line 134 by a distance d. The distance d may be the maximum distance between the first channel region 1361 and the data line 134 in a direction perpendicular to the second direction D2. In some embodiments, the second channel region 1362 is separated from the data line 134 by a distance d' in a direction perpendicular to the second direction D2. In some embodiments, the distance d and the distance d' may be the same or different, and one of the distance d and the distance d' may be 0. For example, the semiconductor layer 136 may be arranged so that at least one of the first channel region 1361 and the second channel region 1362 does not overlap with the data line 134. In some embodiments, when the first channel region 1361 and the second channel region 1362 do not overlap with the data line 134, the electrical signal or voltage state of the first channel region 1361 and the second channel region 1362 is less likely to be affected by the electrical signal or voltage on the data line 134, that is, the coupling effect of the data line 134 on the first channel region 1361 and the second channel region 1362 is less obvious, which helps to stabilize the performance of the first channel region 1361 and the second channel region 1362, so that the pixel layer 130 provides a better driving effect. In some embodiments, the distance d can be greater than or equal to 1 micrometer (μm) and can be less than or equal to the distance PD between the two data lines 134 (marked at Figure 2 The so-called interval PD between two data lines 134 can be regarded as the distance between the middle lines of two adjacent data lines 134 in the first direction D1, the maximum distance between the left boundary lines of two adjacent data lines 134 in the first direction D1, or the maximum distance between the right boundary lines of two adjacent data lines 134 in the first direction D1.

[0038] In addition, due to the pattern design of the first branch 1321A and the second branch 1321B, the first gate G1 and the second gate G2 can be electrically connected in parallel with each other. The impedance caused by the first channel region 1361 of the semiconductor layer 136 overlapping the first gate G1 to the scan line 132 and the impedance caused by the second channel region 1362 of the semiconductor layer 136 overlapping the second gate G2 to the scan line 132 are also connected in parallel with each other. Such parallel impedance connection helps to reduce the equivalent impedance caused by the semiconductor layer 136 to the scan line 132, which helps to reduce the load of the scan line 132, thereby reducing the resistance-capacitance delay effect of the scan line 132, which helps to improve the signal transmission performance and quality of the scan line 132.

[0039] Figure 5 for Figure 3 A schematic diagram of an implementation of the cross-sectional structure of the driving layer along the section line II. Figure 3 , Figure 4 and Figure 5The driving layer 130 is, for example, disposed on the first substrate 110 , and in addition to the scan line 132 , the data line 134 , the semiconductor layer 136 and the common line 138 , the driving layer 130 further includes a pixel electrode 131 , a common electrode 133 , a light shielding layer 135 and a plurality of insulating layers 137A-137E. Figure 4 Only the first gate G1, the second gate G2 and the second scan line segment 1322 of the scan line 132 are shown, but the specific layout of the scan line can be referred to Figure 3 and related instructions.

[0040] Depend on Figure 5 It can be seen that in this embodiment, the light shielding layer 135 is disposed on the first substrate 110, and the first channel region 1361 and the second channel region 1362 of the semiconductor layer 136 overlap the light shielding layer 135. In this way, the light shielding layer 135 can reduce the external light irradiation on the first channel region 1361 and the second channel region 1362 to ensure the electrical characteristics of the first channel region 1361 and the second channel region 1362. For example, the leakage caused by the light irradiation on the first channel region 1361 and the second channel region 1362 can be reduced. In some embodiments, the light shielding layer 135 can be made of opaque metal material or other materials. The insulating layer 137A is disposed on the first substrate 110 and covers the light shielding layer 135. Here, the insulating layer 137A may include a first sub-layer 137A1 and a second sub-layer 137A2, but is not limited thereto. The material of the first sub-layer 137A1 may include silicon nitride, and the material of the second sub-layer 137A2 may include silicon oxide. In other embodiments, the insulating layer 137A may be made of other insulating materials, and the insulating layer 137A may consist of only a single layer, or may alternatively consist of three or more layers.

[0041] The semiconductor layer 136 is disposed on the first substrate 110 and formed on the insulating layer 137A. In other embodiments, the light shielding layer 135 and the insulating layer 137A may be omitted, and the semiconductor layer 136 may be directly disposed on the first substrate 110. The material of the semiconductor layer 136 may include low-temperature polysilicon, amorphous silicon, crystalline silicon, metal oxide semiconductors, organic semiconductors or other materials with semiconductor properties or a combination thereof, but is not limited thereto. In addition, the insulating layer 137B is disposed on the first substrate 110 and covers the semiconductor layer 136. The scan line 132 including the first gate G1, the second gate G2 and the second scan line segment 1322 is disposed on the insulating layer 137B. In addition, Figure 3The shared line 138 in the embodiment may also be disposed on the insulating layer 137B and be the same film layer as the scan line 132, but not limited thereto. Here, the insulating layer 137B is located between the semiconductor layer 136 and the scan line 132 to serve as a gate insulating layer. In some embodiments, the material of the insulating layer 137B may include silicon oxide, but not limited thereto. In other embodiments, the material of the insulating layer 137B may include silicon oxide, silicon nitride, silicon oxynitride, hafnium oxynitride or a combination thereof, but not limited thereto. In this embodiment, the scan line 132 and the semiconductor layer 136 can define an active component TFT, wherein the semiconductor layer 136 can be divided into a first segment 136A, a second segment 136B and a third segment 136C according to a pattern (or an extension direction of different segments) in a top view, and can also be divided into a first channel region 1361, a second channel region 1362, an intermediate region 1363, a low-doped region 1364, a drain region 1365, a low-doped region 1366 and a source region 1367 according to different doping levels.

[0042] The insulating layer 137C covers the scan line 132, and the data line 134 is disposed on the insulating layer 137C. In the present embodiment, the insulating layer 137C covering the scan line 132 includes a third sublayer 137C1 and a fourth sublayer 137C2, but is not limited thereto. In other embodiments, the insulating layer 137C may be a single film layer. The third sublayer 137C1 and the fourth sublayer 137C2 may be made of the same material or different materials, wherein the materials of the third sublayer 137C1 and the fourth sublayer 137C2 may include silicon oxide, silicon nitride, silicon oxynitride, hafnium oxynitride or a combination thereof, respectively, but is not limited thereto. In some embodiments, the third sublayer 137C1 and the fourth sublayer 137C2 may be made of different materials, for example, the material of the third sublayer 137C1 may include silicon nitride and the material of the fourth sublayer 137C2 may include silicon oxide.

[0043] The data line 134 is formed on the insulating layer 137C, and contacts and electrically connects to the source region 1367 of the semiconductor layer 136 through the through hole VA1. The materials of the scan line 132 and the data line 134 may include conductive materials composed of molybdenum, aluminum, copper, titanium or a combination thereof, but are not limited thereto. The through hole VA1 penetrates the insulating layer 137C and the insulating layer 137B, and the data line 134 extends into the through hole VA1 to connect to the source region 1367 both physically and electrically. In addition, the pixel connection electrode 131' may be formed while the data line 134 is being made. The pixel connection electrode 131' is disposed on the insulating layer 137C, and electrically connects to the drain region 1365 of the semiconductor layer 136 through the through hole VA2. The through hole VA2 penetrates the insulating layer 137C and the insulating layer 137B, and the pixel connection electrode 131' extends to the through hole VA2 to connect to the drain region 1365 both physically and electrically.

[0044] The insulating layer 137D is disposed on the insulating layer 137C and covers at least a portion of the data line 134. The insulating layer 137D can be an insulating layer of organic material, which can be thicker than other insulating layers to provide a planarization effect. The insulating layer 137D is composed of materials such as perfluoroalkoxy polymer resin (PFA), polymer film on array (PFA), fluoroelastomers, etc., but is not limited thereto. The common electrode 133 is disposed on the insulating layer 137D, and the common electrode 133 can be connected to Figure 3 The common line 138 shown in FIG. The material of the common electrode 133 includes indium tin oxide, indium zinc oxide, aluminum zinc oxide, etc. The insulating layer 137E is disposed on the first substrate 110 and covers the common electrode 133. The material of the insulating layer 137E includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxynitride or a combination thereof.

[0045] The pixel electrode 131 is disposed on the insulating layer 137E, and the pixel electrode 131 is physically connected (or electrically connected) to the pixel connection electrode 131', for example, via the through holes VA3 and VA4. Here, the through hole VA3 penetrates the insulating layer 137D and exposes the pixel connection electrode 131', wherein the insulating layer 137E can extend into the through hole VA3. The through hole VA4 penetrates the insulating layer 137E and exposes the pixel connection electrode 131', wherein the pixel electrode 131 can extend into the through hole VA4 to be physically connected (or electrically connected) to the pixel connection electrode 131'. In other embodiments, the common electrode 133 and the through hole VA3 can be formed simultaneously when the through hole VA3 is formed. Figure 3 The through hole (not shown) between the common line 138 shown. In this embodiment, the pixel electrode 131 and the common electrode 133 may partially overlap, and the pixel electrode 131 may have multiple slits 131S. The slits 131S may overlap the common electrode 133 in the normal direction of the first substrate 110. In this way, when the pixel electrode 131 and the common electrode 133 are respectively written with corresponding voltages, a driving electric field may be formed to drive the dielectric layer (e.g. Figure 1 In other embodiments, the stacking order of the pixel electrode 131 and the common electrode 133 can be reversed, that is, the pixel electrode 131 can be disposed between the insulating layer 137D and the insulating layer 137E, and the common electrode 133 is disposed on the surface of the insulating layer 137E away from the first substrate 110. Figure 5 The pixel electrode 131 and the common electrode 133 shown are for illustration only. In other embodiments, the pixel electrode 131 and the common electrode 133 may have other suitable patterns or configurations, but are not limited thereto.

[0046] Figure 6FIG. 1 is a partial top view schematic diagram of a driving layer according to another embodiment of the present disclosure, wherein Figure 6 Show Figure 2 Another embodiment of a local driving layer in area A. Figure 7 for Figure 6 A schematic diagram of an embodiment of a cross-sectional structure of a driving layer along the section line II-II. Figure 6 and Figure 7 In the embodiment, the driving layer 230 is substantially similar to Figures 3 to 5 The driving layer 130 of the first substrate 110 is used, so the same and similar component symbols are used in the two embodiments to represent the same and similar components. Specifically, the driving layer 230 configured on the first substrate 110 includes at least a scan line 232, a data line 134 and a semiconductor layer 136, and the scan line 232 includes a first scan line segment 1321 and a second scan line segment 2322 connected to the first scan line segment 1321. Here, the specific structure, material, function, etc. of the first scan line segment 1321 of the scan line 232, the data line 134 and the semiconductor layer 136 can refer to the description of the previous embodiment and will not be repeated. In addition, in Figure 6 In the embodiment, the pixel electrode 131 , the pixel connection electrode 131 ′, the common electrode 133 , the light shielding layer 135 and the insulating layers 137A to 137E of the driving layer 230 may also refer to the description of the above-mentioned embodiment and will not be repeated here.

[0047] Specifically, in the present embodiment, the scan line 232 includes a first scan line segment 1321 and a second scan line segment 2322. The second scan line segment 2322 and the first scan line segment 1321 are different film layers, and are electrically connected to each other via the through hole VA5. Specifically, the second scan line segment 2322 can be the same film layer as the data line 134. In other words, the second scan line segment 2322 is made of a film layer located between the insulating layer 137C and the insulating layer 137D. In contrast, the first scan line segment 1321 is made of a film layer located between the insulating layer 137B and the insulating layer 137C. The through hole VA5 can penetrate the insulating layer 137C to expose a portion of the first scan line segment 1321, and the second scan line segment 2322 extends to the through hole VA5 to physically connect (or electrically connect) the first scan line segment 1321.

[0048] In some embodiments, the materials of the first scan line segment 1321 and the second scan line segment 2322 may include conductive materials composed of molybdenum, aluminum, copper, titanium or a combination thereof, but are not limited thereto. In some embodiments, at least one of the first scan line segment 1321 and the second scan line segment 2322 has a multilayer structure formed by stacking multiple conductive material layers. In some embodiments, the first scan line segment 1321 and the second scan line segment 2322 may have different materials. For example, the material of the second scan line segment 2322 may have better conductivity than the first scan line segment 1321. In this way, in addition to the parallel connection of the first branch 1321A and the second branch 1321B in the first scan line segment 1321, which can reduce the impedance of the scan line 232, the better conductivity of the second scan line segment 2322 also helps to reduce the impedance of the scan line 232, thereby helping to reduce the resistance-capacitance delay effect of the scan line 232.

[0049] Figure 8 FIG. 1 is a partial top view of a driving layer according to another embodiment of the present disclosure, wherein Figure 8 Show Figure 2 Another embodiment of the local driving layer of area A. Fig. 9 for Figure 8 A schematic diagram of an embodiment of a cross-sectional structure of a driving layer along the section line III-III. Figure 8 and Fig. 9 In the embodiment, the driving layer 330 is substantially similar to Figures 3 to 5 The driving layer 130 is a semiconductor layer 136. Therefore, the same or similar component symbols are used in the two embodiments to represent the same or similar components. Specifically, the driving layer 330 at least includes a scanning line 132, a data line 134 and a semiconductor layer 136. Here, the specific structure, material, function, etc. of the scanning line 132, the data line 134 and the semiconductor layer 136 can refer to the description of the previous embodiment and will not be repeated. In addition, in Fig. 9 In the embodiment, the pixel electrode 131, the pixel connection electrode 131', the common electrode 133, the light shielding layer 135 and the insulating layers 137A-137E of the driving layer 330 can also refer to the description of the above embodiment, and will not be repeated. Figures 3 to 5 The embodiment is that the driving layer 330 of this embodiment also includes an auxiliary scanning line 339, a scanning connection electrode 339', an insulating layer 337F and an auxiliary pixel connection electrode 331', wherein the insulating layer 337F is arranged between the insulating layer 137D and the insulating layer 137E so that the shared electrode 133 is located between the insulating layer 137E and the insulating layer 137F.

[0050] The auxiliary scanning line 339 substantially overlaps the scanning line 132, and the auxiliary scanning line 339 and the scanning line 132 are different film layers. The line width W3 of the auxiliary scanning line 339 may be not greater than the first scanning line width W1 of the scanning line 132 or even not greater than the second scanning line width W2 of the scanning line 132, but is not limited thereto. In some embodiments, the line width W3 may be the maximum width of the auxiliary scanning line 339 in a direction perpendicular to the first direction D1. In addition, by Fig. 9 It can be seen that the scan line 132 is located between the insulating layer 137B and the insulating layer 137C, and the auxiliary scan line 339 is located between the insulating layer 137D and the insulating layer 337F. In the present embodiment, the auxiliary scan line 339 can be electrically connected to the scan line 132 via the scan connection electrode 339'. For example, the auxiliary scan line 339 can be physically connected (or electrically connected) to the scan connection electrode 339' via the through hole VA6, and the scan connection electrode 339' can be physically connected (or electrically connected) to the scan line 132 via the through hole VA7. The through hole VA6 penetrates the insulating layer 137D and exposes the scan connection electrode 339', and the through hole VA7 penetrates the insulating layer 137C and exposes the scan line 132. In other words, the through hole VA6, the scan connection electrode 339' and the through hole VA7 constitute a connection structure between the auxiliary scan line 339 and the scan line 132. In this embodiment, although not shown in the figure, a plurality of connecting structures may be provided between the auxiliary scanning line 339 and the scanning line 132 so that the auxiliary scanning line 339 is electrically connected in parallel with the scanning line 132, thereby reducing the impedance of the scanning line 132, thereby helping to reduce the resistance-capacitance delay effect of the scanning line 132.

[0051] In addition, the film layer of the auxiliary scanning line 339 is different from the film layer of the scanning line 132 and the film layer of the data line 134. The auxiliary scanning line 339 can be the same film layer as the auxiliary pixel connection electrode 331'. For example, when the through hole VA6 is made, the through hole VA3 can be formed corresponding to the pixel connection electrode 131', and when the auxiliary scanning line 339 is made, the auxiliary pixel connection electrode 331' can be made corresponding to the through hole VA3. In this way, the auxiliary pixel connection electrode 331' can be physically connected (or electrically connected) to the pixel connection electrode 131' through the through hole VA3. Afterwards, before the pixel electrode 131 is made, the through hole VA8 can be formed. The through hole VA8 penetrates the insulating layer 337F and the insulating layer 137E and exposes the auxiliary pixel connection electrode 331'. Next, when the pixel electrode 131 is made, the pixel electrode 131 is extended into the through hole VA8, and the pixel electrode 131 can be physically connected (or electrically connected) to the auxiliary pixel connection electrode 331' through the through hole VA8. In this way, the pixel electrode 131 is physically connected (or electrically connected) to the auxiliary pixel connection electrode 331', the auxiliary pixel connection electrode 331' is physically connected (or electrically connected) to the pixel connection electrode 131', and the pixel connection electrode 131' is physically connected (or electrically connected) to the semiconductor layer 136 to achieve the required electrical connection relationship.

[0052] According to the above, in the electronic device of the embodiment of the present disclosure, the scan line of the driving layer includes a first scan line segment, and the first scan line segment has a first branch and a second branch, and the first branch and the second branch are electrically connected in parallel. The data line intersects with the first branch and the second branch, so that the impedance load caused by the data line to the scan line is reduced, thereby reducing the resistance-capacitance delay effect of the scan line. The semiconductor layer intersects with the first branch and the second branch to form an active component of a double gate, and because the first branch and the second branch are connected in parallel, the impedance load formed by the double gate for the scan line will also be reduced, thereby reducing the resistance-capacitance delay effect of the scan line. In addition, in some embodiments, different line segments of the scan line can be composed of different film layers, and the conductivity of different film layers is different, which also helps to adjust the impedance of the scan line. In some other embodiments, the driving layer of the electronic device is additionally provided with an auxiliary scan line, so that the auxiliary scan line is electrically connected in parallel with the scan line, which also helps to reduce the resistance-capacitance delay effect of the scan line. Therefore, the electronic device according to the embodiment of the present disclosure can provide ideal driving performance, which helps to improve or stabilize the display effect of the electronic device.

[0053] Although the present disclosure has been described with reference to preferred aspects, those skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the present disclosure. The features of the various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

Claims

1. An electronic device, characterized in that: The electronic device comprises: a first substrate; A first conductive line is disposed on the first substrate; a second conductive line, disposed on the first conductive line and electrically connected to the first conductive line via a through hole; and The metal oxide semiconductor straddles the first conductive line and the second conductive line. 2 . The electronic device according to claim 1 , wherein the first conductive line extends along a first direction, the first conductive line has a protrusion in a second direction, and the first direction is different from the second direction.

3. The electronic device according to claim 1, wherein the first conductive line and the second conductive line both extend along a first direction, a maximum width of the first conductive line in a second direction is different from a maximum width of the second conductive line in the second direction, and the first direction is different from the second direction. 4 . The electronic device according to claim 3 , wherein the maximum width of the first conductive line in the second direction is greater than the maximum width of the second conductive line in the second direction. The electronic device according to claim 1 , wherein the first conductive line and the second conductive line are used to transmit a scan signal.

6. An electronic device, characterized in that: The electronic device comprises: a first substrate; A first conductive line is disposed on the first substrate, extends along a first direction, and has a protruding portion protruding along a second direction, the first direction being different from the second direction; A second conductive line overlaps the first conductive line and extends along the first direction; a semiconductor overlapping the protrusion of the first conductive line; and Two through holes are connected to the semiconductor, wherein the two through holes are respectively located on two different sides of the first conductive line and on two different sides of the second conductive line. The electronic device according to claim 6 , wherein the material of the semiconductor comprises a metal oxide semiconductor. 8 . The electronic device of claim 6 , wherein a maximum width of the first conductive line in the second direction is different from a maximum width of the second conductive line in the second direction. 9 . The electronic device of claim 8 , wherein the maximum width of the first conductive line in the second direction is greater than the maximum width of the second conductive line in the second direction. 10 . The electronic device as claimed in claim 6 , wherein the first conductive line and the second conductive line are used to transmit a scan signal.

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