Display device

Abstract

The invention provides a display device. A display panel of the display device comprises a gate drive circuit and a plurality of pixels. The gate driving circuit comprises multiple stages of cascaded gate driving sub-circuits, and each stage of gate driving sub-circuit comprises a plurality of transistors. In order to solve the problem of unstable work of a gate drive circuit caused by threshold voltage drift of a semiconductor transistor in a high-temperature and high-humidity environment, the invention adopts the following technical scheme: 1, in a blanking period of a driving period of each frame of picture, a fifteenth transistor is controlled to be switched on through a control signal; performing high-level voltage writing on the node Ki; and a twenty-sixth transistor is additionally arranged between the fourteenth transistor and the node Ki, and the critical conversion voltage of the node between the fourteenth transistor and the twenty-sixth transistor is 3-5 volts lower than the critical conversion voltage of the node Ki. According to the technical scheme, the working stability of the gate drive circuit in a high-temperature and high-humidity environment can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] In the field of display panel technology, CMOS (Complementary Metal-Oxide-Semiconductor) GOA (Gate-driver On Array) technology can realize the function of zoned frequency division. However, in the dual 85 (temperature 85°C, humidity 85%) reliability verification (RA) environment, the threshold voltage (Vth) of the IGZO transistor of the display panel will drift over a large area, resulting in the inability to maintain the stability of the circuit operation. This situation seriously affects the working stability of the gate drive circuit in the dual 85 environment. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a display device, aiming to improve the working stability of a CMOS GOA circuit in a dual 85 environment.

[0004] An embodiment of the present application provides a display device, comprising: a display panel, the display panel comprising a gate driving circuit and a plurality of pixels, the gate driving circuit comprising a plurality of cascaded gate driving sub-circuits, the i-th gate driving sub-circuit of the plurality of gate driving sub-circuits comprising at least a shift register module, a self-stabilizing module, a first gate driving signal frequency division control module and a second gate driving signal frequency division control module, the shift register module being electrically connected to the self-stabilizing module, the first gate driving signal frequency division control module and the second gate driving signal frequency division control module being both electrically connected to the shift register module and the self-stabilizing module; the self-stabilizing module comprising at least: a first transistor, the gate of the first transistor being electrically connected to a node K_i, the node K_i being a node of a connection line between the shift register module and the first gate driving signal frequency division control module and / or the second gate driving signal frequency division control module, one of a source and a drain of the first transistor being electrically connected to a first low level signal input terminal, the other of a source and a drain of the first transistor being electrically connected to a node P_i, the node P_i being a node of a connection line between the shift register module and the first gate driving signal frequency division control module and / or the second gate driving signal frequency division control module, a node of a connection line between a gate drive signal frequency division control module and the second gate drive signal frequency division control module; a third transistor, the gate of the third transistor is electrically connected to the node K_i, one of the source and the drain of the third transistor is electrically connected to the first high level signal input terminal, and the other of the source and the drain of the third transistor is electrically connected to the node P_i; a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the node P_i, and one of the source and the drain of the fourteenth transistor is electrically connected to the second low level signal input terminal , the other of the source and the drain of the fourteenth transistor is electrically connected to the node K_i; and a fifteenth transistor, the gate of the fifteenth transistor is electrically connected to the control signal input terminal, one of the source and the drain of the fifteenth transistor is electrically connected to the first high level signal input terminal, and the other of the source and the drain of the fifteenth transistor is electrically connected to the node K_i; wherein the signal of the control signal input terminal is used to control the fifteenth transistor to write a high level voltage to the node K_i during the blanking period of the driving cycle of each frame of the picture.

[0005] In the above display device, the control signal is at a low level during a blanking period of a driving cycle of each frame, and is at a high level during a non-blanking period of a driving cycle of each frame.

[0006] In the above display device, the low level duration of the control signal is less than or equal to the duration of the blanking period.

[0007] In the above display device, the blanking period accounts for 10%-30% of the driving period of one frame.

[0008] In the above display device, an on-resistance of the fifteenth transistor is smaller than an on-resistance of any one of the first transistor, the third transistor and the fourteenth transistor.

[0009] In the above display device, the first transistor is an N-type double-gate transistor, the third transistor is a P-type single-gate transistor, the fourteenth transistor is an N-type double-gate transistor, and the fifteenth transistor is a P-type single-gate transistor.

[0010] The embodiment of the present application also provides a display device, characterized in that it includes: a display panel, the display panel includes a gate drive circuit and a plurality of pixels, the gate drive circuit includes a multi-stage cascaded gate drive sub-circuit, the i-th stage gate drive sub-circuit in the multi-stage gate drive sub-circuit includes at least a shift register module, a self-stabilizing module, a first gate drive signal frequency division control module and a second gate drive signal frequency division control module, the shift register module is electrically connected to the self-stabilizing module, the first gate drive signal frequency division control module and the second gate drive signal frequency division control module are both connected to the shift register module. The module is electrically connected to the self-stabilizing module; the self-stabilizing module at least includes: a first transistor, one of the source and the drain of the first transistor is electrically connected to the first low-level signal input terminal, the gate of the first transistor is electrically connected to a node K_i, the node K_i is a node of a connection line between the shift register module and the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module, the other of the source and the drain of the first transistor is electrically connected to a node P_i, the node P_i is a node of a connection line between the first gate drive signal frequency division control module and the second gate a node of a connection line between the driving signal frequency division control modules; a third transistor, the gate of the third transistor is electrically connected to the node K_i, one of the source and the drain of the third transistor is electrically connected to the first high-level signal input terminal, and the other of the source and the drain of the third transistor is electrically connected to the node P_i; a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the node P_i, and one of the source and the drain of the fourteenth transistor is electrically connected to the second low-level signal input terminal; and a twenty-sixth transistor, the gate of the twenty-sixth transistor is electrically connected to the fourth clock signal input terminal The shift register module at least comprises: a second transistor, a gate of the second transistor being electrically connected to a first clock signal input terminal, one of a source and a drain of the second transistor being electrically connected to the first high level signal input terminal, and the other of a source and a drain of the second transistor being electrically connected to the node K_i; wherein the signal at the fourth clock signal input terminal is inverted with the signal at the first clock signal input terminal.

[0011] In the above display device, the first transistor, the fourteenth transistor and the twenty-sixth transistor are all N-type transistors.

[0012] In the above display device, the first transistor, the fourteenth transistor and the twenty-sixth transistor are all double-gate transistors.

[0013] In the above-mentioned display device, the i-th level gate driving subcircuit also includes: a third transistor, the gate of the third transistor is electrically connected to the node K_i, one of the source and the drain of the third transistor is electrically connected to the first high-level signal input terminal, and the other of the source and the drain of the third transistor is electrically connected to the node P_i.

[0014] In the above display device, the inverter formed by the first transistor and the third transistor is used to invert the level signal of the node K_i and output it to the node P_i.

[0015] In the above display device, a critical switching voltage of a node between the other of the source and the drain of the fourteenth transistor and the source of the twenty-sixth transistor is 3V to 5V lower than a critical switching voltage of the node K_i.

[0016] In the above display device, a rising edge of the signal at the fourth clock signal input terminal is aligned in time with a falling edge of the signal at the first clock signal input terminal.

[0017] In the above display device, the duty cycle of the signal at the fourth clock signal input terminal is the same as the duty cycle of the signal at the first clock signal input terminal.

[0018] In the above display device, the first transistor, the fourteenth transistor and the twenty-sixth transistor are IGZO transistors, and the second transistor and the third transistor are LTPS transistors.

[0019] The display device provided in the present application improves the working stability of the gate drive circuit in a high temperature and high humidity environment through the following two technical solutions:

[0020] The first technical solution is to control the fifteenth transistor to be turned on by the signal at the control signal input terminal during the blanking period of the driving cycle of each frame, so that the high-level voltage of the first high-level signal input terminal is written into the node K_i. Since the first transistor and the third transistor constitute an inverter, when the level of the node K_i is pulled high, the inverter acts to pull the level of the node P_i down. In this way, by periodically adjusting the levels of the nodes K_i and P_i during the blanking period, even when the threshold voltage of the semiconductor transistor drifts, it can be ensured that the level of the node P_i can be normally changed from a high level to a low level, thereby avoiding the abnormal conduction of the fourteenth transistor and affecting the normal change of the level of the node K_i.

[0021] The second technical solution is to add a twenty-sixth transistor between the other of the source and drain of the fourteenth transistor and the node K_i, and use the signal of the fourth clock signal input terminal that is inverted with the signal of the first clock signal input terminal to control the conduction and cutoff of the twenty-sixth transistor. Since the critical switching voltage of the node between the other of the source and drain of the fourteenth transistor and the source of the twenty-sixth transistor is 3 volts to 5 volts lower than the critical switching voltage of the node K_i, even if the threshold voltage of the semiconductor transistor drifts, the voltage between the source and drain of the fourteenth transistor will also be reduced by 3 volts to 5 volts, thereby reducing the conduction current of the fourteenth transistor and avoiding the abnormal conduction of the fourteenth transistor from affecting the normal change of the level of the node K_i.

[0022] Both of the above technical solutions can effectively solve the problem that the levels of node K_i and node P_i cannot change normally due to the threshold voltage drift of the semiconductor transistor in the gate driving circuit under high temperature and high humidity environment, thereby improving the working stability of the gate driving circuit under high temperature and high humidity environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of a display device provided in this application.

[0024] Figure 2 A circuit diagram of a gate driving subcircuit in a display device provided in the present application.

[0025] Figure 3 Another circuit diagram of a gate driving subcircuit in a display device provided in the present application.

[0026] Figure 4 The diagram is a schematic diagram of the performance of a conventional gate driving sub-circuit of a display device when the threshold voltages of the first transistor and the third transistor drift.

[0027] Figure 5 for Figure 3 The schematic diagram of the performance of the gate driving sub-circuit when the threshold voltages of the first transistor and the third transistor drift is shown.

[0028] Figure 6 1 is a waveform diagram of various signals when the threshold voltage of the first transistor in the gate driving sub-circuit in the conventional display device drifts by 6 volts.

[0029] Figure 7 for Figure 3 The gate driving sub-circuit shown is a waveform diagram of various signals when the threshold voltage of the first transistor drifts by 6 volts. DETAILED DESCRIPTION

[0030] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0031] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0032] The embodiments of the present application may be combined with each other.

[0033] The present application relates to the field of display technology, and more specifically to a technical solution for improving the display abnormality of a display device in a high temperature and high humidity environment. The technology is mainly applied to the gate drive circuit of the display device, aiming to improve the stability and reliability of the gate drive circuit in a specific harsh environment, and ensure the normal operation of the display device.

[0034] like Figure 1 As shown, the display device provided by the embodiment of the present application includes a display panel. The display panel includes a gate driving circuit and a plurality of pixels. The gate driving circuit includes a plurality of cascaded gate driving sub-circuits.

[0035] The display panel includes a display area and a non-display area. The display area is provided with a plurality of pixels arranged in an array, and the non-display area is located around the display area. The display panel also includes a plurality of scan lines, a plurality of data lines and a gate drive circuit. The plurality of scan lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along the second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit is provided in the non-display area and is electrically connected to the plurality of scan lines. The source drive circuit is electrically connected to the plurality of data lines through a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit.

[0036] The display panel includes an organic light emitting diode array substrate and an encapsulation layer. The organic light emitting diode array substrate includes a base substrate, a buffer layer arranged on the base substrate, an active layer arranged on the buffer layer, a gate insulating layer arranged on the active layer, a first metal layer arranged on the gate insulating layer, an interlayer insulating layer arranged on the first metal layer, a second metal layer arranged on the interlayer insulating layer, a planarization layer arranged on the second metal layer, a first electrode layer arranged on the planarization layer, a pixel defining layer arranged on the first electrode layer, an organic light emitting layer arranged in an opening area defined by the pixel defining layer, and a second electrode layer arranged on the organic light emitting layer. The first metal layer includes a scan line and a gate electrode. The second metal layer includes a data line, a source electrode, and a drain electrode. The encapsulation layer is sealed and connected to the organic light emitting diode array substrate.

[0037] Each pixel includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes at least two transistors and a storage capacitor. One of the transistors is used as a switching transistor, and its gate is electrically connected to the corresponding scan line, and its source is electrically connected to the corresponding data line; the other transistor is used as a driving transistor, and its gate is electrically connected to the drain of the switching transistor, the source is electrically connected to the first power supply voltage line, and the drain is electrically connected to the anode of the light-emitting device. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to the source or drain of the driving transistor. The cathode of the light-emitting device is electrically connected to the second power supply voltage line.

[0038] The gate drive circuit includes multiple stages of cascaded gate drive subcircuits, and each stage of the gate drive subcircuit is electrically connected to a scan line. Under the control of the timing controller, the gate drive subcircuit outputs scan signals in sequence to scan each row of pixels in the display area line by line. Under the control of the timing controller, the source drive circuit generates and outputs data signals according to the image data. The timing controller is used to receive and process externally input image data and timing signals, generate control signals, and transmit image data to the source drive circuit. The power management chip is used to provide operating voltages for various parts of the display device, including providing a second power supply voltage for the cathode of the light-emitting device, providing a first power supply voltage for the first power supply voltage line, and providing a gate drive voltage for the gate drive circuit.

[0039] The display device of the present application includes a display panel, and the display panel includes a gate driving circuit and a plurality of pixels. The gate driving circuit includes a plurality of cascaded gate driving subcircuits, and the circuit structure of each gate driving subcircuit is as follows: Figure 2 In view of the problems of the gate driving circuit in a high temperature and high humidity environment, the present application proposes two embodiments to improve the stability of the node K_i and the node P_i under the positive bias temperature stress of the IGZO transistor, thereby improving the stability of the gate driving circuit in a high temperature and high humidity environment.

[0040] The embodiments of this application are based on Figure 2 The gate driving sub-circuit shown in FIG. 1 includes a plurality of transistors and capacitors.

[0041] Specifically, the i-th stage gate driving sub-circuit includes a first transistor T1_i, a third transistor T3_i, a fourteenth transistor T14_i, and a fifteenth transistor T15_i.

[0042] The gate of the first transistor T1_i is electrically connected to the node K_i, one of the source and the drain of the first transistor T1_i is electrically connected to the first low-level signal input terminal PVGL, and the other of the source and the drain of the first transistor T1_i is electrically connected to the node P_i; the gate of the third transistor T3_i is electrically connected to the node K_i, one of the source and the drain of the third transistor T3_i is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and the drain of the third transistor T3_i is electrically connected to the node P_i; the gate of the fourteenth transistor T14_i is electrically connected to the node P_i, and the source and the drain of the fourteenth transistor T14_i are electrically connected to the node P_i. One of the sources and drains of the fourteenth transistor T14_i is electrically connected to the second low-level signal input terminal NVGL, and the other of the source and drain of the fourteenth transistor T14_i is electrically connected to the node K_i; the gate of the fifteenth transistor T15_i is electrically connected to the control signal input terminal Ctrl, one of the source and drain of the fifteenth transistor T15_i is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and drain of the fifteenth transistor T15_i is electrically connected to the node K_i; wherein the signal of the control signal input terminal Ctrl is used to control the fifteenth transistor T15_i to write a high-level voltage to the node K_i during the blanking period of the driving cycle of each frame.

[0043] The signal at the control signal input terminal Ctrl is at a low level during a blanking period of a driving cycle of each frame, and is at a high level during a non-blanking period of a driving cycle of each frame.

[0044] The low level duration of the signal at the control signal input terminal Ctrl is less than or equal to the duration of the blanking period.

[0045] The i-th level gate driving sub-circuit also includes a second transistor T2_i, a fourth transistor T4_i, a fifth transistor T5_i, a sixth transistor T6_i, a seventh transistor T7_i, an eighth transistor T8_i, a ninth transistor T9_i, a tenth transistor T10_i, an eleventh transistor T11_i, a twelfth transistor T12_i, a thirteenth transistor T13_i, a sixteenth transistor T16_i, a seventeenth transistor T17_i, an eighteenth transistor T18_i, a nineteenth transistor T19_i, a twentieth transistor T20_i, a twenty-first transistor T21_i, a twenty-second transistor T22_i, a twenty-third transistor T23_i, a twenty-fourth transistor T24_i, and a twenty-fifth transistor T25_i.

[0046] The first transistor T1_i, the fourth transistor T4_i, the tenth transistor T10_i, the thirteenth transistor T13_i, the fourteenth transistor T14_i, the seventeenth transistor T17_i, and the twenty-first transistor T21_i are N-type double-gate transistors (two gates of each transistor are electrically connected), and these transistors can be, for example, IGZO transistors; the second transistor T2_i, the third transistor T3_i, the fifth transistor T5_i, the sixth transistor T6_i, the seventh transistor T7_i, and the eighth ... IGZO transistors; The transistor T8_i, the ninth transistor T9_i, the eleventh transistor T11_i, the twelfth transistor T12_i, the fifteenth transistor T15_i, the sixteenth transistor T16_i, the eighteenth transistor T18_i, the nineteenth transistor T19_i, the twentieth transistor T20_i, the twenty-second transistor T22_i, the twenty-third transistor T23_i, the twenty-fourth transistor T24_i, and the twenty-fifth transistor T25_i are P-type single-gate transistors, which may be, for example, LTPS transistors.

[0047] The gate of the second transistor T2_i is electrically connected to the first clock signal input terminal XCK1, one of the source and the drain is electrically connected to the node O_i (one of the source and the drain of the second transistor is electrically connected to the first high level signal input terminal PVGH through the twelfth transistor, and is electrically connected to the second low level signal input terminal NVGL through the thirteenth transistor T13_i), and the other of the source and the drain is electrically connected to the node K_i; the gate of the fourth transistor T4_i is electrically connected to the first clock signal input terminal XCK1, one of the source and the drain is electrically connected to the node K_i, and the other of the source and the drain is electrically connected to the other of the source and the drain of the fifth transistor T5_i; the gate of the fifth transistor T5_i is electrically connected to the node P_ i is electrically connected, one of the source and the drain is electrically connected to the first high-level signal input terminal PVGH, the other of the source and the drain of the fifth transistor T5_i is electrically connected to the other of the source and the drain of the fourth transistor T4_i; the gate of the sixth transistor T6_i is electrically connected to the node Q1_i, one of the source and the drain is electrically connected to the second clock signal CK1, and the other of the source and the drain is electrically connected to the first gate drive signal output terminal Pout1_i; the gate of the seventh transistor T7_i is electrically connected to the node P_i, one of the source and the drain is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and the drain is electrically connected to the first gate drive signal output terminal Pout1_i; the eighth transistor T8_ The gate of the ninth transistor T9_i is electrically connected to the node W_i, one of the source and the drain is electrically connected to the second high level signal input terminal NVGH, and the other of the source and the drain is electrically connected to the second gate drive signal output terminal Nout_i; the gate of the tenth transistor T10_i is electrically connected to the node K_i, one of the source and the drain is electrically connected to the second low level signal input terminal NVGH, and the other of the source and the drain is electrically connected to the second gate drive signal output terminal Nout_i. The input terminal NVGL is electrically connected, and the other of the source and the drain is electrically connected to the second gate drive signal output terminal Nout_i; one of the source and the drain of the eleventh transistor T11_i is electrically connected to the node K_i, and the other of the source and the drain is electrically connected to the node W_i; the gate of the twelfth transistor T12_i is electrically connected to the start signal input terminal STV / the node P_i-1 in the i-1th gate drive sub-circuit (the node P_i-1 in the i-1th gate drive sub-circuit corresponds to the node P_i in the i-th gate drive sub-circuit in terms of position, connection relationship, and function), one of the source and the drain is electrically connected to the first high level signal input terminal PVGH, and the other of the source and the drain is electrically connected to the node O_i;The gate of the thirteenth transistor T13_i is electrically connected to the start signal input terminal STV, one of the source and the drain is electrically connected to the second low level signal input terminal NVGL, and the other of the source and the drain is electrically connected to the node O_i; the gate of the sixteenth transistor T16_i is electrically connected to the node P_i, one of the source and the drain is electrically connected to the first partition allocation control signal input terminal NLF, and the other of the source and the drain is electrically connected to the gate of the eleventh transistor T11_i; the gate of the seventeenth transistor T17_i is electrically connected to the first clock signal input terminal XCK1, and one of the source and the drain is electrically connected to the node W_i; The gate of the eighteenth transistor T18_i is electrically connected to the node P_i, one of the source and the drain is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and the drain is electrically connected to the other of the source and the drain of the seventeenth transistor T17_i; the source and the drain of the nineteenth transistor T19_i are electrically connected to the node K_i, and the other of the source and the drain is electrically connected to the node M_i; the gate of the twentieth transistor T20_i is electrically connected to the node P_i, one of the source and the drain is electrically connected to the second partition allocation control signal input terminal PLF, and the other of the source and the drain is electrically connected to the nineteenth transistor The gate of the twenty-first transistor T21_i is electrically connected to the first clock signal input terminal XCK1, and one of the source and the drain is electrically connected to the node M_i; the gate of the twenty-second transistor T22_i is electrically connected to the node P_i, one of the source and the drain is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and the drain is electrically connected to the other of the source and the drain of the twenty-first transistor T21_i; the gate of the twenty-third transistor T23_i is electrically connected to the node P_i-2 in the i-2nd level gate driving sub-circuit, and one of the source and the drain is electrically connected to the node M_i The gate of the twenty-fourth transistor T24_i is electrically connected to the node Q2_i, one of the source and the drain is electrically connected to the third clock signal CK2, and the other of the source and the drain is electrically connected to the third gate drive signal output terminal Pout2_i (level transfer signal output terminal); the gate of the twenty-fifth transistor T25_i is electrically connected to the node P_i, one of the source and the drain is electrically connected to the first high level signal input terminal PVGH, and the other of the source and the drain is electrically connected to the third gate drive signal output terminal Pout2_i (level transfer signal output terminal). ;

[0048] In addition, the i-th level gate drive sub-circuit also includes four capacitors, one plate of the first capacitor C1 is electrically connected to the node Q1_i, and the other plate is electrically connected to the first gate drive signal output terminal Pout1_i; one plate of the second capacitor C2 is electrically connected to the node W_i, and the other plate is electrically connected to the gate of the eleventh transistor T11_i; one plate of the third capacitor C3 is electrically connected to the node Mi_i, and the other plate is electrically connected to the gate of the nineteenth transistor T19_i; one plate of the fourth capacitor C4 is electrically connected to the node Q2_i, and the other plate is electrically connected to the third gate drive signal output terminal Pout2_i (level transmission signal output terminal).

[0049] The second transistor T2_i, the twelfth transistor T12_i, and the thirteenth transistor T13_i constitute a shift register module 201, the first transistor T1_i, the third transistor T3_i, the fourth transistor T4_i, the fifth transistor T5_i, the fourteenth transistor T14_i, and the fifteenth transistor T15_i constitute a self-stabilizing module 202, the eleventh transistor T11_i, the sixteenth transistor T16_i, the seventeenth transistor T17_i, the eighteenth transistor T18_i, and the second capacitor C2_i constitute a first gate drive signal frequency division control module 203, the ninth transistor T9_i and the tenth transistor T10_i constitute a first gate drive signal frequency division control module 204, The nineteenth transistor T19_i, the twentieth transistor T20_i, the twenty-first transistor T21_i, the twenty-second transistor T22_i, and the third capacitor C3_i constitute a second gate drive signal frequency division control module 205, the sixth transistor T6_i, the seventh transistor T7_i, the eighth transistor T8_i, and the first capacitor C1_i constitute a second gate drive signal output module 206, the twenty-third transistor T23_i, the twenty-fourth transistor T24_i, the twenty-fifth transistor T25_i, and the fourth capacitor C4_i constitute a third gate drive signal output module (stage transmission signal output module) 207.

[0050] The shift register module 201 is electrically connected to the self-stabilizing module 202, the first gate drive signal frequency division control module 203 and the second gate drive signal frequency division control module 205 are both electrically connected to the shift register module 201 and the self-stabilizing module 202, the first gate drive signal output module 204 is electrically connected to the self-stabilizing module 202 and the first gate drive signal frequency division control module 203, and the second gate drive signal output module 206 and the third gate drive signal output module 207 are both electrically connected to the second gate drive signal frequency division control module 205 and the self-stabilizing module 202.

[0051] After analysis, the reason why the gate drive circuit is not good under high temperature and high humidity environment is that the node K_i cannot be pulled up and the node P_i cannot be pulled down. The node K_i is the node of the connection line between the shift register module and the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module, and the node P_i is the node of the connection line between the first gate drive signal frequency division control module and the second gate drive signal frequency division control module. In view of this, the countermeasure of this embodiment is to periodically reset the node K_i. Specifically, the signal of the control signal input terminal Ctrl is used to write the voltage of the first high level signal input terminal PVGH to the node K_i during the blanking period of the driving cycle of each frame through the fifteenth transistor T15_i. The voltage of the first high level signal input terminal PVGH here is a relatively high voltage value, and its specific value is 10 volts to 20 volts, for example, it can be 10 volts, 12 volts, 14 volts, 16 volts, 18 volts or 20 volts. The voltage of the first high-level signal input terminal PVGH is selected based on the ability to effectively change the potential of the node K_i and affect the potential of the node P_i through the inverter action of the first transistor T1_i and the third transistor T3_i. The voltage of the first high-level signal input terminal PVGH needs to be high enough to overcome the resistance loss in the circuit and the voltage drop of other components to ensure that the potential of the node K_i can be reliably pulled up.

[0052] The blanking period needs to be long enough so that the fifteenth transistor T15_i has enough time to write the voltage of the first high-level signal input terminal PVGH into the node K_i and complete the subsequent process of affecting the potential of the node P_i through the first transistor T1_i and the third transistor T3_i inverter. At the same time, it cannot be too long, so as not to affect the time of the display stage and cause the frame rate of the display picture to decrease. The proportion of the blanking period to the driving cycle of a frame is 10%-30%.

[0053] When the fifteenth transistor T15_i is turned on during the blanking period, the voltage of the first high-level signal input terminal PVGH is transmitted to the node K_i through the fifteenth transistor T15_i, so that the potential of the node K_i increases. This high voltage will be converted into a signal of the first low-level signal input terminal PVGL through the inverter composed of the first transistor T1_i and the third transistor T3_i. The inverter composed of the first transistor T1_i and the third transistor T3_i utilizes the characteristics of the first transistor T1_i of the N-type transistor and the third transistor T3_i of the P-type transistor. When the node K_i is at a high level, the first transistor T1_i is turned on and the third transistor T3_i is turned off, so that the potential of the node P_i is pulled down, thereby achieving the purpose of changing the pull-down of the node P_i and the pull-up of the node K_i. Through such a periodic reset operation, the potential of the node K_i is adjusted during the blanking period of the driving cycle of each frame, which improves the working state of the node K_i and the node P_i, and improves the stability of the gate drive circuit in a high temperature and high humidity environment.

[0054] On the basis of the above embodiment, as an improvement, the signal of the control signal input terminal Ctrl is optimized, specifically including: adjusting the frequency, amplitude or duty cycle of the signal to adapt to different display panel requirements and working environments. For example, the frequency of the control signal is increased to make the periodic reset of the node K_i more frequent, thereby more accurately adjusting the potential of the node K_i and the node P_i, and further improving the stability of the circuit; according to different power supply conditions and circuit component characteristics, the signal amplitude is adjusted to ensure that when writing the voltage of the first high-level signal input terminal PVGH, the node potential can be effectively changed without causing excessive electrical pressure on other components; the duty cycle is optimized according to the specific duration requirements of the display phase and the blanking phase in a frame of the picture to achieve the best circuit performance.

[0055] As an improvement, for application scenarios with low power consumption requirements, a transistor with a smaller on-resistance (for example, less than 1 kiloohm) is selected as the fifteenth transistor T15_i, or a transistor with an on-resistance smaller than the on-resistance of other transistors (for example, any one of the first transistor T1_i to the fourteenth transistor T14_i, the sixteenth transistor T16_i to the twenty-sixth transistor T26_i) is selected as the fifteenth transistor T15_i, thereby reducing energy loss when transmitting the voltage of the first high-level signal input terminal PVGH, and also enabling the potential of the node K_i to be adjusted more quickly.

[0056] In view of the problem that the node K_i cannot be pulled up and the node P_i cannot be pulled down, the above embodiment directly improves the working state of the node K_i and the node P_i by periodically resetting the node K_i. The specific operation of the periodic reset is to use the signal of the control signal input terminal Ctrl to write the voltage of the first high-level signal input terminal PVGH to the node K_i during the blanking period through the fifteenth transistor T15_i, and change the node P_i pull-down and the node K_i pull-up through the inverter action of the first transistor T1_i and the third transistor T3_i, thereby improving the stability of the gate drive circuit in a high temperature and high humidity environment.

[0057] In the embodiments of the present application, Figure 2 On the basis of the circuit shown in FIG. 1 , a twenty-sixth transistor T26_i is added between the node K_i and the drain of the fourteenth transistor T14_i. The twenty-sixth transistor T26_i is an N-type double-gate transistor. The twenty-sixth transistor T26_i may be, for example, an IGZO transistor. Figure 3 shown.

[0058] Specifically, the i-th stage gate driving sub-circuit further includes a twenty-sixth transistor T26_i. The gate of the twenty-sixth transistor T26_i is electrically connected to the fourth clock signal input terminal XCK2, the source of the twenty-sixth transistor T26_i is electrically connected to the other of the source and the drain of the fourteenth transistor T14_i, and the drain of the twenty-sixth transistor T26_i is electrically connected to the node K_i; wherein the signal of the fourth clock signal input terminal XCK2 is inverted with the signal of the first clock signal input terminal XCK1.

[0059] The inverter formed by the first transistor T1_i and the third transistor T3_i is used to invert the level signal of the node K_i and output it to the node P_i.

[0060] The threshold switching voltage of the node X_i between the other of the source and the drain of the fourteenth transistor T14_i and the source of the twenty-sixth transistor T26_i is 3V-5V lower than the threshold switching voltage of the node K_i.

[0061] The rising edge of the signal at the fourth clock signal input terminal XCK2 is aligned in time with the falling edge of the signal at the first clock signal input terminal XCK1. The duty cycle of the signal at the fourth clock signal input terminal XCK2 is the same as the duty cycle of the signal at the first clock signal input terminal XCK1 (including absolutely the same and substantially the same, wherein substantially the same means that the difference does not exceed 10%).

[0062] The drain of the fourteenth transistor T14_i is no longer directly electrically connected to the node K_i, but is electrically connected through the twenty-sixth transistor T26_i. The twenty-sixth transistor T26_i is controlled by the signal of the fourth clock signal input terminal XCK2, and the signal of the fourth clock signal input terminal XCK2 is inverted with the signal of the first clock signal input terminal XCK1. Specifically, the gate of the twenty-sixth transistor T26_i is electrically connected to the fourth clock signal input terminal XCK2, the source is electrically connected to the drain of the fourteenth transistor T14_i, and the drain is electrically connected to the node K_i. The twenty-sixth transistor T26_i is an N-type double-gate transistor.

[0063] The threshold voltage of the twenty-sixth transistor T26_i is set to make the critical switching voltage of the node X_i 3V-5V lower than that of the node K_i, so that the drain current of the fourteenth transistor T14_i can be limited in advance when the threshold voltage drifts.

[0064] Since the first transistor T1_i and the third transistor T3_i constitute an inverter, the input end of the inverter is electrically connected to the node K_i, and the output end is electrically connected to the node P_i. In a high temperature and high humidity environment, when the threshold voltage of the first transistor T1_i drifts, it will affect the normal operation of the inverter. Specifically, when the node K_i is at a high level, the first transistor T1_i should be turned on to pull the node P_i down to a low level, but if the threshold voltage of the first transistor T1_i drifts too much, it will cause the first transistor T1_i to fail to turn on normally, thereby failing to pull the node P_i down to a low level.

[0065] After adding the twenty-sixth transistor T26_i, since the critical switching voltage of the node X_i between the source of the twenty-sixth transistor T26_i and the drain of the fourteenth transistor T14_i is 3 volts to 5 volts lower than the critical switching voltage of the node K_i, when the threshold voltage of the first transistor T1_i drifts, the voltage of the node X_i reaches the critical value earlier. When the voltage of the node X_i reaches the critical value, the drain current of the fourteenth transistor T14_i is limited, thereby reducing the pull-down effect of the fourteenth transistor T14_i on the node K_i. In this way, even if the threshold voltage of the first transistor T1_i drifts significantly, the node K_i can still be maintained at a higher level, ensuring that the first transistor T1_i can be normally turned on, thereby ensuring the normal operation of the inverter.

[0066] Therefore, by adding the twenty-sixth transistor T26_i, when the threshold voltage of the first transistor T1_i drifts, the level of the node K_i can be maintained by controlling the drain current of the fourteenth transistor T14_i, thereby improving the tolerance of the first transistor T1_i to the threshold voltage drift.

[0067] The signal of the fourth clock signal input terminal XCK2 is inverted with the signal of the first clock signal input terminal XCK1, which means that the turn-on / turn-off timing of the twenty-sixth transistor T26_i is complementary to the transistor (such as the second transistor T2_i and the fourth transistor T4_i) controlled by the signal of the first clock signal input terminal XCK1, ensuring that in the critical time period (such as the reset period of the node K_i), the twenty-sixth transistor T26_i cuts off the drain path of the fourteenth transistor T14_i to avoid current competition. Specifically, when the signal of the fourth clock signal input terminal XCK2 is at a high level, the twenty-sixth transistor T26_i is turned on, and a path is formed between the drain of the fourteenth transistor T14_i and the node K_i, but the threshold voltage characteristic of the twenty-sixth transistor T26_i will affect the equivalent resistance of the path. The critical conversion voltage of the node X_i is 3 volts-5 volts lower than that of the node K_i, which means that when the threshold voltage drifts, the voltage of the node X_i reaches the critical value earlier, thereby limiting the drain current of the fourteenth transistor T14_i in advance. Since the voltage of the node X_i is pulled down by the twenty-sixth transistor T26_i (the conduction of T26_i introduces a voltage divider between the nodes K_i and T14_i), the drain voltage of the fourteenth transistor T14_i is reduced (the potential (V_X) of the node X_i is lower than that of the node K_i), resulting in a reduction of the source-drain voltage difference of the fourteenth transistor T14_i by 3 volts to 5 volts. The reduction of the source-drain voltage difference directly leads to a reduction in the pull-down current of the fourteenth transistor T14_i, thereby avoiding the problem that the node K_i cannot be pulled up, significantly improving the threshold voltage tolerance of the circuit, and improving the stability of the circuit in a high temperature and high humidity environment.

[0068] The threshold voltage is an important parameter of the transistor, which determines when the transistor is turned on or off. The critical switching voltage refers to the voltage critical value that will trigger the change of the working state of at least one transistor when the voltage of a specific node in the circuit reaches a preset threshold. The critical switching voltage of a node is usually determined based on the threshold voltage of the transistor connected to the node. For example, in the present application, when the voltage of the node X_i reaches a certain critical value related to the threshold voltage of the twenty-sixth transistor T26_i, the working state of the fourteenth transistor T14_i will change, thereby affecting the current and voltage distribution of the entire circuit. The critical switching voltage is generated when the inverter switches between high and low levels, and the failure of the gate drive circuit is caused by the failure of the high and low level switching to be successfully completed.

[0069] The signal of the fourth clock signal input terminal XCK2 is used to control the twenty-sixth transistor T26_i, which is inverse to the signal of the first clock signal input terminal XCK1. Since the on / off timing of the twenty-sixth transistor T26_i is complementary to the on / off timing of the transistor controlled by the signal of the first clock signal input terminal XCK1, during the reset period of the node K_i, when the signal of the first clock signal input terminal XCK1 is in a certain state so that other related transistors are in a specific working state, the signal of the fourth clock signal input terminal XCK2 puts the twenty-sixth transistor T26_i in the opposite state, cuts off the drain path of the fourteenth transistor T14_i, prevents the flow of undesired current in this time period, and avoids the influence of current competition on the stability of the circuit. This complementary signal control method ensures that the circuit can operate stably under complex working conditions, especially in the case of threshold voltage drift, by controlling the on and off of the twenty-sixth transistor T26_i, the normal operation of the circuit is maintained.

[0070] The embodiment of the present application adds a twenty-sixth transistor T26_i between the node K_i and the drain of the fourteenth transistor T14_i, and uses the signal control of the fourth clock signal input terminal XCK2 to reduce the pull-down current of the fourteenth transistor T14_i, thereby solving the problem that the node K_i cannot be pulled up, and enhancing the stability of the circuit when the threshold voltage drifts. The coordinated work of the twenty-sixth transistor T26_i and the signal of the fourth clock signal input terminal XCK2 makes the critical conversion voltage of the node X_i lower than that of the node K_i by 3 volts to 5 volts, thereby reducing the source-drain voltage difference and the pull-down current of the fourteenth transistor T14_i, improving the stability of the gate drive circuit in a high temperature and high humidity environment, and improving the stability of the node K_i and the node P_i under the positive bias temperature stress of the semiconductor material.

[0071] By comparison Figure 4 The prior art gate drive subcircuit shown is Figure 5 It can be seen from the waveform diagram of the gate driving sub-circuit of the second embodiment of the present application that:

[0072] In the prior art, when the threshold voltage of the first transistor T1_i drifts 0.5V and the threshold voltage of the third transistor T3_i drifts 0V to 4V, the gate drive circuit operates normally. However, when the threshold voltage of the first transistor T1_i drifts 0.5V and the threshold voltage of the third transistor T3_i (the channel width of the third transistor T3 is 12 microns) drifts more than 4V, for example, 4V to 7V, the gate drive subcircuit fails, and in particular, in the t3 time period after t2, the level of the node P_i cannot be changed from a high level to a low level, causing the level of the gate drive signal output terminal Nout_i to fluctuate alternately between a medium level and a high level, and cannot be stably maintained at a low level. This shows that the gate drive subcircuit of the prior art has poor working stability in a high temperature and high humidity environment.

[0073] In the second embodiment of the present application, a twenty-sixth transistor T26 is added between the other of the source and drain of the fourteenth transistor T14 and the node K, and the critical switching voltage of the node between the other of the source and drain of the fourteenth transistor T14 and the source of the twenty-sixth transistor T26 is 3 volts to 5 volts lower than the critical switching voltage of the node K, so that under the same conditions, that is, when the threshold voltage of the first transistor T1_i drifts by 0.5V and the threshold voltage of the third transistor T3_i (the channel width of the third transistor T3 is 12 microns) drifts by 0V to 7V, the gate drive circuit still operates normally, especially, in the time period t3 after t2, the level of the node P_i can be stably maintained at a low level, and the level of the gate drive signal output terminal Nout_i can also be stably maintained at a low level. This shows that the gate drive sub-circuit of the second embodiment of the present application significantly improves the working stability in a high temperature and high humidity environment.

[0074] By comparison Figure 6 The prior art gate drive subcircuit shown is Figure 7 It can be seen from the waveform diagram of the gate driving sub-circuit of the second embodiment of the present application that:

[0075] In the prior art, due to the drift of the threshold voltage of the transistor (for example, the first transistor T1_i and the third transistor T3_i), the node P_i cannot be changed from a high level to a low level in the time period t3 after t2, causing the transistor T14_i to be continuously turned on, generating a continuous pull-down current. Since the transistor T14_i is continuously turned on, the level of the node K_i fluctuates alternately between a medium level and a low level, and cannot be stably maintained at a high level. At the same time, since the level of the node K_i cannot be stably maintained at a high level, the level of the gate drive signal output terminal Nout_i decreases to a certain extent when the node K_i is at a medium level, affecting the output stability of the gate drive signal.

[0076] In the second embodiment of the present application, a 26th transistor T26_i is added between the other of the source and drain of the 14th transistor T14_i and the node K_i, and the signal of the fourth clock signal input terminal XCK2 which is inverse to the signal of the first clock signal input terminal XCK1 is used to control the conduction and cutoff of the 26th transistor T26_i, so that the critical switching voltage of the node between the other of the source and drain of the 14th transistor T14_i and the source of the 26th transistor T26_i is 3 volts to 5 volts lower than the critical switching voltage of the node K_i. In this way, even if the threshold voltage of the transistor (for example, the first transistor T1_i and the third transistor T3_i) drifts, in the time period t3 after t2, the node K_i can still be stably maintained at a high level, so that the node P_i can be stably maintained at a low level, and the gate drive signal output terminal Nout_i can also be stably maintained at a low level, which effectively improves the working stability of the gate drive circuit in a high temperature and high humidity environment.

[0077] In the embodiment of the present application, by periodically resetting and / or adding the twenty-sixth transistor T26_i, the stability of the node K_i and the node P_i under the positive bias temperature stress of the semiconductor material is effectively improved, thereby improving the stability of the gate drive circuit in a high temperature and high humidity environment. This enables the display device to work normally in a harsh environment of high temperature and high humidity, reduces display abnormalities caused by circuit instability, and improves display quality and reliability.

[0078] And / or, through the cooperation between the twenty-sixth transistor T26_i and the signal of the fourth clock signal input terminal XCK2, the threshold voltage tolerance of the first transistor T1_i is improved by more than 3 volts, thereby enhancing the circuit's tolerance to threshold voltage drift. This means that when the threshold voltage of the semiconductor material drifts over a large range, the circuit can still maintain normal operation, thereby reducing the risk of circuit failure caused by changes in material properties.

[0079] The embodiments of the present application are described in detail above, and the contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: include: A display panel, wherein the display panel comprises a gate driving circuit and a plurality of pixels, wherein the gate driving circuit comprises a plurality of cascaded gate driving sub-circuits, wherein the i-th gate driving sub-circuit in the plurality of gate driving sub-circuits comprises at least a shift register module, a self-stabilizing module, a first gate driving signal frequency division control module and a second gate driving signal frequency division control module, wherein the shift register module is electrically connected to the self-stabilizing module, and the first gate driving signal frequency division control module and the second gate driving signal frequency division control module are both electrically connected to the shift register module and the self-stabilizing module; The self-stabilizing module at least comprises: a first transistor, wherein the gate of the first transistor is electrically connected to a node K_i, the node K_i being a node of a connection line between the shift register module and the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module, one of a source and a drain of the first transistor being electrically connected to a first low level signal input terminal, the other of a source and a drain of the first transistor being electrically connected to a node P_i, the node P_i being a node of a connection line between the first gate drive signal frequency division control module and the second gate drive signal frequency division control module; a third transistor, wherein a gate of the third transistor is electrically connected to the node K_i, one of a source and a drain of the third transistor is electrically connected to the first high-level signal input terminal, and the other of a source and a drain of the third transistor is electrically connected to the node P_i; a fourteenth transistor, a gate of the fourteenth transistor being electrically connected to the node P_i, one of a source and a drain of the fourteenth transistor being electrically connected to the second low-level signal input terminal, and the other of a source and a drain of the fourteenth transistor being electrically connected to the node K_i; and a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the control signal input terminal, one of a source and a drain of the fifteenth transistor is electrically connected to the first high level signal input terminal, and the other of a source and a drain of the fifteenth transistor is electrically connected to the node K_i; The signal at the control signal input terminal is used to control the fifteenth transistor to write a high level voltage to the node K_i during the blanking period of the driving cycle of each frame.

2. The display device according to claim 1, characterized in that The control signal is at a low level during a blanking period of a driving cycle of each frame, and is at a high level during a non-blanking period of a driving cycle of each frame.

3. The display device according to claim 1, characterized in that The low level duration of the control signal is less than or equal to the duration of the blanking period.

4. The display device according to claim 1, characterized in that The blanking period accounts for 10%-30% of the driving period of one frame.

5. The display device according to claim 1, characterized in that An on-resistance of the fifteenth transistor is smaller than an on-resistance of any one of the first transistor, the third transistor, and the fourteenth transistor.

6. The display device according to claim 1, characterized in that: The first transistor is an N-type double-gate transistor, the third transistor is a P-type single-gate transistor, the fourteenth transistor is an N-type double-gate transistor, and the fifteenth transistor is a P-type single-gate transistor.

7. A display device, characterized in that: include: A display panel, wherein the display panel comprises a gate driving circuit and a plurality of pixels, wherein the gate driving circuit comprises a plurality of cascaded gate driving sub-circuits, wherein the i-th gate driving sub-circuit in the plurality of gate driving sub-circuits comprises at least a shift register module, a self-stabilizing module, a first gate driving signal frequency division control module and a second gate driving signal frequency division control module, wherein the shift register module is electrically connected to the self-stabilizing module, and the first gate driving signal frequency division control module and the second gate driving signal frequency division control module are both electrically connected to the shift register module and the self-stabilizing module; The self-stabilizing module at least comprises: a first transistor, one of the source and the drain of the first transistor being electrically connected to the first low-level signal input terminal, the gate of the first transistor being electrically connected to a node K_i, the node K_i being a node of a connection line between the shift register module and the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module, the other of the source and the drain of the first transistor being electrically connected to a node P_i, the node P_i being a node of a connection line between the first gate drive signal frequency division control module and the second gate drive signal frequency division control module; a third transistor, wherein a gate of the third transistor is electrically connected to the node K_i, one of a source and a drain of the third transistor is electrically connected to the first high-level signal input terminal, and the other of a source and a drain of the third transistor is electrically connected to the node P_i; a fourteenth transistor, a gate of the fourteenth transistor being electrically connected to the node P_i, and one of a source and a drain of the fourteenth transistor being electrically connected to a second low-level signal input terminal; and a twenty-sixth transistor, wherein a gate of the twenty-sixth transistor is electrically connected to the fourth clock signal input terminal, a source of the twenty-sixth transistor is electrically connected to the other of the source and the drain of the fourteenth transistor, and a drain of the twenty-sixth transistor is electrically connected to the node K_i; The shift register module at least includes: a second transistor, wherein a gate of the second transistor is electrically connected to the first clock signal input terminal, one of a source and a drain of the second transistor is electrically connected to the first high level signal input terminal, and the other of a source and a drain of the second transistor is electrically connected to the node K_i; The signal at the fourth clock signal input terminal is in phase opposite to the signal at the first clock signal input terminal.

8. The display device according to claim 7, characterized in that: The first transistor, the fourteenth transistor and the twenty-sixth transistor are all N-type transistors.

9. The display device according to claim 7, characterized in that: The first transistor, the fourteenth transistor and the twenty-sixth transistor are all double-gate transistors.

10. The display device according to claim 7, characterized in that: The i-th level gate driving sub-circuit further includes: A third transistor, wherein the gate of the third transistor is electrically connected to the node K_i, one of the source and the drain of the third transistor is electrically connected to the first high-level signal input terminal, and the other of the source and the drain of the third transistor is electrically connected to the node P_i.

11. The display device according to claim 10, characterized in that: The inverter formed by the first transistor and the third transistor is used to invert the level signal of the node K_i and output it to the node P_i.

12. The display device according to claim 7, characterized in that: A threshold switching voltage of a node between the other of the source and the drain of the fourteenth transistor and the source of the twenty-sixth transistor is 3V to 5V lower than a threshold switching voltage of the node K_i.

13. The display device according to claim 7, characterized in that: A rising edge of the signal at the fourth clock signal input terminal is aligned in time with a falling edge of the signal at the first clock signal input terminal.

14. The display device according to claim 7, characterized in that: The duty cycle of the signal at the fourth clock signal input terminal is the same as the duty cycle of the signal at the first clock signal input terminal.

15. The display device according to claim 7, characterized in that: The first transistor, the fourteenth transistor, and the twenty-sixth transistor are IGZO transistors, and the second transistor and the third transistor are LTPS transistors.

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