Display panel

Abstract

The embodiment of the invention discloses a display panel. According to the display panel, the first capacitor is additionally arranged between the first initial signal line of the first reset circuit and the second initial signal line of the second reset circuit, so that the capacitance of the second initial signal line is increased, the anti-coupling capability is improved, when the fourth node is reset, the influence of data line coupling on the second initial signal line is reduced, and the reliability of the display panel is improved. Therefore, the risk of bright and dark lines is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] Among the existing low temperature polycrystalline oxide (LTPO) thin film transistor driven products, the products using 8T (8 thin film transistors) pixel driving circuits are widely promoted in the market. However, when the 8T LTPO product is at a low gray scale, bright and dark lines will appear in the middle of the screen, affecting the display effect. Summary of the invention

[0003] The embodiments of the present application provide a display panel, which can reduce the risk of bright and dark lines appearing on the display panel.

[0004] An embodiment of the present application provides a pixel driving circuit, which includes:

[0005] a first transistor, wherein the first transistor is a driving transistor, a gate of the first transistor is connected to a first node, a first electrode of the first transistor is connected to a second node, and a second electrode of the first transistor is connected to a third node;

[0006] a data writing circuit, the data writing circuit being connected to the second node, the data writing circuit being used for writing a data signal into the second node in response to a first gate driving signal;

[0007] a threshold compensation circuit, the threshold compensation circuit connecting the first node and the third node, the threshold compensation circuit being used to connect the first node and the third node in response to a second gate driving signal;

[0008] a first reset circuit, the first reset circuit being connected to the first node and a first initial signal line and being used for transmitting a signal of the first initial signal line to the first node in response to a first reset signal;

[0009] a control circuit, the control circuit being connected to the second node, the third node and the fourth node, and being used for transmitting the signal of the first power supply terminal to the second node in response to an enable signal, and for connecting the third node and the fourth node in response to the enable signal;

[0010] a second reset circuit, connected to the fourth node and the second initial signal line, for transmitting a signal of the second initial signal line to the fourth node in response to a second reset signal;

[0011] a first capacitor, one end of which is connected to the first initial signal line, and the other end of which is connected to the second initial signal line; and

[0012] A light emitting device, wherein an anode of the light emitting device is connected to the fourth node.

[0013] Optionally, in some embodiments of the present application, the pixel driving circuit further includes a second capacitor, a third capacitor and a third reset circuit, one end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the control end of the data writing circuit;

[0014] One end of the third capacitor is connected to the first node, and the other end of the third capacitor is connected to the first power supply end;

[0015] The third reset circuit is connected to the second node and the second power supply terminal, and is used for inputting a signal from the second power supply terminal to the second node in response to the second reset signal.

[0016] Optionally, in some embodiments of the present application, the data writing circuit includes a second transistor, the gate of the second transistor is connected to the second capacitor and used to access the first gate driving signal, the first electrode of the second transistor is used to access the data signal, and the second electrode of the second transistor is connected to the second node;

[0017] The threshold compensation circuit includes a third transistor, the gate of the third transistor is used to access the second gate drive signal, the first electrode of the third transistor is connected to the first node, and the second electrode of the third transistor is connected to the third node;

[0018] The first reset circuit includes a fourth transistor, a gate of the fourth transistor is used to receive the first reset signal, a first electrode of the fourth transistor is connected to the first initial signal line, and a second electrode of the fourth transistor is connected to the first node;

[0019] The control circuit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is used to access the enable signal, the first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode of the fifth transistor is connected to the second node, the gate of the sixth transistor is used to access the enable signal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node;

[0020] The second reset circuit comprises a seventh transistor, a gate of the seventh transistor is used to receive the second reset signal, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the fourth node;

[0021] The third reset circuit includes an eighth transistor, a gate of the eighth transistor is used to receive the second reset signal, a first electrode of the eighth transistor is connected to the second power supply terminal, and a second electrode of the eighth transistor is connected to the second node.

[0022] Optionally, in some embodiments of the present application, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type low-temperature polysilicon transistors, and the third transistor and the fourth transistor are N-type oxide transistors.

[0023] Optionally, in some embodiments of the present application, the capacitance value of the first capacitor is greater than or equal to 14.4fF.

[0024] Correspondingly, an embodiment of the present application further provides a display panel, which includes a pixel driving circuit as described in any one of the above embodiments.

[0025] Optionally, in some embodiments of the present application, the display panel includes a substrate, a first insulating layer and a second insulating layer, the first initial signal line includes a first segment, the first capacitor includes a first electrode plate and a second electrode plate, the first segment is arranged on the substrate, the first insulating layer covers the first segment, the first electrode plate is arranged on a side of the first insulating layer away from the substrate, the first segment is connected to the first electrode plate, and the second insulating layer covers the first electrode plate;

[0026] The second initial signal line includes a second section, the second section is connected to the second electrode plate and is arranged in the same layer as the second electrode plate on a side of the second insulating layer away from the substrate; in a direction perpendicular to the panel surface of the display panel, the first electrode plate and the second electrode plate are overlapped.

[0027] Optionally, in some embodiments of the present application, the display panel also includes a data line for accessing the data signal, and the data line is arranged on a side of the second insulating layer away from the substrate, and in a direction perpendicular to the panel surface of the display panel, the data line and the second segment are partially overlapped, and the data line and the second segment form a parasitic capacitance, and the first capacitance is greater than the parasitic capacitance.

[0028] Optionally, in some embodiments of the present application, the first capacitor also includes a compensation plate formed by extending the first segment in the direction of the first electrode, and the compensation plate includes a first part and a second part that are connected, wherein, in the orthographic projection pattern of the display panel, the first part is overlapped with the first electrode plate and the second electrode plate respectively, and the second part is located on the outside of the first electrode plate, and the second part is partially overlapped with the second electrode plate.

[0029] Optionally, in some embodiments of the present application, the resistivity of the compensation plate is smaller than the resistivity of the first plate.

[0030] Optionally, in some embodiments of the present application, the first initial signal line also includes a transfer section, a connecting section and a first input section, the transfer section is on the same layer as the second section and is arranged at intervals on the second insulating layer, the connecting section, the first input section and the first electrode plate are arranged on the same layer on the first insulating layer, the connecting section is connected to the first electrode plate and the first input section, the first input section is connected to the first reset circuit, and a first via and a second via are provided on the second insulating layer, the first via also penetrates the first insulating layer and exposes the first section, the second via exposes the connecting section, one end of the transfer section is connected to the first section through the first via, and the other end of the transfer section is connected to the connecting section through the second via.

[0031] Optionally, in some embodiments of the present application, the connecting section, the first input section, the first electrode plate and the active layer of the fourth transistor of the first reset circuit are arranged in the same layer and the materials of the four all include metal oxide semiconductors.

[0032] In the pixel driving circuit and display panel of the embodiments of the present application, a first capacitor is added between the first initial signal line of the first reset circuit and the second initial signal line of the second reset circuit, so that the capacitance of the second initial signal line is increased and the anti-coupling capability is improved. When the fourth node is reset, the influence of the coupling of the data line on the second initial signal line is reduced, thereby reducing the risk of bright and dark lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is an equivalent circuit diagram of a pixel driving circuit provided in an embodiment of the present application;

[0034] Figure 2 is a timing diagram of a pixel driving circuit provided in an embodiment of the present application;

[0035] Figure 3 is a structural schematic diagram of a partial orthographic projection of a display panel provided in an embodiment of the present application;

[0036] Figure 4 is a schematic cross-sectional structural diagram of a display panel provided in an embodiment of the present application;

[0037] Figure 5 yes Figure 3 A schematic diagram of the orthographic projection structure of the film layer where the first section of the first initial signal line is located;

[0038] Figure 6 yes Figure 3A schematic diagram of the orthographic projection structure of the film layer where the first electrode plate is located;

[0039] Figure 7 yes Figure 3 Schematic diagram of the orthographic projection structure of the film layer where the second section of the second initial signal line is located. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0041] Those skilled in the art will appreciate that the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0042] The embodiments of the present application provide a pixel driving circuit and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0043] Please refer to Figure 1 An embodiment of the present application provides a pixel driving circuit, which includes a first transistor T1, a data writing circuit D1, a threshold compensation circuit D2, a first reset circuit D3, a control circuit D4, a second reset circuit D5, a first capacitor C1 and a light emitting device EL.

[0044] The first transistor T1 is a driving transistor. The gate of the first transistor T1 is connected to the first node Q, the first electrode of the first transistor T1 is connected to the second node A, and the second electrode of the first transistor T1 is connected to the third node B.

[0045] The data writing circuit D1 is connected to the second node A. The data writing circuit D1 is used for writing the data signal Data into the second node A in response to the first gate driving signal Pscan.

[0046] The threshold compensation circuit D2 connects the first node Q and the third node B. The threshold compensation circuit D2 is configured to connect the first node Q and the third node B in response to the second gate driving signal Nscan1.

[0047] The first reset circuit D3 is connected to the first node Q and the first initial signal line, and is configured to transmit the signal Vi1 of the first initial signal line to the first node Q in response to the first reset signal Nscan2.

[0048] The control circuit D4 connects the first power supply terminal, the second node A, the third node B and the fourth node C. The control circuit D4 is used to transmit the signal VDD of the first power supply terminal to the second node A in response to the enable signal EM, and to connect the third node B and the fourth node C in response to the enable signal EM.

[0049] The second reset circuit D5 is connected to the fourth node C and the second initial signal line. The second reset circuit D5 is used to transmit the signal Vi2 of the second initial signal line to the fourth node C in response to the second reset signal Pscan2.

[0050] One end of the first capacitor C1 is connected to the first initial signal line, and the other end of the first capacitor C1 is connected to the second initial signal line. The anode of the light emitting device EL is connected to the fourth node C. The cathode of the light emitting device EL is connected to the third power signal VSS.

[0051] In the pixel driving circuit of the prior art, there is a parasitic capacitor between the data line and the second initial signal line. When the data signal of the data line jumps, the second initial signal line is coupled, resulting in a change in the reset of the fourth node, causing the problem of bright and dark lines. In the pixel driving circuit of the embodiment of the present application, a first capacitor C1 is added between the first initial signal line of the first reset circuit D3 and the second initial signal line of the second reset circuit D5, so that the capacitance of the second initial signal line is increased, and the anti-coupling capability is improved. When the fourth node C is reset, the second initial signal line is reduced The influence of the coupling of the data line is reduced, thereby reducing the risk of bright and dark lines.

[0052] Optionally, the light emitting device EL may be a light emitting diode. Writing the second initial signal Vi2 to the fourth node C can eliminate the uncombined carriers on the light emitting interface inside the light emitting diode, thereby alleviating the aging of the light emitting diode.

[0053] Optionally, the pixel driving circuit further includes a second capacitor Cboost, a third capacitor Cst and a third reset circuit D6.

[0054] One end of the second capacitor Cboost is connected to the first node Q, and the other end of the second capacitor Cboost is connected to the control end of the data writing circuit D1. One end of the third capacitor Cst is connected to the first node Q, and the other end of the third capacitor Cst is connected to the first power supply end.

[0055] The third reset circuit D6 is connected to the second node A and the second power supply terminal. The third reset circuit D6 is used to input the signal Vi3 of the second power supply terminal to the second node A in response to the second reset signal Pscan2.

[0056] Optionally, in some embodiments of the present application, the data write circuit D1 includes a second transistor T2, the gate of the second transistor T2 is connected to the second capacitor Cboost and is used to access the first gate drive signal Pscan, the first electrode of the second transistor T2 is used to access the data signal Data, and the second electrode of the second transistor T2 is connected to the second node A.

[0057] The threshold compensation circuit D2 includes a third transistor T3, a gate of the third transistor T3 is used to access the second gate driving signal Nscan1, a first electrode of the third transistor T3 is connected to the first node Q, and a second electrode of the third transistor T3 is connected to the third node B.

[0058] The first reset circuit D3 includes a fourth transistor T4, a gate of the fourth transistor T4 is used to access the first reset signal Nscan2, a first electrode of the fourth transistor T4 is connected to the first initial signal line, and a second electrode of the fourth transistor T4 is connected to the first node Q.

[0059] The control circuit D4 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is used to access the enable signal EM, the first electrode of the fifth transistor T5 is connected to the first power supply terminal, and the second electrode of the fifth transistor T5 is connected to the second node A. The gate of the sixth transistor T6 is used to access the enable signal EM, the first electrode of the sixth transistor T6 is connected to the third node B, and the second electrode of the sixth transistor T6 is connected to the fourth node C.

[0060] The second reset circuit D5 includes a seventh transistor T7, a gate of the seventh transistor T7 is used to receive the second reset signal Pscan2, a first electrode of the seventh transistor T7 is connected to the second initial signal line, and a second electrode of the seventh transistor T7 is connected to the fourth node C.

[0061] The third reset circuit D6 includes an eighth transistor T8, a gate of the eighth transistor T8 is used to receive the second reset signal Pscan2, a first electrode of the eighth transistor T8 is connected to the second power supply end, and a second electrode of the eighth transistor T8 is connected to the second node A.

[0062] Optionally, the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 and the eighth transistor T8 are P-type low-temperature polysilicon transistors, and the third transistor T3 and the fourth transistor T4 are N-type oxide transistors.

[0063] The N-type metal oxide transistor has a small leakage current, so that the third node B can be prevented from leaking through the third transistor T3 and the fourth transistor T4 during the light-emitting stage. The low-temperature polysilicon transistor has a high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density and high aperture ratio.

[0064] Optionally, in some embodiments, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may also be N-type transistors, and the third transistor T3 and the fourth transistor T4 may also be P-type transistors, which is not limited in the embodiments of the present application.

[0065] Optionally, in the pixel driving circuit in the embodiment of the present application, the capacitance value of the first capacitor C1 is greater than or equal to 14.4fF (femtofarad). It can be understood that the larger the capacitance value of the first capacitor C1, the better the anti-coupling effect of the second initial signal line, and the lower the risk of bright and dark lines.

[0066] According to the table below, when the first capacitor C1 reaches 14.4fF, full optimization is achieved, the influence of the second initial signal line on the data line coupling is improved from 9.3% to 3%, and no bright or dark lines appear in the product.

[0067]

[0068] Optionally, the first capacitor C1 can be 14.4fF, 14.5fF, 14.6fF, 14.7fF, 14.8fF, 14.9fF, 15fF, 15.1fF, 15.2fF, 15.3fF, 15.4fF, 15.5fF, 15.6fF, 15.7fF, 15.8fF, 15.9fF, 16fF, 16.1fF, 16.2fF , 16.3fF, 16.4fF, 16.5fF, 16.6fF, 16.7fF, 16.8fF, 16.9fF, 17fF, 17.5fF, 18fF, 18. 5fF, 19fF, 19.5fF, 20fF, 21fF, 22fF, 23fF, 24fF, 25fF, 26fF, 27fF, 28fF, 29fF or 30fF.

[0069] In some embodiments, the first capacitor C1 may also be less than 14.4fF, for example, 14fF, 13fF, 12fF, 11fF, 10fF, 9fF, 8fF, 7fF, 6fF, 5fF, 4fF, 3fF, 2fF or 1fF.

[0070] It is understandable that the total capacitance of the second initial signal line can be increased by adding the first capacitor C1, thereby improving the anti-coupling effect. When the capacitance of the first capacitor C1 reaches 14.4 fF, the effect of no bright or dark lines is achieved.

[0071] Optionally, the first capacitor C1 is greater than 0.64 fF, so that the second initial signal line can better resist the coupling effect of the data line.

[0072] Please refer to Figure 2 The pixel driving circuit of this embodiment includes six stages: a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5 and a sixth stage t6.

[0073] Among them, in the first stage t1, the enable signal EM, the first gate drive signal Pscan, and the second gate drive signal Nscan1 output high-level signals, the first reset signal Nscan2 and the second reset signal Pscan2 output low-level signals, the first transistor T1, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 are turned on, and the other transistors are turned off. The first power supply terminal inputs the signal Vi3 of the second power supply terminal to the second node A, the third node B, and the first node Q for charging. The second initial signal line inputs the signal Vi2 of the second initial signal line to the fourth node C for reset.

[0074] In the second stage t2, the enable signal EM, the first reset signal Nscan2, the second reset signal Pscan2 and the first gate drive signal Pscan output high level signals, the second gate drive signal Nscan1 outputs a low level signal, the fourth transistor T4 is turned on, and the other transistors are turned off. The first initial signal line inputs the signal Vi1 of the first initial signal line to the first node Q for reset.

[0075] In the third stage t3, the enable signal EM, the second gate drive signal Nscan1, the first reset signal Nscan2, the second reset signal Pscan2 and the first gate drive signal Pscan output high level signals, the first transistor T1, the third transistor T3 and the fourth transistor T4 are turned on, and the other transistors are turned off. The first initial signal line writes the signal Vi1 of the first initial signal line to the first node Q, the second node A and the third node B for reset.

[0076] In the fourth stage t4, the enable signal EM, the second gate drive signal Nscan1 and the second reset signal Pscan2 output high-level signals, the first gate drive signal Pscan and the first reset signal Nscan2 output low-level signals, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, and the other transistors are turned off, and the data line writes the data signal Data into the first node Q.

[0077] In the fifth stage t5, the enable signal EM and the first gate drive signal Pscan output high level signals, the first reset signal Nscan2, the second gate drive signal Nscan1 and the second reset signal Pscan2 output low level signals, and the first transistor T1, the second transistor T2 and the seventh transistor T7 are turned on. The first power supply terminal inputs the signal Vi3 of the second power supply terminal to the second node A and the third node B for charging. The second initial signal line inputs the signal Vi2 of the second initial signal line to the fourth node C for reset.

[0078] In the sixth stage t6, the first gate drive signal Pscan and the second reset signal Pscan2 output high-level signals, the enable signal EM, the second gate drive signal Nscan1 and the first reset signal Nscan2 output low-level signals, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned on, the other transistors are turned off, and the light-emitting device EL emits light.

[0079] Accordingly, the embodiment of the present application further provides a display panel 100, which includes a pixel driving circuit as in any of the above embodiments. That is, the structure of the pixel driving circuit of the display panel 100 of the embodiment of the present application is similar or identical to the structure of the pixel driving circuit of the above embodiments.

[0080] In the display panel of the 8T product of the prior art, there is a parasitic capacitor between the data line and the second initial signal line. When the data signal of the data line jumps, the second initial signal line is coupled, resulting in a change in the reset of the fourth node, causing the problem of bright and dark lines. The display panel 100 of the embodiment of the present application adds a first capacitor C1 between the first initial signal line of the first reset circuit D3 of the pixel driving circuit and the second initial signal line of the second reset circuit D5, so that the capacitance of the second initial signal line is increased, and the anti-coupling capability is improved. When the fourth node C is reset, the second initial signal line is reduced The influence of the coupling of the data line is reduced, thereby reducing the risk of bright and dark lines.

[0081] Optional, see Figure 3 and Figure 4The display panel 100 includes a substrate 11, a first insulating layer 12 and a second insulating layer 13. The first initial signal line R1 includes a first segment r11. The first capacitor C1 includes a first electrode plate c11 and a second electrode plate c12. The first segment r11 is disposed on the substrate 11. The first insulating layer 12 covers the first segment r11. The first electrode plate c11 is disposed on a side of the first insulating layer 12 away from the substrate 11. The first segment r11 is connected to the first electrode plate c11. The second insulating layer 13 covers the first electrode plate c11.

[0082] The second initial signal line R2 includes a second segment r21, which is connected to the second electrode plate c12 and is disposed in the same layer as the second electrode plate c12 on a side of the second insulating layer 13 away from the substrate 11. In a direction perpendicular to the surface of the display panel 100, the first electrode plate c11 and the second electrode plate c12 are overlapped.

[0083] The display panel 100 further includes a data line Dt for receiving a data signal Data. The data line Dt is disposed on a side of the second insulating layer 13 away from the substrate 11. In a direction perpendicular to the surface of the display panel 100, the data line Dt and the second segment r21 are partially overlapped. The data line Dt and the second segment r21 form a parasitic capacitor, and the first capacitor C1 is greater than the parasitic capacitor.

[0084] The first capacitor C1 is larger than the parasitic capacitor, so that the second initial signal line R2 can better resist the coupling effect of the data line Dt.

[0085] Optionally, the data line Dt is connected to the first electrode of the second transistor T2.

[0086] Optionally, the first section r11, the second section r21, and the second electrode c12 may be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. In addition, the first section r11, the second section r21, and the second electrode c12 may have a single-layer structure or a stacked structure of two or more layers, such as titanium / aluminum / titanium.

[0087] Optional, please combine Figure 5 The first capacitor C1 further includes a compensation plate c13 formed by extending the first segment r11 toward the first plate c11, and the compensation plate c13 includes a first portion c131 and a second portion c132 connected to each other. In the orthographic projection pattern of the display panel 100, the first portion c131 is overlapped with the first plate c11 and the second plate c12 respectively, the second portion c132 is located outside the first plate c11, and the second portion c132 is overlapped with a portion of the second plate c12.

[0088] The compensation plate c13 and the first plate c11 are connected to form a lower electrode plate, the second plate c12 is an upper electrode plate, and the upper electrode plate and the lower electrode plate overlap to form a first capacitor C1.

[0089] It can be understood that the provision of the compensation plate c13 can increase the capacitance of the first capacitor C1.

[0090] Secondly, the distance between the compensation plate c13 and the second plate c12 is greater than the distance between the first plate c11 and the second plate c12, so that per unit area, the capacitance of the second portion c132 of the compensation plate c13 and the second plate c12 is smaller than the capacitance of the first plate c11 and the second plate c12. That is, by providing the second portion c132 of the compensation plate c13, the capacitance value of the first capacitor C1 can be better adjusted and the idle space can be fully utilized.

[0091] Optionally, the resistivity of the compensation plate c13 is less than the resistivity of the first plate c11. That is, the resistivity of the first plate c11 is higher, its conductivity is poor, and the potential difference is larger, so the electric field strength formed by the first plate c11 and the second plate c12 is stronger and the capacitance value is larger.

[0092] The overlapping area of ​​the first electrode plate c11 and the second electrode plate c12 is larger than the overlapping area of ​​the second portion c132 of the compensation electrode plate c13 and the second electrode plate c12, so that a first capacitor C1 with a larger capacitance can be formed in a limited space.

[0093] Optional, combined Figure 6 and Figure 7 , the first initial signal line R1 also includes a transfer section r12, a connection section r13 and a first input section r14. The transfer section r12 is in the same layer as the second section r21 and is arranged on the second insulating layer 13 at intervals. The connection section r13, the first input section r14 and the first electrode plate c11 are arranged on the first insulating layer 12 in the same layer. The connection section r13 is connected to the first electrode plate c11 and the first input section r14. The first input section r14 is connected to the first reset circuit D3. The second insulating layer 13 is provided with a first via k1 and a second via k2, the first via k1 also penetrates the first insulating layer 12 and exposes the first section r11, and the second via k2 exposes the connection section r13. One end of the transfer section r12 is connected to the first section r11 through the first via k1, and the other end of the transfer section r12 is connected to the connection section r13 through the second via k2.

[0094] The first section r11 and the connection section r13 are connected via a transfer section r12 of a different layer, which can save wiring space in the horizontal direction.

[0095] Optionally, the connecting section r13, the first input section r14, the first electrode plate c11 and the active layer yy of the fourth transistor T4 of the first reset circuit D3 are arranged in the same layer, and the materials of the four all include metal oxide semiconductors.

[0096] The connecting section r13, the first input section r14, the first electrode c11 and the active layer of the fourth transistor T4 of the first reset circuit D3 can be manufactured using the same photomask process, thereby saving the process and increasing the capacitance of the first capacitor C1.

[0097] Optionally, the fourth transistor T4 further includes a gate g, which is connected to the first reset signal line R3 through a third via k3. The first reset signal line R3 is arranged in the same layer as the second segment r21 of the second initial signal line R2. The gate g is arranged in a different layer from the first reset signal line R3. The first electrode and the second electrode of the fourth transistor T4 are integrally formed with the active layer yy.

[0098] A third insulating layer 14 is disposed between the gate g and the first reset signal line R3 . The gate g is disposed on a side of the second insulating layer 13 away from the substrate 11 . The third insulating layer 14 covers the gate g and the second insulating layer 13 . The first reset signal line R3 is disposed on the third insulating layer 14 .

[0099] Optionally, the second segment r21, the connecting segment r13, the second electrode plate c12 and the first reset signal line R3 may be manufactured using the same photomask process, and the materials of the four are the same.

[0100] Optionally, the second initial signal line R2 further includes a second input segment r22. The second input segment r22 is disposed on the substrate 11. The second segment r21 is connected to the second input segment r22 through a fourth via k4. The second input segment r22 is linked to the first electrode of the seventh transistor T7.

[0101] The second input section r22 is disposed in the same layer as the active layer of the seventh transistor T7. The material of the second input section r22 is polysilicon.

[0102] A fourth insulating layer 15 is disposed between the second input section r22 and the first section r11. The second input section r22 is disposed on the substrate 11. The fourth insulating layer 15 covers the second input section r22 and the substrate 11. The first section r11 and the compensation plate c13 are disposed on a side of the fourth insulating layer 15 away from the substrate 11.

[0103] Optionally, the second input section r22 and the active layer of the seventh transistor T7 are formed by the same photomask process, and the materials of the two are the same.

[0104] The above is a detailed introduction to a pixel driving circuit and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, comprising a pixel driving circuit, characterized in that: The display panel comprises a substrate, a first initial signal line, a second initial signal line, a first insulating layer and a second insulating layer, the first initial signal line is configured to input a first initial signal to a first reset circuit of the pixel driving circuit, the first initial signal line comprises a first segment, the first segment is arranged on the substrate, the first insulating layer covers the first segment, a first electrode plate is arranged on a side of the first insulating layer away from the substrate, the first segment is connected to the first electrode plate, and the second insulating layer covers the first electrode plate; The second initial signal line is configured to input a second initial signal to the second reset circuit of the pixel driving circuit, the second initial signal line comprises a second segment, the second segment is arranged on a side of the second insulating layer away from the substrate, a second electrode plate is connected to the second segment, and an extension direction of the second electrode plate intersects with an extension direction of the second segment; In a direction perpendicular to the plate surface of the display panel, the first electrode plate and the second electrode plate are in different layers and overlapped to form a first capacitor.

2. The display panel according to claim 1, characterized in that: The display panel also includes a data line for accessing a data signal, wherein the data line is arranged on a side of the second insulating layer away from the substrate, and in a direction perpendicular to the surface of the display panel, the data line and the second segment are partially overlapped, and a parasitic capacitance is formed between the data line and the second segment, and the first capacitance is greater than the parasitic capacitance.

3. The display panel according to claim 2, characterized in that: The first capacitor also includes a compensation plate formed by extending the first section in the direction of the first electrode plate, and the compensation plate includes a first part and a second part that are connected, wherein, in the orthographic projection pattern of the display panel, the first part is overlapped with the first electrode plate and the second electrode plate respectively, and the second part is located on the outside of the first electrode plate, and the second part is overlapped with the second electrode plate part.

4. The display panel according to claim 3, characterized in that: The resistivity of the compensation plate is smaller than the resistivity of the first plate.

5. The display panel according to claim 3 or 4, characterized in that: The first initial signal line also includes a transfer section, a connecting section and a first input section. The transfer section is in the same layer as the second section and is arranged at intervals on the second insulating layer. The connecting section, the first input section and the first electrode plate are arranged in the same layer on the first insulating layer. The connecting section is connected to the first electrode plate and the first input section. The first input section is connected to the first reset circuit. The second insulating layer is provided with a first via and a second via. The first via also penetrates the first insulating layer and exposes the first section. The second via exposes the connecting section. One end of the transfer section is connected to the first section through the first via, and the other end of the transfer section is connected to the connecting section through the second via.

6. The display panel according to claim 5, characterized in that: The connecting section, the first input section, the first electrode plate and the active layer of the fourth transistor of the first reset circuit are arranged in the same layer, and the materials of the four all include metal oxide semiconductors.

7. The display panel according to any one of claims 1 to 4, characterized in that: The pixel driving circuit comprises: a first transistor, wherein the first transistor is a driving transistor, a gate of the first transistor is connected to a first node, a first electrode of the first transistor is connected to a second node, and a second electrode of the first transistor is connected to a third node; a data writing circuit, the data writing circuit being connected to the second node, the data writing circuit being used for writing a data signal into the second node in response to a first gate driving signal; a threshold compensation circuit, the threshold compensation circuit connecting the first node and the third node, the threshold compensation circuit being used to connect the first node and the third node in response to a second gate driving signal; the first reset circuit, the first reset circuit being connected to the first node and the first initial signal line and being used for transmitting a signal of the first initial signal line to the first node in response to a first reset signal; a control circuit, the control circuit being connected to the first power supply terminal, the second node, the third node and the fourth node, the control circuit being used to transmit the signal of the first power supply terminal to the second node in response to an enable signal, and being used to connect the third node and the fourth node in response to the enable signal; the second reset circuit, the second reset circuit being connected to the fourth node and the second initial signal line, the second reset circuit being used for transmitting a signal of the second initial signal line to the fourth node in response to a second reset signal; The first capacitor, one end of the first capacitor is connected to the first initial signal line, and the other end of the first capacitor is connected to the second initial signal line; and A light emitting device, wherein an anode of the light emitting device is connected to the fourth node.

8. The display panel according to claim 7, characterized in that: The pixel driving circuit further includes a second capacitor, a third capacitor and a third reset circuit, one end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the control end of the data writing circuit; One end of the third capacitor is connected to the first node, and the other end of the third capacitor is connected to the first power supply end; The third reset circuit is connected to the second node and the second power supply terminal, and is used for inputting a signal from the second power supply terminal to the second node in response to the second reset signal.

9. The display panel according to claim 8, characterized in that: The data writing circuit comprises a second transistor, the gate of the second transistor is connected to the second capacitor and used to access the first gate driving signal, the first electrode of the second transistor is used to access the data signal, and the second electrode of the second transistor is connected to the second node; The threshold compensation circuit includes a third transistor, the gate of the third transistor is used to access the second gate drive signal, the first electrode of the third transistor is connected to the first node, and the second electrode of the third transistor is connected to the third node; The first reset circuit includes a fourth transistor, a gate of the fourth transistor is used to receive the first reset signal, a first electrode of the fourth transistor is connected to the first initial signal line, and a second electrode of the fourth transistor is connected to the first node; The control circuit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is used to access the enable signal, the first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode of the fifth transistor is connected to the second node, the gate of the sixth transistor is used to access the enable signal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node; The second reset circuit comprises a seventh transistor, a gate of the seventh transistor is used to receive the second reset signal, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the fourth node; The third reset circuit includes an eighth transistor, a gate of the eighth transistor is used to receive the second reset signal, a first electrode of the eighth transistor is connected to the second power supply terminal, and a second electrode of the eighth transistor is connected to the second node.

10. The display panel according to claim 9, characterized in that: The first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type low temperature polysilicon transistors, and the third transistor and the fourth transistor are N-type oxide transistors.

11. The display panel according to claim 7, characterized in that: The capacitance of the first capacitor is greater than or equal to 14.4 fF.

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