Display panel and display device

Abstract

The application provides a display panel and a display device, and relates to the technical field of display, and aims to solve the problem of crosstalk between data lines with a short distance and display defects caused by excessive data lines due to limited layout space. In the display panel, each column of driving circuit columns corresponds to two data lines, the first odd number of sub-pixel driving circuits in the driving circuit column are coupled with the first data line, and the second even number of sub-pixel driving circuits in the driving circuit column are coupled with the second data line; at least part of the data lines are divided into a plurality of first data line groups and a plurality of second data line groups, the first data line groups and the second data line groups are alternately arranged, each data line group comprises two adjacent data lines; the distance between the two data lines in the first data line group is smaller than the distance between the two data lines in the second data line group; the two data lines in the same first data line group are both the first data line or both the second data line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] At present, the market end cost demand is reduced, and the corresponding driving chip (Source IC) function is reduced and the driving chip size is reduced in the display device end. Therefore, the Dual Data Line (DDL) design is introduced in the display device design, so as to optimize the insufficient data writing problem caused by the reduction of Source IC. However, due to the limited layout space, the design of too many data lines will cause crosstalk between the data lines close to each other, and the crosstalk type display defect will occur. SUMMARY

[0003] The purpose of the present application is to provide a display panel and a display device, which can solve the problem that the design of too many data lines will cause crosstalk between the data lines close to each other due to the limited layout space, and the crosstalk type display defect will occur.

[0004] In order to achieve the above purpose, the present application provides the following technical scheme:

[0005] The first aspect of the present application provides a display panel, comprising: a substrate and a plurality of sub-pixels arranged on the substrate, the sub-pixels comprising a sub-pixel driving circuit, the sub-pixel driving circuit comprising a driving transistor, the plurality of sub-pixels comprising a plurality of sub-pixel driving circuit columns; the display panel further comprises:

[0006] a plurality of data lines, each driving circuit column corresponding to two data lines, the first odd number of sub-pixel driving circuits in the driving circuit column being coupled to the first data line of the two data lines, and the second even number of sub-pixel driving circuits in the driving circuit column being coupled to the second data line of the two data lines;

[0007] At least part of the data lines is divided into a plurality of first data line groups and a plurality of second data line groups, the first data line groups and the second data line groups are arranged alternately, each data line group comprises two adjacent data lines, the first data line group has a driving transistor gate included in a driving circuit column, and the second data line group has a driving transistor gate included in a driving circuit column; the distance between the two data lines in the first data line group is less than the distance between the two data lines in the second data line group;

[0008] Two data lines in the same group of the first data line group are the first data line or the second data line.

[0009] Optionally, the plurality of drive circuit columns are divided into a plurality of drive circuit groups, each drive circuit group including two adjacent drive circuit columns.

[0010] The normal projection of the gate of the two drive transistors in the drive circuit group on the substrate is arranged alternately with the normal projection of the first data line group on the substrate, and the normal projection of the second data line group on the substrate is located between the normal projection of the gate of the two drive transistors in the corresponding drive circuit group on the substrate.

[0011] In the two adjacent drive circuit groups, in the data lines coupled by one drive circuit group, the first data line is located at the first side of the corresponding drive circuit column, and the second data line is located at the second side of the corresponding drive circuit column; in the data lines coupled by the other drive circuit group, the first data line is located at the second side of the corresponding drive circuit column, and the second data line is located at the first side of the corresponding drive circuit column; the first side and the second side are opposite along the first direction.

[0012] Optionally, the display panel further includes a plurality of gate-on units, the gate-on unit includes a first gate-on subunit, a second gate-on subunit, a third gate-on subunit and a fourth gate-on subunit; the display panel further includes a first gate-on control line, a second gate-on control line, a third gate-on control line and a fourth gate-on control line.

[0013] The first gate-on subunit is coupled with the first gate-on control line, the corresponding data signal input end and the corresponding first data line of the first drive circuit column in the corresponding drive circuit group, respectively, for controlling the electrical connection between the data signal input end and the first data line to be turned on or turned off under the control of the first gate-on control line.

[0014] The second gate-on subunit is coupled with the second gate-on control line, the corresponding data signal input end and the corresponding first data line of the second drive circuit column in the corresponding drive circuit group, respectively, for controlling the electrical connection between the data signal input end and the first data line to be turned on or turned off under the control of the second gate-on control line.

[0015] The third gate-on subunit is coupled with the third gate-on control line, the corresponding data signal input end and the corresponding second data line of the first drive circuit column in the corresponding drive circuit group, respectively, for controlling the electrical connection between the data signal input end and the second data line to be turned on or turned off under the control of the third gate-on control line.

[0016] The fourth gating subunit is coupled with the fourth gating control line, the corresponding data signal input end, and the second data line corresponding to the second column of driving circuit in the second column of driving circuit group in the second column of driving circuit group, for controlling the electrical connection between the data signal input end and the second data line under the control of the fourth gating control line.

[0017] Optionally, the sub-pixel driving circuit further comprises a data writing transistor, a first reset transistor, a first conductive connection part, and a second conductive connection part.

[0018] The first pole of the data writing transistor is coupled with the corresponding data line through the first conductive connection part, and the second pole of the data writing transistor is coupled with the first pole of the driving transistor; the second pole of the first reset transistor is coupled with the gate of the driving transistor through the second conductive connection part.

[0019] In at least part of the sub-pixels, the orthogonal projection of the second conductive connection part on the substrate substrate is located between the orthogonal projection of the active layer of the data writing transistor on the substrate substrate and the orthogonal projection of the data line coupled with the data writing transistor on the substrate substrate; in the at least part of the sub-pixels, the first conductive connection part comprises a first connection part and a second connection part coupled with each other, the extension direction of the first connection part intersects with the extension direction of the second connection part, the first connection part is coupled with the corresponding data line, and the second connection part is coupled with the first pole of the data writing transistor.

[0020] Optionally, the display panel further comprises a power line, and the orthogonal projection of the first conductive connection part on the substrate substrate at least partially overlaps with the orthogonal projection of the power line on the substrate substrate.

[0021] Optionally, the plurality of sub-pixels comprises red sub-pixels, green sub-pixels, and blue sub-pixels.

[0022] In the driving circuit group, the first column of driving circuit comprises sub-pixel driving circuits of red sub-pixels and sub-pixel driving circuits of blue sub-pixels arranged alternately, and the second column of driving circuit comprises a plurality of sub-pixel driving circuits of green sub-pixels arranged in sequence.

[0023] Optionally, in the two adjacent driving circuit groups, the first column of driving circuit in one of the driving circuit groups comprises sub-pixel driving circuits of red sub-pixels and sub-pixel driving circuits of blue sub-pixels arranged alternately, and the first column of driving circuit in the other of the driving circuit groups comprises sub-pixel driving circuits of blue sub-pixels and sub-pixel driving circuits of red sub-pixels arranged alternately.

[0024] Optionally, two data lines in the same group of the second data line group include the first data line and the second data line.

[0025] Optionally, the display panel further includes a plurality of first signal lines, and one of the first signal lines is between two data lines in the second data line group.

[0026] Optionally, the display panel further includes a plurality of power supply lines, and a normal projection of a power supply line corresponding to the driving circuit column on the substrate substrate is located between normal projections of two data lines corresponding to the driving circuit column on the substrate substrate.

[0027] Optionally, the plurality of sub-pixels are divided into a plurality of driving circuit rows, and in the same driving circuit row, two adjacent sub-pixels include sub-pixel driving circuits that are mirror-symmetric.

[0028] Optionally, the display panel includes a hole region, an isolation region, and a pixel region, the isolation region is located between the hole region and the pixel region; the plurality of data lines include a plurality of hole-region-crossing data lines, the plurality of hole-region-crossing data lines include a plurality of first-type data lines and a plurality of second-type data lines.

[0029] The first-type data line includes a first data portion, a first-type cross-region data portion, and a second data portion that are sequentially coupled, the first data portion and the second data portion are located on opposite sides of the hole region, and the first data portion, the first-type cross-region data portion, and the second data portion are all located in the pixel region.

[0030] The second-type data line includes a third data portion, a second-type cross-region data portion, and a fourth data portion that are sequentially coupled, the third data portion and the fourth data portion are located on opposite sides of the hole region, and the third data portion and the fourth data portion are both located in the pixel region, and the second-type cross-region data portion is located in the isolation region.

[0031] Optionally, the plurality of second-type data lines are divided into a first portion of second-type data lines and a second portion of second-type data lines, and the plurality of first-type data lines are located between the first portion of second-type data lines and the second portion of second-type data lines.

[0032] Optionally, the first data portion included in the first-type data line and the third data portion included in the second-type data line are alternately arranged; and the second data portion included in the first-type data line and the fourth data portion included in the second-type data line are alternately arranged.

[0033] Optionally, the first-type data line is coupled to a corresponding green sub-pixel, and the second-type data line is coupled to a corresponding red sub-pixel and / or blue sub-pixel.

[0034] Based on the technical solution of the display panel, the second aspect of the present application provides a display device comprising the display panel.

[0035] In the technical solution provided by the present application, two data lines are arranged corresponding to each column of driving circuit columns, the first odd-numbered sub-pixel driving circuit in the driving circuit column is coupled with the first data line of the two data lines, and the first even-numbered sub-pixel driving circuit in the driving circuit column is coupled with the second data line of the two data lines. This arrangement allows the first odd-numbered sub-pixel driving circuit and the first even-numbered sub-pixel driving circuit in a column of driving circuit columns to be provided with data signals from different data lines, thereby prolonging the time for the data lines to write data signals to the corresponding sub-pixel driving circuits and ensuring that each sub-pixel driving circuit can be fully written with data signals, thereby avoiding display problems caused by insufficient writing of data signals.

[0036] In the technical solution provided by the present application, the distance between the two data lines in the first data line group is less than the distance between the two data lines in the second data line group, and the two data lines in the same first data line group are either both the first data line or both the second data line. When scanning an odd-numbered row of sub-pixels or an even-numbered row of sub-pixels in the display panel, the two data lines in the first data line group that are closer in distance can write data signals to the sub-pixel driving circuits in the same odd-numbered row or to the sub-pixels in the same even-numbered row. In this way, the two data lines in the first data line group that are closer in distance can be controlled by the gate sub-unit, and the time for writing data signals is close, i.e., the time for the two data lines to write data signals to the sub-pixel driving circuits is the same, thereby shortening the time difference for the two data lines in the first data line group that are closer in distance to write data signals and reducing the risk of one data line being in a floating state after completing data writing and being disturbed by another data line. Therefore, the technical solution provided by the present application effectively reduces the crosstalk problem between data lines that are closer in distance and improves the crosstalk-related display problems caused by crosstalk between data lines. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which are included to provide a further understanding of the present application, form a part of the present application and illustrate the illustrative embodiments of the present application and its description, and do not constitute improper limitations on the present application. In the drawings:

[0038] Figure 1 The circuit schematic diagram of the sub-pixel driving circuit provided for the embodiments of the present application;

[0039] Figure 2A layout schematic diagram of an active layer in an array distributed sub-pixel provided by the embodiment of the present application is shown in the figure;

[0040] Figure 3 A layout schematic diagram of an active layer and a first gate metal layer in an array distributed sub-pixel provided by the embodiment of the present application is shown in the figure;

[0041] Figure 4 A layout schematic diagram of a second gate metal layer in an array distributed sub-pixel provided by the embodiment of the present application is shown in the figure;

[0042] Figure 5 A layout schematic diagram of a second gate metal layer added on the basis of Figure 3 ;

[0043] Figure 6 A layout schematic diagram of an interlayer insulating layer via in an array distributed sub-pixel provided by the embodiment of the present application is shown in the figure;

[0044] Figure 7 A layout schematic diagram of an interlayer insulating layer via added on the basis of Figure 5 ;

[0045] Figure 8 A layout schematic diagram of a first source-drain metal layer in an array distributed sub-pixel provided by the embodiment of the present application is shown in the figure;

[0046] Figure 9 A layout schematic diagram of a first source-drain metal layer added on the basis of Figure 7 ;

[0047] Figure 10 A layout schematic diagram of a passivation layer via added on the basis of Figure 9 ;

[0048] Figure 11 A layout schematic diagram of a planarization layer via in an array distributed sub-pixel provided by the embodiment of the present application is shown in the figure;

[0049] Figure 12 A layout schematic diagram of a planarization layer via added on the basis of Figure 10 ;

[0050] Figure 13 A layout schematic diagram of a second source-drain metal layer in an array distributed sub-pixel provided by the embodiment of the present application is shown in the figure;

[0051] Figure 14 A layout schematic diagram of a second source-drain metal layer added on the basis of Figure 12 ;

[0052] Figure 15 A connection schematic diagram of a data line and a selection unit in a display panel provided by the embodiment of the present application is shown in the figure;

[0053] Figure 16 A timing diagram of the gate control line provided by the embodiment of the present application;

[0054] Figure 17 A layout schematic diagram of the gate unit provided by the embodiment of the present application;

[0055] Figure 18 A first layout schematic diagram near the hole region provided by the embodiment of the present application;

[0056] Figure 19 A second layout schematic diagram near the hole region provided by the embodiment of the present application;

[0057] Figure 20 A corresponding wiring schematic diagram provided by the embodiment of the present application; Figure 18

[0058] Figure 21 A mirror layout schematic diagram of the sub-pixel driving circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to further illustrate the display panel and the display device provided by the embodiment of the present application, the following will be described in detail in combination with the drawings of the specification.

[0060] Please refer to Figures 1 to 14 The embodiment of the present application provides a display panel, comprising: a substrate and a plurality of sub-pixels provided on the substrate, the sub-pixels comprising a sub-pixel driving circuit, the sub-pixel driving circuit comprising a driving transistor, the plurality of sub-pixels comprising a plurality of sub-pixel driving circuits divided into a plurality of driving circuit columns; the display panel further comprises:

[0061] a plurality of data lines, each driving circuit column corresponding to two data lines, the first odd-numbered sub-pixel driving circuit in the driving circuit column being coupled to a first data line DA1 in the two data lines, and the first even-numbered sub-pixel driving circuit in the driving circuit column being coupled to a second data line DA2 in the two data lines;

[0062] At least part of the data lines is divided into a plurality of first data line groups Z11 and a plurality of second data line groups Z12, the first data line groups Z11 and the second data line groups Z12 being arranged alternately, each data line group comprising two adjacent data lines, the first data line group Z11 having a projection on the substrate between the projection of the adjacent second data line group Z12 on the substrate and the projection of the gate of the driving transistor included in the driving circuit column on the substrate; the distance between the two data lines in the first data line group Z11 is smaller than the distance between the two data lines in the second data line group Z12;

[0063] ​The two data lines in the same group of the first data line group Z11 are both the first data line DA1 or both the second data line DA2.

[0064] Exemplarily, the display substrate comprises a plurality of sub-pixels, and a plurality of sub-pixel driving circuits included in the plurality of sub-pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of driving circuit rows and a plurality of columns of driving circuit columns. The plurality of rows of driving circuit rows are arranged along a second direction, and each row of driving circuit rows comprises a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of driving circuit columns are arranged along the first direction, and each column of driving circuit columns comprises a plurality of sub-pixel driving circuits arranged along the second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction comprises a horizontal direction, and the second direction comprises a vertical direction.

[0065] Exemplarily, the sub-pixel comprises a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element, and is configured to provide a driving signal for the light-emitting element to drive the light-emitting element to emit light.

[0066] Exemplarily, the specific structure of the sub-pixel driving circuit is various, for example, a 7T1C (7 transistors and 1 capacitor) circuit structure, an 8T1C (8 transistors and 1 capacitor) circuit structure, and the like, but is not limited thereto.

[0067] Hereinafter, taking the sub-pixel driving circuit adopting the 7T1C circuit structure as an example, the connection relationship of the sub-pixel driving circuit belonging to the nth row of driving circuit rows is described in detail.

[0068] The sub-pixel driving circuit comprises a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a data writing transistor T4, a power supply control transistor T5, a light-emitting control transistor T6, and a storage capacitor Cst.

[0069] The gate of the first reset transistor T1 is coupled to a corresponding first scan line GA1, the first electrode of the first reset transistor T1 is coupled to a corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g (i.e., the first node N1) of the driving transistor T3.

[0070] The gate of the compensation transistor T2 is coupled to a corresponding second scan line GA2, the first electrode of the compensation transistor T2 is coupled to the second electrode (i.e., the third node N3) of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0071] A gate of the data write transistor T4 is coupled with a corresponding second scan line GA2, a first electrode of the data write transistor T4 is coupled with a corresponding data line DA, and a second electrode of the data write transistor T4 is coupled with the first electrode (i.e., the second node N2) of the drive transistor T3.

[0072] A gate of the power control transistor T5 is coupled with a corresponding light emitting control signal line EM, a first electrode of the power control transistor T5 is coupled with a corresponding power supply line VDD, and a second electrode of the power control transistor T5 is coupled with the first electrode of the drive transistor T3.

[0073] A gate of the light emitting control transistor T6 is coupled with a corresponding light emitting control signal line EM, a first electrode of the light emitting control transistor T6 is coupled with the second electrode of the drive transistor T3, and a second electrode of the light emitting control transistor T6 is coupled with an anode of a corresponding light emitting element (i.e., the fourth node N4). A cathode of the light emitting element receives a negative power supply signal VSS.

[0074] A gate of the second reset transistor T7 is coupled with a corresponding first scan line GA1’ of an adjacent next row of drive circuit rows, a first electrode of the second reset transistor T7 is coupled with a corresponding second initialization signal line Vinit2, and a second electrode of the second reset transistor T7 is coupled with an anode of a corresponding light emitting element.

[0075] A first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the drive transistor T3, and a second plate Cst2 of the storage capacitor Cst is coupled with a corresponding power supply line VDD.

[0076] Illustratively, the display panel further includes a plurality of data lines, the plurality of data lines are arranged along the first direction, each data line includes at least a portion extending along the second direction. Each drive circuit column corresponds to two data lines, and a normal projection of the gate of the drive transistor included in the drive circuit column on the substrate is located between normal projections of the corresponding two data lines on the substrate.

[0077] Illustratively, the plurality of data lines includes a start data line, an end data line, and a plurality of intermediate data lines located between the start data line and the end data line; the plurality of intermediate data lines is divided into a plurality of first data line groups Z11 and a plurality of second data line groups Z12, the first data line groups Z11 and the second data line groups Z12 are arranged alternately along the first direction. The first data line groups Z11 and the second data line groups Z12 each include two adjacent data lines.

[0078] Exemplarily, the minimum distance between two data lines in the first data line group Z11 is less than the minimum distance between two data lines in the second data line group Z12. The minimum distance between the adjacent first data line group Z11 and the second data line group Z12 is greater than the minimum distance between two data lines in the second data line group Z12.

[0079] Exemplarily, the two data lines in the same group of the first data line group Z11 are both the first data line DA1, that is, the two data lines in the same group of the first data line group Z11 are both coupled to the first odd-numbered sub-pixel; or, the two data lines in the same group of the first data line group Z11 are both the second data line DA2, that is, the two data lines in the same group of the first data line group Z11 are both coupled to the first even-numbered sub-pixel.

[0080] According to the specific structure of the display panel, in the display panel provided by the embodiment of the present application, two data lines are arranged corresponding to each column of driving circuit columns, the first odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to the first data line DA1 of the two data lines, and the first even-numbered sub-pixel driving circuit in the driving circuit column is coupled to the second data line DA2 of the two data lines; this arrangement makes the first odd-numbered sub-pixel driving circuit and the first even-numbered sub-pixel driving circuit in one column of driving circuit columns provided with data signals by different data lines, prolongs the time for the data line to write data signals to the corresponding sub-pixel driving circuit, ensures that each sub-pixel driving circuit can be fully written with data signals, and avoids the display defect problem caused by insufficient writing of data signals.

[0081] The display panel provided by the embodiment of the present application has the following advantages: the distance between two data lines in the first data line group Z11 is less than the distance between two data lines in the second data line group Z12, and the two data lines in the same first data line group Z11 are the first data line DA1 or the second data line DA2; when scanning an odd row of sub-pixels or an even row of sub-pixels in the display panel, the two data lines in the first data line group Z11 that are close to each other can write data signals to the sub-pixel drive circuits in the same odd row or the sub-pixels in the same even row; in this way, the two data lines in the first data line group Z11 that are close to each other can be controlled by the gate sub-unit, and the time for writing data signals is close, that is, the time for the two data lines to write data signals to the sub-pixel drive circuits is the same, thereby shortening the time difference for the two data lines in the first data line group Z11 that are close to each other to write data signals and reducing the risk that one data line is in a floating state and is disturbed by another data line after completing data writing. Therefore, the display panel provided by the embodiment of the present application effectively reduces the crosstalk problem between data lines that are close to each other and improves the crosstalk display problem caused by the crosstalk between data lines.

[0082] As shown in Figures 2 to 14 In some embodiments, the plurality of drive circuit columns is divided into a plurality of drive circuit groups Z2, each drive circuit group Z2 includes two adjacent drive circuit columns;

[0083] The normal projection of the gates of the two drive transistors in the drive circuit group Z2 on the substrate is arranged alternately with the normal projection of the first data line group Z11 on the substrate, and the normal projection of the second data line group Z12 on the substrate is located between the normal projection of the gates of the two drive transistors in the corresponding drive circuit group Z2 on the substrate.

[0084] In the two adjacent drive circuit groups Z2, in the data lines coupled by one drive circuit group Z2, the first data line DA1 is located on the first side of the corresponding drive circuit column, and the second data line DA2 is located on the second side of the corresponding drive circuit column; in the data lines coupled by the other drive circuit group Z2, the first data line DA1 is located on the second side of the corresponding drive circuit column, and the second data line DA2 is located on the first side of the corresponding drive circuit column; the first side and the second side are opposite along the first direction.

[0085] For example, the plurality of drive circuit columns is divided into a plurality of drive circuit groups Z2, and the plurality of drive circuit groups Z2 are arranged along the first direction. The two drive circuit columns in the drive circuit group Z2 include two drive transistors.

[0086] The above setting mode can realize that two data lines in the same group of the first data line group are the first data line DA1 or the second data line DA2.

[0087] As shown in FIG. 1, in some embodiments, the display panel further includes a plurality of gating units, and each gating unit includes a first gating sub-unit (including a first gating transistor T8), a second gating sub-unit (including a second gating transistor T9), a third gating sub-unit (including a third gating transistor T10), and a fourth gating sub-unit (including a fourth gating transistor T11). Figures 13 to 17

[0088] The first gating sub-unit is coupled with the first gating control line MUX1, a corresponding data signal input end (such as A1, A2, A3, A4), and a first data line DA1 corresponding to a first column of driving circuit columns in the corresponding driving circuit group Z2, respectively, and is used to control the electrical connection between the data signal input end A1 and the first data line DA1 to be turned on or turned off under the control of the first gating control line MUX1.

[0089] The second gating sub-unit is coupled with the second gating control line MUX2, a corresponding data signal input end, and a first data line DA1 corresponding to a second column of driving circuit columns in the corresponding driving circuit group Z2, respectively, and is used to control the electrical connection between the data signal input end and the first data line DA1 to be turned on or turned off under the control of the second gating control line MUX2.

[0090] The third gating sub-unit is coupled with the third gating control line MUX3, a corresponding data signal input end, and a second data line DA2 corresponding to the first column of driving circuit columns in the corresponding driving circuit group Z2, respectively, and is used to control the electrical connection between the data signal input end and the second data line DA2 to be turned on or turned off under the control of the third gating control line MUX3.

[0091] The fourth gating sub-unit is coupled with the fourth gating control line MUX4, a corresponding data signal input end, and a second data line DA2 corresponding to the second column of driving circuit columns in the corresponding driving circuit group Z2, respectively, and is used to control the electrical connection between the data signal input end and the second data line DA2 to be turned on or turned off under the control of the fourth gating control line MUX4.

[0092] ​Exemplarily, the first gating subunit comprises a first gating transistor T8, a gate of the first gating transistor T8 is coupled with the first gating control line MUX1, a first pole of the first gating transistor T8 is coupled with a corresponding data signal input end, and a second pole of the first gating transistor T8 is coupled with a corresponding first data line DA1 in a first column driving circuit column of the corresponding driving circuit group Z2.

[0093] Exemplarily, the second gating subunit comprises a second gating transistor T9, a gate of the second gating transistor T9 is coupled with the second gating control line MUX2, a first pole of the second gating transistor T9 is coupled with a corresponding data signal input end, and a second pole of the second gating transistor T9 is coupled with a corresponding first data line DA1 in a second column driving circuit column of the corresponding driving circuit group Z2.

[0094] Exemplarily, the third gating subunit comprises a third gating transistor T10, a gate of the third gating transistor T10 is coupled with the third gating control line MUX3, a first pole of the third gating transistor T10 is coupled with a corresponding data signal input end, and a second pole of the third gating transistor T10 is coupled with a corresponding second data line DA2 in the first column driving circuit column of the corresponding driving circuit group Z2.

[0095] Exemplarily, the fourth gating subunit comprises a fourth gating transistor T11, a gate of the fourth gating transistor T11 is coupled with the fourth gating control line MUX4, a first pole of the fourth gating transistor T11 is coupled with a corresponding data signal input end, and a second pole of the fourth gating transistor T11 is coupled with a corresponding second data line DA2 in the second column driving circuit column of the corresponding driving circuit group Z2.

[0096] Exemplarily, the first gating transistor T8, the second gating transistor T9, the third gating transistor T10 and the fourth gating transistor T11 are all P-type transistors, but are not limited thereto.

[0097] More specifically, the above embodiment is based on MUX1:4 (i.e. one data signal input end corresponds to four data lines), i.e. column MUX1:2 (i.e. one column driving circuit column corresponds to two data lines) + row MUX1:2 (i.e. an odd-numbered row driving circuit row corresponds to a first data line, and an even-numbered row driving circuit row corresponds to a second data line) combined with shift register unit odd and even row driving, which can improve sub-pixel threshold voltage compensation time and improve display uniformity. However, due to MUX1:4, the number of data lines to be set is doubled, and in spatial arrangement, the distance between adjacent data lines will necessarily decrease, i.e. the parasitic capacitance between adjacent data lines will increase. At the same time, the crosstalk between data lines will increase, which is easy to form crosstalk type display defects.

[0098] As shown in Figure 15 The first selection signal transmitted by the first gate control line MUX1, the second selection signal transmitted by the second gate control line MUX2, the third selection signal transmitted by the third gate control line MUX3 and the fourth selection signal transmitted by the fourth gate control line MUX4 are in turn at the active level (such as low level), and when the selection signal is at the active level, the corresponding gate transistor is turned on, and the data signal provided by the data signal input end is written into the corresponding data line.

[0099] As shown in the time period boxed by the dashed box in Figure 15 corresponding to the low potential of the scanning signal GateP[2n-1], at this time the data writing transistor T4 in the 2n-1 row sub-pixel is opened, and the data line controlled by the first gate control line MUX1 and the second gate control line MUX2 writes the data signal to the gate of the driving transistor T3 through the data writing transistor T4 and the compensation transistor T2 (the data signal on this data line is pre-stored or written in the current period), that is, the data line controlled by the first gate control line MUX1 and the second gate control line MUX2 writes the data signal to the N1 node, and in this time period, the data line corresponding to the 2n row sub-pixel is controlled by the third gate control line MUX3 and the fourth gate control line MUX4 to write data signal to the data line and store in the data line, so as to realize writing the corresponding sub-pixel driving circuit when the scanning signal GateP[2n] is at low level; if the data line controlled by the third gate control line MUX3 and the fourth gate control line MUX4 has large parasitic capacitance with the data line controlled by the first gate control line MUX1 and the second gate control line MUX2, then the data line controlled by the third gate control line MUX3 and the fourth gate control line MUX4 will directly pull the data voltage of the data line controlled by the first gate control line MUX1 and the second gate control line MUX2 when the data voltage jumps, and since the scanning signal GateP[2n-1] is at low level at this time, the pulled data voltage will be directly written into the corresponding sub-pixel driving circuit, resulting in signal writing abnormality of the sub-pixel driving circuit, which is manifested as poor crosstalk.

[0100] The display panel provided by the above embodiment adopts DDL combined with MUX1:4 driving design, and the two data lines with large parasitic capacitance in the same first data line group are adjusted to the data line corresponding to the same row of sub-pixels through MUX transformation, so that in the whole display panel, the two data lines close to each other are only the second data line DA2 controlled by MUX3 and MUX4, or the first data line DA1 controlled by MUX1 and MUX2, greatly reducing the crosstalk problem between the data lines in the same first data line group.

[0101] AsFigures 2 to 14 In some embodiments, the sub-pixel driving circuit further comprises a data writing transistor T4, a first reset transistor T1, a first conductive connection 31 and a second conductive connection 32.

[0102] In at least part of the sub-pixels, a first electrode of the data writing transistor T4 is coupled with a corresponding data line through the first conductive connection 31, and a second electrode of the data writing transistor T4 is coupled with a first electrode of the driving transistor T3; a second electrode of the first reset transistor T1 is coupled with a gate electrode of the driving transistor through the second conductive connection 32.

[0103] In at least part of the sub-pixels, a normal projection of the second conductive connection 32 on the substrate substrate is located between a normal projection of an active layer of the data writing transistor T4 on the substrate substrate and a normal projection of a data line coupled with the data writing transistor T4 on the substrate substrate; in the at least part of the sub-pixels, the first conductive connection 31 comprises a first connection portion 311 and a second connection portion 312 coupled with each other, an extension direction of the first connection portion 311 intersects with an extension direction of the second connection portion 312, the first connection portion 311 is coupled with the corresponding data line, and the second connection portion 312 is coupled with the first electrode of the data writing transistor T4.

[0104] For example, the first conductive connection 31 and the second conductive connection 32 are provided in the same layer and with the same material, but are not limited thereto.

[0105] For example, in at least part of the sub-pixels, the data writing transistor T4 included in the sub-pixel is close to one side of the sub-pixel driving circuit included in the sub-pixel, and a data line coupled with the data writing transistor T4 included in the sub-pixel is close to the other side of the sub-pixel driving circuit, i.e., the data writing transistor T4 included in the sub-pixel and the data line coupled with the data writing transistor T4 are located on opposite sides of the sub-pixel driving circuit.

[0106] For example, the first conductive connection 31 comprises a first connection portion 311 and a second connection portion 312 coupled with each other, and the first connection portion 311 and the second connection portion 312 are formed in an integrated structure.

[0107] The above arrangement allows the data writing transistor T4 and the data line coupled therewith to be connected through the first conductive connection 31 in the at least part of the sub-pixels.

[0108] For example, the data writing transistor T4 is located on one side of the sub-pixel driving circuit, and the data line coupled with the data writing transistor T4 is located on the other side of the sub-pixel driving circuit. Figure 8 , Figure 13 and Figure 14As shown, in some embodiments, the display panel further includes a power line VDD, and the orthographic projection of the first conductive connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the power line VDD on the substrate.

[0109] The above configuration enables the power line VDD to shield the signal transmitted by the first conductive connection 31 from interference from surrounding signals, thus ensuring the stability of the signal transmitted by the first conductive connection 31.

[0110] In some embodiments, the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels; in the driving circuit group Z2, the first column of driving circuits includes sub-pixel driving circuits for alternating red sub-pixels and sub-pixel driving circuits for alternating blue sub-pixels, and the second column of driving circuits includes sub-pixel driving circuits for a plurality of green sub-pixels arranged in sequence.

[0111] For example, the first column of driving circuits includes sub-pixel driving circuits for red sub-pixels and blue sub-pixels arranged alternately along the second direction, and the second column of driving circuits includes sub-pixel driving circuits for a plurality of green sub-pixels arranged sequentially along the second direction.

[0112] For example, in two adjacent sets of driving circuit groups Z2, the first column of driving circuits in one set of driving circuit groups Z2 includes alternating sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels, and the first column of driving circuits in the other set of driving circuit groups Z2 includes alternating sub-pixel driving circuits for blue sub-pixels and sub-pixel driving circuits for red sub-pixels.

[0113] By arranging subpixels in the above manner, each data line can be coupled to a subpixel of only one color. This means that the range of data signal transitions on each data line is small. Thus, even if one data line in the first data line group Z11 experiences a data signal transition, the crosstalk to the other data line is also small. Similarly, if one data line in the second data line group Z12 experiences a data signal transition, the crosstalk to the other data line is also small.

[0114] like Figure 13 As shown, in some embodiments, the display panel further includes multiple power lines VDD, and the orthographic projection of the power line VDD corresponding to the driving circuit column on the substrate is located between the orthographic projections of the two data lines corresponding to the driving circuit column on the substrate.

[0115] For example, the power line VDD is used to transmit a power signal with a stable potential.

[0116] For example, the orthographic projection of the power line VDD corresponding to the drive circuit column on the substrate is located between the orthographic projection of the first data line DA1 and the second data line DA2 corresponding to the drive circuit column on the substrate.

[0117] For example, the power line VDD corresponding to the driving circuit column is located between the red data line used to transmit the data signal corresponding to the red sub-pixel and the blue data line used to transmit the data signal corresponding to the blue sub-pixel; or, the power line VDD corresponding to the driving circuit column is located between the green data line used to transmit the data signal corresponding to the green sub-pixel and the green data line used to transmit the data signal corresponding to the green sub-pixel.

[0118] The above configuration allows the power line VDD to effectively shield the crosstalk between the two data lines corresponding to the drive circuit column.

[0119] In some embodiments, the display panel further includes a shielding line whose orthogonal projection on the substrate is located between the orthogonal projections of the two data lines in the first data line group on the substrate.

[0120] For example, the shielded wire is used to transmit an initialization signal, that is, the shielded wire is multiplexed as an initialization signal line; or, the shielded wire is used to transmit a power signal, that is, the shielded wire is multiplexed as a power line VDD.

[0121] It should be noted that the shielding line can be set when the product PPI is relatively small, that is, the pixel size is relatively large and there is sufficient layout space.

[0122] The above configuration enables the shielding cable to effectively shield crosstalk between the two data lines in the first data line group.

[0123] like Figure 13 As shown, in some embodiments, the two data lines in the same group of second data lines Z12 include a first data line DA1 and a second data line DA2.

[0124] For example, the display panel also includes a plurality of first signal lines 40, with one of the first signal lines 40 between two data lines in the second data line group Z12.

[0125] Exemplarily, the first signal line 40 includes an FIP lead, but is not limited thereto. It should be noted that, in order to meet the demand of narrowing the lower frame of the display panel, the display panel can be designed by FIP, that is, the data lines of the left frame and the right frame of the display panel are connected with the FIP lead, the lead is extended to the middle region of the display panel, and then extended to the lower frame region from the middle region, so as to narrow the width of the lower frame of the display panel.

[0126] Exemplarily, the first signal line 40 includes a power supply line VDD or an initialization signal line, but is not limited thereto.

[0127] The above-mentioned arrangement that the two data lines in the second data line group Z12 are provided with the first signal line 40 between the two data lines, so that the first signal line 40 can effectively shield the crosstalk between the two data lines in the second data line group Z12.

[0128] As shown in FIG. 1, Figure 21 In some embodiments, the plurality of sub-pixels are divided into a plurality of driving circuit rows, and in the same driving circuit row, the sub-pixel driving circuits included in adjacent two sub-pixels are mirror-symmetrical.

[0129] It should be noted that, Figure 21 F in FIG. 2 represents a sub-pixel driving circuit, and is not a layout of the sub-pixel driving circuit in the shape of F. It can be seen that in the same driving circuit row, the sub-pixel driving circuits included in adjacent two sub-pixels are mirror-symmetrical, and in the same driving circuit column, the sub-pixel driving circuits have the same layout and are not mirror-processed.

[0130] Exemplarily, in the same driving circuit row, the odd-numbered sub-pixel driving circuits and the even-numbered sub-pixel driving circuits are mirror-symmetrical.

[0131] Exemplarily, the sub-pixel driving circuits included in adjacent two sub-pixels are mirror-symmetrical, and the axis of symmetry of the mirror symmetry is located between the sub-pixel driving circuits included in the adjacent two sub-pixels and extends along the second direction.

[0132] The above-mentioned arrangement is beneficial to the display panel to achieve a higher PPI, and the FIP horizontal and vertical wiring layout is more optimal and has better symmetry, and the anode layer in the display panel has better flatness.

[0133] As shown in FIG. 1, Figures 18 to 20 In some embodiments, the display panel includes a hole region 50, an isolation region 51 and a pixel region 52, the isolation region 51 is located between the hole region 50 and the pixel region 52; the plurality of data lines include a plurality of hole-region-crossing data lines, the plurality of hole-region-crossing data lines include a plurality of first-type data lines and a plurality of second-type data lines;

[0134] The first type of data line comprises a first data portion 61, a first type of cross-region data portion 62 and a second data portion 63 coupled in sequence, the first data portion 61 and the second data portion 63 are located on opposite sides of the hole region 50, and the first data portion 61, the first type of cross-region data portion 62 and the second data portion 63 are all located in the pixel region 52.

[0135] The second type of data line comprises a third data portion 71, a second type of cross-region data portion 72 and a fourth data portion 73 coupled in sequence, the third data portion 71 and the fourth data portion 73 are located on opposite sides of the hole region 50, and the third data portion 71 and the fourth data portion 73 are both located in the pixel region 52, and the second type of cross-region data portion 72 is located in the isolation region 51.

[0136] Illustratively, the display panel comprises a hole region 50, an isolation region 51 and a pixel region 52, the isolation region 51 is located between the hole region 50 and the pixel region 52, the isolation region 51 surrounds the hole region 50, and the pixel region 52 surrounds the isolation region 51.

[0137] Illustratively, the plurality of data lines comprises a plurality of cross-hole region data lines, the cross-hole region data line refers to the data line that will pass through the hole region 50 if the data line is extended in the second direction, and in the actual layout, the data line will bypass the hole region 50, that is, will not pass through the hole region 50.

[0138] Illustratively, the first type of data line comprises a first data portion 61, a first type of cross-region data portion 62 and a second data portion 63 coupled in sequence, the first data portion 61 and the second data portion 63 are located on opposite sides of the hole region 50 in the second direction.

[0139] Illustratively, the first data portion 61 and the second data portion 63 both extend in the second direction, and the first type of cross-region data portion 62 comprises a portion extending in the first direction and a portion extending in the second direction. When the first type of data line adopts the above structure, it is formed in a HIP winding mode.

[0140] Illustratively, the second type of data line comprises a third data portion 71, a second type of cross-region data portion 72 and a fourth data portion 73 coupled in sequence, the third data portion 71 and the fourth data portion 73 are located on opposite sides of the hole region 50 in the second direction.

[0141] Exemplarily, the third data portion 71 and the fourth data portion 73 both extend along the second direction, and the second type of cross-zone data portion 72 extends along the edge of the hole zone 50. When the first type of data line adopts the above structure, that is, is formed in a Fanout winding mode.

[0142] Exemplarily, as shown in Figure 18 and Figure 20 Exemplarily, the plurality of second type of data lines are divided into a first part of second type of data lines and a second part of second type of data lines, and the plurality of first type of data lines (located in the B1 region) are located between the first part of second type of data lines (located in the B2 region) and the second part of second type of data lines (located in the B3 region).

[0143] Exemplarily, as shown in Figure 19 Exemplarily, the first data portion 61 (located in the C1 region) included in the first type of data line and the third data portion 71 (located in the C2 region) included in the second type of data line are alternately arranged; and the second data portion 63 (located in the C3 region) included in the first type of data line and the fourth data portion 73 (located in the C4 region) included in the second type of data line are alternately arranged. For example, the first type of data line is coupled with a corresponding green sub-pixel, and the second type of data line is coupled with a corresponding red sub-pixel and / or blue sub-pixel.

[0144] It is worth noting that, by adopting the design that each column of driving circuit columns corresponds to two data lines (that is, the DDL design), the number of data lines in the display panel will be doubled, so that the number of data lines that need to be wound in the hole zone 50 will also be doubled. If only the Fanout winding mode is adopted, the doubled number of winding in the hole zone 50 will lead to an increase in the wiring space of the isolation zone 51, which will directly lead to an increase in the frame of the hole zone 50.

[0145] The above setting mode adopts a combination of the HIP winding mode and the Fanout winding mode, which can greatly narrow the frame width of the hole zone 50 under the DDL design. More specifically, the display panel provided by the embodiment of the present application can reduce the Fanout winding by 152, and the frame width of the hole zone 50 can be reduced by about 190 microns.

[0146] It should be noted that, as shown in Figure 2 Exemplarily, the third active layer 23 included in the driving transistor T3, the first active layer 21 included in the first reset transistor T1, the seventh active layer 27 included in the second reset transistor T7, the second active layer 22 included in the compensation transistor T2, the fourth active layer 24 included in the data writing transistor T4, the fifth active layer 25 included in the power control transistor T5, and the sixth active layer 26 included in the light-emitting control transistor T6 are shown.

[0147] As shown in Figures 3 to 14As shown, the first conductive connection part 31 is coupled with the first electrode of the data writing transistor T4 through the sixth via Via6, and coupled with the corresponding data line through the twelfth via Via12 and the seventeenth via Via17.

[0148] The second conductive connection part 32 is coupled with the second electrode of the compensation transistor T2 and the second electrode of the first reset transistor T1 respectively through the fifth via Via5, and coupled with the gate T3-g of the driving transistor T3 through the seventh via Via7.

[0149] The third conductive connection part 33 is coupled with the first initialization signal line Vinit1 through the first via Via1, and coupled with the first electrode of the first reset transistor T1 through the second via Via2.

[0150] The fourth conductive connection part 34 is coupled with the first electrode of the data writing transistor T4 through the via Via0, and coupled with the corresponding data line through the thirteenth via Via13 and the twentieth via Via20.

[0151] The fifth conductive connection part 35 is coupled with the first electrode of the second reset transistor T7 through the third via Via3, and coupled with the second initialization signal line Vinit2 through the fourth via Via4.

[0152] The sixth conductive connection part 36 is coupled with the second electrode of the light-emitting control transistor T6 and the second electrode of the second reset transistor T7 respectively through the ninth via Via9, and coupled with the ninth conductive connection part 39 through the fifteenth via Via15 and the nineteenth via Via19, the ninth conductive connection part 39 being coupled with the corresponding anode layer.

[0153] The power supply compensation line 38 is coupled with the second plate Cst2 of the storage capacitor Cst through the eighth via Via8 and the eleventh via Via11, coupled with the first electrode of the power supply control transistor T5 through the tenth via Via10, and coupled with the power supply line VDD through the fourteenth via Via14 and the eighteenth via Via18.

[0154] The FIP transverse lead 37 is coupled with the corresponding longitudinal FIP lead through the sixteenth via Via16.

[0155] The display panel provided by the embodiments of the present application is also provided.

[0156] It should be noted that the display device can be any product or component with display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further comprises a flexible circuit board, a printed circuit board, a back plate, etc.

[0157] In the display panel provided by the above embodiment, two data lines are arranged corresponding to each column of driving circuit columns, an odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to a first data line DA1 of the two data lines, and an even-numbered sub-pixel driving circuit in the driving circuit column is coupled to a second data line DA2 of the two data lines. In this way, the odd-numbered and even-numbered sub-pixel driving circuits in a column of driving circuit columns are provided with data signals from different data lines, the time for the data lines to write data signals to the corresponding sub-pixel driving circuits is extended, the data signals can be fully written to each sub-pixel driving circuit, and the display defects caused by insufficient writing of data signals are avoided.

[0158] In the display panel provided by the above embodiment, the distance between two data lines in the first data line group Z11 is less than the distance between two data lines in the second data line group Z12, and the two data lines in the same group of the first data line group Z11 are both the first data line DA1 or both the second data line DA2. When scanning an odd-numbered row of sub-pixels or an even-numbered row of sub-pixels in the display panel, the two data lines close to each other in the first data line group Z11 can write data signals to the sub-pixel driving circuits in the same odd-numbered row or write data signals to the sub-pixels in the same even-numbered row. In this way, the two data lines close to each other in the first data line group Z11 can be controlled by the gate sub-unit, the time for writing data signals is close, that is, the time for the two data lines to write data signals to the sub-pixel driving circuits is the same, thereby shortening the time difference for the two data lines close to each other in the first data line group Z11 to write data signals and reducing the risk that one data line is in a floating state and is disturbed by another data line after completing data writing. Therefore, the display panel provided by the above embodiment effectively reduces the crosstalk between the two data lines close to each other and improves the crosstalk display defects caused by the crosstalk between the data lines.

[0159] The display device provided by the embodiment of the present application also has the beneficial effects of the above display panel, which will not be described here.

[0160] It should be noted that the signal line extending in a certain direction refers to that the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0161] It should be noted that the layout area of the column unit is the layout area occupied by all the sub-pixel driving circuits in the column unit. The layout area occupied by each sub-pixel driving circuit can be a region capable of accommodating the sub-pixel driving circuit. For example, the region can be a rectangular region, but is not limited thereto.

[0162] It should be noted that the "same layer" in the embodiments of the present application can refer to a film layer on the same structure layer. Alternatively, for example, the film layers on the same layer can be layers formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by a one-time patterning process using the same mask plate. According to different specific patterns, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous. These specific patterns can also be at different heights or have different thicknesses.

[0163] In the method embodiments of the present application, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the changes in the sequence of the steps without creative labor are also within the protection scope of the present application.

[0164] It should be noted that each embodiment in the present specification is described in a progressive manner, and the same or similar parts between each embodiment can be referred to each other, and each embodiment mainly describes the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the product embodiments.

[0165] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present application pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect", "couple", or "link" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0166] It can be understood that when an element such as a layer, a film, a region, or a substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be an intermediate element.

[0167] In the description of the above-mentioned embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0168] The above description is merely that of specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, and all such changes or replacements should be encompassed within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the scope of protection of the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate and a plurality of sub-pixels arranged on the substrate, the sub-pixels comprising sub-pixel driving circuits, the sub-pixel driving circuits comprising driving transistors, the plurality of sub-pixels comprising a plurality of sub-pixel driving circuit columns; the display panel further comprises: a plurality of data lines, each driving circuit column corresponding to two data lines, the first data line in the two data lines being coupled to the odd-numbered sub-pixel driving circuits in the driving circuit column, and the second data line in the two data lines being coupled to the even-numbered sub-pixel driving circuits in the driving circuit column; at least part of the data lines are divided into a plurality of first data line groups and a plurality of second data line groups, the first data line groups and the second data line groups being arranged alternately, each data line group comprising two adjacent data lines, the first data line group and the adjacent second data line group having a projection on the substrate, and the gate of the driving transistor in the driving circuit column having a projection on the substrate between the projection of the first data line group and the projection of the adjacent second data line group; the distance between the two data lines in the first data line group is smaller than the distance between the two data lines in the second data line group; the two data lines in the same first data line group are both the first data line or both the second data line.

2. The display panel of claim 1, wherein, the plurality of driving circuit columns are divided into a plurality of driving circuit groups, each driving circuit group comprising two adjacent driving circuit columns; the projections of the gates of the two driving transistors in the driving circuit group on the substrate and the projections of the first data line groups on the substrate are arranged alternately, and the projection of the second data line group on the substrate is located between the projections of the gates of the two driving transistors in the corresponding driving circuit group on the substrate; in the two adjacent driving circuit groups, the first data line is located on the first side of the corresponding driving circuit column, and the second data line is located on the second side of the corresponding driving circuit column in the data lines coupled by one driving circuit group; the first data line is located on the second side of the corresponding driving circuit column, and the second data line is located on the first side of the corresponding driving circuit column in the data lines coupled by the other driving circuit group; the first side and the second side are opposite along a first direction.

3. The display panel of claim 2, wherein, the display panel further comprises a plurality of gate control units, the gate control units comprising first gate sub-units, second gate sub-units, third gate sub-units, and fourth gate sub-units; the display panel further comprises first gate control lines, second gate control lines, third gate control lines, and fourth gate control lines; the first gate sub-unit is coupled to the first gate control line, the corresponding data signal input end, and the corresponding first data line in the first driving circuit column in the corresponding driving circuit group, respectively, for controlling the electrical connection between the data signal input end and the first data line to be turned on or turned off under the control of the first gate control line. The second gating subunit is coupled with the second gating control line, a corresponding data signal input end and a first data line corresponding to the second column of driving circuit in the corresponding driving circuit group, respectively, for controlling the electrical connection between the data signal input end and the first data line under the control of the second gating control line. The third gating subunit is coupled with the third gating control line, a corresponding data signal input end and a second data line corresponding to the first column of driving circuit in the corresponding driving circuit group, respectively, for controlling the electrical connection between the data signal input end and the second data line under the control of the third gating control line. The fourth gating subunit is coupled with the fourth gating control line, a corresponding data signal input end and a second data line corresponding to the second column of driving circuit in the corresponding driving circuit group, respectively, for controlling the electrical connection between the data signal input end and the second data line under the control of the fourth gating control line.

4. The display panel of claim 2, wherein, The sub-pixel driving circuit further comprises a data writing transistor, a first reset transistor, a first conductive connection part and a second conductive connection part. In at least part of the sub-pixels, the first pole of the data writing transistor is coupled with the corresponding data line through the first conductive connection part, and the second pole of the data writing transistor is coupled with the first pole of the driving transistor; the second pole of the first reset transistor is coupled with the gate of the driving transistor through the second conductive connection part. In at least part of the sub-pixels, the orthogonal projection of the second conductive connection part on the substrate substrate is located between the orthogonal projection of the active layer of the data writing transistor on the substrate substrate and the orthogonal projection of the data line coupled with the data writing transistor on the substrate substrate. In the at least part of the sub-pixels, the first conductive connection part comprises a first connection part and a second connection part coupled with each other, the extension direction of the first connection part intersects with the extension direction of the second connection part, the first connection part is coupled with the corresponding data line, and the second connection part is coupled with the first pole of the data writing transistor.

5. The display panel of claim 4, wherein, The display panel further comprises a power line, and the orthogonal projection of the first conductive connection part on the substrate substrate at least partially overlaps with the orthogonal projection of the power line on the substrate substrate.

6. The display panel of claim 2, wherein, The plurality of sub-pixels comprises red sub-pixels, green sub-pixels and blue sub-pixels. In the driving circuit group, the first column of driving circuit comprises red sub-pixel sub-pixel driving circuits and blue sub-pixel sub-pixel driving circuits arranged alternately, and the second column of driving circuit comprises a plurality of green sub-pixel sub-pixel driving circuits arranged in sequence.

7. The display panel of claim 6, wherein, In the two adjacent driving circuit groups, the first column of driving circuit in one driving circuit group comprises red sub-pixel sub-pixel driving circuits and blue sub-pixel sub-pixel driving circuits arranged alternately, and the first column of driving circuit in the other driving circuit group comprises blue sub-pixel sub-pixel driving circuits and red sub-pixel sub-pixel driving circuits arranged alternately.

8. The display panel of claim 1, wherein, Two data lines in the same group of the second data line group include the first data line and the second data line.

9. The display panel of claim 8, wherein, The display panel further includes a plurality of first signal lines, and one first signal line is between two data lines in the second data line group.

10. The display panel of claim 1, wherein, The display panel further includes a plurality of power supply lines, and a projection of a power supply line corresponding to the driving circuit column on the substrate substrate is located between projections of two data lines corresponding to the driving circuit column on the substrate substrate.

11. The display panel of any one of claims 1-10, wherein, The plurality of sub-pixels are divided into a plurality of driving circuit rows, and in the same driving circuit row, two adjacent sub-pixels include sub-pixel driving circuits that are mirror-symmetric.

12. The display panel of any one of claims 1-10, wherein, The display panel includes a hole region, an isolation region, and a pixel region, the isolation region is located between the hole region and the pixel region; the plurality of data lines include a plurality of hole region crossing data lines, the plurality of hole region crossing data lines include a plurality of first type data lines and a plurality of second type data lines. The first type data line includes a first data portion, a first type cross-region data portion, and a second data portion coupled in sequence, the first data portion and the second data portion are located on opposite sides of the hole region, and the first data portion, the first type cross-region data portion, and the second data portion are located in the pixel region. The second type data line includes a third data portion, a second type cross-region data portion, and a fourth data portion coupled in sequence, the third data portion and the fourth data portion are located on opposite sides of the hole region, and the third data portion and the fourth data portion are located in the pixel region, and the second type cross-region data portion is located in the isolation region.

13. The display panel of claim 12, wherein, The plurality of second type data lines are divided into a first part second type data line and a second part second type data line, and the plurality of first type data lines are located between the first part second type data line and the second part second type data line.

14. The display panel of claim 12, wherein, The first data portion included in the first type data line and the third data portion included in the second type data line are alternately arranged; and the second data portion included in the first type data line and the fourth data portion included in the second type data line are alternately arranged.

15. The display panel of claim 14, wherein, The first type data line is coupled with a corresponding green sub-pixel, and the second type data line is coupled with a corresponding red sub-pixel and / or blue sub-pixel.

16. A display device comprising: The display panel includes any one of claims 1-15. The display panel includes any one of claims 1-15.

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