Control method of display apparatus and display apparatus

Abstract

The application discloses a display device control method and a display device. The method is applied to a display device including a high-frequency refresh area and a low-frequency refresh area. The high-frequency refresh area and the low-frequency refresh area occupy different row pixel circuits. The method comprises the following steps: controlling a data signal corresponding to a first range to be input to a data line at a first frequency, and controlling a data signal corresponding to a second range to be input to the data line at a second frequency; and controlling the data signal to be written into the pixel circuit according to a partition enabling signal. The application can improve the display effect of the display device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device control method and display device. BACKGROUND

[0002] With the improvement of people's living standards, people are in contact with electronic products at all times, so the demand for display panels is increasing, and display technology has developed rapidly. Now the ordinary display effect can not meet the quality of people's life, and the refresh technology of sub-area is needed, because the refresh frequency is different in different areas of the screen, so that better power consumption benefit can be obtained and the use time of electronic products is prolonged.

[0003] However, when the sub-area refresh function is turned on, the refresh frequencies of different sub-areas are inconsistent. If the load of the driving chip jumps from the light load state of the low refresh frequency area to the heavy load state of the high refresh frequency area, the voltage stability is affected, causing display abnormalities. SUMMARY

[0004] Therefore, the present application provides a display device control method and display device to solve the problem of display abnormalities when the sub-area refresh function is turned on in the prior art.

[0005] The first aspect of the present application provides a display device control method applied to a display device including a high-frequency refresh area and a low-frequency refresh area, the high-frequency refresh area and the low-frequency refresh area occupying different rows of pixel circuits, the method comprising: controlling the data signal corresponding to the first range to input the data line at a first frequency, and controlling the data signal corresponding to the second range to input the data line at a second frequency, wherein the first frequency is greater than the second frequency, the low-frequency refresh area includes a first sub-area adjacent to the high-frequency refresh area and a second sub-area located on the side of the first sub-area away from the high-frequency refresh area, the first range includes the high-frequency refresh area and the first sub-area, and the second range includes the second sub-area; and controlling the data signal to be written into the pixel circuit according to the sub-area enable signal.

[0006] Optionally, the display device includes a first gate drive circuit, a plurality of rows of pixel circuits, and at least one sub-area enable signal line, the first gate drive circuit is connected with the sub-area enable signal line, the first gate drive circuit is connected with the pixel circuit, and the pixel circuit is connected with the data line,

[0007] Each display frame in at least one display frame includes a first period corresponding to the low-frequency refresh area and a second period corresponding to the high-frequency refresh area, the first period includes a first sub-period corresponding to the first sub-area and a second sub-period corresponding to the second sub-area;

[0008] At least one display frame includes a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, and the first type of display frame is a holding frame of the low-frequency refresh area,

[0009] The method further comprises:

[0010] In the first type of display frame, a fixed potential is input to the data line in the second sub-period; a data signal or a signal with a potential change is input to the data line in the first sub-period, or a potential different from the potential input to the data line in the second sub-period is input to the data line in the first sub-period, and a data signal corresponding to the high-frequency refresh region is input to the data line in the second period;

[0011] In the first type of display frame, a non-enable level is input to the sub-region enable signal line in at least part of the second sub-period; a non-enable level is input to the sub-region enable signal line in at least part of the first sub-period, and an enable level is input to the sub-region enable signal line in at least part of the second period;

[0012] Optionally, the first gate drive circuit is configured to control the first gate drive circuit to output pulse signals with different frequencies to the high-frequency refresh region and the low-frequency refresh region according to the sub-region enable signal of the sub-region enable signal line;

[0013] Optionally, the number of rows of pixel circuits in the first sub-region is greater than or equal to 1 row;

[0014] The first sub-period is less than or equal to a row period of the pixel circuit.

[0015] Optionally, the at least one display frame includes a second type of display frame, the second type of display frame is a refresh frame of the high-frequency refresh region, and the second type of display frame is a refresh frame of the low-frequency refresh region,

[0016] The control method of the display device further comprises:

[0017] In the second type of display frame, a data signal corresponding to the second sub-region is input to the data line in the second sub-period; a data signal corresponding to the first sub-region is input to the data line in the first sub-period; and a data signal corresponding to the high-frequency refresh region is input to the data line in the second period;

[0018] In the second type of display frame, an enable level is input to the sub-region enable signal line in the second sub-period; an enable level is input to the sub-region enable signal line in the first sub-period; and an enable level is input to the sub-region enable signal line in the second period;

[0019] Optionally, M first type of display frames are arranged between adjacent second type of display frames, and a ratio of the first frequency to the second frequency is equal to M+1, where M is an integer greater than or equal to 1.

[0020] Optionally, the control method of the display device further comprises:

[0021] The at least one low-frequency refresh area includes a first low-frequency refresh area adjacent to the high-frequency refresh area and performing data writing before the high-frequency refresh area performs data writing in the second type of display frame; and a second sub-period corresponding to the first low-frequency refresh area is before a first sub-period corresponding to the first low-frequency refresh area.

[0022] The at least one low-frequency refresh area includes a second low-frequency refresh area adjacent to the high-frequency refresh area and performing data writing after the high-frequency refresh area performs data writing in the second type of display frame; and a second sub-period corresponding to the second low-frequency refresh area is after a first sub-period corresponding to the second low-frequency refresh area.

[0023] Optionally, the first low-frequency refresh area and the second low-frequency refresh area are located at opposite sides of the high-frequency refresh area.

[0024] Optionally, a length of the first sub-period corresponding to the first low-frequency refresh area is greater than or equal to a length of the first sub-period corresponding to the second low-frequency refresh area.

[0025] Optionally, the plurality of partition enabling signal lines are connected to the plurality of shift register units.

[0026] The first gate drive circuit includes a plurality of cascaded shift register groups, each shift register group including k cascaded shift register units, k being an integer greater than or equal to 2, each shift register unit including m shift registers, m being an integer greater than or equal to 1, different shift register units in the same shift register group being electrically connected to different partition enabling signal lines, different shift register groups being electrically connected to the same k partition enabling signal lines, and an output terminal of a first shift register being electrically connected to n rows of pixel circuits, n being an integer greater than or equal to 1.

[0027] The number of rows of pixel circuits in the first sub-area is less than or equal to k*m*n rows.

[0028] The first sub-period is less than or equal to k*m*n times a row period of the pixel circuits.

[0029] Optionally, the number of rows of pixel circuits in the first sub-area is greater than or equal to k*m*n / 4 rows.

[0030] The first sub-period is less than or equal to k*m*n / 4 times a row period of the pixel circuits.

[0031] Optionally, in the first type of display frame, a time at which the partition enabling signal line jumps from the non-enabling level to the enabling level is less than or equal to k*m*n row periods of the pixel circuits from a time at which the signal input to the data line is switched from the fixed potential to the data signal.

[0032] And / or, in the first type of display frame, the time when the partition enable signal line jumps from the enable level to the disable level and the time when the signal input to the data line switches from the data signal to the fixed potential are less than or equal to k*m*n pixel circuit row periods.

[0033] Optionally, in the first type of display frame, the time when the partition enable signal line jumps from the disabled level to the enabled level and the time when the signal input to the data line switches from the fixed potential to the data signal are greater than or equal to k*m*n / 4 pixel circuit line periods.

[0034] And / or, in the first type of display frame, the time when the partition enable signal line jumps from the enable level to the disable level and the time when the signal input to the data line switches from the data signal to the fixed potential are greater than or equal to k*m*n / 4 pixel circuit line periods.

[0035] Optionally, in the first type of display frame, the pulse transitions of the signals on the k partition enable signal lines to the enable level are sequentially delayed; in the second type of display frame, the signals on the k partition enable signal lines are at the enable level.

[0036] Optionally, k-1 shift register units are connected between two adjacent shift register units connected to the same partition enable signal line;

[0037] Optionally, the second time period includes a third sub-time period and a fourth sub-time period. The third sub-time period is located before the fourth sub-time period. In the third sub-time period of the first type of display frame, the pulse jump of the signal on the k partition enable signal line to the enable level is delayed sequentially.

[0038] In the fourth sub-period of the first type of display frame, the moments when the pulses of the signals on the k partition enable signal lines transition to the disabled level are sequentially delayed;

[0039] Optionally, in the first type of display frame, the moment when the signal on the k partition enable signal line changes from an inactive level to an enable level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area, and / or, in the first type of display frame, the moment when the signal on the k partition enable signal line changes from an enable level to an inactive level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area.

[0040] Optionally, the first gate drive circuit includes multiple cascaded shift registers.

[0041] The pixel circuit includes a driving unit and a threshold compensation unit. The threshold compensation unit is connected between the control terminal and the first terminal of the driving unit. The control terminal of the threshold compensation unit is electrically connected to the output terminal of the shift register in the first gate driving circuit.

[0042] Optionally, the threshold compensation unit includes an N-type transistor;

[0043] And / or, the shift register includes a shift unit and an output unit, the output unit being electrically connected to the shift unit, and the output unit being connected to the partition enable signal line.

[0044] When the partition enable signal line is at the enable level, when the shift unit outputs a pulse signal, the output unit connected to the shift unit outputs a pulse signal synchronously; when the partition enable signal line is at the disable level, when the shift unit outputs a pulse signal, the output unit connected to the shift unit maintains a constant output level.

[0045] Optionally, the output unit includes a first transistor and a second transistor;

[0046] The control terminals of the first transistor and the second transistor are both connected to the shift unit. The first terminal of the first transistor is electrically connected to the partition enable signal line, and the second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the output terminal of the shift register.

[0047] The second terminal of the second transistor is electrically connected to the first power signal line.

[0048] Optionally, the display device includes a first gate driving circuit, a multi-row pixel circuit, and at least one partition enable signal line. The first gate driving circuit is connected to the partition enable signal line, the first gate driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the data line.

[0049] At least one display frame includes a first type of display frame, which is a refresh frame in the high-frequency refresh area and a hold frame in the low-frequency refresh area.

[0050] In the first type of display frame, the moment when the signal on the partition enable signal line jumps from a disabled level to an enable level is different from the moment when the signal input to the data line switches from a fixed potential to a data signal.

[0051] And / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from an enable level to an enable level is different from the moment when the signal input to the data line switches from a data signal to a fixed potential;

[0052] Optionally, in the first type of display frame, the moment when the signal on the partition enable signal line changes from a disabled level to an enable level occurs after the moment when the signal input to the data line changes from a fixed potential to a data signal;

[0053] And / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the disable level is before the moment when the signal input to the data line switches from the data signal to the fixed potential;

[0054] Optionally, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from a disabled level to an enable level differs from the moment when the signal input to the data line switches from a fixed potential to a data signal by one or more pixel circuit line cycles.

[0055] And / or, in the first type of display frame, the time when the signal on the partition enable signal line jumps from an enable level to an enable level and the time when the signal input to the data line switches from a data signal to a fixed potential differs by one or more pixel circuit line cycles.

[0056] Optionally, the control method for the display device also includes:

[0057] Subtract N1 rows from the start refresh line position parameter corresponding to the high-frequency refresh area to advance the start time of the input data signal to the data line by N1 pixel circuit line cycles, and / or add N2 rows to the end refresh line position parameter corresponding to the high-frequency refresh area to delay the end time of the input data signal to the data line by N2 pixel circuit line cycles, so as to obtain the first control signal corresponding to the start and end times of the input data signal to the data line, where N1 and N2 are integers greater than or equal to 1;

[0058] The first control signal is delayed to obtain the second control signal, which is delayed by N3 pixel circuit row periods compared to the first control signal; N3 is an integer greater than or equal to 1.

[0059] The parameters corresponding to the end refresh row position of the second control signal are adjusted to obtain the partition enable signal;

[0060] Optionally, the moment when the partition enable signal changes from an disabled level to an enable level corresponds to the moment when the data signal corresponding to the start refresh row position of the high-frequency refresh zone is input to the data line; and / or, the moment when the partition enable signal changes from an enable level to an disabled level corresponds to the moment when the data signal corresponding to the end refresh row position of the high-frequency refresh zone is input to the data line.

[0061] Optional, N1=N2=N3.

[0062] A second aspect of this application provides a display device. The display area of ​​the display device includes a high-frequency refresh area and a low-frequency refresh area, wherein the refresh frequency of the high-frequency refresh area is higher than the refresh frequency of the low-frequency refresh area. The display device includes: a plurality of pixel circuits located in the high-frequency refresh area and the low-frequency refresh area; a first gate driving circuit; a data line connected to the pixel circuits; and at least one partition enable signal line. The first gate driving circuit is connected to the partition enable signal line and to the pixel circuits. Each display frame in at least one display frame includes a first time period corresponding to the low-frequency refresh area and a second time period corresponding to the high-frequency refresh area. The first time period includes a first sub-time period and a second sub-time period, the first sub-time period being located between the second sub-time period and the second time period. The at least one display frame includes a first time period corresponding to the low-frequency refresh area and a second time period corresponding to the high-frequency refresh area. A type of display frame, comprising a refresh frame in the high-frequency refresh zone and a hold frame in the low-frequency refresh zone, wherein in the first type of display frame, a fixed potential is input to the data line in the second sub-time period; a data signal or a potential change signal is input to the data line in the first sub-time period, and / or, in the first sub-time period, a potential different from the potential input to the data line in the second sub-time period is input to the data line; in the second time period, a data signal corresponding to the high-frequency refresh zone is input to the data line; in the first type of display frame, a disabled level is input to the partition enable signal line in at least a portion of the second sub-time period; a disabled level is input to the partition enable signal line in at least a portion of the first sub-time period, and an enable level is input to the partition enable signal line in at least a portion of the second time period.

[0063] This application improves the phenomenon that the boundary between the high-frequency refresh area and the low-frequency refresh area is abnormally displayed because the load of the driver chip changes abruptly at the boundary between the high-frequency refresh area and the low-frequency refresh area. This is achieved by increasing the frequency of the data signal input data line corresponding to the first sub-region, or by increasing the time period of the data signal input data line of the first type of display frame (e.g., a partial refresh frame). Attached Figure Description

[0064] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0065] Figure 1 This is a flowchart of the steps of a control method for a display device according to an embodiment of this application;

[0066] Figure 2A This is a schematic diagram of a display device applicable to embodiments of this application;

[0067] Figure 2B This is a schematic diagram of another display device applicable to embodiments of this application;

[0068] Figure 2C This is a schematic diagram of another display device applicable to embodiments of this application;

[0069] Figure 3A This is a signal timing diagram of a first type of display frame according to an embodiment of this application;

[0070] Figure 3B This is a signal timing diagram of a first type of display frame according to another embodiment of this application;

[0071] Figure 3C This is a signal timing diagram of a first type of display frame according to another embodiment of this application;

[0072] Figure 4 This is a signal timing diagram of another embodiment of this application;

[0073] Figure 5 This is a signal timing diagram of another embodiment of this application;

[0074] Figure 6 This is a schematic diagram of yet another display device applicable to embodiments of this application;

[0075] Figure 7 This is a schematic diagram of the partition enable signal transition according to an embodiment of this application;

[0076] Figure 8 This is a schematic diagram of the partition enable signal transition according to another embodiment of this application;

[0077] Figure 9 This is a circuit diagram of a shift register according to an embodiment of this application;

[0078] Figure 10 This is a schematic diagram of the signal waveform in a first type of display frame according to an embodiment of this application;

[0079] Figure 11 This is a schematic diagram of the signal waveform in a second type of display frame according to an embodiment of this application;

[0080] Figure 12 This is a schematic diagram of the pixel circuit according to an embodiment of this application;

[0081] Figure 13 This is a signal timing diagram of another embodiment of this application;

[0082] Figure 14 This is a schematic diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0083] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0084] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0085] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0086] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0087] With the improvement of people's living standards, electronic products are constantly in use, leading to an increasing demand for display panels and rapid development of display technology. However, ordinary display effects can no longer meet people's quality of life, hence the development of a new display effect: partitioned refresh. Different areas of the screen have different refresh rates, providing better power efficiency and extending the lifespan of electronic products. However, when the partitioned refresh function is enabled, the refresh rates of different areas are inconsistent. If the system transitions from a lightly loaded state in a low refresh rate area to a heavily loaded state in a high refresh rate area, the load on the driver chip will jump, affecting voltage stability and causing display abnormalities. Therefore, this application proposes a control method, apparatus, electronic device, and computer storage medium for a display device to at least partially solve the above problems.

[0088] Figure 1 This is a flowchart illustrating the steps of a control method for a display device according to an embodiment of this application. Figure 1 As shown, the control method for the display device is applied to a display device including a high-frequency refresh area and a low-frequency refresh area, where the high-frequency refresh area and the low-frequency refresh area occupy pixel circuits in different rows. The display device can, as shown... Figures 2A-2C As shown, in Figures 2A-2C The refresh rate of the low-frequency refresh zone is 1Hz, and the refresh rate of the high-frequency refresh zone is 120Hz. In practice, the refresh rates of the high-frequency refresh zone and the low-frequency refresh zone can be set differently, as long as the refresh rate of the high-frequency refresh zone is higher than that of the low-frequency refresh zone.

[0089] The control method for the display device includes the following steps:

[0090] Step 101: Control the data signal corresponding to the first range to be input to the data line at the first frequency, and control the data signal corresponding to the second range to be input to the data line at the second frequency.

[0091] Wherein, the first frequency is greater than the second frequency, the low-frequency refresh area B includes a first sub-area D1 adjacent to the high-frequency refresh area A and a second sub-area D2 located on the side of the first sub-area D1 away from the high-frequency refresh area A, the first range R1 includes the high-frequency refresh area and the first sub-area, and the second range R2 includes the second sub-area. For example, in the first type of display frame, i.e., the partial refresh frame, during the scanning period corresponding to the first sub-area, a data signal is input to the data line to reduce the degree of load jump of the driver chip at the boundary between the high-frequency refresh area and the low-frequency refresh area, so that the load of the driver chip changes slowly earlier or later than that of the high-frequency refresh area A, reducing the risk of display abnormalities at the boundary between the high-frequency refresh area and the low-frequency refresh area, and improving the display effect at the boundary between the high-frequency refresh area and the low-frequency refresh area. Before the data signal transmission time of the first row pixel circuit of the high-frequency refresh area A, a data signal is input to the data line for a period of time in advance, and / or, after the data signal transmission time of the last row pixel circuit of the high-frequency refresh area A, a data signal continues to be input to the data line for a period of time. The driver chip can input data signals to the data line.

[0092] Step 102: Write the control data signal into the pixel circuit according to the partition enable signal.

[0093] To address the potential load abrupt changes in the driver chip, the data signal (source) first needs to be configured so that the data signal corresponding to the first range is input to the data line at a higher first frequency, and the data signal corresponding to the second range is input to the data line at a lower second frequency. The first range R1 includes a high-frequency refresh area and a first sub-region, with the first sub-region adjacent to the high-frequency refresh area. That is, the first range includes the high-frequency refresh area and a portion of the low-frequency refresh area adjacent to it. The second range R2 includes a second sub-region located on the side of the first sub-region furthest from the high-frequency refresh area. That is, the low-frequency refresh area includes the area of ​​the display device excluding the high-frequency refresh area. During display, the data signal can be written to the pixel circuit, causing the pixel circuit to display. For example, the display device can be configured as follows: Figure 2A As shown, it includes a high-frequency refresh area A and two low-frequency refresh areas B. For example, the high-frequency refresh area A occupies 500 rows of pixel circuits, and each of the two low-frequency refresh areas B occupies 500 rows of pixel circuits. The first sub-area D1 may include 100 rows of pixel circuits adjacent to the high-frequency refresh area A. The first sub-area D1 adjacent to the high-frequency refresh area A occupies 100 rows of pixel circuits. For example, the first range R1 occupies 600 rows of pixel circuits. Correspondingly, the second range R2 occupies the pixel circuits in the display device excluding the first range R1. For example, it occupies 400 rows of pixel circuits in each of the two low-frequency refresh areas B, for a total of 800 rows of pixel circuits. The display device can also be as follows. Figure 2B and Figure 2C As shown, it includes only one high-frequency refresh area A and one low-frequency refresh area B. The high-frequency refresh area can be used to display images with high-frequency refresh requirements, such as games, while the low-frequency refresh area can be used to display images with lower refresh requirements, such as novels or web pages. In the first type of display frame, also known as a partial refresh frame, where the high-frequency refresh area needs to refresh but the low-frequency refresh area does not, the power load corresponding to the data signal changes slowly during the scanning period corresponding to the first sub-area. However, at this time, the control data signal is not written to the pixel circuit of the first sub-area, so no abnormality is displayed on the display device. At the boundary between the high-frequency and low-frequency refresh areas, the power load corresponding to the data signal does not change or changes slowly. Therefore, the load of the driver chip will not suddenly jump significantly, thus avoiding the abnormal display of bright lines at the boundary between the high-frequency and low-frequency refresh areas on the display screen. The position where the data signal changes (the on position) avoids the start and end positions of the partial refresh area A. The load has already stabilized at the start and end positions of the partial high-frequency refresh area A, thus avoiding sudden changes in the load of the driver chip.

[0094] Specifically, such as Figure 6As shown, the display device may include: a first gate driving circuit, a multi-row pixel circuit 1113, and at least one partition enable signal line VFE. The first gate driving circuit is connected to the partition enable signal line VFE, the first gate driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the data line DATA.

[0095] Optionally, the first gate drive circuit is used to control the first gate drive circuit to output pulse signals of different frequencies to the high-frequency refresh region A and the low-frequency refresh region B according to the partition enable signal (including enable level and disable level) of the partition enable signal line VFE. One of the enable level and disable level is high, and the other is low. For example, the enable level is high and the disable level is low.

[0096] The display device may include one or more display frames. Each display frame in at least one display frame includes a first time period t1 corresponding to a low-frequency refresh area and a second time period t2 corresponding to a high-frequency refresh area. The first time period t1 includes a first sub-time period t11 corresponding to a first sub-area D1 and a second sub-time period t12 corresponding to a second sub-area. At least one display frame includes a first type of display frame (i.e., a partial refresh frame), where the first type of display frame is a refresh frame of the high-frequency refresh area A and a hold frame of the low-frequency refresh area B.

[0097] The first type of display frame is the refresh frame of the high-frequency refresh area A. In this first type of display frame, the pixel circuit of the high-frequency refresh area A performs data writing, refreshing the gate voltage of the driving transistor in the pixel circuit of the high-frequency refresh area A. The second type of display frame is the hold frame of the low-frequency refresh area B. In this first type of display frame, the pixel circuit of the low-frequency refresh area B does not perform data writing, and the gate voltage of the driving transistor in the pixel circuit of the low-frequency refresh area B is not refreshed; the gate voltage of the driving transistor in the pixel circuit of the low-frequency refresh area B remains the same as the voltage of the previous display frame.

[0098] Optionally, the control method for the display device may also include:

[0099] like Figures 3A-3C As shown, in the first type of display frame F1, in the second sub-time period t12, a fixed potential is input to the data line DATA. In the first sub-time period t11, a data signal (which can be the data signal corresponding to the first sub-area D1 of the previous second type of display frame, but will not be written into the pixel circuit of the first sub-area D1) or a potential change signal is input to the data line DATA. Alternatively, in the first sub-time period t11, a potential different from the potential input to the data line DATA in the second sub-time period t12 is input to the data line DATA. In the second time period t2, a data signal corresponding to the high-frequency refresh area A is input to the data line DATA.

[0100] Since the first type of display frame is a partial refresh frame, the second sub-time period t12 included in the first type of display frame does not need to be refreshed in the second sub-region D2 included in the low frequency refresh area B. At this time, a fixed potential or DC potential needs to be input to the data line DATA to reduce power consumption.

[0101] The first sub-time period t11 and the second sub-time period t2 included in the first type of display frame correspond to the first sub-area D1 and the high-frequency refresh area, respectively. At this time, in the first sub-time period t11, a data signal or a potential change signal is input to the data line DATA, or a potential different from the potential input to the data line DATA in the second sub-time period t12. In the second sub-time period t2, a data signal corresponding to the high-frequency refresh area A is input to the data line DATA to reduce the risk of display abnormalities at the boundary (i.e., the dividing line) between the high-frequency refresh area and the low-frequency refresh area.

[0102] like Figures 3A-3C and Figure 10 As shown, in the first type of display frame, at least a portion of the second sub-period t12 is used to input an inactive level (e.g., a low level) to the partition enable signal line VFE, so that the first gate drive circuit maintains a constant potential in the second sub-period t12 and does not output a pulse signal to the pixel circuit of the second sub-region D2.

[0103] As shown in Figure 3 A-3C and Figure 10 As shown, in the first type of display frame, during at least a portion of the first sub-period t11, an inactive level (e.g., a low level) is input to the partition enable signal line VFE so that the first gate drive circuit maintains a constant potential during the first sub-period t11 and does not output a pulse signal to the pixel circuit of the first sub-region D1.

[0104] In the first type of display frame, during at least a portion of the second time period t2, an enable level (e.g., a high level) is input to the partition enable signal line VFE so that the first gate drive circuit outputs a pulse signal to the pixel circuit of the high-frequency refresh area A during the second time period t2.

[0105] Optionally, the number of rows of the pixel circuit in the first sub-region is greater than or equal to 1 row, and the first sub-time period is less than or equal to the row period Tc of the pixel circuit. The row period Tc can be equal to the second time period t2, which is the time difference between the start times of two adjacent pulse signals output by the first gate driving circuit.

[0106] Specifically, at least one display frame includes a second type of display frame F2 (which may be a global refresh frame), where the second type of display frame F2 is a refresh frame of the high-frequency refresh zone A, and the second type of display frame is a refresh frame of the low-frequency refresh zone B.

[0107] The second type of display frame, F2, is the refresh frame for the high-frequency refresh area A. In other words, during this second type of display frame, the pixel circuit of the high-frequency refresh area A performs data writing, refreshing the gate voltage of the driving transistors in the pixel circuit of the high-frequency refresh area A. The second type of display frame, F2, is also the refresh frame for the low-frequency refresh area B. In other words, during this second type of display frame, the pixel circuit of the low-frequency refresh area B performs data writing, refreshing the gate voltage of the driving transistors in the pixel circuit of the low-frequency refresh area B.

[0108] Optionally, the control method for the display device may also include:

[0109] In the second type of display frame F2, during the second sub-period t12, a data signal corresponding to the second sub-region D2 is input to the data line DATA in order to refresh the gate voltage of the driving transistor in the pixel circuit of the second sub-region D2.

[0110] In the second type of display frame F2, a data signal corresponding to the first sub-region D1 is input to the data line DATA in the first sub-period t11 so as to refresh the gate voltage of the driving transistor in the pixel circuit of the first sub-region D1.

[0111] In the second type of display frame F2, a data signal corresponding to the high-frequency refresh area A is input to the data line DATA during the second time period t2, so as to refresh the gate voltage of the driving transistor in the pixel circuit of the high-frequency refresh area A.

[0112] In the second type of display frame F2, during the second sub-period t12, an enable level is input to the partition enable signal line VFE so that the first gate drive circuit outputs a pulse signal to the pixel circuit of the second sub-region D2 during the second sub-period t12.

[0113] In the second type of display frame F2, an enable level is input to the partition enable signal line VFE in the first sub-period t11, so that the first gate drive circuit outputs a pulse signal to the pixel circuit of the first sub-region D1 in the first sub-period t11.

[0114] In the second type of display frame F2, an enable level is input to the partition enable signal line VFE in the second time period t2, so that the first gate drive circuit outputs a pulse signal to the pixel circuit of the high-frequency refresh area A in the second time period t2.

[0115] Optionally, M first-class display frames F1 are set between adjacent second-class display frames F2, and the ratio of the first frequency to the second frequency is equal to M+1, where M is an integer greater than or equal to 1.

[0116] The more first-class display frames F1 there are between adjacent second-class display frames F2, the lower the refresh rate of the low-frequency refresh zone B.

[0117] For example, the number of first-type display frames (partial refresh frames) set between adjacent second-type display frames (global refresh frames) can be calculated using the following formula:

[0118]

[0119] Here, f2 is used to characterize the second frequency, and f1 is used to characterize the first frequency.

[0120] Specifically, at least one low-frequency refresh zone B includes a first low-frequency refresh zone B1, which is adjacent to the high-frequency refresh zone A and performs data writing in the second type of display frame F2 before data writing is performed in the high-frequency refresh zone A; the second sub-time period t12 corresponding to the first low-frequency refresh zone B1 is before the first sub-time period t11 corresponding to the first low-frequency refresh zone B1. The first time period t1 corresponding to the first low-frequency refresh zone B1 is before the second time period t2 corresponding to the high-frequency refresh zone A.

[0121] And / or, at least one low-frequency refresh area B includes a second low-frequency refresh area B2, which is adjacent to the high-frequency refresh area A and performs data writing in the second type of display frame F2 after data writing is performed in the high-frequency refresh area A; the second sub-time period t12 corresponding to the second low-frequency refresh area B2 is after the first sub-time period t11 corresponding to the second low-frequency refresh area B2. The first time period t1 corresponding to the second low-frequency refresh area B2 is after the second time period t2 corresponding to the high-frequency refresh area A.

[0122] The display device may include one or more of a first low-frequency refresh area B1 and a second low-frequency refresh area B2. The display device may include two display zones with different refresh rates; for example, the display device may include a first low-frequency refresh area B1 and a high-frequency refresh area A, or the display device may include a high-frequency refresh area A and a second low-frequency refresh area B2. Alternatively, the display device may include three display zones with different refresh rates, such as a first low-frequency refresh area B1, a high-frequency refresh area A, and a second low-frequency refresh area B2.

[0123] The display device may include two low-frequency refresh areas, one adjacent to the upper edge of the high-frequency refresh area and the other to the lower edge of the high-frequency refresh area. Since the data lines are connected to the pixel circuits column-by-column, and the first gate driving circuit is connected to the pixel circuits row-by-row, for example, in the area to be refreshed, data signals are input to the data lines row by row. Under the synchronous control of the partition enable signal, the first gate driving circuit outputs a scan pulse signal, causing the corresponding transistors in the pixel circuits of the area to be refreshed to conduct, thereby refreshing the gate voltage of the driving transistors in the pixel circuits of the area to be refreshed row by row. Therefore, in a global refresh frame, the first low-frequency refresh area adjacent to the upper edge of the high-frequency refresh area performs data writing before the high-frequency refresh area. Furthermore, within the first low-frequency refresh area, the second sub-region performs data writing before the first sub-region. The second sub-time period corresponding to the first low-frequency refresh area is input to the data lines first, that is, the data signal corresponding to the second sub-region of the first low-frequency refresh area is input to the data lines first, and then the data signal corresponding to the first sub-region of the first low-frequency refresh area is input to the data lines. Correspondingly, the second low-frequency refresh area adjacent to the lower edge of the high-frequency refresh area will perform data writing after the high-frequency refresh area performs data writing. In the second low-frequency refresh area, the second sub-area will perform data writing after the first sub-area performs data writing. The second sub-time period corresponding to the second low-frequency refresh area is after the first sub-time period. That is, the data signal corresponding to the first sub-area of ​​the second low-frequency refresh area is first input to the data line, and then the data signal corresponding to the second sub-area of ​​the second low-frequency refresh area is input to the data line.

[0124] Optionally, the first low-frequency refresh area B1 and the second low-frequency refresh area B2 are located on opposite sides of the high-frequency refresh area A. For example, the first low-frequency refresh area B1 and the second low-frequency refresh area B2 are located on opposite sides of the high-frequency refresh area A along a first direction. The data lines extend along the first direction y and are arranged along the second direction x, and the first and second directions intersect, for example, perpendicularly.

[0125] Optionally, the duration of the first sub-time period t11 corresponding to the first low-frequency refresh zone B1 is greater than or equal to the duration of the first sub-time period t11 corresponding to the second low-frequency refresh zone B2, that is, as follows Figure 4 As shown.

[0126] Optionally, the second low-frequency refresh area B2 may not have a first sub-area set, that is, as follows Figure 5 As shown, in the first type of display frame F1, a fixed potential is input to the data line DATA during the first time period t1 corresponding to the second low-frequency refresh area B2.

[0127] Optional, such as Figure 6As shown, there are multiple partition enable signal lines, such as VFE1, VFE2, VFE3, and VFE4. The first gate drive circuit includes multiple cascaded shift register groups 10. Each shift register group 10 includes k cascaded shift register units 11, where k is an integer greater than or equal to 2. Each shift register unit 11 includes m shift registers 111, where m is an integer greater than or equal to 1. Different shift register units 11 within the same shift register group 10 are electrically connected to different partition enable signal lines. Different shift register groups 10 are connected to the same k partition enable signal lines. The output of the first-level shift register 111 is electrically connected to n rows of pixel circuits 1113, where n is an integer greater than or equal to 1. The number of rows in the pixel circuit of the first sub-region D1 is less than or equal to k*m*n rows.

[0128] Specifically, the number of rows of the pixel circuit in the first sub-region D1 cannot be too large, otherwise the power consumption will increase. Conversely, the number of rows of the pixel circuit in the first sub-region D1 cannot be too small; it needs to be greater than or equal to m*n rows. This ensures that the number of rows of the pixel circuit is greater than or equal to the number of rows of data signal input controlled by the enable signal in a partition enable signal line; otherwise, there will be display abnormalities at the boundary between the low-frequency refresh area B and the high-frequency refresh area A.

[0129] For example, the number of rows of the pixel circuit in the first sub-region D1 of the first low-frequency refresh area B1 is greater than or equal to k*m*n / 2 rows.

[0130] For example, the number of rows of the pixel circuit in the first sub-region D1 of the second low-frequency refresh area B2 is less than or equal to k*m*n / 2 rows.

[0131] For example, such as Figure 6As shown, the display device includes a first gate driving circuit, a multi-row pixel circuit 1113, and four partition enable signal lines. The multi-row pixel circuit 1113 is divided into two low-frequency refresh areas B and one high-frequency refresh area A. The first gate driving circuit includes multiple cascaded shift register groups 10. Each shift register group 10 includes four cascaded shift register units 11. Each shift register unit 11 includes four shift registers 111. Different shift register units 11 in the same shift register group 10 are electrically connected to different partition enable signal lines VFE. Different shift register groups 10 are connected to the same four partition enable signal lines VFE. The output terminal of the first-level shift register 111 is electrically connected to the first-row pixel circuit 1113 through a scan line 1112 (which can extend along the second direction x). The number of rows of the pixel circuit 1113 in the first sub-region R1 is greater than or equal to 64 rows. When the data signal is input through the data line Data, the shift register 111 controls whether to output a scan pulse signal to the pixel circuit according to the partition enable signal input through the partition enable signal line VFE, so as to control whether the data signal is written to the pixel circuit 1113. Since the data line Data is output row by row, when the data signal of the pixel circuit corresponding to the same row is input in the same row cycle, the data line Data will input data signals to each column pixel circuit 1113. At this time, under the control of the partition enable signal, the corresponding first-level shift register 111 outputs a scan pulse signal. At this time, the row pixel circuit 1113 corresponding to the shift register 111 will write the data signal, refresh the gate voltage of the driving transistor, that is, write the voltage related to the data signal to the gate of the driving transistor, thereby realizing refresh display.

[0132] In some embodiments, all shift registers 111 in the first gate drive circuit may be connected to the same partition enable signal line VFE.

[0133] Specifically, the row period Tc of the pixel circuit in the first sub-time period t11 is less than or equal to k*m*n times. That is, the number of rows of the pixel circuit in the first sub-region D1 is less than or equal to k*m*n rows.

[0134] Optionally, the number of rows of the pixel circuit in the first sub-region D1 is greater than or equal to k*m*n / 4 rows. The first sub-time period t11 is less than or equal to k*m*n / 4 times the row period Tc of the pixel circuit.

[0135] Optionally, in the first type of display frame F1, the time tA when the partition enable signal line VFE transitions from an inactive level to an enable level is different from the time tB when the signal input to the data line DATA switches from a fixed potential to a data signal (e.g., ...). Figure 3A (As shown). For example, tB leads tA. tA-tB can be equal to the duration of the first sub-period t11 corresponding to the first low-frequency refresh zone B1.

[0136] Optionally, in the first type of display frame F1, the time tA when the partition enable signal line VFE jumps from the disabled level to the enabled level and the time tB when the signal input to the data line DATA switches from the fixed potential to the data signal are less than or equal to the row period Tc of k*m*n pixel circuits.

[0137] Optionally, in the first type of display frame F1, the time tC when the partition enable signal line VFE changes from an enable level to an enable level is different from the time tD when the signal input to the data line DATA changes from a data signal to a fixed potential (e.g., ...). Figure 3A (As shown). For example, tD lags behind tC. tD-tC can be equal to the duration of the first sub-period t11 corresponding to the second low-frequency refresh zone B2.

[0138] Optionally, in the first type of display frame F1, the time tC when the partition enable signal line VFE changes from an enable level to an enable level is the same as the time tD when the signal input to the data line DATA changes from a data signal to a fixed potential (e.g., ...). Figure 5 (As shown).

[0139] Optionally, in the first type of display frame F1, the time tC when the partition enable signal line VFE jumps from the enable level to the disable level and the time tD when the signal input to the data line DATA switches from the data signal to the fixed potential are less than or equal to the row period Tc of k*m*n pixel circuits.

[0140] That is, in the first type of display frame F1, the range of fixed potential input to the data line shrinks, or the range of data signal input to the data line expands to the first sub-region, while the enable signal in the partition enable signal line does not expand outward.

[0141] Optionally, in the first type of display frame F1, the time tA when the partition enable signal line VFE jumps from the disabled level to the enabled level and the time tB when the signal input to the data line DATA switches from the fixed potential to the data signal are greater than or equal to the row period Tc of k*m*n / 4 pixel circuits.

[0142] And / or, in the first type of display frame F1, the time tC when the partition enable signal line VFE jumps from the enable level to the disable level and the time tD when the signal input to the data line DATA switches from the data signal to the fixed potential are greater than or equal to the row period Tc of k*m*n / 4 pixel circuits.

[0143] Optional, such as Figure 6 or Figure 10 As shown, in the first type of display frame F1, the pulses of the signals on the k partition enable signal lines change to the enable level in sequence with delay. In the second type of display frame F2, the signals on the k partition enable signal lines are at the enable level, that is, they are maintained at a constant potential.

[0144] Since the partition enable signal is related to the data signal, the configuration of the data signal causes the data signal to expand outward relative to the boundary between the high-frequency refresh area and the low-frequency refresh area. Therefore, the signal on the partition enable signal line needs to be delayed in the local refresh frame to ensure that the first partition located above the high-frequency refresh area will not refresh abnormally.

[0145] Optionally, k-1 shift register units 11 are connected between two adjacent shift register units 11 connected to the same partition enable signal line. For example, as Figure 6 As shown, there are three shift register units 11 connected between two adjacent shift register units 11 connected to the partition enable signal line VFE1.

[0146] Optionally, the second time period t2 includes a third sub-time period t21 and a fourth sub-time period t22. The third sub-time period t21 precedes the fourth sub-time period t23. In the third sub-time period t21 of the first type of display frame F1, the pulses of the signals on the k partition enable signal lines transitioning to the enable level are sequentially delayed. In the fourth sub-time period t22 of the first type of display frame F1, the pulses of the signals on the k partition enable signal lines transitioning to the disable level are sequentially delayed.

[0147] Optionally, in the first type of display frame F1, the moment when the signal on the k partition enable signal line changes from an inactive level to an enable level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area, and / or, in the first type of display frame, the moment when the signal on the k partition enable signal line changes from an enable level to an inactive level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area.

[0148] Optionally, the first gate driving circuit includes multiple cascaded shift registers, and the pixel circuit 1113 includes a driving unit 310 and a threshold compensation unit 320. The threshold compensation unit 320 is connected between the control terminal and the first terminal of the driving unit 310. The control terminal SN2 of the threshold compensation unit 320 is electrically connected to the output terminal GOUT of the shift register in the first gate driving circuit. Optionally, the threshold compensation unit 320 may include an N-type transistor, and / or the shift register includes a shift unit 210 and an output unit 220. The output unit 220 is electrically connected to the shift unit 210 and is connected to the partition enable signal line VFE. When the partition enable signal line VFE is at an enabled level, when the shift unit 210 outputs a pulse signal, the output unit 220 connected to the shift unit 210 synchronously outputs a pulse signal; when the partition enable signal line VFE is at an disabled level, when the shift unit 210 outputs a pulse signal, the output unit 220 connected to the shift unit 210 maintains a constant output level. The control terminal SN2 of the threshold compensation unit 320 is electrically connected to the output terminal GOUT of the shift register in the first gate drive circuit through the scan line 1112.

[0149] That is, such as Figures 7-8 , Figures 10-11 , Figure 12 As shown, when the partition enable signal line is at the enable level (e.g., VH), the data signal in the data line needs to be written to the pixel circuit. At this time, the shift unit outputs a pulse signal, causing the output unit connected to the shift unit to output a pulse signal synchronously, so that the threshold compensation unit 320 is turned on to realize data writing and refresh the voltage of the control terminal of the drive unit. When the partition enable signal line is at the disabled level, and the shift unit outputs a pulse signal, the data signal in the data line should not be written to the pixel circuit. Therefore, at this time, the output unit connected to the shift unit maintains a constant level to turn off the threshold compensation unit 320 to perform data writing. The voltage of the control terminal of the drive unit will not be refreshed, and the control terminal of the drive unit will maintain the voltage of the previous display frame.

[0150] The pixel circuit may also include a data writing unit 340, which is connected between the data line Data and the second terminal of the driving unit 310. For example, the data writing unit includes a fifth transistor T5.

[0151] The pixel circuit may also include some or all of the initialization unit, light-emitting control unit, and reset unit. The initialization unit includes a sixth transistor T6, the light-emitting control unit includes a seventh transistor T7 and / or an eighth transistor T8, and the reset unit includes a ninth transistor T9 and / or a tenth transistor T10. The first terminal of the fifth transistor T5 is connected to the data line Data, the second terminal of the fifth transistor T5 is connected to the second terminal of the driving transistor T3 (which can be used as the second terminal of the driving unit), and the control terminal of the fifth transistor T5 is connected to the first scan line SP1. The seventh transistor T7, the driving transistor T3, the eighth transistor T8, and the light-emitting unit 130 are connected in series between the second power line ELVDD and the third power line ELVSS. The control terminals of the seventh transistor T7 and the eighth transistor T8 are connected to the light-emitting control line EM. The two ends of the storage capacitor Cst are connected to the control terminal of the driving module 310 and the power line ELVDD, respectively. The sixth transistor T6 and the fourth transistor T4 are connected in series between the first signal line Vrefn1 and the control terminal of the driving module 310. The control terminal of the fourth transistor T4, as the control terminal of the threshold compensation unit 320, is electrically connected to the output terminal of the shift register in the first gate driving circuit. The control terminal of the sixth transistor T6 is connected to the third scan line SN1. The second terminal of the ninth transistor T9 is connected to the second signal line Vrefp, and the control terminal of the ninth transistor T9 is connected to the second scan line SP2. The second terminal of the tenth transistor T10 is connected to the third signal line Vrefn2, and the control terminal of the tenth transistor T10 is connected to the second scan line SP2. The first terminal of the ninth transistor T9 can be connected to either the first or second terminal of the driving transistor. The first terminal of the tenth transistor T10 is connected to the first terminal of the light-emitting unit.

[0152] Optionally, in the first initialization phase, the initialization unit and the threshold compensation unit 320 are turned on to initialize the driving transistor. In the data writing phase, the data writing unit and the threshold compensation unit 320 are turned on to write a voltage to the gate of the driving transistor T3, resulting in a voltage that compensates the threshold voltage of the driving transistor T3 to the target driving value. In the second initialization phase (e.g., overlapping or staggered with the first initialization phase or the data writing phase), the reset unit is turned on to reset the first terminal of the light-emitting unit 130 and / or the first or second terminal of the driving transistor. In the light-emitting phase, the seventh transistor T7 and the eighth transistor T8 are turned on, and the light-emitting unit 130 emits light.

[0153] A refresh frame may include a first initialization phase, a data writing phase, a second initialization phase, and a light-emitting phase. A hold frame may include a second initialization phase and a light-emitting phase. A hold frame may not include the first initialization phase and the data writing phase. Optionally, a sixth transistor T6 may be connected between the first signal line Vrefn1 and the control terminal of the driver module 310. A fourth transistor T4 may be connected between the second terminal of the driver module 310 and the control terminal of the driver module 310.

[0154] Optional, such as Figure 9 As shown, the shift register includes a shift unit 210 and an output unit 220. The output unit 220 is electrically connected to the shift unit 210. The output unit 220 includes a first transistor T21 and a second transistor T2. The control terminals of the first transistor T1 and the second transistor T2 are both connected to the shift unit 210. The first terminal of the first transistor T1 is electrically connected to the partition enable signal line VFE (e.g., one of VFE1 to VFE4). The second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T2 and the output terminal GOUT of the shift register. The second terminal of the second transistor T2 is electrically connected to the first power supply signal line NVGL (which can be a low voltage).

[0155] The shift unit 210 includes an output subunit and a control subunit. The output subunit may include an eleventh transistor T11 and a twelfth transistor T12. The control subunit may include some or all of the following: thirteenth transistors T13 to twenty-third transistors T23, a first capacitor C1, a second capacitor C2, and a third capacitor C3. Specifically, the first terminal of the eighteenth transistor T18, the control terminal of the seventeenth transistor T17, the control terminal of the sixteenth transistor T16, and the control terminal of the thirteenth transistor T13 are all connected to the first power supply signal line NVGL. The control terminals of the eighteenth transistor T18 and the twentieth transistor T20 are both connected to the first clock signal terminal SCK1. The first terminal of the fifteenth transistor T15 and the fourteenth transistor T14... The control terminal of transistor T22, the control terminal of transistor T22, and the first terminal of the second capacitor C2 are all connected to the second clock signal terminal SCK2. The first terminals of transistor T21 and T23 are all connected to the fourth power supply line NVGH. The first terminal of transistor T20 is connected to the start signal line SIN. The first terminal of transistor T11 is connected to the fourth power supply line NVGH (which can be high voltage). The second terminal of transistor T11 outputs the shift signal SOUT. The first terminal of transistor T12 is connected to the first power supply signal line NVGL.

[0156] Specifically, the display device includes a first gate driving circuit, a multi-row pixel circuit, and at least one partition enable signal line. The first gate driving circuit is connected to the partition enable signal line, the first gate driving circuit is connected to the pixel circuit, the pixel circuit is connected to the data line, and at least one display frame includes a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, and the first type of display frame is a hold frame of the low-frequency refresh area.

[0157] In the first type of display frame, the moment when the signal on the partition enable signal line jumps from an enabled level to an enabled level is different from the moment when the signal input to the data line switches from a fixed potential to a data signal; and / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from an enabled level to an enabled level is different from the moment when the signal input to the data line switches from a data signal to a fixed potential.

[0158] Optionally, in the first type of display frame, the moment when the signal on the partition enable signal line changes from an enabled level to an enabled level is after the moment when the signal input to the data line changes from a fixed potential to a data signal; and / or, in the first type of display frame, the moment when the signal on the partition enable signal line changes from an enabled level to an enabled level is before the moment when the signal input to the data line changes from a data signal to a fixed potential.

[0159] Optionally, in the first type of display frame, the time when the signal on the partition enable signal line jumps from an enabled level to an enabled level differs from the time when the signal input to the data line switches from a fixed potential to a data signal by one or more pixel circuit line cycles; and / or, in the first type of display frame, the time when the signal on the partition enable signal line jumps from an enabled level to an enabled level differs from the time when the signal input to the data line switches from a data signal to a fixed potential by one or more pixel circuit line cycles.

[0160] Optional, such as Figure 13 As shown, the control method of the display device may further include: subtracting N1 rows from the start refresh line position parameter corresponding to the high-frequency refresh area, so that the start time of the data signal input to the data line is advanced by N1 row periods of the pixel circuit, and / or adding N2 rows to the end refresh line position parameter corresponding to the high-frequency refresh area, so that the end time of the data signal input to the data line is delayed by N2 row periods of the pixel circuit, to obtain a first control signal corresponding to the start and end times of the data signal input to the data line. N1 and N2 are integers greater than or equal to 1. N1*Tc may be equal to the duration of the first sub-time period t11 corresponding to the first low-frequency refresh area B1. N2*Tc may be equal to the duration of the first sub-time period t11 corresponding to the first low-frequency refresh area B2.

[0161] In the first type of display frame, the first sub-region of the first low-frequency refresh area receives the data signal before the high-frequency refresh area. This can be achieved by subtracting N1 rows from the starting refresh line position parameter corresponding to the high-frequency refresh area, thereby modifying the starting refresh line position of the high-frequency refresh area to the edge of the first sub-region furthest from the high-frequency refresh area. In the first type of display frame, the first sub-region of the second low-frequency refresh area receives the data signal later than the high-frequency refresh area. This can be achieved by adding N2 rows to the starting refresh line position parameter corresponding to the high-frequency refresh area, thereby modifying the starting refresh line position of the high-frequency refresh area to the edge of the first sub-region furthest from the high-frequency refresh area.

[0162] Optionally, the control method of the display device may further include: delaying the first control signal to obtain a second control signal, wherein the second control signal is delayed by N3 pixel circuit row periods compared to the first control signal; N3 is an integer greater than or equal to 1.

[0163] The parameters corresponding to the end refresh row position of the second control signal are adjusted to obtain the partition enable signal.

[0164] Optionally, the moment when the partition enable signal transitions from an disabled level to an enable level corresponds to the moment when the data signal corresponding to the start refresh row position of the high-frequency refresh zone is input to the data line; and / or, the moment when the partition enable signal transitions from an enable level to an disabled level corresponds to the moment when the data signal corresponding to the end refresh row position of the high-frequency refresh zone is input to the data line.

[0165] like Figure 6 , Figures 10-11 As shown, Figure 6 , Figure 10 and Figure 11 The diagram illustrates the case where k=4 and m=4. The display device may include 3n shift registers. The two low-frequency refresh areas B and the high-frequency refresh area A are each connected to n shift registers. SOUT1-SOUTn are the shift pulse signals output by the shift units in the first n-stage shift registers corresponding to the first low-frequency refresh area B1, respectively; SOUTn+1-SOUT2n are the shift pulse signals output by the shift units in the (n+1)th to 2nth stage shift registers corresponding to the high-frequency refresh area A, respectively; and SOUT2n+1-SOUT3n are the shift pulse signals output by the shift units in the (2n+1)th to 3nth stage shift registers corresponding to the second low-frequency refresh area B2, respectively.

[0166] GOUT1-GOUTn are the scan pulse signals output from the first n-stage shift registers corresponding to the first low-frequency refresh area B1, respectively; GOUTn+1-GOUT2n are the scan pulse signals output from the (n+1)th to the 2nth stage shift registers corresponding to the high-frequency refresh area A, respectively; GOUT2n+1-GOUT3n are the scan pulse signals output from the (2n+1)th to the 3nth stage shift registers corresponding to the second low-frequency refresh area B2, respectively.

[0167] refer to Figure 10 In the first type of display frame F1, the refresh frequency of the two low-frequency refresh zones B is the low refresh frequency. The corresponding partition enable signals in the partition enable signal lines (e.g., VFE1 to VFE4) are all at a disabled level, such as low level VL. The output terminal GOUT of the shift register outputs a disabled level (i.e., an invalid level, such as a turn-off level), such as low level VL. The two low-frequency refresh zones B will not receive the enable level pulse (i.e., scan pulse signal, such as a turn-on pulse signal) output by the corresponding shift register output terminal GOUT. The high-frequency refresh area A has a high refresh rate. The partition enable signal on the partition enable signal lines (e.g., VFE1 to VFE4) is at enable level VH, and the pulse transitions of the signals on the four partition enable signal lines to the enable level are sequentially delayed. For example, during the delay time between partition enable signal line VFE2 and partition enable signal line VFE1, GOUTn+1 to GOUTn+4 are sequentially enable level pulses (i.e., the conduction pulses of the threshold compensation unit); during the delay time between partition enable signal line VFE3 and partition enable signal line VFE2, GOUTn+5 to GOUTn+8 are sequentially enable level pulses; and during the delay time between partition enable signal line VFE4 and partition enable signal line VFE3, GOUTn+9 to GOUTn+12 are sequentially enable level pulses. The high-frequency refresh area A can receive the enable level pulses output by the corresponding shift register output terminal GOUT.

[0168] refer to Figure 11 In the second type of display frame F2, both the low-frequency refresh area B and the high-frequency refresh area A can receive the scan pulse signal output from the corresponding shift register output terminal GOUT. That is, GOUT1 to GOUT3n are scan pulse signals in sequence. Therefore, the partition enable signal on the four partition enable signal lines (e.g., VFE1 to VFE4) is the enable level VH. The scan pulse signal output by the shift register, that is, the signal output by the output terminal of output unit 220, is the same as the shift signal output by the output terminal of shift unit 210.

[0169] Pixel circuits can be like Figure 12As shown, the pixel driving circuit includes a threshold compensation unit 320. The control terminal of the threshold compensation unit 320 is used to receive the output signal of the first gate driving circuit. The pulse frequency of the output signal of the first gate driving circuit can be controlled by the partition enable signal. The display device includes partition enable signal lines, and each partition enable signal line can receive the partition enable signal output by the chip. During the scanning process of the first type of display frame, when entering the high-frequency refresh area A from the low-frequency refresh area B1, the partition enable signal changes from a low level to a high level. This corresponds to the time period in the first type of display frame corresponding to the display partition of the low-frequency refresh area. During this time period, the partition enable signal is at a non-enabled level, such as a low level, so that the first gate driving circuit does not output a conduction pulse to the low refresh frequency display partition and continuously outputs the off level of the threshold compensation unit 320. During the scanning time period corresponding to the high-frequency refresh area, the partition enable signal is at an enabled level, such as a high level, so that the first gate driving circuit outputs a conduction pulse to the high-frequency refresh area, thereby enabling the threshold compensation unit 320 to conduct.

[0170] This application also provides a display device. The display area of ​​the display device includes a high-frequency refresh area and a low-frequency refresh area, wherein the refresh frequency of the high-frequency refresh area is higher than the refresh frequency of the low-frequency refresh area.

[0171] The display device includes:

[0172] Multiple pixel circuits 1113 are located in the high-frequency refresh area A and the low-frequency refresh area B;

[0173] First gate drive circuit;

[0174] The data cable connects to the pixel circuitry.

[0175] At least one partition enable signal line is provided. A first gate drive circuit is connected to the partition enable signal line and a first gate drive circuit is connected to a pixel circuit. Each display frame in at least one display frame includes a first time period t1 corresponding to a low-frequency refresh area B and a second time period t2 corresponding to a high-frequency refresh area A. The first time period includes a first sub-time period and a second sub-time period, and the first sub-time period is located between the second sub-time period and the second time period.

[0176] At least one display frame includes a first type of display frame, which is a refresh frame in the high-frequency refresh area and a hold frame in the low-frequency refresh area.

[0177] In the first type of display frame, a fixed potential is input to the data line in the second sub-time period; a data signal or a potential change signal is input to the data line in the first sub-time period, and / or, in the first sub-time period, a potential different from the potential input to the data line in the second sub-time period is input to the data line; in the second time period, a data signal corresponding to the high-frequency refresh area is input to the data line.

[0178] In the first type of display frame, during at least a portion of the second sub-time period, a disabled level is input to the partition enable signal line; during at least a portion of the first sub-time period, a disabled level is input to the partition enable signal line; and during at least a portion of the second time period, an enable level is input to the partition enable signal line.

[0179] This embodiment can be combined with some or all of the features in the above embodiments, which will not be repeated here.

[0180] Display devices may include mobile phones, smart wearable devices, in-vehicle displays, laptops, or tablets.

[0181] The specific implementation of each device and module in the display device can be found in the corresponding steps and units described in the aforementioned control method embodiments of the display device, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and modules described above can be referred to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0182] In this embodiment, an electronic device 500 is provided, such as... Figure 14 As shown, the electronic device 500 may include: a processor 501, a communications interface 502, a memory 503, and a communication bus 504. Wherein:

[0183] The processor 501, communication interface 502, and memory 503 communicate with each other through the communication bus 504.

[0184] Communication interface 502 is used for communication with other electronic devices or servers.

[0185] The processor 501 is used to execute program 505, which can specifically execute the relevant steps in the aforementioned control method embodiment of the display device.

[0186] Specifically, program 505 may include program code that includes computer operation instructions.

[0187] Processor 501 may be a CPU, an Application Specific Integrated Circuit (ASIC), or configured as one or more integrated circuits. A smart device may include one or more processors, which can be of the same type, such as one or more CPUs; or they may be of different types, such as one or more CPUs and one or more ASICs.

[0188] Memory 503 is used to store program 505. Memory 503 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0189] Specifically, program 505 can be used to cause processor 501 to execute the control method of the display device in the foregoing embodiments.

[0190] The specific implementation of each step in program 505 can be found in the corresponding steps and units described in the aforementioned control method embodiments of the display device, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0191] The electronic device 500 of this application embodiment increases the frequency of the data signal input data line corresponding to the first sub-region, or in other words, increases the time period of the data signal input data line of the first type of display frame (e.g., a partial refresh frame), in order to improve the phenomenon that the boundary line between the high-frequency refresh area and the low-frequency refresh area is abnormally displayed due to the sudden change in the load of the driver chip at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0192] In this embodiment, a computer-readable storage medium is provided, storing instructions for causing a machine to perform a control method for a display device as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0193] In this case, the program code read from the storage medium can itself implement the functions described in the above method embodiments, so the program code and the storage medium storing the program code constitute a part of this application.

[0194] Storage media embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0195] In this embodiment, a computer program product is provided, including computer instructions that instruct a computing device to perform the operations corresponding to the above-described method embodiments.

[0196] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0197] The methods described above according to embodiments of this application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or implemented as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and to be stored on a local recording medium after being downloaded over a network. Thus, the methods described herein can be stored on such software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for performing the methods shown herein. Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementations of this specification shown herein.

[0198] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0199] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0200] The above description is provided to enable any person skilled in the art to implement and use this application. Various details are set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0201] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0202] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application. The above descriptions are merely specific implementations of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A control method of a display device, applied to a display device including a high-frequency refresh area and a low-frequency refresh area, the high-frequency refresh area and the low-frequency refresh area occupying different row pixel circuits, characterized in that, The method comprises: controlling the data signal corresponding to the first range to input the data line at a first frequency, and controlling the data signal corresponding to the second range to input the data line at a second frequency, wherein the first frequency is greater than the second frequency, the low-frequency refresh area comprises a first sub-area adjacent to the high-frequency refresh area and a second sub-area located on a side of the first sub-area away from the high-frequency refresh area, the first range comprises the high-frequency refresh area and the first sub-area, and the second range comprises the second sub-area; controlling the data signal to write into the pixel circuit according to the sub-area enable signal, wherein the sub-area enable signal is at a non-enable level during a scanning period corresponding to the range of the first sub-area.

2. The method of claim 1, wherein, The display device comprises a first gate drive circuit, a plurality of rows of pixel circuits, and at least one sub-area enable signal line, the first gate drive circuit is connected with the sub-area enable signal line, the first gate drive circuit is connected with the pixel circuit, and the pixel circuit is connected with the data line, each of the at least one display frame comprises a first period corresponding to the low-frequency refresh area and a second period corresponding to the high-frequency refresh area, the first period comprises a first sub-period corresponding to the first sub-area and a second sub-period corresponding to the second sub-area; the at least one display frame comprises a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, and the first type of display frame is a holding frame of the low-frequency refresh area, the method further comprises: in the first type of display frame, a fixed potential is input to the data line in the second sub-period, a data signal or a signal with a changing potential is input to the data line in the first sub-period, or a potential different from the potential input to the data line in the second sub-period is input to the data line in the first sub-period, and a data signal corresponding to the high-frequency refresh area is input to the data line in the second period; in the first type of display frame, a non-enable level is input to the sub-area enable signal line in at least part of the second sub-period, a non-enable level is input to the sub-area enable signal line in at least part of the first sub-period, and an enable level is input to the sub-area enable signal line in at least part of the second period.

3. The method of claim 2, wherein the first gate drive circuit is configured to control the first gate drive circuit to output pulse signals of different frequencies to the high-frequency refresh area and the low-frequency refresh area according to the sub-area enable signal of the sub-area enable signal line.

4. The method of claim 2, wherein the number of rows of pixel circuits in the first sub-area is greater than or equal to 1 row; the first sub-period is less than or equal to a row period of the pixel circuit.

5. The method of claim 2, wherein, the at least one display frame comprises a second type of display frame, the second type of display frame is a refresh frame of the high-frequency refresh area, and the second type of display frame is a refresh frame of the low-frequency refresh area, the method further comprises: In the second type of display frame, in the second sub-period, a data signal corresponding to the second sub-region is input to the data line; in the first sub-period, a data signal corresponding to the first sub-region is input to the data line; and in the second period, a data signal corresponding to the high-frequency refresh region is input to the data line. In the second type of display frame, in the second sub-period, an enable level is input to the partition enable signal line; in the first sub-period, an enable level is input to the partition enable signal line; and in the second period, an enable level is input to the partition enable signal line.

6. The method of claim 5, wherein, M first type of display frames are arranged between adjacent second type of display frames, and a ratio of the first frequency to the second frequency is equal to M+1, where M is an integer greater than or equal to 1.

7. The method of claim 5, wherein, The method further comprises: The at least one low-frequency refresh region includes a first low-frequency refresh region, the first low-frequency refresh region is adjacent to the high-frequency refresh region, and data writing is performed before data writing in the high-frequency refresh region in the second type of display frame; the second sub-period corresponding to the first low-frequency refresh region is before the first sub-period corresponding to the first low-frequency refresh region; And / or, the at least one low-frequency refresh region includes a second low-frequency refresh region, the second low-frequency refresh region is adjacent to the high-frequency refresh region, and data writing is performed after data writing in the high-frequency refresh region in the second type of display frame; the second sub-period corresponding to the second low-frequency refresh region is after the first sub-period corresponding to the second low-frequency refresh region.

8. The method of claim 7, wherein, The first low-frequency refresh region and the second low-frequency refresh region are located on opposite sides of the high-frequency refresh region.

9. The method of claim 7, wherein, The duration of the first sub-period corresponding to the first low-frequency refresh region is greater than or equal to the duration of the first sub-period corresponding to the second low-frequency refresh region.

10. The method of claim 5, wherein, The partition enable signal line is a plurality of, The first gate drive circuit includes a plurality of cascaded shift register groups, each shift register group includes k cascaded shift register units, k is an integer greater than or equal to 2, each shift register unit includes m shift registers, m is an integer greater than or equal to 1, different shift register units in the same shift register group are electrically connected to different partition enable signal lines, different shift register groups are connected to the same k partition enable signal lines, and the output end of a shift register is electrically connected to n rows of pixel circuits, n is an integer greater than or equal to 1; The number of rows of pixel circuits in the first sub-region is less than or equal to k*m*n rows; The first sub-period is less than or equal to k*m*n times the row period of the pixel circuit.

11. The method of claim 10, wherein, The number of rows of pixel circuits in the first sub-region is greater than or equal to k*m*n / 4 rows; The first sub-period is less than or equal to k*m*n / 4 times the row period of the pixel circuit.

12. The method of claim 10, wherein, in the first type of display frame, a time point at which the sub-region enable signal line jumps from the non-enable level to the enable level is less than or equal to k*m*n row periods of the pixel circuit from a time point at which the signal input to the data line switches from the fixed potential to the data signal; and / or, in the first type of display frame, a time point at which the sub-region enable signal line jumps from the enable level to the non-enable level is less than or equal to k*m*n row periods of the pixel circuit from a time point at which the signal input to the data line switches from the data signal to the fixed potential.

13. The method of claim 10, wherein, in the first type of display frame, a time point at which the sub-region enable signal line jumps from the non-enable level to the enable level is greater than or equal to k*m*n / 4 row periods of the pixel circuit from a time point at which the signal input to the data line switches from the fixed potential to the data signal; and / or, in the first type of display frame, a time point at which the sub-region enable signal line jumps from the enable level to the non-enable level is greater than or equal to k*m*n / 4 row periods of the pixel circuit from a time point at which the signal input to the data line switches from the data signal to the fixed potential.

14. The method of claim 10, wherein, in the first type of display frame, time points at which the signals on the k sub-region enable signal lines jump to the enable level are sequentially delayed; and in the second type of display frame, the signals on the k sub-region enable signal lines are at the enable level. k-1 shift register units are connected between two adjacent shift register units connected to the same sub-region enable signal line.

16. The method of claim 15, wherein, the second time period comprises a third sub-time period and a fourth sub-time period, the third sub-time period is before the fourth sub-time period, in the third sub-time period of the first type of display frame, time points at which the signals on the k sub-region enable signal lines jump to the enable level are sequentially delayed; and in the fourth sub-time period of the first type of display frame, time points at which the signals on the k sub-region enable signal lines jump to the non-enable level are sequentially delayed.

17. The method of claim 15, wherein, in the first type of display frame, time points at which the signals on the k sub-region enable signal lines jump from the non-enable level to the enable level are related to positions of a boundary between the high-frequency refresh region and the low-frequency refresh region, and / or, in the first type of display frame, time points at which the signals on the k sub-region enable signal lines jump from the enable level to the non-enable level are related to positions of the boundary between the high-frequency refresh region and the low-frequency refresh region. the first gate drive circuit comprises a plurality of cascaded shift register units, the pixel circuit comprises a driving unit and a threshold compensation unit, the threshold compensation unit is connected between a control terminal and a first terminal of the driving unit, and a control terminal of the threshold compensation unit is electrically connected to an output terminal of the shift register in the first gate drive circuit.

15. The method of claim 10, wherein, 19. The method of claim 18, wherein, ​ ​ ​ ​ ​ 18. The method of claim 2, wherein, ​ ​ ​ The threshold compensation unit comprises an N-type transistor; And / or, the shift register comprises a shift unit and an output unit, the output unit is electrically connected with the shift unit, and the output unit is connected with the partition enable signal line, When the partition enable signal line is at the enable level, the output unit connected with the shift unit synchronously outputs the pulse signal when the shift unit outputs the pulse signal; When the partition enable signal line is at the non-enable level, the output unit connected with the shift unit outputs the constant level when the shift unit outputs the pulse signal.

20. The method of claim 19, wherein, The output unit comprises a first transistor and a second transistor; The control end of the first transistor and the control end of the second transistor are connected with the shift unit, the first end of the first transistor is electrically connected with the partition enable signal line, and the second end of the first transistor is electrically connected with the first end of the second transistor and the output end of the shift register; The second end of the second transistor is electrically connected with a first power supply signal line.

21. The method of claim 1, wherein, The display device comprises a first gate driving circuit, a plurality of pixel circuits, and at least one partition enable signal line, the first gate driving circuit is connected with the partition enable signal line, the first gate driving circuit is connected with the pixel circuit, and the pixel circuit is connected with the data line, The at least one display frame comprises a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, and the first type of display frame is a holding frame of the low-frequency refresh area, In the first type of display frame, the time when the signal on the partition enable signal line jumps from the non-enable level to the enable level is different from the time when the signal input to the data line switches from the fixed potential to the data signal; And / or, in the first type of display frame, the time when the signal on the partition enable signal line jumps from the enable level to the non-enable level is different from the time when the signal input to the data line switches from the data signal to the fixed potential.

22. The method of claim 21, wherein, In the first type of display frame, the time when the signal on the partition enable signal line jumps from the non-enable level to the enable level is after the time when the signal input to the data line switches from the fixed potential to the data signal; And / or, in the first type of display frame, the time when the signal on the partition enable signal line jumps from the enable level to the non-enable level is before the time when the signal input to the data line switches from the data signal to the fixed potential.

23. The method of claim 21, wherein, In the first type of display frame, the time when the signal on the partition enable signal line jumps from the non-enable level to the enable level is different from the time when the signal input to the data line switches from the fixed potential to the data signal by one or more row periods of the pixel circuit. And / or, in the first type of display frame, the time when the signal on the partition enabling signal line jumps from the enabling level to the non-enabling level is different from the time when the signal input to the data line switches from the data signal to the fixed potential by one or more row periods of the pixel circuit.

24. The method of claim 1, wherein, The method further comprises: subtracting N1 rows from the starting refresh row position parameter corresponding to the high-frequency refresh area to advance the start time of inputting the data signal to the data line by N1 row periods of the pixel circuit, and / or adding N2 rows to the ending refresh row position parameter corresponding to the high-frequency refresh area to delay the end time of inputting the data signal to the data line by N2 row periods of the pixel circuit, to obtain a first control signal corresponding to the start and end times of inputting the data signal to the data line, wherein N1 and N2 are integers greater than or equal to 1; delaying the first control signal to obtain a second control signal, the second control signal being delayed by N3 row periods of the pixel circuit compared to the first control signal; N3 is an integer greater than or equal to 1; adjusting the parameter of the second control signal corresponding to the ending refresh row position to obtain a partition enabling signal.

25. The method of claim 24, wherein the time when the partition enabling signal jumps from the non-enabling level to the enabling level corresponds to the time when the data signal corresponding to the starting refresh row position of the high-frequency refresh area is input to the data line; and / or the time when the partition enabling signal jumps from the enabling level to the non-enabling level corresponds to the time when the data signal corresponding to the ending refresh row position of the high-frequency refresh area is input to the data line.

26. The method of claim 24, wherein N1 = N2 = N3.

27. A display device comprising: The display area of the display device includes a high-frequency refresh area and a low-frequency refresh area, and the refresh frequency of the high-frequency refresh area is higher than that of the low-frequency refresh area. The display device comprises: a plurality of pixel circuits located in the high-frequency refresh area and the low-frequency refresh area; a first gate drive circuit; a data line connected to the pixel circuit; at least one partition enabling signal line, the first gate drive circuit is connected to the partition enabling signal line, and the first gate drive circuit is connected to the pixel circuit, wherein each of the at least one display frame includes a first period corresponding to the low-frequency refresh area and a second period corresponding to the high-frequency refresh area, the first period includes a first sub-period and a second sub-period, and the first sub-period is located between the second sub-period and the second period; at least one display frame includes a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, and the first type of display frame is a holding frame of the low-frequency refresh area, In the first type of display frame, in the second sub-period, a fixed potential is input to the data line; in the first sub-period, a data signal or a signal of potential change is input to the data line, and / or, in the first sub-period, a potential different from the potential input to the data line in the second sub-period is input to the data line; in the second period, a data signal corresponding to the high-frequency refresh area is input to the data line; In the first type of display frame, in at least part of the second sub-period, a non- enabling level is input to the partition enable signal line; in at least part of the first sub-period, a non-enabling level is input to the partition enable signal line, and in at least part of the second period, an enabling level is input to the partition enable signal line.

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