Display device

Abstract

The embodiment of the invention provides a display device, which comprises a gate drive circuit, a data drive circuit, a power supply circuit, a plurality of sub-pixels and corresponding sub-pixel drive circuits, in the sub-pixel drive circuits, a light-emitting duration control circuit obtains light-emitting duration compensation data and control power supply signals based on the light-emitting duration compensation data and the control power supply signals obtained by a first end of a first capacitor in a display period; light-emitting duration driving data is determined, and the level state of a first light-emitting control signal output by the second end of the first capacitor is adjusted according to the light-emitting duration driving data and the change condition of the control power supply signal, so that the duration of generating a driving signal by a light-emitting driving circuit electrically connected with the second end of the first capacitor is adjusted; in the above process, the process that the power line transmitting high level continuously transmits the electric energy to the power line transmitting low level does not exist, the energy consumption in the light emitting duration regulation and control process is reduced, and therefore the loss generated in the sub-pixel driving process is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technology, and in particular, to a display device. Background Art

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life, the display application field based on micro-LEDs has developed rapidly and has become a research hotspot for display devices.

[0003] The pixel driving circuit of the micro LED can drive the micro LED to emit light through pulse width modulation (PWM) + pulse amplitude modulation (PAM), that is, the pixel driving circuit controls the conduction state of the PWM driving transistor according to the PWM signal and the changing ramp signal it obtains, so as to regulate the time when the pixel driving circuit generates the driving signal, that is, the light-emitting time of the micro transistor in each frame display cycle; and then determine the current value in the driving signal according to the PAM signal to determine the light intensity of the micro transistor during the light-emitting process, thereby determining the brightness of the micro LED in each frame display cycle.

[0004] However, in the circuit for pulse width modulation within the pixel driving circuit, two transistors are connected to both ends of the PWM driving transistor. When the luminous time is adjusted, the PWM driving transistor and the two transistors will be turned on at the same time, and the power line transmitting a high level will transmit an electrical signal to the power line transmitting a low level through the two turned-on transistors and the PWM driving transistor, resulting in high energy consumption when the luminous duration is adjusted by using the on-state of the PWM driving transistor. Summary of the invention

[0005] The present application provides a display device for solving the technical problem of high energy consumption when adjusting the light emission duration by using the on-state of a PWM driving transistor.

[0006] An embodiment of the present application provides a display device, including:

[0007] A gate driving circuit, a data driving circuit, a power supply circuit, a plurality of sub-pixels and corresponding sub-pixel driving circuits;

[0008] The sub-pixel driving circuit comprises:

[0009] a light-emission duration control circuit, electrically connected to the gate drive circuit, the data drive circuit, and the power supply circuit, wherein the light-emission duration control circuit comprises a first capacitor, and is configured to determine the light-emission duration driving data based on a control power supply signal and light-emission duration compensation data obtained at a first end of the first capacitor during a display period; the control power supply signal is a signal obtained during a data writing phase, and the light-emission duration compensation signal is a signal obtained before the data writing phase;

[0010] The light emission duration control circuit is further configured to generate a first light emission control signal according to the light emission duration driving data and the variation of the control power supply signal, and output the first light emission control signal from the second end of the first capacitor;

[0011] a light-emitting driving circuit, electrically connected to the second end of the first capacitor and the gate driving circuit, and configured to adjust the duration of generating the driving signal in the display period according to the first light-emitting control signal;

[0012] The sub-pixel is electrically connected to the light-emitting driving circuit and is configured to emit light according to the driving signal.

[0013] In the above technical solution, a display device is provided, in which a sub-pixel driving circuit includes a light-emitting duration driving circuit and a light-emitting control circuit. A first capacitor is set in the light-emitting duration driving circuit. The first end of the first capacitor determines the light-emitting duration driving data in each display cycle according to the light-emitting duration compensation data and the control power signal obtained in sequence, so as to adjust the level state of the second end of the first capacitor, that is, the level state of the first light-emitting control signal, according to the changes of the light-emitting duration driving data and the control power signal, so as to regulate the duration of the light-emitting driving circuit to generate the driving signal, so as to regulate the light intensity of the sub-pixel. In the above process, there is no process in which the power line transmitting a high level continuously transmits electrical energy to the power line transmitting a low level, thereby reducing the energy consumption generated in the light-emitting duration regulation process, thereby reducing the loss generated in the sub-pixel driving process.

[0014] In a feasible implementation manner, the display cycle includes the first stage, the data writing stage and the display stage in sequence; the light emission duration control circuit also includes a data writing unit;

[0015] The light emission duration control circuit is configured to determine light emission duration driving data based on the control power supply signal and light emission duration compensation data obtained by the first capacitor during a display period, including:

[0016] The first end of the data writing unit is electrically connected to the data driving circuit, the second end thereof is electrically connected to the power supply circuit, and the output end thereof is electrically connected to the first end of the first capacitor, and is configured such that in the first stage, the output end is connected to the first end, and the second end is disconnected, and the light emission duration compensation data obtained by the first end is output from the output end;

[0017] The data writing unit is further configured to output the preset data obtained by the first end from the output end during the data writing phase;

[0018] The first capacitor is configured to determine the light-emitting duration driving data according to a difference between the light-emitting duration compensation data and the preset data during the data writing phase.

[0019] In a feasible implementation manner, the light-emitting duration control circuit is further configured to generate and output a first light-emitting control signal from the second end of the first capacitor according to the light-emitting duration driving data and the change amount of the control power supply signal, including:

[0020] The data writing unit is configured to connect the output end and the second end and disconnect the first end in the display phase, and output the control power signal obtained by the second end from the output end, wherein the initial level value of the control power signal in the display phase is the same as the level value of the preset data;

[0021] The first capacitor is also configured to determine and output the first light-emitting control signal from its second end during the display phase according to the light-emitting duration driving data, the change in the control power supply signal and its capacitance.

[0022] In the above technical solution, the luminous duration control circuit adjusts the first end and the second end of the data writing unit therein to be alternately connected to the output end in each display cycle, so that when the first end and the output end are connected, the luminous duration compensation data and the preset data are sequentially transmitted to the first end of the first capacitor electrically connected to the output end, so that the first capacitor determines and stores the luminous duration driving data according to the data difference obtained above, and when the first end of the data writing unit and the output end are disconnected and the second end and the output end are connected, since the initial level of the control power signal transmitted from the second end to the output end is the same as the level of the preset data, the terminal change is prevented from affecting the luminous duration driving data stored in the first capacitor. According to the influence of the control power signal, in the display stage when the second end and the output end are connected, based on the initial level of the control power signal, the level of the first end of the first capacitor is adjusted by adjusting the level of the control power signal, thereby adjusting the level of the first light-emitting control signal output from the second end of the first capacitor, thereby realizing the regulation of the light-emitting duration of the driving transistor in the light-emitting driving circuit. Compared with regulating the on and off states of the PWM driving transistor electrically connected to the power line that transmits high and low levels to control the conduction of the driving transistor, the energy loss generated during the conduction of the PWM driving transistor is saved, thereby reducing the loss generated during the sub-pixel driving process.

[0023] The display device provided in the embodiment of the present application includes a gate driving circuit, a data driving circuit, a power supply circuit, a plurality of sub-pixels and a corresponding sub-pixel driving circuit. The sub-pixel driving circuit includes a light-emitting duration control circuit and a light-emitting driving circuit. A first capacitor is set in the light-emitting duration control circuit. The first capacitor determines the light-emitting duration driving data according to the light-emitting duration compensation data and the control power supply signal obtained at its first end during the display period, and adjusts the level state of the first light-emitting control signal output from the second end of the first capacitor according to the change of the light-emitting duration driving data and the control power supply signal, thereby adjusting the duration of the driving light-emitting driving circuit electrically connected to the second end of the first capacitor to generate the driving signal, so as to regulate the light intensity generated by the sub-pixel. In the above process, there is no process in which the power line transmitting a high level continuously transmits electrical energy to the power line transmitting a low level, thereby reducing the energy consumption generated in the light-emitting duration regulation process, thereby reducing the loss generated in the sub-pixel driving process. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] Figure 1 A schematic diagram of the structure of a display provided by the present application according to an exemplary embodiment;

[0026] Figure 2A schematic diagram of the structure of a display provided according to another exemplary embodiment of the present application;

[0027] Figure 3 A circuit structure diagram of a conventional pixel driving circuit provided by the present application according to an exemplary embodiment;

[0028] Figure 4 A schematic diagram of the structure of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0029] Figure 5 A driving signal timing diagram of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0030] FIG. 6A to FIG. 6E This is an operating state diagram of a P-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0031] Figure 7 This is a schematic structural diagram of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment;

[0032] Figure 8 This is a driving signal timing diagram of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment.

[0033] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0034] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0035] It should be noted that, in this article, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, the parts, features, and elements with the same names in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment. It should be further understood that the terms "include", "comprise" indicate the existence of features, steps, operations, elements, components, projects, types, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, types, and / or groups.

[0036] In the description of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0037] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life, the display application field based on micro-LEDs has developed rapidly and has become a research hotspot for display devices.

[0039] The structural diagram of the display device is shown in Figure 1 and Figure 2As shown, the display device includes a control circuit 250, a data driving circuit 20, a gate driving circuit 30, a display panel 40, and a power supply circuit 280. The control circuit 250 and the data driving circuit 20 are electrically connected, and the control circuit 250 and the gate driving circuit 30 are electrically connected. The display panel 40 and the data driving circuit 20, the gate driving circuit 30, and the power supply circuit 280 are electrically connected.

[0040] The display panel is provided with a power line 90 , a plurality of gate lines 60 , a plurality of data lines 50 and a plurality of pixel units 80 . The plurality of pixel units 80 are arranged in an array, and each pixel unit 80 is located in a region where the gate line 60 and the data line 50 intersect.

[0041] The gate drive circuit 30 is electrically connected to the gate line 60. The gate drive circuit 30 is configured to obtain a clock signal and a trigger signal from the control circuit 250, and generate a gate drive signal based on the clock signal and the trigger signal, and transmit the gate drive signal to the corresponding pixel unit 80 through the gate line 60 to control the transistor in the pixel unit 80 to be turned on or off.

[0042] More specifically, the gate driver circuit 30 can be made into a separate gate driver integrated circuit (GDIC), and the gate driver circuit 30 can also be integrated into the display panel. The way of integrating the gate driver circuit 30 into the display panel is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the display panel 40 through the COG process (Chip on Glass), and the GDIC can be electrically connected to the display panel 40 through the COF process (Chipon Film). In the COF process, the component is electrically connected to the display panel 40 through a flexible printed circuit (FPC).

[0043] The data driving circuit 20 is a circuit for driving the data line 50, and is configured to obtain display data from the control circuit 250, convert it into an analog data voltage (Vdata), and transmit the data analog voltage to the corresponding pixel unit 80 through the data line 50, so that the sub-pixel 813 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the light-emitting brightness of the sub-pixel 813.

[0044] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

[0045] The power circuit 280 is a circuit for providing stable electrical signals, and is configured to provide corresponding required power signals to the display panel 40 , the control circuit 250 , the data driving circuit 20 , and the gate driving circuit 30 .

[0046] In one case, each pixel unit 80 includes three sub-pixel circuits 810, which are respectively used to display red light, blue light, and green light. In another case, each pixel unit 80 includes four sub-pixel circuits 810, which are respectively used to display red light, blue light, green light, and white light. This is not specifically limited here.

[0047] The luminous color of each sub-pixel unit 810 is determined by the properties of the sub-pixel 813. The sub-pixel 813 can be any luminous device, including but not limited to OLED and micro LED.

[0048] Micro LED refers to a micro light emitting body made of inorganic semiconductor layers. Micro LEDs can generally include a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, such as vertical, horizontal, flip-chip, etc., and is not particularly limited to a specific structure.

[0049] More specifically, a sub-pixel circuit 810 includes a sub-pixel driving circuit 814 and a sub-pixel 813. The sub-pixel driving circuit 814 is electrically connected to the sub-pixel 813, and the sub-pixel driving circuit 814 is configured to drive the sub-pixel 813 to emit light. The signals required by the sub-pixel driving circuit 814 include a driving signal, a scanning signal (Scan), and an emission control signal (Emission, referred to as: EM control signal).

[0050] The driving signal may be generated by the control circuit 250 or obtained from the outside. It includes but is not limited to a start pulse signal, a clock signal, and an enable signal. The light-emitting control signal may be a global signal provided by the control circuit 250 or a signal generated by the gate drive circuit 30, which is not specifically limited here. The scanning signal is a successive displacement signal generated by the gate drive circuit 30.

[0051] If the EM control signal is a global signal generated by the control circuit 250 , the gate driving circuit 30 obtains the EM control signal from the control circuit 250 , and transmits the EM control signal to the corresponding pixel driving circuit 814 through the gate line 60 .

[0052] If both the EM control signal and the scan signal are generated by the gate driving circuit 30, the gate driving circuit 30 includes a scan signal generating circuit 301 and an EM control signal generating circuit 302. The scan signal generating circuit 301 outputs the scan signal, and the EM control signal generating circuit 302 outputs the EM control signal.

[0053] Figure 3 It is a circuit structure diagram of a traditional pixel driving circuit provided in the present application according to an exemplary embodiment, including a PWM driving circuit 803 and a PAM driving circuit 804 .

[0054] The PWM driving circuit 803 is configured to obtain the lighting duration driving data PWMD and the control power signal SWEEP, and adjust the level of the first lighting control signal generated by it according to the lighting duration driving data PWMD and the control power signal SWEEP, and the level of the lighting control signal is the first level or the second level.

[0055] The PAM driving circuit 804 is electrically connected to the PWM driving circuit 803 and the sub-pixel LED, and is configured to obtain a first light-emitting control signal and current brightness driving data PAMD, and generate a driving signal according to the first light-emitting control signal and the current brightness driving data PAMD to drive the sub-pixel LED to emit light. The first light-emitting control signal is used to adjust the light-emitting duration of the sub-pixel LED, and the current brightness driving data PAMD is used to adjust the magnitude of the current passing through the sub-pixel LED.

[0056] The PWM driving circuit 803 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. All of the above transistors are N-type transistors.

[0057] The fourth transistor T4 has a first end electrically connected to the power line 90, a second end electrically connected to the first end of the sixth transistor T6, and a control end electrically connected to the gate line 60. The fourth transistor T4 is configured to obtain a low-level power signal VGL from its first end, obtain a second light-emitting control signal EM1 from its control end, turn on when the second light-emitting control signal EM1 is at a high level, and transmit the power signal VGL obtained at its first end to the first end of the sixth transistor T6.

[0058] The first end of the fifth transistor T5 is electrically connected to the second end of the sixth transistor T6, the second end is electrically connected to the power line 90, and the control end is electrically connected to the gate line 60. It is configured to obtain a high-level reference power signal REF from its second end, obtain a second light-emitting control signal EM1 from its control end, turn on when the second light-emitting control signal EM1 is at a high level, and transmit the reference power signal REF obtained at its first end to the second end.

[0059] The sixth transistor T6 is configured to be turned on when the electrical signal obtained at the control terminal thereof is greater than a preset threshold, and to be turned off when the electrical signal obtained at the control terminal thereof is less than the preset threshold.

[0060] When the sixth transistor T6 is turned on, since the size of the sixth transistor T6 is larger than the fifth transistor T5, the potential value of its second end is determined by the electrical signal obtained at its first end, which is a low level; when the sixth transistor T6 is turned off, the potential value of the second end of the sixth transistor T6 is determined by the fifth transistor T5 electrically connected to this point, which is a high level.

[0061] The PAM driving circuit 804 adjusts the time period for generating the driving signal according to the level state provided by the second end of the sixth transistor T6, that is, when the second end of the sixth transistor T6 is at a high level, it stops generating the driving signal, and the sub-pixel LED does not emit light; when the first end of the sixth transistor T6 is at a low level, it generates the driving signal, and the sub-pixel LED emits light.

[0062] Since when the sixth transistor T6 is turned on, the fifth transistor T5 and the fourth transistor T4 are also turned on, the power line providing the reference power signal REF transmits the electrical signal to the power line providing the power signal VGL through the turned-on fifth transistor T5, the sixth transistor T6 and the fourth transistor T4, and a cross-charging phenomenon occurs in the sixth transistor T6, consuming a large amount of power.

[0063] In order to solve the above problems, the present application provides a display device to solve the technical problem of high energy consumption when adjusting the light-emitting duration by using the conduction state of a PWM driving transistor. The technical concept of the present application is to provide a sub-pixel driving circuit, including a light-emitting duration driving circuit and a light-emitting control circuit, wherein the light-emitting duration control circuit determines the light-emitting duration driving data according to the light-emitting duration compensation data and the control power supply signal obtained by the first end of the first capacitor, and adjusts the level state of the first light-emitting control signal output by the second end of the first capacitor according to the change of the light-emitting duration driving data and the control power supply signal, so as to adjust the duration of the driving transistor to generate the driving signal, thereby adjusting the light intensity of the sub-pixel. In the above process, there is no process in which the power line transmitting a high level continuously transmits electric energy to the power line transmitting a low level, thereby reducing the energy consumption in the light-emitting duration adjustment process, thereby reducing the loss generated in the sub-pixel driving process.

[0064] The pixel driving circuit proposed in this application is explained in detail below. Figure 4 The schematic diagram of the structure of a pixel driving circuit provided by the present application according to an exemplary embodiment is shown in FIG.

[0065] like Figure 4 As shown, the pixel driving circuit provided in the present application includes a light emitting duration control circuit 901 and a light emitting driving circuit 902 .

[0066] The light-emission duration control circuit 901 is electrically connected to the power line 90 and the data line 50. The light-emission duration control circuit 901 includes a first capacitor C1 and is configured to determine and store light-emission duration driving data based on a control power signal Sweep and light-emission duration compensation data PWMD obtained at a first end of the first capacitor C1 during a display period. The control power signal Sweep is a signal obtained during a data writing phase, and the light-emission duration compensation signal PWMD is a signal obtained before the data writing phase.

[0067] The light emission duration control circuit 901 is further configured to generate and output a first light emission control signal from the second end (point A) of the first capacitor C1 according to the light emission duration driving data and the change amount of the control power supply signal Sweep.

[0068] The light-emitting driving circuit 902 is electrically connected to the second end of the first capacitor C1 and is configured to adjust the duration of generating the driving signal in the display period according to the first light-emitting control signal.

[0069] The sub-pixel LED is electrically connected to the light-emitting driving circuit 902 and is configured to emit light according to a driving signal.

[0070] In the above technical scheme, the light-emitting duration control circuit including the first capacitor determines the light-emitting duration driving data based on the light-emitting duration compensation data and the control power signal of the first end of the first capacitor, and adjusts the level state of the first light-emitting control signal output from the second end of the first capacitor according to the changes of the light-emitting duration driving data and the control power signal to regulate the duration of the light-emitting driving circuit to generate the driving signal, thereby regulating the light intensity of the sub-pixel. In the above process, there is no process in which the power line transmitting a high level continuously transmits electrical energy to the power line transmitting a low level, which reduces the energy consumption in the light-emitting duration regulation process, thereby reducing the loss generated in the sub-pixel driving process.

[0071] The light-emitting duration control circuit 901 includes a data writing unit 903 and a first capacitor C1. The display cycle includes a first phase, the data writing phase and a display phase in sequence.

[0072] The first end of the data writing unit 903 is electrically connected to the data line 50, the second end thereof is electrically connected to the power line 90, and the output end thereof is electrically connected to the first end of the first capacitor C1. The data writing unit 903 is configured such that in the first stage, the output end thereof is connected to the first end thereof, and the second end thereof is disconnected, and the luminous duration compensation data PWMD is obtained from the first end thereof, and the luminous duration compensation data PWMD is output from the output end thereof.

[0073] The data writing unit 903 is further configured to obtain preset data from its first end and output the preset data from its output end during the data writing phase.

[0074] The first capacitor C1 is configured to determine the light-emitting duration driving data according to the difference between the light-emitting duration compensation data and the preset data during the data writing phase.

[0075] More specifically, the potential value of the second end of the first capacitor C1 changes with the change of its first end. After the data obtained at its first end is adjusted from the luminous duration compensation data to the preset data, the level state of its second end is adjusted according to the difference in the level determined by its first end, its capacitance and the capacitance in the circuit structure electrically connected to its second end, and the level value of the second end is determined as the level value corresponding to the luminous duration driving data.

[0076] The data writing unit 903 is further configured to connect its output terminal and the second terminal and disconnect its first terminal in the display phase, obtain a control power signal Sweep from its second terminal, and output the control power signal Sweep from the output terminal.

[0077] The initial level value of the control power signal in the display stage is the same as the level value of the preset data, so as to prevent the potential value of the output end of the data writing unit 903 from jumping when the terminal is adjusted.

[0078] The first capacitor C1 is also configured to output a first light-emitting control signal from its second end during the display phase according to the light-emitting duration driving data determined during the data writing phase and the control power signal Sweep that changes during the light-emitting phase. Wherein, the first end of the first capacitor C1 only receives the control power signal Sweep during the display phase, and the level of its second end will increase with the increase of the control power signal Sweep based on the level value corresponding to the determined light-emitting duration driving data, and decrease with the decrease of the control power signal Sweep.

[0079] When the second end of the first capacitor C1 is electrically connected to other capacitors, when the potential value of the control power signal SWEEP obtained at the first end thereof changes, the first capacitor C1 will couple with other capacitors to adjust the potential value of point A.

[0080] The data writing unit 903 includes a fifth transistor T5 and a seventh transistor T7.

[0081] The first end of the fifth transistor T5 serves as the first end of the data writing unit 903, and the second end thereof serves as the output end of the data writing unit 903. The control end thereof is electrically connected to the gate line 60, and is configured to obtain the third scanning signal S3 from the control end thereof, and the conduction state thereof is controlled by the third scanning signal S3.

[0082] The fifth transistor T5 is turned on when the third scanning signal S3 is at a low level, and outputs the luminous duration compensation data PWMD or preset data obtained at the first end from its second end; and is turned off when the third scanning signal S3 is at a high level, stopping the transmission of the electrical signal.

[0083] The first end of the seventh transistor T7 serves as the second end of the data writing unit 903, the second end thereof is electrically connected to the second end of the fifth transistor T5, the control end thereof is electrically connected to the gate line 60, and it is configured to obtain the third light emitting control signal EM2 from its control end, and its conduction state is controlled by the third light emitting control signal EM2.

[0084] The seventh transistor T7 is turned on when the third light emitting control signal EM2 is at a low level, and outputs the power control signal Sweep from its second end; and is turned off when the third light emitting control signal EM2 is at a high level, and stops outputting the power control signal Sweep.

[0085] In the above technical solution, the luminous duration control circuit adjusts the first end and the second end of the data writing unit therein to be alternately connected to the output end in each display cycle, so that when the first end and the output end are connected, the luminous duration compensation data and the preset data are sequentially transmitted to the first end of the first capacitor electrically connected to the output end, so that the first capacitor determines and stores the luminous duration driving data according to the data difference obtained above, and when the first end of the data writing unit and the output end are disconnected and the second end and the output end are connected, since the initial level of the control power signal transmitted from the second end to the output end is the same as the level of the preset data, the terminal change is prevented from affecting the luminous duration stored in the first capacitor. In the display stage when the second end and the output end are connected, based on the initial level of the control power signal, the level of the control power signal is adjusted to adjust the level of the first end of the first capacitor, thereby adjusting the level of the first light-emitting control signal output from the second end of the first capacitor, so as to realize the regulation of the light-emitting duration of the driving transistor. Compared with regulating the on and off state of the PWM driving transistor electrically connected to the power line that transmits high and low levels to control the conduction of the driving transistor, the energy loss generated during the conduction of the PWM driving transistor is saved, thereby reducing the loss generated during the sub-pixel driving process.

[0086] The light-emitting driving circuit 902 includes a light-emitting control circuit 906 , a light-emitting threshold compensation circuit 905 and a reset circuit 904 .

[0087] The first end of the reset circuit 904 is electrically connected to the power line 90, and the second end thereof is electrically connected to the luminescence threshold compensation circuit 905 and the second end of the first capacitor C1 at point A. The reset circuit 904 is configured to obtain a reference power signal REF from the power line 90 at its first end before the compensation stage, and transmit the reference power signal REF to the luminescence threshold compensation circuit 905 and the second end of the first capacitor C1 when it is turned on.

[0088] The luminescence threshold compensation circuit 905 and the first capacitor C1 are configured to perform a reset operation according to the reference power supply signal REF so that the potential value of the second end of the first capacitor C1 and the potential value of the device terminal electrically connected to point A in the luminescence threshold compensation circuit 905 are adjusted to the same low level as the reference power supply signal REF.

[0089] The control end of the luminous threshold compensation circuit 905 is electrically connected to the second end of the first capacitor C1 through point A, its first end is electrically connected to the third end of the luminous control circuit 906 through point C, its second end is electrically connected to the fourth end of the luminous control circuit 906 through point E, and its power supply end is electrically connected to the power line 90 through point B.

[0090] The luminous threshold compensation circuit 905 is configured to obtain a first power supply signal VDD from its power supply end and its first end respectively during the compensation stage, store the threshold voltage of the driving transistor T2 according to the first power supply signal VDD, and generate and transmit a driving signal to the luminous control circuit 906 according to the stored threshold voltage and the first luminous control signal during the display stage.

[0091] The first end of the light-emitting control circuit 906 is electrically connected to the power line 90 through point B, the second end is electrically connected to the sub-pixel LED through point F, the third end is electrically connected to the light-emitting threshold compensation circuit 905 through point C, and the fourth end is electrically connected to the light-emitting threshold compensation circuit 905 through point E.

[0092] The light-emitting control circuit 906 is configured to obtain a first power signal VDD from the power line 90 at its first end, output the first power signal from its third end to the light-emitting threshold compensation circuit 905 during the compensation phase and the display phase of the display cycle, and transmit the drive signal generated by the light-emitting threshold compensation circuit 905 obtained at its fourth end during the display phase to the sub-pixel LED from its second end to drive the sub-pixel LED to emit light.

[0093] The reset circuit 904 includes a first transistor T1 .

[0094] The first end of the first transistor T1 is electrically connected to the power line 90, the control end thereof is electrically connected to the gate line 60, the second end thereof is electrically connected to the second end of the first capacitor C1, the second end of the second capacitor C2, and the control end of the driving transistor T2, and is configured to obtain the first scanning signal S1 from its control end and obtain the reference power signal REF from its first end, and its conduction state is controlled by the first scanning signal S1.

[0095] The first transistor T1 is turned on when the first scan signal S1 is at a low level, and outputs a reference power signal REF from its second end for resetting the device electrically connected to the second end; it is turned off when the first scan signal S1 is at a high level, and stops outputting the reference power signal REF.

[0096] The light emitting control circuit 906 includes a fourth transistor T4 and a sixth transistor T6.

[0097] The first end of the fourth transistor T4 serves as the first end of the light emitting control circuit 906, and the second end thereof serves as the third end of the light emitting control circuit 906. The control end thereof is electrically connected to the gate line 60, and is configured to obtain the first power supply signal VDD from the first end thereof and the second light emitting control signal EM1 from the control end thereof, and the conduction state thereof is controlled by the second light emitting control signal EM1.

[0098] The fourth transistor T4 is turned on when the second light emitting control signal EM1 is at a low level, and outputs the first power signal VDD from its second end; and is turned off when the second light emitting control signal EM1 is at a high level, and stops the transmission of the first power signal VDD.

[0099] The first end of the sixth transistor T6 serves as the fourth end of the light-emitting control circuit 906, and the second end thereof serves as the second end of the light-emitting control circuit 906. The control end thereof is electrically connected to the gate line 60, and is configured to obtain the third light-emitting control signal EM2 from the control end thereof, and the conduction state thereof is controlled by the third light-emitting control signal EM2.

[0100] The sixth transistor T6 is turned on when the third light emitting control signal EM2 is at a low level, and when a driving signal is obtained at its first end, the driving signal is transmitted from its second end to the positive electrode of the sub-pixel LED, so that the sub-pixel LED emits light according to the driving signal.

[0101] The light emission threshold compensation circuit 905 includes: a second capacitor C2, a driving transistor T2 and a third transistor T3.

[0102] The first end of the third transistor T3 serves as the control end of the light-emitting threshold compensation circuit 905 and is electrically connected to the control end of the driving transistor T2. The control end is electrically connected to the gate line 60. The second end of the third transistor T3 serves as the second end of the light-emitting threshold compensation circuit 905 and is electrically connected to the second end of the driving transistor T2. The third transistor T3 is configured to obtain the second scanning signal S2 from its control end, and its conduction state is controlled by the second scanning signal.

[0103] The third transistor T3 is turned on when the second scanning signal S2 is at a low level, short-circuiting the control terminal and the second terminal of the driving transistor T2; and is turned off when the second scanning signal S2 is at a high level, disconnecting the control terminal and the second terminal of the driving transistor T2.

[0104] The first end of the driving transistor T2 is used as the first end of the light emitting threshold compensation circuit 905, and is configured to be short-circuited between its control end and its second end, and when its first end obtains the first power supply signal VDD transmitted by the fourth transistor T4, the first power supply signal VDD compensated by its threshold voltage is output from its control end, and the voltage value is V A =VVDD +V th , where V A represents the potential value of point A, that is, the potential value of the control terminal of the driving transistor T2, V VDD represents the potential value of the first power signal VDD, V th represents the threshold voltage of the driving transistor T2.

[0105] The driving transistor T2 is further configured to control its conduction state by an electrical signal obtained from its control terminal when the control terminal and the second terminal are disconnected.

[0106] The driving transistor T2 is turned on to generate a driving signal when the voltage value of the electrical signal obtained at its control end is within a preset voltage range; it is turned off to stop generating the driving signal when the voltage value of the electrical signal obtained at its control end is not within the preset voltage range.

[0107] The first end of the second capacitor C2 is electrically connected to the power line 90, and the second end is electrically connected to the control end of the driving transistor T2. The second capacitor C2 is configured to obtain a stable power signal (e.g., the first power signal VDD) from the first end and adjust the stored data according to the electrical signal obtained at the second end.

[0108] The second capacitor C2 is configured to maintain a reference power signal REF for resetting at its second end when the first transistor T1 is turned on, so that the control end of the driving transistor T2 can continuously obtain the low-level reference power signal REF and maintain the turned-on state.

[0109] The second capacitor C2 is further configured to obtain the threshold voltage compensated first power signal generated by the control terminal of the driving transistor T2 at its second terminal, and determine the voltage difference between its two terminals as the threshold voltage VDD of the driving transistor T2 according to the first power signal VDD obtained at its first terminal. th , and store the threshold voltage.

[0110] Since the second end of the second capacitor C2 is also electrically connected to the second end of the first capacitor C1, after the driving transistor T2 generates the first power supply signal for threshold voltage compensation, when the first end of the first capacitor C1 obtains the electrical signal transmitted by the fifth transistor T5 and adjusts the light-emitting duration compensation data to the preset data, the first capacitor C1 and the second capacitor C2 are coupled to adjust the stored electrical energy, and the potential value of point A is changed: Among them, ▲V PWMD represents the potential difference between the preset data and the light-emitting duration compensation data, c1 represents the capacitance of the first capacitor C1, and c2 represents the capacitance of the second capacitor C2.

[0111] When the electrical signal obtained at the first end of the first capacitor C1 is adjusted to the control power signal Sweep transmitted by the seventh transistor T7, the first capacitor C1 and the second capacitor C2 are coupled to adjust the potential value of point A according to the change amount of the control power signal Sweep: Among them, ▲V Sweep Indicates the change in the control power signal Sweep.

[0112] In the above technical solution, the pixel driving circuit not only utilizes the change in the potential value of the first end of the first capacitor to regulate the conduction time of the driving transistor in the process of controlling the conduction of the driving transistor, but also replaces the function of the transistor for regulating the change in the potential value, thereby saving the power consumption of the transistor used for regulation. At the same time, compared with the traditional pixel driving circuit, the above pixel driving circuit simplifies the circuit structure, reduces the use of transistors, saves the area occupied by the pixel circuit in the display panel, and can effectively improve the pixel density and panel resolution.

[0113] Figure 4 The circuit structure shown is composed of Figure 5 Drive according to the driving signal timing diagram shown.

[0114] Combine the following FIG. 6A to FIG. 6E The process diagram shown is Figure 4 The circuit structure shown is used to explain the circuit operation in a display cycle. A display cycle T includes a first stage T1, a data writing stage t3 and a display stage t4 in sequence. The first stage T1 includes a reset stage t1 and a compensation stage t2 in sequence.

[0115] In the period corresponding to the reset phase t1 in the driving signal timing diagram, the first scanning signal S1 and the third scanning signal S3 are at a low level, the second scanning signal S2, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a high level, and the reference power signal REF is at a low level. The control power signal SWEEP is adjusted from a low level to a high level, and the driving data is the preset data.

[0116] Since the first scanning signal S1 is at a low level, the first transistor T1 is turned on, and the reference power signal REF obtained at the first end thereof is transmitted to the A point.

[0117] Since the second light emitting control signal EM1 is at a high level, the fourth transistor T4 is turned off and cannot transmit the first power signal VDD to the driving transistor T2.

[0118] Since the reference power signal REF is at a low level, the signal obtained by the control terminal of the driving transistor T2 is at a low level, and the driving transistor T2 is turned on; since the first terminal of the driving transistor T2 does not obtain the first power signal VDD, the driving transistor T2 does not generate a driving signal.

[0119] In addition, the second end of the first capacitor C1 and the second end of the second capacitor C2 follow the signal obtained at point A to adjust the potential to initialize the second ends thereof, wherein the adjusted potential value is the same as the potential value of the reference power signal REF.

[0120] Since the third scan signal S3 is at a low level, the fifth transistor T5 is turned on and transmits the preset data obtained at its first end to the first end of the first capacitor C1, so that the first capacitor C1 adjusts the potential of its first end to the same potential as the preset data according to the preset data, thereby achieving initialization.

[0121] The control power signal SWEEP is adjusted from a low level to a high level to prepare for level change according to the ramp signal during the display stage t4, thereby avoiding affecting the accuracy of the data stored in the first capacitor when adjusting the level during the display stage t4.

[0122] Since the third light emitting control signal EM2 is at a high level, the seventh transistor T7 is turned off, and the control power signal SWEEP obtained by the first end thereof will not be transmitted to the second end, and thus the potential value of the first end of the first capacitor C1 will not be affected in the reset stage t1.

[0123] Then, during the period corresponding to the reset phase t1, the operation state of the sub-pixel driving circuit is as follows: Fig. 6A As shown, the first transistor T1 , the fifth transistor T5 , and the driving transistor T2 with arrows next to them are turned on, and the other transistors are turned off.

[0124] During the period corresponding to the compensation phase t2 in the driving signal timing diagram, the second scanning signal S2, the third scanning signal S3, and the second light-emitting control signal EM1 are at a low level, and the first scanning signal S1, the third light-emitting control signal EM2 and the control power signal SWEEP are at a high level.

[0125] Since the first scanning signal S1 is at a high level, the first transistor T1 is turned off and stops transmitting the reference power signal REF to each capacitor.

[0126] Since the second light emitting control signal EM1 is at a low level, the fourth transistor T4 is turned on, and the first power signal VDD obtained at the first end thereof is transmitted to the first end of the driving transistor T2.

[0127] Since the second scanning signal S2 is at a low level, the third transistor T3 is turned on, and the control terminal and the second terminal of the driving transistor T2 are short-circuited.

[0128] Since the control terminal and the second terminal of the driving transistor T2 are short-circuited, and the first terminal thereof obtains the first power supply signal VDD, the potential value obtained from the control terminal thereof is V DD +V th , then the potential value of the second end of each capacitor is adjusted to VDD +V th .

[0129] The second end of the first capacitor C1 and the second end of the second capacitor C2 store the threshold-compensated first power signal VDD.

[0130] Then, during the period corresponding to the compensation stage t2, the operating state of the sub-pixel driving circuit is as follows: Figure 6B As shown, the fifth transistor T5, the fourth transistor T4, the driving transistor T2 and the third transistor T3 with arrows next to them are turned on, and the other transistors are turned off.

[0131] During the period corresponding to the data writing phase t3 in the driving signal timing diagram, the third scanning signal S3 is at a low level, and the first scanning signal S1, the second scanning signal S2, the second light-emitting control signal EM1, the third light-emitting control signal EM2 and the control power supply signal SWEEP are at a high level.

[0132] Since the second light emitting control signal EM1 is at a high level, the fourth transistor T4 is turned off, and stops transmitting the first power signal VDD obtained at its first end to the first end of the driving transistor T2.

[0133] Since the second scanning signal S2 is at a high level, the third transistor T3 is turned off, and the control terminal and the second terminal of the driving transistor T2 are disconnected.

[0134] Since the electric signal obtained by the control terminal of the driving transistor T2 is the electric signal stored in the capacitor (V DD +V th ), the signal is at a high level, and the driving transistor T2 is turned off.

[0135] Since the third scan signal S3 is at a low level, the fifth transistor T5 is turned on, and the data electrical signal obtained at the first end thereof is transmitted to the first end of the third capacitor C3.

[0136] Then, during the period corresponding to the data writing phase t3, the operation state of the sub-pixel driving circuit is as follows: Figure 6C As shown, the fifth transistor T5 with an arrow next to it is turned on, and the other transistors are turned off.

[0137] The data writing phase t3 can be further divided into: a first data writing sub-phase and a second data writing sub-phase.

[0138] In the first data writing sub-phase, since the data electrical signal obtained by the first end of the fifth transistor T5 is still the electrical signal corresponding to the light emission duration compensation data, the level value of the first end of the first capacitor C1 remains unchanged.

[0139] In the second data writing sub-phase, the data electrical signal obtained at the first end of the fifth transistor T5 is adjusted to an electrical signal corresponding to the preset data, and the second end of the first capacitor C1 determines the light-emitting duration driving data according to the potential value change of the first end, its capacitance, and the capacitance of the second capacitor C2, and adjusts the potential value of the second end accordingly:

[0140] It is worth noting that at the end of the second data writing sub-stage, before the fifth transistor T5 is turned off, the first end of the first capacitor C1 still remains in the state of receiving the preset data. After the fifth transistor T5 is turned off, the transmission of the original light-emitting duration driving data is stopped to ensure the accuracy of the target light-emitting duration driving data obtained by coupling the second ends of each capacitor.

[0141] After entering the display phase, the data line 50 continues to transmit the preset data for a period of time and then jumps back to the state of transmitting the light-emitting duration compensation data. The duration of the data line 50 transmitting the preset data in the display phase is the same as the duration of the data line 50 transmitting the light-emitting duration compensation data in the data writing phase, so that the clock signal used by the data line 50 when transmitting the driving data is the same as the clock signal used by the gate line 50 when transmitting the scanning signal, thereby ensuring a simple structure of the driving circuit.

[0142] In the driving signal timing diagram, during the time period corresponding to stage t4, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a low level, the first scanning signal S1, the second scanning signal S2 and the third scanning signal S3 are at a high level, and the control power signal SWEEP is a ramp signal adjusted from a high level to a low level.

[0143] Since the second light emitting control signal EM1 is at a low level, the fourth transistor T4 is turned on, and the first power signal VDD obtained at the first end thereof is transmitted to the first end of the driving transistor T2.

[0144] Since the second scanning signal S2 is at a high level, the third transistor T3 is turned off, the control terminal and the second terminal of the driving transistor T2 are disconnected, and the driving transistor T2 adjusts its conduction state according to the level state of the electrical signal obtained at its control terminal.

[0145] Since the third scan signal S3 is at a high level, the fifth transistor T5 is turned off, and the fifth transistor T5 stops transmitting data to the first end of the first capacitor C1.

[0146] Since the third light emitting control signal EM2 is at a low level, the seventh transistor T7 is turned on, and the control power signal Sweep obtained at the first end thereof is transmitted to the first end of the first capacitor C1.

[0147] Since the level of the control power signal Sweep is the same as the level of the preset data transmitted by the fifth transistor T5 when the seventh transistor T7 is turned on, the potential value of the second end of the first capacitor C1 is not affected during the transistor switching process.

[0148] Since the control power signal SWEEP is a ramp signal adjusted from a high level to a low level, the potential value of the first light emitting control signal generated at the second end of the first capacitor C1 decreases as the potential value of the first end decreases.

[0149] The potential value of the second end of the first capacitor C1 is determined according to the coupling effect of each capacitor and the potential change value of the first end thereof: Where, ΔV A represents the potential change at the second end of the first capacitor C1, ΔV SWEEP represents the potential change of the control power signal SWEEP obtained by the first end of the first capacitor C1, c1 represents the capacitance of the first capacitor C1, and c2 represents the capacitance of the first capacitor C2.

[0150] According to the change of the potential value of the second end of the first capacitor C1 and the turn-on voltage range of the driving transistor T2, the display stage T4 is divided into a non-light-emitting stage and a light-emitting stage.

[0151] In the non-light-emitting stage, when the potential value of the second end of the first capacitor C1 continues to decrease but is still not within the preset voltage range corresponding to the driving transistor T2 being turned on, the driving transistor T2 remains in the turned-off state.

[0152] In this embodiment, the potential value of the second end of the first capacitor C1 is not within the preset voltage range corresponding to the driving transistor T2 being turned on, which means that the potential value of the second end of the first capacitor C1 is greater than the first turn-on preset voltage threshold.

[0153] In the light-emitting stage, when the potential value of the second end of the first capacitor C1 continues to decrease and is within the driving voltage range corresponding to the driving transistor T2 being turned on, the driving transistor T2 is turned on, and a driving signal is generated according to the first power signal VDD obtained at its first end, the potential value obtained at its control end and its threshold voltage, which is Right now Wherein, k is the current conversion coefficient associated with the driving transistor T2.

[0154] In this embodiment, the potential value of the second end of the first capacitor C1 being within the preset voltage range corresponding to turning on the driving transistor T2 indicates that the potential value of the second end of the first capacitor C1 is less than or equal to the first turn-on preset voltage threshold.

[0155] Since the third light emitting control signal EM2 is at a low level, the sixth transistor T6 is turned on.

[0156] In the non-luminous stage, the first end of the sixth transistor T6 does not receive the driving signal transmitted by the driving transistor T2, and thus cannot transmit the driving signal to the sub-pixel LED, and the sub-pixel LED does not emit light. Fig.6D As shown, the seventh transistor T7, the fourth transistor T4, and the sixth transistor T6 with arrows next to them are turned on, and the other transistors are turned off.

[0157] In the light-emitting stage, the sixth transistor T6 transmits the driving signal obtained at its first terminal to the positive electrode of the sub-pixel LED, and the sub-pixel LED emits light. Correspondingly, the operating state of the sub-pixel driving circuit is as follows: Fig. 6E As shown, the seventh transistor T7 , the fourth transistor T4 , the sixth transistor T6 , and the driving transistor T2 with arrows next to them are turned on, and the other transistors are turned off.

[0158] Figure 7 Schematic diagram of the structure of an N-type pixel driving circuit provided by the present application according to an exemplary embodiment, in which each transistor in the pixel driving circuit is an N-type transistor. Figure 4 The circuit structure shown is Figure 7 The circuit structure shown is briefly explained.

[0159] Compared to Figure 4 The circuit structure shown is different in that:

[0160] Each transistor is turned on when a high level is obtained and turned off when a low level is obtained;

[0161] The reference power signal REF obtained by the first end of the first transistor T1 from the power line 90 is a high level signal, the first end of the fourth transistor T4 and the first end of the second capacitor C2 obtain the first power signal VSS from the power line 90 as a low level signal, the second end of the sixth transistor T6 is electrically connected to the cathode of the sub-pixel LED, and the sub-pixel LED emits light when its anode obtains the second power signal VDD and its cathode obtains the driving signal transmitted by the sixth transistor T6.

[0162] Other circuit connections and Figure 4 The circuit structure shown is the same and will not be repeated here.

[0163] Figure 7 The circuit structure shown is composed of Figure 8 Drive according to the driving signal timing diagram shown.

[0164] In the period corresponding to the reset phase t1 in the driving signal timing diagram, the first scanning signal S1 and the third scanning signal S3 are at a high level, the second scanning signal S2, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a low level, and the reference power signal REF is at a high level. The control power signal SWEEP is adjusted from a high level to a low level.

[0165] The first transistor T1 is turned on according to the first scanning signal S1, and transmits the reference power signal REF obtained at its first end to the second end of each capacitor and the control end of the driving transistor T2, so as to reset the second end of each capacitor and control the driving transistor T2 to turn on.

[0166] The fifth transistor T5 is turned on according to the third scanning signal S3, and transmits the light emission duration compensation data obtained at the first end thereof to the first end of the first capacitor C1, so as to reset the first end of the first capacitor C1.

[0167] During the period corresponding to the compensation phase t2 in the driving signal timing diagram, the second scanning signal S2, the third scanning signal S3 and the second light-emitting control signal EM1 are at high levels, and the first scanning signal S1, the third light-emitting control signal EM2 and the control power signal SWEEP are at low levels.

[0168] The fourth transistor T4 is turned on according to the second light emitting control signal EM1 , and transmits the first power signal VSS obtained at the first end thereof to the first end of the driving transistor T2 .

[0169] The third transistor T3 is turned on according to the second scanning signal S2, and the second end and the control end of the driving transistor T2 are short-circuited, so that the driving transistor T2 determines the first power signal VSS+Vth after threshold voltage compensation from its control end according to the first power signal VSS obtained at its first end, and stores the compensated first power signal at the second end of each capacitor, wherein Vth is the threshold voltage of the driving transistor T2.

[0170] In the period corresponding to the data writing phase t3 in the driving signal timing diagram, the third scanning signal S3 is at a high level, and the first scanning signal S1, the second scanning signal S2, the second light-emitting control signal EM1, the third light-emitting control signal EM2 and the control power signal SWEEP are at a low level.

[0171] The fifth transistor T5 is turned on according to the third scanning signal S3, and the preset data obtained at its first end is transmitted to the first end of the first capacitor C1. The first capacitor C1 combines with other capacitors to couple the change of the driving data obtained at its first end, stores the light-emitting duration driving data at the second end of each capacitor, and adjusts the potential value of point A according to the light-emitting duration driving data, which is

[0172] Since the control end of the driving transistor T2 is electrically connected to the second end of each capacitor, the driving data is turned off according to the above determined target light emitting duration.

[0173] In the driving signal timing diagram, during the time period corresponding to stage t4, the second light-emitting control signal EM1 and the third light-emitting control signal EM2 are at a high level, the first scanning signal S1, the second scanning signal S2 and the third scanning signal S3 are at a low level, and the control power signal SWEEP is a ramp signal adjusted from a low level to a high level.

[0174] The fifth transistor T5 is turned off according to the third scan signal S3 to stop the transmission of driving data.

[0175] The seventh transistor T7 is turned on according to the third light emitting control signal EM2 , and transmits the control power signal Sweep obtained at the first end thereof to the first end of the first capacitor C1 .

[0176] The second end of the first capacitor C1 follows the change of the control power signal SWEEP obtained by the first end thereof to adjust the potential value of the first light emitting control signal outputted by it, which is:

[0177] The fourth transistor T4 is turned on according to the second light emitting control signal EM1 , and transmits the first power signal VSS obtained at the first end thereof to the first end of the driving transistor T2 .

[0178] When the potential value of the first light emitting control signal is smaller than the second on-preset voltage threshold for turning on the driving transistor T2 , the driving transistor T2 is not turned on and does not generate a driving signal.

[0179] As the control power signal SWEEP increases, the potential value of the first light-emitting control signal increases. When its potential value is greater than or equal to the second turn-on preset voltage threshold that turns on the driving transistor T2, the driving transistor T2 is turned on, and a driving signal is generated according to the first power signal VSS obtained at its first end and its threshold voltage. Right now Wherein, k is the current conversion coefficient associated with the driving transistor T2.

[0180] The sixth transistor T6 is turned on according to the third light emitting control signal EM2 , and transmits the driving signal obtained at its first end to the cathode of the sub-pixel LED when the driving transistor T2 generates the driving signal.

[0181] The sub-pixel LED emits light according to the driving signal.

[0182] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0183] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display device, comprising: A gate driving circuit, a data driving circuit, a power supply circuit, a plurality of sub-pixels and corresponding sub-pixel driving circuits; Characterized in that, the sub-pixel driving circuit comprises: a light-emission duration control circuit, electrically connected to the gate drive circuit, the data drive circuit, and the power supply circuit, wherein the light-emission duration control circuit comprises a first capacitor, and is configured to determine the light-emission duration driving data based on a control power supply signal and light-emission duration compensation data obtained at a first end of the first capacitor during a display period; the control power supply signal is a signal obtained during a data writing phase, and the light-emission duration compensation signal is a signal obtained before the data writing phase; The light emission duration control circuit is further configured to generate a first light emission control signal according to the light emission duration driving data and the variation of the control power supply signal, and output the first light emission control signal from the second end of the first capacitor; a light-emitting driving circuit, electrically connected to the second end of the first capacitor and the gate driving circuit, and configured to adjust the duration of generating the driving signal in the display period according to the first light-emitting control signal; The sub-pixel is electrically connected to the light-emitting driving circuit and is configured to emit light according to the driving signal.

2. The display device according to claim 1, characterized in that The display cycle includes the first stage, the data writing stage and the display stage in sequence, and the light emission duration control circuit also includes a data writing unit; The light-emission duration control circuit is configured to determine light-emission duration driving data based on the control power supply signal obtained at the first end of the first capacitor and the light-emission duration compensation data within a display period, including: The first end of the data writing unit is electrically connected to the data driving circuit, the second end thereof is electrically connected to the power supply circuit, and the output end thereof is electrically connected to the first end of the first capacitor, and is configured such that in the first stage, the output end is connected to the first end, and the second end is disconnected, and the light emission duration compensation data obtained by the first end is output from the output end; The data writing unit is further configured to output the preset data obtained by the first end from the output end during the data writing phase; The first capacitor is configured to determine the light-emitting duration driving data according to a difference between the light-emitting duration compensation data and the preset data during the data writing phase.

3. The display device according to claim 2, characterized in that: The light-emission duration control circuit is further configured to generate and output a first light-emission control signal from a second end of the first capacitor according to the light-emission duration driving data and a change amount of the control power supply signal, including: The data writing unit is configured to connect the output end and the second end and disconnect the first end in the display phase, and output the control power signal obtained by the second end from the output end, wherein the initial level value of the control power signal in the display phase is the same as the level value of the preset data; The first capacitor is also configured to determine and output the first light-emitting control signal from its second end during the display phase according to the light-emitting duration driving data, the change in the control power supply signal and its capacitance.

4. The display device according to claim 2 or 3, characterized in that: The data writing unit comprises: a fifth transistor, a first end of which serves as the first end of the data writing unit, a second end of which serves as the output end of the data writing unit, a control end of which is electrically connected to the gate driving circuit, and is configured to obtain a third scanning signal from the control end of the fifth transistor, and to control its conduction state by the third scanning signal; A seventh transistor, whose first end serves as the second end of the data writing unit, whose second end is electrically connected to the second end of the fifth transistor, and whose control end is electrically connected to the gate driving circuit, is configured to obtain a third light-emitting control signal from its control end, and whose conduction state is controlled by the third light-emitting control signal.

5. The display device according to claim 1, characterized in that The light-emitting driving circuit includes a light-emitting control circuit, a light-emitting threshold compensation circuit and a reset circuit; the first stage includes a reset stage and a compensation stage in sequence; The reset circuit is electrically connected to the gate drive circuit, the power supply circuit, the light emission threshold compensation circuit, and the second end of the first capacitor, and is configured to obtain a first scanning signal from the gate drive circuit, obtain a reference power supply signal from the power supply circuit, and output the reference power supply signal by controlling the first scanning signal to reset the light emission threshold compensation circuit and the second end of the first capacitor; The light emitting control circuit is electrically connected to the gate driving circuit, the power supply circuit, and the light emitting threshold compensation circuit, and is configured to obtain a first power supply signal from the power supply circuit, obtain a second light emitting control signal from the gate driving circuit, and control the output of the first power supply signal by the second light emitting control signal during the compensation phase and the display phase of the display cycle; The light emission threshold compensation circuit is electrically connected to the gate driving circuit and the second end of the first capacitor, and the light emission threshold compensation circuit includes a driving transistor, and is configured to obtain a second scanning signal from the gate driving circuit, store a threshold voltage of the driving transistor in the first capacitor when the second scanning signal is at a first level, and generate a driving signal based on the first light emission control signal when the second scanning signal is at a second level; The light emitting control circuit is also electrically connected to the sub-pixel, and is configured to obtain a third light emitting control signal from the gate driving circuit, obtain the driving signal from the light emitting threshold compensation circuit, and output the driving signal under the control of the third light emitting control signal.

6. The display device according to claim 1, characterized in that: A display cycle includes a reset phase, a compensation phase, a data writing phase and a display phase in sequence; In the reset stage, the first scanning signal and the third scanning signal are at a first level, the second scanning signal, the second light-emitting control signal and the third light-emitting control signal are at a second level, and the control power supply signal is adjusted from the first level to the second level; The reset circuit is turned on according to the first scanning signal, and transmits the reference power supply signal obtained by the reset circuit to the second end of the first capacitor and the light emitting threshold compensation circuit; The first capacitor resets its second end according to the reference power signal; The light emission threshold compensation circuit is reset according to the reference power supply signal; The fifth transistor is turned on according to the third scanning signal, transmits the light emitting duration compensation data obtained at its first end to its second end, and stores it at the first end of the first capacitor.

7. The display device according to claim 6, characterized in that: In the compensation stage, the second scanning signal, the third scanning signal and the second light-emitting control signal are at a first level, and the first scanning signal, the third light-emitting control signal and the control power supply signal are at a second level; The light emitting control circuit transmits the first power supply signal obtained by the light emitting control circuit to the light emitting threshold compensation circuit according to the second light emitting control signal; The light emission threshold compensation circuit obtains a first power supply signal for threshold voltage compensation of the driving transistor according to the second scanning signal and the first power supply signal; The first capacitor stores the first power signal for threshold voltage compensation; The fifth transistor maintains a state of outputting the light emission duration compensation data according to the third scanning signal, so that the potential value of the first end of the first capacitor remains unchanged.

8. The display device according to claim 6, characterized in that: In the data writing stage, the third scanning signal is at a first level, and the first scanning signal, the second scanning signal, the second light emitting control signal, the third light emitting control signal and the control power supply signal are at a second level; The fifth transistor is turned on according to the third scanning signal, and transmits the preset data acquired by the first end thereof to the first end of the first capacitor; The first capacitor determines and stores the light-emitting duration driving data from its second end according to the difference between the light-emitting duration compensation data and the preset data, its capacitance value and the first power supply signal compensated by the threshold voltage of the driving transistor; The level value of the preset data is the same as the level value of the second level.

9. The display device according to claim 6, characterized in that: In the display stage, the second light-emitting control signal and the third light-emitting control signal are at a first level, the first scanning signal, the second scanning signal and the third scanning signal are at a second level, and the control power supply signal is a ramp signal adjusted from the second level to the first level; The light emitting control circuit transmits the first power supply signal obtained by the light emitting control circuit to the light emitting threshold compensation circuit according to the second light emitting control signal; The seventh transistor is turned on according to the third light emitting control signal, and transmits the control power signal obtained at the first end thereof to the first end of the first capacitor; The first capacitor outputs the first light-emitting control signal from the second end thereof according to the potential change amount of the first end thereof and the light-emitting duration driving data stored therein; The light emitting threshold compensation circuit determines a preset voltage range according to the first power supply signal, and generates a driving signal according to the first light emitting control signal and the preset voltage range; The light emitting control circuit transmits the driving signal to the sub-pixel when the driving signal is obtained according to the third light emitting control signal; The sub-pixel emits light according to the driving signal.

10. The display device according to claim 9, characterized in that: The display phase includes a non-luminous period and a luminous period; The light-emitting threshold compensation circuit determines a preset voltage range according to the first power supply signal, and generates a driving signal according to the first light-emitting control signal and the preset voltage range, including: In the non-light-emitting period, the control power supply signal is a ramp signal adjusted from the second level to a third level, the potential value of the first light-emitting control signal is not within a preset voltage range, and the light-emitting threshold compensation circuit does not generate a driving signal; In the light-emitting period, the control power supply signal is a ramp signal adjusted from the third level to the first level, the potential value of the first light-emitting control signal is within the preset voltage range, and the light-emitting threshold compensation circuit generates a driving signal; The third level is between the first level and the second level.

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