Partition display circuit and driving method thereof, display panel and display device

Abstract

The application discloses a partition display circuit and a driving method thereof, a display panel and a display device, and relates to the technical field of display. The circuit comprises a display driving module, a main display area and a sub-display area. The display driving module comprises a main display driving element and a sub-display driving element. The main display driving element is electrically connected with a plurality of pixel rows of the main display area. The sub-display driving element is electrically connected with a plurality of pixel rows of the sub-display area. The display driving module is configured to acquire a partition display requirement of a user, determine a target display area according to the partition display requirement, enable the main display driving element to supply power to the plurality of pixel rows of the main display area according to a preset main driving timing sequence according to the target display area for the main display area, or enable the sub-display driving element to supply power to the plurality of pixel rows of the sub-display area according to a preset sub-driving timing sequence according to the target display area for the sub-display area. The application realizes partition display of the display panel to reduce display power consumption.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a partitioned display circuit and its driving method, a display panel, and a display device. Background Technology

[0002] In the current field of display technology, with the widespread application of display devices, reducing display power consumption has become an important direction for technological development.

[0003] While existing display panels have made significant progress in resolution and display quality, they still face many inconveniences in local dimming. For example, traditional display panels typically use overall backlight control, which cannot precisely adjust the brightness according to the display needs of different areas, resulting in higher power consumption. In addition, traditional display panels struggle to achieve independent driving and brightness adjustment for different areas when using local dimming, thus affecting display quality and power consumption control, and consequently severely restricting the energy-saving development of display panels.

[0004] Therefore, how to achieve partitioned display on the display panel to reduce display power consumption is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a partitioned display circuit and its driving method, a display panel, and a display device, which aim to achieve partitioned display of the display panel to reduce display power consumption.

[0006] To achieve the above objectives, this application provides a partitioned display circuit, which includes a display driving module, a main display area, and a secondary display area. The display driving module includes a main display driver and a secondary display driver. The main display driver is electrically connected to multiple pixel rows of the main display area, and the secondary display driver is electrically connected to multiple pixel rows of the secondary display area.

[0007] The display driver module is configured to acquire the user's partition display requirements, determine the target display area based on the partition display requirements, and enable the main display driver to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence for the main display area based on the target display area; or, enable the secondary display driver to supply power to multiple pixel rows of the secondary display area according to a preset secondary drive timing sequence for the secondary display area based on the target display area.

[0008] In one embodiment, the main display driver includes a first main driving module, which includes a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a first capacitor, and a second capacitor.

[0009] The gate terminal of the first thin-film transistor and the first pass terminal of the first thin-film transistor are both electrically connected to the two main gate terminals before the current main gate terminal. The second pass terminal of the first thin-film transistor is electrically connected to the first terminal of the first capacitor and the gate terminal of the second thin-film transistor, respectively. The first pass terminal of the second thin-film transistor is electrically connected to the current main clock signal terminal.

[0010] The gate terminal of the third thin-film transistor, the first path terminal of the third thin-film transistor, the second terminal of the first capacitor, and the second path terminal of the second thin-film transistor are all electrically connected to the current main gate terminal. The second path terminal of the third thin-film transistor is electrically connected to the gate terminal of the second capacitor and the fourth thin-film transistor, respectively. The first path terminal of the fourth thin-film transistor is electrically connected to the main clock terminals of the two stages following the current main clock signal terminal. The second path terminal of the fourth thin-film transistor is electrically connected to the main gate terminals of the two stages following the current main gate terminal.

[0011] In one embodiment, the main display driver further includes a second main driving module, which includes a fifth thin-film transistor, a sixth thin-film transistor, a seventh thin-film transistor, an eighth thin-film transistor, a third capacitor, and a fourth capacitor.

[0012] The gate terminal of the fifth thin-film transistor and the first pass terminal of the fifth thin-film transistor are both electrically connected to the previous stage main gate terminal of the current main gate terminal. The second pass terminal of the fifth thin-film transistor is electrically connected to the first terminal of the third capacitor and the gate terminal of the sixth thin-film transistor, respectively. The first pass terminal of the sixth thin-film transistor is electrically connected to the next stage main clock signal terminal of the current stage main clock signal terminal.

[0013] The gate terminal of the seventh thin-film transistor, the first path terminal of the seventh thin-film transistor, the second terminal of the third capacitor, and the second path terminal of the sixth thin-film transistor are all electrically connected to the next stage main gate terminal of the current main gate terminal. The second path terminal of the seventh thin-film transistor is electrically connected to the gate terminals of the fourth capacitor and the eighth thin-film transistor, respectively. The first path terminal of the eighth thin-film transistor is electrically connected to the next three stages of the main clock signal terminal of the current stage. The second path terminal of the eighth thin-film transistor is electrically connected to the next three stages of the main gate terminal of the current main gate terminal.

[0014] In one embodiment, the secondary display area includes an upper display area and a lower display area, with the upper display area and the lower display area respectively disposed on both sides of the main display area; wherein,

[0015] The number of pixel rows in the upper display area is the same as the number of pixel rows in the lower display area, and the total number of pixel rows between the number of pixel rows in the upper display area and the number of pixel rows in the lower display area is less than the number of pixel rows in the main display area.

[0016] In one embodiment, the sub-display driver includes an upper display driver corresponding to the upper display area and a lower display driver corresponding to the lower display area;

[0017] The upper display driver is electrically connected to multiple pixel rows in the upper display area, and the lower display driver is electrically connected to multiple pixel rows in the lower display area.

[0018] In one embodiment, the upper display driver includes a ninth thin-film transistor, a tenth thin-film transistor, an eleventh thin-film transistor, a twelfth thin-film transistor, a fifth capacitor, and a sixth capacitor;

[0019] The gate terminal of the ninth thin film transistor and the first pass terminal of the ninth thin film transistor are both electrically connected to the previous stage upper gate terminal of the current upper gate terminal. The second pass terminal of the ninth thin film transistor is electrically connected to the first terminal of the fifth capacitor and the gate terminal of the tenth thin film transistor, respectively. The first pass terminal of the tenth thin film transistor is electrically connected to the current stage upper clock signal terminal.

[0020] The gate terminal of the eleventh thin-film transistor, the first path terminal of the eleventh thin-film transistor, the second terminal of the fifth capacitor, and the second path terminal of the tenth thin-film transistor are all electrically connected to the current upper gate terminal. The second path terminal of the eleventh thin-film transistor is electrically connected to the gate terminals of the sixth capacitor and the twelfth thin-film transistor, respectively. The first path terminal of the twelfth thin-film transistor is electrically connected to the next stage upper clock terminal after the current stage upper clock signal terminal. The second path terminal of the twelfth thin-film transistor is electrically connected to the next stage upper gate terminal after the current upper gate terminal.

[0021] In one embodiment, the lower display driver includes a thirteenth thin-film transistor, a fourteenth thin-film transistor, a fifteenth thin-film transistor, a sixteenth thin-film transistor, a seventh capacitor, and an eighth capacitor;

[0022] The gate terminal of the thirteenth thin-film transistor and the first path terminal of the thirteenth thin-film transistor are both electrically connected to the previous stage lower gate terminal of the current lower gate terminal. The second path terminal of the thirteenth thin-film transistor is electrically connected to the first terminal of the seventh capacitor and the gate terminal of the fourteenth thin-film transistor, respectively. The first path terminal of the fourteenth thin-film transistor is electrically connected to the current stage lower clock signal terminal.

[0023] The gate terminal of the fifteenth thin-film transistor, the first path terminal of the fifteenth thin-film transistor, the second terminal of the seventh capacitor, and the second path terminal of the fourteenth thin-film transistor are all electrically connected to the current lower gate terminal. The second path terminal of the fifteenth thin-film transistor is electrically connected to the gate terminals of the eighth capacitor and the sixteenth thin-film transistor, respectively. The first path terminal of the sixteenth thin-film transistor is electrically connected to the next stage lower clock terminal after the current stage lower clock signal terminal. The second path terminal of the sixteenth thin-film transistor is electrically connected to the next stage lower gate terminal after the current lower gate terminal.

[0024] Furthermore, to achieve the above objectives, this application also provides a driving method for a partitioned display circuit, which is applied to the partitioned display circuit described in any of the above claims, the driving method comprising:

[0025] The display driver module obtains the user's partition display requirements and determines the target display area based on these requirements.

[0026] Based on the target display area being the main display area, the main display driver in the display driver module is enabled to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence; or, based on the target display area being the secondary display area, the secondary display driver in the display driver module is enabled to supply power to multiple pixel rows of the secondary display area according to a preset secondary drive timing sequence.

[0027] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the partitioned display circuit described in any of the above claims.

[0028] Furthermore, to achieve the above objectives, this application also provides a display device, which includes the aforementioned display panel; or,

[0029] The display device includes a processor, a memory, and a driver program stored in the memory that can be executed by the processor, wherein when the driver program is executed by the processor, it implements the steps of the above-described driving method.

[0030] The partitioned display circuit described in this application enables partitioned display of the display panel to reduce display power consumption. This partitioned display circuit includes a display driver module, a main display area, and a secondary display area. The display driver module integrates a main display driver and a secondary display driver. The main display driver is electrically connected to multiple pixel rows of the main display area, while the secondary display driver is electrically connected to multiple pixel rows of the secondary display area, thus achieving independent partitioned driving of the main and secondary display areas. Specifically, the display driver module can accurately determine the target display area based on the user's partitioned display requirements. Then, it selectively enables either the main or secondary display driver based on the target display area. When the target display area is the main display area, the main display driver is enabled to supply power to multiple pixel rows of the main display area according to a preset main driving timing sequence. When the target display area is the secondary display area, the secondary display driver is enabled to supply power to multiple pixel rows of the secondary display area according to a preset secondary driving timing sequence. This achieves power supply to the pixel rows within the specified display area for partitioned display requirements, effectively avoiding unnecessary power waste under overall backlight control in traditional display panels and significantly reducing the display panel's power consumption. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a structural block diagram of the first embodiment of the partitioned display circuit of this application;

[0034] Figure 2 This is a schematic diagram of the partitioned display circuit involved in the embodiments of this application;

[0035] Figure 3 This is a schematic diagram of the signal waveforms of the partition display circuit involved in the embodiments of this application;

[0036] Figure 4 This is a schematic diagram of the upper display area involved in the embodiments of this application;

[0037] Figure 5 This is a schematic diagram of the main display area involved in the embodiments of this application;

[0038] Figure 6 This is a schematic diagram of the lower display area involved in the embodiments of this application;

[0039] Figure 7 This is a schematic diagram of the structure of the display device involved in the embodiments of this application.

[0040] Explanation of reference numerals: 10, Main display driver; 20, Sub-display driver; 11, First main driver module; T1, First thin-film transistor; T2, Second thin-film transistor; T3, Third thin-film transistor; T4, Fourth thin-film transistor; C1, First capacitor; C2, Second capacitor; 12, Second main driver module; T5, Fifth thin-film transistor; T6, Sixth thin-film transistor; T7, Seventh thin-film transistor; T8, Eighth thin-film transistor; C3, Third capacitor; C4, Fourth capacitor; 21, Upper display driver; T9, Ninth thin-film transistor; T10, Tenth thin-film transistor; T11, Eleventh thin-film transistor; T12, Twelfth thin-film transistor; C5, Fifth capacitor; C6, Sixth capacitor; 22, Lower display driver; T13, Thirteenth thin-film transistor; T14, Fourteenth thin-film transistor; T15, Fifteenth thin-film transistor; T16, Sixteenth thin-film transistor; C7, Seventh capacitor; C8, Eighth capacitor.

[0041] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0043] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0044] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0046] In the current field of display technology, with the widespread application of display devices, reducing display power consumption has become an important direction for technological development.

[0047] While existing display panels have made significant progress in resolution and display quality, they still face many inconveniences in local dimming. For example, traditional display panels typically use overall backlight control, which cannot precisely adjust the brightness according to the display needs of different areas, resulting in higher power consumption. In addition, traditional display panels struggle to achieve independent driving and brightness adjustment for different areas when using local dimming, thus affecting display quality and power consumption control, and consequently severely restricting the energy-saving development of display panels.

[0048] Therefore, how to achieve partitioned display on the display panel to reduce display power consumption is a technical problem that urgently needs to be solved.

[0049] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art.

[0050] To address the technical deficiencies mentioned above, this application provides a partitioned display circuit and its driving method, a display panel, and a display device.

[0051] This application provides a partitioned display circuit, referring to... Figure 1 As shown, Figure 1This is a structural block diagram of the first embodiment of the partitioned display circuit of this application. The partitioned display circuit includes a display driving module, a main display area, and a sub-display area. The display driving module includes a main display driver 10 and a sub-display driver 20. The main display driver 10 is electrically connected to multiple pixel rows of the main display area, and the sub-display driver 20 is electrically connected to multiple pixel rows of the sub-display area.

[0052] In this embodiment, the partitioned display circuit provided in this application divides the display panel into a main display area and a secondary display area, and is equipped with a main display driver 10 and a secondary display driver 20 respectively, realizing independent control of different display areas, thereby significantly improving the power consumption management capability and display flexibility of the display panel.

[0053] In a specific embodiment, the main display driver 10 is electrically connected to multiple pixels in the main display area and can independently adjust its main driving timing and brightness output according to the display content requirements of the main display area; the secondary display driver 20 is electrically connected to multiple pixels in the secondary display area and can also independently adjust its secondary driving timing and brightness output according to the display content requirements of the secondary display area, so that the display panel can flexibly adjust the display status of the main display area and the secondary display area according to the actual usage scenario.

[0054] The display driver module is configured to acquire the user's partitioned display requirements, determine the target display area based on the partitioned display requirements, and enable the main display driver 10 to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence for the main display area based on the target display area; or, enable the secondary display driver 20 to supply power to multiple pixel rows of the secondary display area according to a preset secondary drive timing sequence for the secondary display area based on the target display area.

[0055] In this embodiment, after the display driver module receives the user's partition display request based on the preset human-computer interaction interface, it obtains the partition display scene corresponding to the partition display request. When the partition display scene is the main display area usage scene, the target display area is determined to be the main display area. Next, according to the response of the driver chip in the display driver module to the target display area as the main display area, the display driving state of the main display driver 10 is switched from the off state to the driving state, and a stable and reliable power supply is provided to multiple pixel rows in the main display area for normal display according to the preset main driving timing. At the same time, the driver chip also responds to the target display area as the main display area, enabling the sub-display driver 20 to remain in the off state, thereby avoiding the sub-display area from consuming additional power when displaying unnecessarily.

[0056] In another implementation, when the partitioned display scenario is a secondary display area usage scenario, the target display area is determined to be the secondary display area. Next, based on the response of the driver chip in the display driver module to the target display area being a secondary display area, the display driver state of the secondary display driver 20 is enabled to switch from the off state to the driving state, and a stable and reliable power supply is provided to multiple pixel rows in the secondary display area according to the preset secondary driving timing for normal display. At the same time, the driver chip also responds to the target display area being a secondary display area by enabling the main display driver 10 to remain in the off state, thereby avoiding the main display area consuming additional power when displaying unnecessarily.

[0057] It should be noted that the main display area can be understood as a scenario for displaying dynamic content, such as game screens, movie screens, and novel browsing screens. The secondary display area can be understood as a scenario for displaying static content, such as time displays, phone screens, and SMS screens.

[0058] The secondary display driver 20 includes an upper display driver 21 and a lower display driver 22; the preset secondary drive timing can include an upper drive timing and a lower drive timing; the secondary display area can include an upper display area and a lower display area; the upper display area can be used to display static information such as time, telephone or SMS notifications, and the lower display area can display other auxiliary content, such as system status, shortcut operation buttons or a typing keyboard. The above is only one feasible implementation of this application, and the functions of the upper display area and the lower display area can be interchanged. This application does not impose any restrictions here.

[0059] For example, when the user's partition display needs are basic interfaces such as time display or the display panel's display power meets the preset single-zone display power threshold, the display driver 21 can provide a stable and reliable power supply to multiple pixel rows in the upper display area according to the upper driving sequence for normal display. This not only fulfills the user's display needs by displaying the upper display area separately, but also effectively reduces power consumption.

[0060] Furthermore, in some feasible embodiments, reference is made to Figure 2 , Figure 2This is a schematic diagram of the partitioned display circuit involved in the embodiment of this application. The main display driver 10 includes a first main driver module 11, which includes a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, a fourth thin-film transistor T4, a first capacitor C1, and a second capacitor C2. The gate terminal and the first pass terminal of the first thin-film transistor T1 are electrically connected to the two preceding main gate terminals of the current main gate terminal. The second pass terminal of the first thin-film transistor T1 is electrically connected to the first terminal of the first capacitor C1 and the gate terminal of the second thin-film transistor T2, respectively. The first pass terminal of the second thin-film transistor T2 is connected to the current main gate terminal. The master clock signal terminal is electrically connected; the gate terminal of the third thin film transistor T3, the first path terminal of the third thin film transistor T3, the second terminal of the first capacitor C1, and the second path terminal of the second thin film transistor T2 are all electrically connected to the current master gate terminal; the second path terminal of the third thin film transistor T3 is electrically connected to the second capacitor C2 and the gate terminal of the fourth thin film transistor T4, respectively; the first path terminal of the fourth thin film transistor T4 is electrically connected to the master clock terminals of the two stages following the current master clock signal terminal; and the second path terminal of the fourth thin film transistor T4 is electrically connected to the master gate terminals of the two stages following the current master gate terminal.

[0061] In this embodiment, when the target display area is the main display area, the driver chip provides signal STV2 to the current level master clock signal terminal in the first driver module, as well as the master clock terminals of the two levels after the current level master clock signal terminal.

[0062] It should be noted that the clock signal input to the current stage master clock signal terminal can be used Figure 2 The signal clk3 shown represents the current stage's main clock signal; the main clock signals of the two stages following the current stage can be represented by... Figure 2 The signal clk5 shown represents the gate drive signals connected to the first two main gate stages at the current main gate terminal; these signals can be represented by... Figure 2 The signal Gn-2 shown represents the current gate drive signal connected to the main gate terminal; it can be represented by... Figure 2 The signal Gn shown represents the gate drive signals connected to the last two main gate stages at the current main gate terminal. Figure 2 The signal Gn+2 shown is characterized.

[0063] For example, refer to Figures 2 to 3 The driver chip configured in this application responds to the target display area being the main display area, and the enable signal STV2 is emitted from... Figure 3 The low potential is switched to a high potential; next, signal STV2 turns on signals clk3 and clk5 to a high potential, that is, signals clk3 and clk5 are switched from low potential to high potential respectively.

[0064] Furthermore, in some other feasible embodiments, reference is made to... Figure 2 The main display driver 10 further includes a second main driver module 12, which includes a fifth thin-film transistor T5, a sixth thin-film transistor T6, a seventh thin-film transistor T7, an eighth thin-film transistor T8, a third capacitor C3, and a fourth capacitor C4. The gate terminal and the first pass terminal of the fifth thin-film transistor T5 are electrically connected to the preceding main gate terminal of the current main gate terminal. The second pass terminal of the fifth thin-film transistor T5 is electrically connected to the first terminal of the third capacitor C3 and the gate terminal of the sixth thin-film transistor T6, respectively. The first pass terminal of the sixth thin-film transistor T6 is connected to the following terminal of the current main clock signal terminal. The primary master clock signal terminal is electrically connected; the gate terminal of the seventh thin-film transistor T7, the first path terminal of the seventh thin-film transistor T7, the second terminal of the third capacitor C3, and the second path terminal of the sixth thin-film transistor T6 are all electrically connected to the next stage master gate terminal of the current master gate terminal; the second path terminal of the seventh thin-film transistor T7 is electrically connected to the gate terminal of the fourth capacitor C4 and the eighth thin-film transistor T8 respectively; the first path terminal of the eighth thin-film transistor T8 is electrically connected to the next three stage master clock terminals of the current master clock signal terminal; and the second path terminal of the eighth thin-film transistor T8 is electrically connected to the next three stage master gate terminals of the current master gate terminal.

[0065] In this embodiment, the driver chip provides signal STV2 to the current master clock signal terminal and the two master clock terminals after the current master clock signal terminal in the first driver module based on the display status of the target display area as the main display area. At the same time, it also provides signal STV2 to the master clock signal terminal after the current master clock signal terminal and the three master clock terminals after the current master clock signal terminal in the second driver module.

[0066] It should be noted that the clock signal input to the next stage's master clock signal terminal after the current stage's master clock signal terminal can be... Figure 2 The signal clk4 shown represents the current stage's main clock signal; the main clock signals of the three stages following the current stage can be represented by... Figure 2 The signal clk6 shown represents the gate drive signal connected to the previous stage's main gate at the current main gate terminal. Figure 2 The signal Gn-1 shown represents the gate drive signal connected to the next stage main gate terminal of the current main gate terminal; it can be represented by... Figure 2 The signal Gn+1 shown represents the gate drive signals connected to the last three main gate stages at the current main gate terminal. Figure 2 The signal Gn+3 shown is characterized.

[0067] For example, refer to Figures 2 to 3The driver chip configured in this application responds to the target display area being the main display area, and the enable signal STV2 is emitted from... Figure 3 The low potential is switched to a high potential; next, signal STV2 enables signals clk4 and clk6 to be at a high potential, that is, signals clk4 and clk6 are respectively connected to... Figure 3 The corresponding signal waveform is shown.

[0068] In a specific example, refer to Figures 2 to 3 The main display area is driven by signal STV2, which sequentially activates signals clk3, clk4, clk5, and clk6 in a 4-clk loop. The main display area typically has around 1500 pixel rows, meaning the 4-clk loop repeats 1500 / 4 = 375 times. In other words, the preset main drive timing is a 4-clk loop, where signals clk3, clk4, clk5, and clk6 work sequentially, driving 4 pixel rows per loop. For example, for 1500 pixel rows in the main display area, signal clk3 drives the first pixel row in each loop (the row electrically connected to signal Gn), signal clk4 drives the second pixel row (the row electrically connected to signal Gn+1), signal clk5 drives the third pixel row (the row electrically connected to signal Gn+2), and signal clk6 drives the third pixel row (the row electrically connected to signal Gn+2).

[0069] Furthermore, in some feasible embodiments, reference is made to Figure 2 The secondary display area includes an upper display area and a lower display area, and the upper display area and the lower display area are respectively arranged on both sides of the main display area; wherein, the number of pixel rows in the upper display area is the same as the number of pixel rows in the lower display area, and the total number of pixel rows between the number of pixel rows in the upper display area and the number of pixel rows in the lower display area is less than the number of pixel rows in the main display area.

[0070] In this embodiment, the secondary display area is divided into an upper display area and a lower display area, which are respectively located on both sides of the main display area. Specifically, the upper and lower display areas have the same number of pixel rows, and the total number of pixel rows between the upper and lower display areas is less than the number of pixel rows in the main display area. This allows the main display area to occupy the central part of the display panel for displaying primary dynamic content, such as game footage or video playback, while the upper and lower display areas can be used to display static or auxiliary information, such as time, notifications, and status bars. In other words, by setting upper and lower display areas on both sides of the main display area, this application allows the display panel to flexibly adjust the display status and power consumption distribution of each area according to different display needs, thereby optimizing the display effect while significantly reducing overall power consumption and improving the energy efficiency of the display panel.

[0071] Furthermore, in some other feasible embodiments, reference is made to... Figure 2 The sub-display driver 20 includes an upper display driver 21 corresponding to the upper display area and a lower display driver 22 corresponding to the lower display area; the upper display driver 21 is electrically connected to a plurality of pixel rows in the upper display area, and the lower display driver 22 is electrically connected to a plurality of pixel rows in the lower display area.

[0072] In this embodiment, the secondary display driver 20 integrates... Figure 2 The upper display driver 21 and lower display driver 22 shown correspond to the driving requirements of the upper and lower display areas, respectively. The upper display driver 21 is electrically connected to multiple pixels in the upper display area and is responsible for controlling the display output of the upper display area; the lower display driver 22 is electrically connected to multiple pixels in the lower display area and is used to control the display output of the lower display area. This allows the upper and lower display areas to be controlled independently of the main display area, achieving more flexible display functions and lower power consumption management. For example, the upper display area can be used to display static information such as time or notifications, while the lower display area can display other auxiliary content, such as system status, shortcut buttons, or a typing keyboard. Through the corresponding upper display driver 21 and lower display driver 22 for each display area, the upper and lower display areas can adjust parameters such as brightness and refresh rate according to their respective display content, further optimizing display effects and power consumption.

[0073] Furthermore, in some feasible embodiments, reference is made to Figure 2The upper display driver 21 includes a ninth thin-film transistor T9, a tenth thin-film transistor T10, an eleventh thin-film transistor T11, a twelfth thin-film transistor T12, a fifth capacitor C5, and a sixth capacitor C6. The gate terminal and the first pass terminal of the ninth thin-film transistor T9 are electrically connected to the gate terminal of the previous stage above the current upper gate terminal. The second pass terminal of the ninth thin-film transistor T9 is electrically connected to the first terminal of the fifth capacitor C5 and the gate terminal of the tenth thin-film transistor T10, respectively. The first pass terminal of the tenth thin-film transistor T10 is electrically connected to the clock signal terminal of the current stage. The gate terminal of a thin-film transistor T11, the first path terminal of the eleventh thin-film transistor T11, the second terminal of the fifth capacitor C5, and the second path terminal of the tenth thin-film transistor T10 are all electrically connected to the current upper gate terminal. The second path terminal of the eleventh thin-film transistor T11 is electrically connected to the gate terminals of the sixth capacitor C6 and the twelfth thin-film transistor T12, respectively. The first path terminal of the twelfth thin-film transistor T12 is electrically connected to the upper clock terminal of the next stage after the current upper clock signal terminal. The second path terminal of the twelfth thin-film transistor T12 is electrically connected to the upper gate terminal of the next stage after the current upper gate terminal.

[0074] In this embodiment, when the target display area is the upper display area in the sub-display area, the driver chip provides signal STV1 to the current level clock signal terminal in the upper display area and the next level clock signal terminal after the current level clock signal terminal.

[0075] It should be noted that the clock signal input to the clock signal terminal of the current stage can be used Figure 2 The signal clk1 shown represents the clock signal of the current stage; the clock signal of the next stage can be represented by the clock signal of the previous stage. Figure 2 The signal clk2 shown represents the gate drive signal connected to the previous stage's upper gate terminal; the signal can be represented by the previous stage's upper gate terminal. Figure 2 The signal gn-1 shown represents the current upper gate terminal; it can be represented by... Figure 2 The signal gn shown represents the gate drive signal connected to the next stage upper gate terminal of the current upper gate terminal. Figure 2 The signal gn+1 shown represents this. Furthermore, the preset sub-drive timing can include upper drive timing and lower drive timing.

[0076] For example, refer to Figures 2 to 3 The driver chip configured in this application responds to the target display area being the upper display area in the sub-display area, and the enable signal STV1 is emitted from... Figure 3 The low potential is switched to a high potential; next, signal STV1 turns on signals clk1 and clk2 to the high potential, that is, signals clk1 and clk2 are respectively connected to... Figure 3 The corresponding signal waveform is shown.

[0077] In a specific example, refer to Figures 2 to 3 The display in the upper display area is driven by signal STV1, which sequentially activates signals clk1 and clk2, performing a 2clk loop. Typically, the upper display area has around 60 pixel rows, meaning the 2clk loop repeats 60 / 2 = 30 times. In other words, the upper drive timing is a 2clk loop drive, where signals clk1 and clk2 work sequentially, driving two pixel rows per loop. For example, for the 60 pixel rows in the upper display area, signal clk1 drives the first pixel row in each loop (i.e., the pixel row electrically connected to signal gn), and signal clk2 drives the second pixel row in each loop (i.e., the pixel row electrically connected to signal gn+1).

[0078] Furthermore, in some other feasible embodiments, the lower display driver 22 includes a thirteenth thin-film transistor T13, a fourteenth thin-film transistor T14, a fifteenth thin-film transistor T15, a sixteenth thin-film transistor T16, a seventh capacitor C7, and an eighth capacitor C8; the gate terminal and the first pass terminal of the thirteenth thin-film transistor T13 are both electrically connected to the previous stage's lower gate terminal; the second pass terminal of the thirteenth thin-film transistor T13 is electrically connected to the first terminal of the seventh capacitor C7 and the gate terminal of the fourteenth thin-film transistor T14, respectively; and the first pass terminal of the fourteenth thin-film transistor T14 is electrically connected to the previous stage's lower gate terminal. The clock signal terminal is electrically connected; the gate terminal of the fifteenth thin-film transistor T15, the first path terminal of the fifteenth thin-film transistor T15, the second terminal of the seventh capacitor C7, and the second path terminal of the fourteenth thin-film transistor T14 are all electrically connected to the current lower gate terminal. The second path terminal of the fifteenth thin-film transistor T15 is electrically connected to the gate terminal of the eighth capacitor C8 and the sixteenth thin-film transistor T16, respectively. The first path terminal of the sixteenth thin-film transistor T16 is electrically connected to the next stage lower clock terminal after the current lower clock signal terminal. The second path terminal of the sixteenth thin-film transistor T16 is electrically connected to the next stage lower gate terminal after the current lower gate terminal.

[0079] In this embodiment, when the target display area is the lower display area in the sub-display area, the driver chip provides signal STV3 to the current level lower clock signal terminal in the lower display area and the next level lower clock signal terminal after the current level lower clock signal terminal.

[0080] It should be noted that the clock signal input to the current stage's clock signal terminal can be used Figure 2 The signal clk7 shown represents the following: the next stage's clock signal after the current stage can be represented by... Figure 2The signal clk8 shown represents the gate drive signal connected to the previous stage's lower gate terminal; the gate drive signal connected to the previous stage's lower gate terminal can be represented by... Figure 2 The signal Mn-1 shown represents the current lower gate terminal; it can be represented by... Figure 2 The signal Mn shown represents the gate drive signal connected to the next stage lower gate terminal after the current lower gate terminal. Figure 2 The signal Mn+1 shown is characterized.

[0081] For example, refer to Figures 2 to 3 The driver chip configured in this application responds to the target display area being the lower display area in the sub-display area, and enables the signal STV3 from... Figure 3 The low potential is switched to a high potential; next, signal STV3 enables signals clk7 and clk8 to be at a high potential, that is, signals clk1 and clk2 are respectively connected to... Figure 3 The corresponding signal waveform is shown.

[0082] In a specific example, refer to Figures 2 to 3 The display in the lower display area is driven by signal STV3, which sequentially activates signals clk7 and clk8, performing a 2-clk loop. Typically, the lower display area has around 60 pixel rows, meaning the 2-clk loop repeats 30 times (60 / 2 = 30 times). In other words, the lower drive timing is a 2-clk loop, where signals clk7 and clk8 work sequentially, driving two pixel rows per loop. For example, for the 60 pixel rows in the lower display area, signal clk7 drives the first pixel row in each loop (the row electrically connected to signal Mn), and signal clk8 drives the second pixel row in each loop (the row electrically connected to signal Mn+1).

[0083] In yet another embodiment, reference is made to... Figure 4 , Figure 4 This is a schematic diagram of the upper display area involved in the embodiment of this application. When the target display area is the upper display area, signal STV1 switches from a low potential to a high potential, sequentially activating signals clk1 and clk2, and then proceeds according to... Figure 4 The driving timing corresponding to signals clk1 and clk2 shown in the figure cycles 2clk repeatedly to ensure the normal display of the upper display area; while signals STV2 and STV3 are both kept at low potential, so that the main display area and the lower display area are not displayed.

[0084] In another embodiment, reference Figure 5 , Figure 5 This is a schematic diagram of the main display area involved in the embodiment of this application. When the target display area is the main display area, signal STV2 switches from a low potential to a high potential, sequentially activating signals clk3, clk4, clk5, and clk6, and then proceeds according to... Figure 5 The driving timing corresponding to signals clk3 to clk4 shown is repeatedly cycled 4clk to ensure the normal display of the main display area; while signals STV1 and STV3 are both kept at low potential, so that the upper and lower display areas are not displayed.

[0085] In yet another embodiment, reference is made to... Figure 6 , Figure 6 This is a schematic diagram of the lower display area involved in the embodiment of this application. When the target display area is the lower display area, signal STV3 switches from low potential to high potential, sequentially activating signals clk7 and clk8, and then proceeds according to... Figure 6 The driving timing corresponding to signals clk7 to clk8, as shown, cycles repeatedly with 2clk cycles to ensure normal display in the lower display area; while signals STV1 and STV2 remain at low levels, preventing display in the upper and main display areas. Furthermore, when the user's display requirement is for typing, i.e., no image quality is required, the frequency of the driving timing corresponding to signals clk7 to clk8 can be reduced. This increases the duration of high-level operation for signals clk7 and clk8, thereby reducing the refresh rate of the lower display area and effectively lowering its power consumption.

[0086] In summary, the partitioned display circuit provided in this application enables partitioned display of the display panel to reduce display power consumption. This partitioned display circuit includes a display driving module, a main display area, and a sub-display area. The display driving module integrates a main display driver 10 and a sub-display driver 20. The main display driver 10 is electrically connected to multiple pixel rows in the main display area, while the sub-display driver 20 is electrically connected to multiple pixel rows in the sub-display area, thereby enabling independent partitioned driving of the main display area and the sub-display area. Specifically, the display driver module can accurately determine the target display area based on the user's partitioned display requirements. Next, it selectively enables the main display driver 10 or the sub-display driver 20 depending on the target display area. That is, when the target display area is the main display area, the main display driver 10 is enabled to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence. When the target display area is the sub-display area, the sub-display driver 20 is enabled to supply power to multiple pixel rows of the sub-display area according to a preset sub-drive timing sequence. This achieves power supply to the pixel rows within the display area specified by the partitioned display requirements, thereby effectively avoiding unnecessary power consumption waste under the overall backlight control of traditional display panels and significantly reducing the display power consumption of the display panel.

[0087] Furthermore, based on the first embodiment of the partitioned display circuit of this application, a second embodiment of the driving method of this application is proposed.

[0088] The driving method of this application is applied to the partition display circuit of any of the above claims. The driving method of this application is executed by a terminal device that drives and controls the partition display circuit. The driving method of this application includes the following implementation steps S10 to S20.

[0089] Step S10: Obtain the user's partition display requirements through the display driver module, and determine the target display area based on the partition display requirements.

[0090] In this embodiment, after the display driver module receives the user's partition display request based on the preset human-computer interaction interface, it obtains the partition display scene corresponding to the partition display request. When the partition display scene is a main display area usage scene, the target display area is determined to be the main display area; when the partition display scene is a secondary display area usage scene, the target display area is determined to be the secondary display area.

[0091] Step S20: Based on the target display area being the main display area, enable the main display driver in the display driver module to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence; or, based on the target display area being the secondary display area, enable the secondary display driver in the display driver module to supply power to multiple pixel rows of the secondary display area according to a preset secondary drive timing sequence.

[0092] In this embodiment, based on the response of the driver chip in the display driver module to the target display area being the main display area, the display driving state of the main display driver is switched from the off state to the driving state, and a stable and reliable power supply is provided to multiple pixel rows in the main display area for normal display according to a preset main driving timing sequence. Simultaneously, in response to the target display area being the main display area, the driver chip also enables the secondary display driver to remain in the off state, thereby avoiding the secondary display area consuming additional power when displaying unnecessarily. Alternatively, based on the response of the driver chip in the display driver module to the target display area being the secondary display area, the display driving state of the secondary display driver is switched from the off state to the driving state, and a stable and reliable power supply is provided to multiple pixel rows in the secondary display area for normal display according to a preset secondary driving timing sequence. Simultaneously, in response to the target display area being the secondary display area, the driver chip also enables the main display driver to remain in the off state, thereby avoiding the main display area consuming additional power when displaying unnecessarily.

[0093] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the partitioned display circuit described in any of the above claims.

[0094] In addition, this application also provides a display device. Please refer to... Figure 7, Figure 7 This is a schematic diagram of the display device involved in the embodiments of this application. Specifically, the display device in the embodiments of this application may be a device that runs a local driving method.

[0095] like Figure 7 As shown, the display device in this embodiment may include: the partitioned display circuit described above; or, a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0096] The memory 1005 is disposed on the main body of the display device. The memory 1005 stores a program that performs corresponding operations when executed by the processor 1001. The memory 1005 is also used to store parameters used by the display device. The memory 1005 can be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0097] Those skilled in the art will understand that Figure 7 The display device structure shown does not constitute a limitation on the display device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0098] like Figure 7 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a driver for a display device.

[0099] exist Figure 7 In the display device shown, the processor 1001 can be used to call the display device driver stored in the memory 1005 and execute the steps of the driving method as described above.

[0100] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0101] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0102] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0103] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A zone display circuit, characterized in that, The partitioned display circuit includes a display driving module, a main display area, and a secondary display area. The display driving module includes a driving chip, a main display driver, and a secondary display driver. The main display driver is electrically connected to multiple pixel rows of the main display area, and the secondary display driver is electrically connected to multiple pixel rows of the secondary display area. The main display driver includes a first main driving module and a second main driving module. The display driver module is configured to acquire the user's partition display requirements, determine the target display area based on the partition display requirements, and enable the main display driver to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence for the main display area based on the target display area; or, enable the secondary display driver to supply power to multiple pixel rows of the secondary display area according to a preset secondary drive timing sequence for the secondary display area based on the target display area. The display driver module is further configured to determine the target display area as the primary display area when the partitioned display scenario is a primary display area usage scenario, and to determine the target display area as the secondary display area when the partitioned display scenario is a secondary display area usage scenario; wherein... The main display area is used for displaying game screens, movie screens, and novel browsing screens, while the secondary display area is used for displaying time interfaces, phone interfaces, and text message interfaces. The display driving module is further configured to, based on the response of the driving chip when the target display area is the main display area, simultaneously provide signal STV2 in the second main driving module to the next-next ... The first pixel row is the pixel row electrically connected to the current main gate terminal, the second pixel row is the pixel row electrically connected to the next main gate terminal after the current main gate terminal, the third pixel row is the pixel row electrically connected to the next two main gate terminals after the current main gate terminal, and the fourth pixel row is the pixel row electrically connected to the next three main gate terminals after the current main gate terminal.

2. The partitioned display circuit as described in claim 1, characterized in that, The first main drive module includes a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, a fourth thin-film transistor, a first capacitor, and a second capacitor; The gate terminal of the first thin-film transistor and the first pass terminal of the first thin-film transistor are both electrically connected to the two main gate terminals before the current main gate terminal. The second pass terminal of the first thin-film transistor is electrically connected to the first terminal of the first capacitor and the gate terminal of the second thin-film transistor, respectively. The first pass terminal of the second thin-film transistor is electrically connected to the current main clock signal terminal. The gate terminal of the third thin-film transistor, the first path terminal of the third thin-film transistor, the second terminal of the first capacitor, and the second path terminal of the second thin-film transistor are all electrically connected to the current main gate terminal. The second path terminal of the third thin-film transistor is electrically connected to the gate terminal of the second capacitor and the fourth thin-film transistor, respectively. The first path terminal of the fourth thin-film transistor is electrically connected to the main clock terminals of the two stages following the current main clock signal terminal. The second path terminal of the fourth thin-film transistor is electrically connected to the main gate terminals of the two stages following the current main gate terminal.

3. The partitioned display circuit as described in claim 2, characterized in that, The second main drive module includes a fifth thin-film transistor, a sixth thin-film transistor, a seventh thin-film transistor, an eighth thin-film transistor, a third capacitor, and a fourth capacitor; The gate terminal of the fifth thin-film transistor and the first pass terminal of the fifth thin-film transistor are both electrically connected to the previous stage main gate terminal of the current main gate terminal. The second pass terminal of the fifth thin-film transistor is electrically connected to the first terminal of the third capacitor and the gate terminal of the sixth thin-film transistor, respectively. The first pass terminal of the sixth thin-film transistor is electrically connected to the next stage main clock signal terminal of the current stage main clock signal terminal. The gate terminal of the seventh thin-film transistor, the first path terminal of the seventh thin-film transistor, the second terminal of the third capacitor, and the second path terminal of the sixth thin-film transistor are all electrically connected to the next stage main gate terminal of the current main gate terminal. The second path terminal of the seventh thin-film transistor is electrically connected to the gate terminals of the fourth capacitor and the eighth thin-film transistor, respectively. The first path terminal of the eighth thin-film transistor is electrically connected to the next three stages of the main clock signal terminal of the current stage. The second path terminal of the eighth thin-film transistor is electrically connected to the next three stages of the main gate terminal of the current main gate terminal.

4. The partition display circuit as described in claim 1, characterized in that, The secondary display area includes an upper display area and a lower display area, with the upper display area and the lower display area respectively located on both sides of the main display area; wherein... The number of pixel rows in the upper display area is the same as the number of pixel rows in the lower display area, and the total number of pixel rows between the number of pixel rows in the upper display area and the number of pixel rows in the lower display area is less than the number of pixel rows in the main display area.

5. The partition display circuit as described in claim 4, characterized in that, The sub-display driver includes an upper display driver corresponding to the upper display area and a lower display driver corresponding to the lower display area; The upper display driver is electrically connected to multiple pixel rows in the upper display area, and the lower display driver is electrically connected to multiple pixel rows in the lower display area.

6. The partitioned display circuit as described in claim 5, characterized in that, The upper display driving device includes a ninth thin-film transistor, a tenth thin-film transistor, an eleventh thin-film transistor, a twelfth thin-film transistor, a fifth capacitor, and a sixth capacitor; The gate terminal of the ninth thin film transistor and the first pass terminal of the ninth thin film transistor are both electrically connected to the previous stage upper gate terminal of the current upper gate terminal. The second pass terminal of the ninth thin film transistor is electrically connected to the first terminal of the fifth capacitor and the gate terminal of the tenth thin film transistor, respectively. The first pass terminal of the tenth thin film transistor is electrically connected to the current stage upper clock signal terminal. The gate terminal of the eleventh thin-film transistor, the first path terminal of the eleventh thin-film transistor, the second terminal of the fifth capacitor, and the second path terminal of the tenth thin-film transistor are all electrically connected to the current upper gate terminal. The second path terminal of the eleventh thin-film transistor is electrically connected to the gate terminals of the sixth capacitor and the twelfth thin-film transistor, respectively. The first path terminal of the twelfth thin-film transistor is electrically connected to the next stage upper clock terminal after the current stage upper clock signal terminal. The second path terminal of the twelfth thin-film transistor is electrically connected to the next stage upper gate terminal after the current upper gate terminal.

7. The partitioned display circuit as described in claim 5, characterized in that, The lower display driver includes a thirteenth thin-film transistor, a fourteenth thin-film transistor, a fifteenth thin-film transistor, a sixteenth thin-film transistor, a seventh capacitor, and an eighth capacitor; The gate terminal of the thirteenth thin-film transistor and the first path terminal of the thirteenth thin-film transistor are both electrically connected to the previous stage lower gate terminal of the current lower gate terminal. The second path terminal of the thirteenth thin-film transistor is electrically connected to the first terminal of the seventh capacitor and the gate terminal of the fourteenth thin-film transistor, respectively. The first path terminal of the fourteenth thin-film transistor is electrically connected to the current stage lower clock signal terminal. The gate terminal of the fifteenth thin-film transistor, the first path terminal of the fifteenth thin-film transistor, the second terminal of the seventh capacitor, and the second path terminal of the fourteenth thin-film transistor are all electrically connected to the current lower gate terminal. The second path terminal of the fifteenth thin-film transistor is electrically connected to the gate terminals of the eighth capacitor and the sixteenth thin-film transistor, respectively. The first path terminal of the sixteenth thin-film transistor is electrically connected to the next stage lower clock terminal after the current stage lower clock signal terminal. The second path terminal of the sixteenth thin-film transistor is electrically connected to the next stage lower gate terminal after the current lower gate terminal.

8. A driving method for a partitioned display circuit, characterized in that, The driving method for the partitioned display circuit is applied to the partitioned display circuit, and the driving method includes: The display driver module obtains the user's partition display requirements and determines the target display area based on these requirements. Based on the target display area being the main display area, the main display driver in the display driver module is enabled to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence; or, based on the target display area being the secondary display area, the secondary display driver in the display driver module is enabled to supply power to multiple pixel rows of the secondary display area according to a preset secondary drive timing sequence. The step of determining the target display area based on the partition display requirements includes: When the partitioned display scenario is a primary display area usage scenario, the target display area is determined to be the primary display area; when the partitioned display scenario is a secondary display area usage scenario, the target display area is determined to be the secondary display area. The main display area is used for displaying game screens, movie screens, and novel browsing screens, while the secondary display area is used for displaying time interfaces, phone interfaces, and text message interfaces. The display driver module includes a driver chip, and the main display driver includes a first main driver module and a second main driver module. The step of enabling the main display driver in the display driver module to supply power to multiple pixel rows of the main display area according to a preset main drive timing sequence based on the target display area as the main display area includes: Based on the response of the driver chip when the target display area is the main display area, when the first main driver module provides signal STV2 to the current level main clock signal terminal and the two subsequent level main clock terminals of the current level main clock signal terminal, simultaneously, the second main driver module provides signal STV2 to the next level main clock signal terminal and the three subsequent level main clock terminals of the current level main clock signal terminal. Based on signal STV2, signals clk3, clk4, clk5, and clk6 are sequentially activated to drive the first pixel row, second pixel row, third pixel row, and fourth pixel row in each cycle, respectively; wherein, The first pixel row is the pixel row electrically connected to the current main gate terminal, the second pixel row is the pixel row electrically connected to the next main gate terminal after the current main gate terminal, the third pixel row is the pixel row electrically connected to the next two main gate terminals after the current main gate terminal, and the fourth pixel row is the pixel row electrically connected to the next three main gate terminals after the current main gate terminal.

9. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a partitioned display circuit as described in any one of claims 1 to 7.

10. A display device, characterized in that, The display device includes the display panel as described in claim 9; or... The display device includes a processor, a memory, and a driver stored in the memory that can be executed by the processor, wherein when the driver is executed by the processor, it implements the steps of the driving method as described in claim 8.

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