Semiconductor device and operating method thereof, and storage system

Abstract

The application provides a semiconductor device, an operating method thereof and a storage system. The semiconductor device comprises a mode detection circuit and a charge pump. The mode detection circuit corresponds to a first state mode and a second state mode of the semiconductor device, and provides a first mode enable signal and a second mode enable signal respectively. The charge pump is in a first action mode for generating a first output current and a second action mode for generating a second output current according to the first mode enable signal and the second mode enable signal. The first state mode comprises a same word line access state for successively accessing storage units on a same word line. By the semiconductor device, the charge pump can be adjusted to the first action mode for standby, and only needs to be adjusted to the second action mode for work when the word line is switched. The high voltage required by the word line can be maintained, and the working current and refresh frequency of the charge pump can be greatly reduced, so that the reading power consumption can be greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a semiconductor device, an operating method thereof, and a storage system. BACKGROUND

[0002] Flash memory has data storage function, and includes NAND type flash memory and NOR type flash memory. However, both NAND type flash memory and NOR type flash memory face the problem of power consumption. The problem of power consumption is an important index of flash memory, especially for mobile devices powered by batteries. SUMMARY

[0003] Therefore, the present application provides a semiconductor device, an operating method thereof, and a storage system, which can reduce read power consumption of the semiconductor device and greatly reduce refresh frequency.

[0004] To solve the above problem, the present application provides a semiconductor device, which includes:

[0005] a mode detection circuit, configured to provide a first mode enable signal and a second mode enable signal corresponding to a first state mode and a second state mode of the semiconductor device, respectively; and

[0006] a charge pump, configured to be in a first action mode of generating a first output current and a second action mode of generating a second output current according to the first mode enable signal and the second mode enable signal, respectively.

[0007] The first state mode includes a same word line access state of successively accessing storage units on a same word line.

[0008] In some embodiments, the second state mode includes a different word line access state of successively accessing storage units on different word lines.

[0009] In some embodiments, the first state mode further includes a standby state, and the first action mode includes a standby mode.

[0010] In some embodiments, the second state mode includes a working state of receiving a read instruction, the successive access is a successive read operation, and the second action mode includes a working mode.

[0011] In some embodiments, the first output current is less than the second output current.

[0012] In some embodiments, the first operation mode generates a first output voltage, the second operation mode generates a second output voltage, and the first output voltage is equal to the second output voltage.

[0013] In some embodiments, the mode detection circuit includes a first mode charge pump detection circuit, a second mode charge pump detection circuit, and a switch selection circuit, the first mode charge pump detection circuit is configured to output the first mode enable signal, the second mode charge pump detection circuit is configured to output the second mode enable signal, and the switch selection circuit is configured to select one of the first mode enable signal and the second mode enable signal to output to the charge pump according to the first state mode and the second state mode, respectively.

[0014] In some embodiments, the charge pump includes a first sub-charge pump and a second sub-charge pump, the first sub-charge pump is configured to be in the first operation mode according to the first mode enable signal, and the second sub-charge pump is configured to be in the second operation mode according to the second mode enable signal.

[0015] In some embodiments, the charge pump operates at a first refresh frequency and a second refresh frequency in the first operation mode and the second operation mode, respectively, and the first refresh frequency is lower than the second refresh frequency.

[0016] The present application also provides an operation method of a semiconductor device, the operation method includes:

[0017] providing a first mode enable signal and a second mode enable signal according to a first state mode and a second state mode of the semiconductor device, respectively,

[0018] setting a same word line access state of a storage unit accessed in sequence on a same word line as the first state mode; and

[0019] causing a charge pump to be in a first operation mode generating a first output current and a second operation mode generating a second output current according to the first mode enable signal and the second mode enable signal, respectively.

[0020] In some embodiments, the operation method further includes setting a different word line access state of a storage unit accessed in sequence on different word lines as the second state mode.

[0021] In some embodiments, the operation method further includes setting a standby state of the semiconductor device as the first state mode and setting the charge pump in the first operation mode.

[0022] In some embodiments, the method further comprises setting a working state of receiving the read instruction to the second state mode, and the subsequent access is a subsequent read operation.

[0023] In some embodiments, the method further comprises causing the first operation mode to generate a first output voltage and causing the second operation mode to generate a second output voltage, and the first output voltage is equal to the second output voltage.

[0024] In some embodiments, the step of providing the first mode enable signal and the second mode enable signal comprises outputting the first mode enable signal and the second mode enable signal to the charge pump through a first mode charge pump detection circuit and a second mode charge pump detection circuit, respectively, according to the first state mode and the second state mode.

[0025] In some embodiments, the step of causing the charge pump to be in the first operation mode to generate a first output current and the second operation mode to generate a second output current, respectively, comprises receiving the first mode enable signal by a first sub-charge pump to generate the first output current, and receiving the second mode enable signal by a second sub-charge pump to generate the second output current.

[0026] The application also provides a memory system, comprising the semiconductor device described above, and a controller configured to control the semiconductor device.

[0027] The semiconductor device, the method for operating the semiconductor device, and the memory system provided by the application can reduce read power consumption by setting the semiconductor device to comprise a mode detection circuit and a charge pump, wherein the mode detection circuit is configured to provide a first mode enable signal and a second mode enable signal corresponding to a first state mode and a second state mode of the semiconductor device, respectively; the charge pump is configured to be in a first operation mode to generate a first output current and a second operation mode to generate a second output current according to the first mode enable signal and the second mode enable signal, respectively; and the first state mode comprises a same word line access state of sequentially accessing storage units on a same word line. When the region accessed by internal operation does not need to switch word lines, the charge pump can be adjusted to the first operation mode in standby mode, and only needs to be adjusted to the second operation mode in working mode when the word line needs to be switched, so as to maintain the high voltage required by the word line, while the working current of the charge pump and the refresh frequency can be greatly reduced, thereby greatly reducing read power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description only are some embodiments of the present application, and all other drawings obtained by those skilled in the art based on the drawings without creative effort are within the protection scope of the present application.

[0029] Figure 1 A schematic block diagram of an exemplary memory device disclosed in embodiments of the present application.

[0030] Figure 2A A circuit schematic diagram of a memory array in the memory device disclosed in embodiments of the present application. Figure 1

[0031] A circuit schematic diagram of another memory array in the memory device disclosed in embodiments of the present application. Figure 2B Figure 1 A schematic block diagram of a voltage generator in the memory device disclosed in embodiments of the present application.

[0032] Figure 3 Figure 1 Another schematic block diagram of a voltage generator in the memory device disclosed in embodiments of the present application.

[0033] Figure 4A Yet another schematic block diagram of a voltage generator in the memory device disclosed in embodiments of the present application. Figure 1

[0034] A schematic block diagram of a voltage generator in the memory device disclosed in embodiments of the present application. Figure 4B Figure 1 An exemplary step diagram in a method of operating a semiconductor device disclosed in embodiments of the present application.

[0035] Figure 5 A schematic system block diagram of a memory system provided in embodiments of the present application.

[0036] DETAILED DESCRIPTION Figure 6 The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.

[0038] ​​​In the description of the present application, it needs to be understood that the terms "upper", "lower", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0039] The present application can repeatedly refer to numbers and / or letters in different embodiments. Such repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or arrangements discussed.

[0040] First, please refer to Figure 1 , Figure 1 The figure shows a schematic block diagram of a semiconductor device provided by some embodiments of the present application, taking memory 400 as an example of a semiconductor device. The memory 400 includes a storage array 420 and other peripheral circuits (not numbered). As shown in Figure 1 , the peripheral circuits can at least include other circuits such as page buffer / sense amplifier 411, column decoder / bit line driver 412, row decoder / word line driver 413, voltage generator 414, control logic unit 415, register 416, interface 417, and data bus 418, etc. outside the storage array 420. It should be understood that in some examples, the peripheral circuits can also include other circuits not shown in Figure 1 .

[0041] Figure 1 The block diagram shown can be applied to, for example, two-dimensional or three-dimensional flash type (NAND / NOR flash) or memory type (DRAM) memory, with the difference being the different storage array 420. Therefore, the storage array 420 can be, for example, a storage array of two-dimensional or three-dimensional flash type (NAND / NOR flash) or memory type (DRAM) memory, and the memory can include DRAM, PCRAM, FeRAM, MRAM, etc. The storage array 420 has at least one large-size block-shaped storage platform (GB), and the storage platform includes at least a plurality of array-arranged storage cells (see Figure 2A and Figure 2B ). The plurality of storage cells can be arranged appropriately according to two-dimensional or three-dimensional structures, and can be arranged appropriately according to the use of NAND, NOR, DRAM architecture.

[0042] The page buffer / sense amplifier 411 can be configured to read data from and program (also referred to as "write") data to the memory array 420 in accordance with control signals from the control logic 415. Specifically, in one example, the page buffer / sense amplifier 411 can store data to be programmed to a page of memory cells in the memory array 420. In another example, the page buffer / sense amplifier 411 can also perform a sensing operation on a low power signal from a bit line BL representing data stored in a memory cell and amplify the small voltage swing of the low power signal to an identifiable logic level in a read operation. The page buffer / sense amplifier 411 can be arranged and combined differently depending on the type and design of the memory array 420 and the bit line BL, for example, a plurality of page buffer / sense amplifiers 411 can be used to support a plurality of bit line groups.

[0043] The column decoder / bit line driver 412 can be configured to be controlled by the control logic 415 and to select one or more columns of memory cells by applying a bit line voltage generated from the voltage generator 414. The column decoder / bit line driver 412 can also be arranged and combined differently depending on the type and design of the memory array 420, for example, a plurality of column decoder / bit line drivers 412 can be used.

[0044] The row decoder / word line driver 413 can be configured to be controlled by the control logic 415 to select different memory cells in the memory array 420. The row decoder / word line driver 413 can also be configured to drive a word line WL using a word line voltage generated from the voltage generator 414. The row decoder / word line driver 413 can also be arranged and combined differently depending on the type and design of the memory array 420, for example, a plurality of row decoder / word line drivers 413 can be used.

[0045] The voltage generator 414, which can include a charge pump, can be configured to be controlled by the control logic 415 and to generate the word line voltage and the bit line voltage to be supplied to the memory array 420 and the required current. It is understood that the charge pump can be located anywhere in the semiconductor device, and thus, the so-called voltage generator herein broadly includes the charge pump and its associated circuitry anywhere.

[0046] The control logic 415 can be coupled to and control the operation of each of the circuits in the peripheral circuit 410, such as the page buffer / sense amplifier 411, the column decoder / bit line driver 412, the row decoder / word line driver 413, and the voltage generator 414, as described above.

[0047] The register 416 can be coupled to the control logic unit 415 and can include at least a status register, a command register, and an address register to store status information, command operation codes (OP codes), and addresses for controlling the operation of each of the above-mentioned circuits.

[0048] The interface 417 can be coupled to the control logic unit 415 and act as a control buffer to perform the operation of buffering control commands received from the controller of the memory system 400 and relaying the commands to the control logic unit 415, and the operation of buffering status information received from the control logic unit 415 and relaying the commands to the external controller (not shown). Further, the interface 417 can also be coupled to the column decoder / bit line driver 412 via the data bus 418 and act as a data I / O (Input / Output) interface and data buffer to perform the operation of buffering data and relaying the data to the memory array 420, and the operation of relaying or buffering data from the memory array 420. Figure 1

[0049] In some embodiments, the memory array 420 can be a NOR-type or NAND-type flash memory architecture, or a memory architecture of, for example, 1T1C or 1TXC type (T represents a transistor, C represents a capacitor storage unit, and X represents a number). In addition, the memory array can be a 2D architecture or a 3D architecture, and thus the embodiments of the present application are merely examples.

[0050] Figure 2A A circuit schematic diagram of a NOR-type memory array is shown. In the figure, only a memory array combined with three rows of word lines and eight columns of bit lines is illustrated, i.e., the word lines include Word1 / Word2 / Word3, and the bit lines include Bit0 / Bit1 / Bit2 / Bit3 / Bit4 / Bit5 / Bit6 / Bit7. However, it can be understood that the number of word lines and bit lines can be determined according to the storage capacity of the memory, one bit line represents one bit, and in the figure, Bit0-Bit7 represent eight bits, i.e., one byte, one word line represents one memory page, and if one memory page has a capacity of 1 KB, there are 1024 bytes, i.e., 1024 x 8 bit lines. If the capacity is 1 MB, 1024 word lines can be configured to form 1024 memory pages, i.e., 1024 KB. Therefore, the number of word lines and bit lines in the figure is merely an example. Figure 2A The configuration of the memory cells in the figure is merely an example.

[0051] ​In a read operation, after data enters through the interface 417, the command information and the address information are sent to the control logic unit 415, which decodes the address information through the row decoder 413 and the column decoder 412 to locate the word line and the bit line corresponding to the address, such as the word line Wordl and the bit line BitO~Bit7, and then reads the data of the byte in sequence through the sense amplifier 411. It can be understood that different read addresses can be present on the same word line but on different bit lines of different bytes.

[0052] Figure 2B A circuit schematic diagram of a NAND type memory array is shown. In the figure, only an 8-row word line and 8-column bit line combination is shown, i.e., the word lines include Wordl~Word8, and the bit lines include Bitl~Bit8. However, it can be understood that the number of word lines and bit lines can be determined according to the storage capacity of the memory, as in the NOR type flash memory. One bit line represents one bit, Bitl~Bit8 in the figure represent 8 bits, i.e., one byte. One word line represents one memory page. If one memory page has a capacity of 1 KB, there are 1024 bytes, i.e., 1024x8 bit lines. If the capacity is 1 MB, 1024 word lines can be configured to form 1024 memory pages, i.e., 1024 KB. Therefore, Figure 2B The configuration of the memory cell is only an example.

[0053] Other memory array architectures can also be 2D or 3D memory architectures, which are known to those skilled in the art and are not described here. The application range of the present application is not limited to the 2D NOR type flash memory architecture. Therefore, in the following embodiments, only the 2D NOR type flash memory architecture is described by way of example, but the present application is not limited to the 2D NOR type flash memory architecture.

[0054] Power consumption is an important indicator of various memories, especially for Nor flash, and even more so for mobile devices powered by batteries. Read operation is the most common operation of Nor flash, so how to reduce read power consumption is a problem that needs to be solved urgently.

[0055] Nor flash, the control logic unit 415 will generate a voltage higher than the power supply by the charge pump in the voltage generator 414 in standby mode, and by the clock signal with a certain frequency and switch and capacitor, the charge pump output operating voltage is periodically refreshed. When the user input read instruction, the standby mode of the charge pump is closed, the working mode of the charge pump starts to work, and generates and maintains a voltage as in standby mode. The working current of the charge pump in working mode is much larger than that of the charge pump in standby mode, and the refresh frequency of the charge pump in working mode is much faster than that of the charge pump in standby mode, which greatly increases the power consumption of the circuit. The working mode here can be understood as representing when a certain operation is performed, such as reading or programming, and the working current represents the output current under a certain operation, especially the maximum output current.

[0056] In order to solve the problem of power consumption, Figure 3 A schematic block diagram of a semiconductor device according to an embodiment of the present application is disclosed, and the voltage generator 414 described above is taken as an example of the semiconductor device.

[0057] As Figure 3 As shown, the semiconductor device according to an embodiment of the present application comprises: a mode detection circuit 10 and a charge pump 20; wherein the mode detection circuit 10 is used to correspond to a first state mode M1 and a second state mode M2 of the semiconductor device, and to provide a first mode enable signal E1 and a second mode enable signal E2, respectively; and the charge pump 20 is used to generate a first output current I1 in a first action mode and a second output current I2 in a second action mode according to the first mode enable signal E1 and the second mode enable signal E2, respectively; and wherein the first state mode M1 comprises a same word line access state of successively accessing storage units 42a on the same word line.

[0058] In some embodiments, the second state mode M2 comprises a different word line access state of successively accessing storage units 42a on different word lines.

[0059] In some embodiments, the first state mode M1 further comprises a standby state, and the first action mode comprises a standby mode.

[0060] In some embodiments, the second state mode M2 comprises a working state of receiving a read instruction, and the successive access is a successive read operation, and the second action mode comprises a working mode.

[0061] In some embodiments, the first output current I1 is less than the second output current I2. The first output current refers to the maximum current output value in the first mode of operation, and does not represent a constant current value. Those skilled in the art can understand that the main purpose of this is to express that the charge pump has a smaller maximum output current and power consumption in the first mode of operation compared to the second mode of operation.

[0062] In some embodiments, the charge pump 20 operates at a first refresh frequency and a second refresh frequency according to the first mode enable signal El and the second mode enable signal E2, respectively, and the first refresh frequency is lower than the second refresh frequency.

[0063] Specifically, the mode detection circuit 10 can receive the state of the memory 400 provided by the state logic (not shown) in the control logic unit 415 or the register 416, and detect the state of the memory 400 at present, for example, if it is in the standby state waiting for a command, the mode detection circuit 10 sets it to the first state mode Ml and outputs the first mode enable signal El. It can be understood that in some embodiments, the mode detection circuit 10 can receive the first state mode signal Ml without detection.

[0064] If the control logic unit 415 receives a read command, the state of the memory 400 provided by the state logic (not shown) in the control logic unit 415 or the register 416 will be in the read state, and the voltage setting instruction will be sent to the voltage generator 414, and the address information will be sent to the row decoder 413 and the column decoder 412. At this time, the mode detection circuit 10 receives the voltage setting instruction or the read state provided by the state logic, and sets the state mode of the memory / semiconductor device to the second state mode M2 and outputs the second mode enable signal E2. It can be understood that in some embodiments, the mode detection circuit 10 can receive the second state mode signal M2 without detection.

[0065] Further, if the control logic unit 415 can further judge the word line position of the address after receiving the first address information of the read command, and judge whether the word line position of the next address information changes when receiving the next address information, if not, a first flag information is given, and the mode detection circuit 10 receives the first flag information and outputs the first mode enable signal El. If the word line changes, a second flag information is given, and the mode detection circuit 10 receives and detects the second flag information and outputs the second mode enable signal E2.

[0066] The foregoing embodiment is exemplary of the detection of whether there is a change in the word line by the control logic unit 415, but this detection can also be performed by the mode detection circuit 10, which is not limited herein. Thus, in some embodiments, the mode detection circuit 10 can be configured to receive the first or second state mode signal Ml / M2 and be in the first mode detection circuit or the second mode detection circuit. In some embodiments, the mode detection circuit 10 can be configured to detect the first or second state mode signal Ml / M2 and be in the first mode detection circuit or the second mode detection circuit.

[0067] In addition, in some embodiments, the mode detection circuit 10 is further configured to detect the output voltage and output current of the charge pump 20 to determine whether the output of the charge pump 20 meets the requirements. For example, the mode detection circuit 10 can include an output voltage feedback circuit and a comparator (not shown) to detect whether the output of the charge pump 20 meets the requirements and further output an enable signal.

[0068] Subsequently, the charge pump 20 receives the first mode enable signal El or the second mode enable signal E2 from the mode detection circuit 10 and operates in the first operation mode to generate the first output current I1 and the second operation mode to generate the second output current I2 according to the first mode enable signal El and the second mode enable signal E2, respectively. It can be understood that the voltage generator 414 sends the output to the word line decoded by the row decoder 413 through the charge pump 20, so that the row decoder 413 can output the required output voltage and current from the selected word line.

[0069] Specifically, when there is a change in the word line, i.e., the access to a different word line, which belongs to the second state mode M2 of the general operation, the charge pump 20 receives the second mode enable signal E2 and operates in the second operation mode to provide a larger current to charge the new word line. If there is no change in the word line, i.e., the access to the same word line, which is set as the first state mode Ml of the special operation, the charge pump 20 receives the first mode enable signal El and operates in the first operation mode to provide a smaller output current to reduce power consumption. At this time, since the same word line has been powered, a smaller current can meet the needs.

[0070] In some embodiments, the charge pump 20 can also operate in the first operation mode to generate the first output voltage V1 and the second operation mode to generate the second output voltage V2 according to the first mode enable signal El and the second mode enable signal E2, respectively, and the first output voltage V1 is equal to the second output voltage V2. It can be understood that the charge pump 20 is controlled by the mode detection circuit 10, and the actual voltage waveform provided is sawtooth-shaped, and the voltage values herein refer to the equal voltage target values.

[0071] Furthermore, it is understandable that the charge pump 20 generates a first operating mode and a second operating mode with different currents according to the first mode enable signal E1 and the second mode enable signal E2, respectively. In some embodiments, it can operate at a first refresh frequency F1 and a second refresh frequency F2 corresponding to the first operating mode and the second operating mode, respectively, and the first refresh frequency F1 is lower than the second refresh frequency F2. It is understandable that the load supplied by the charge pump 20, such as a storage array, may experience leakage current. Therefore, after a period of time, in order to maintain the required output voltage and output current, the output voltage of the charge pump needs to be boosted to meet the required output current. The refresh frequency is the frequency at which the output voltage of the charge pump is periodically boosted through a clock signal with a specific frequency, as well as switching switches and capacitors, so that the output voltage reaches the target value.

[0072] With the semiconductor device shown in the embodiments of this application, since Nor flash reads data in the memory array sequentially, when the area accessed by the internal read operation does not require switching word lines, the charge pump can be adjusted to the first operating mode to supply the demand with a lower current. It is only adjusted to the working mode when switching word lines is required to maintain the high voltage required by the word lines. At the same time, the operating current of the charge pump (that is, the output current sent to the word lines during specific operations such as read or standby) and the refresh frequency can also be greatly reduced, thereby greatly reducing read power consumption.

[0073] Furthermore, although the above uses a read operation as an example, it is understood that the operation described in this application can be other than a read operation, such as a programming operation, as long as it involves the switching of bias voltages for different word lines.

[0074] The structure of the semiconductor device according to embodiments of this application is further described below. Figure 4A As shown, Figure 4A for Figure 3 Another schematic block diagram of the voltage generator in the memory shown. Figure 4A The semiconductor device 400 or voltage generator 414a shown includes a mode detection circuit 10a and a charge pump 20; wherein the mode detection circuit 10a further includes a first mode charge pump detection circuit 11, a second mode charge pump detection circuit 12, and a switching selection circuit 13.

[0075] Specifically, in some embodiments, the first mode charge pump detection circuit 11 can be as follows: Figure 4A The circuit, as shown, starts operating by receiving state logic (not shown) from control logic unit 415, standby state provided by register 416, or the first flag information, and uses these signals as the first state mode signal M1. The second mode charge pump detection circuit 12 can be as follows... Figure 4AThe second flag information is received from the state logic (not shown) in the control logic unit 415 or the register 416, and the signals are used as the second state mode M2 to start operation.

[0076] In some embodiments, the first mode charge pump detection circuit 11 and the second mode charge pump detection circuit 12 send out the first mode enable signal El and the second mode enable signal E2, respectively; and can send out a control signal (not shown) to the switch selection circuit 13 to control the closing or opening of the switches SI and S2. In other embodiments, the switch selection circuit 13 can accept control from the control logic unit 415 to turn on or off the selection switches SI or S2, respectively.

[0077] In the standby mode as the first state mode Ml, the switch SI is closed, the switch S2 is opened, the first mode charge pump detection circuit 11 is in normal operation, and the second mode charge pump detection circuit 12 is turned off. The first mode charge pump detection circuit 11 controls the charge pump through the first enable signal El, so that the charge pump 20 generates and maintains a voltage Vl higher than the power supply voltage, and generates the first current II.

[0078] When a read instruction is input, the second state mode M2 is entered, the switch S2 is closed, the switch SI is opened, the second mode charge pump detection circuit is in normal operation, and the first mode charge pump detection circuit 11 is turned off. The second mode charge pump detection circuit 12 controls the charge pump 20 through the second enable signal E2, so that the charge pump 20 generates and maintains a voltage V2 higher than the power supply voltage, and generates the second current I2 for driving the word line corresponding to the read instruction address input.

[0079] When each read operation ends, it is determined whether the read address of the next pen needs to switch the word line. If the word line needs to be switched, the second flag signal is generated, the second state mode M2 is entered, the switch S2 is closed, the switch S1 is disconnected, the second mode charge pump detection circuit 12 normally works, the second enable signal E2 controls the charge pump, so that the charge pump 20 can quickly respond to the output voltage of the charge pump 20 to meet the requirements of the next pen read data to the word line voltage; if the word line does not need to be switched, the first flag signal is generated, the first state mode M1 is entered, the switch S1 is closed, the switch S2 is disconnected, the first mode charge pump detection circuit 11 normally works, the first enable signal E1 is sent to control the charge pump, so that the charge pump 20 provides sufficient driving force to the same word line corresponding to the input read instruction address. Through such a setting, since the first mode charge pump detection circuit 11 can work at a lower response speed than the second mode charge pump detection circuit 12, the number of times of starting the charge pump 20 is also relatively small, so that the working current of the entire detection circuit can be reduced, and the refresh frequency of the charge pump can be greatly reduced by working in the first action mode at the appropriate time, thereby greatly reducing the read power consumption.

[0080] In some embodiments, the first output voltage V1 is equal to the second output voltage V2. It can be understood that the charge pump 20 is controlled by the first or second mode charge pump detection circuit 11 / 12, and the actual voltage waveform provided is sawtooth-shaped, and here the voltage values are equal refers to the voltage target values are equal.

[0081] Figure 4B Further shown is another semiconductor device according to embodiments of the present application. As shown in Figure 4B , Figure 4B for Figure 3 another schematic block diagram of a voltage generator in the memory shown. Figure 4B The semiconductor device or the voltage generator 414b shown includes the mode detection circuit 10 and the charge pump 20b; wherein the charge pump 20b further includes the first sub-charge pump 21 and the second sub-charge pump 22.

[0082] Comparing Figure 3 and 4B , it can be understood that the mode detection circuit 10 of Figure 4B is the same as the mode detection circuit 10 of Figure 3 , which will not be repeated here. It can be understood that the mode detection circuit 10 will generate the first mode enable signal E1 and the second mode enable signal E2 according to the various states described above.

[0083] It can be understood that in some embodiments, the mode detection circuit 10 of Figure 4B may also be the same as the mode detection circuit 10 of Figure 4AThe mode detection circuit 10a is the same as the mode detection circuit 10a, and thus is not repeated here. Under this arrangement, the first mode detection circuit 11 connects the first sub charge pump 21 through the switch S1, and the second mode detection circuit 12 connects the second sub charge pump 22 through the switch S2.

[0084] In Figure 4B the charge pump 20b includes a first sub charge pump 21 and a second sub charge pump 22, which are respectively in a first action mode for generating a first output voltage V1 and a first output current I1, and a second action mode for generating a second output voltage V2 and a second output current I2, according to the first mode enable signal E1 and the second mode enable signal E2. The first sub charge pump 21 can be regarded as a charge pump in standby mode, and the second sub charge pump 22 can be regarded as a charge pump in general working mode. In this way, in standby mode or in a special reading mode in which the word line does not change, the first sub charge pump 21 in standby mode can be used to provide bias voltage and current to the word line; and in general reading mode or when the word line changes, the second sub charge pump 22 in working mode can be used to provide bias voltage and current to the word line.

[0085] Since the Nor flash reads data in the storage array sequentially, when the internal read operation accesses an area that does not need to switch the word line, the second sub charge pump 22 in working mode can be turned off, and the first sub charge pump 21 in standby mode can be turned on to maintain the high voltage required by the word line, thereby greatly reducing the reading power consumption.

[0086] With respect to the semiconductor device exemplified by the memory above, the embodiment of the present application also provides an operation method of a semiconductor device, as shown in Figure 5 , and Figure 5 an exemplary step diagram of an operation method of a semiconductor device according to an embodiment of the present application is shown.

[0087] The operation method of the semiconductor device according to the embodiment of the present application includes: providing a first mode enable signal E1 and a second mode enable signal E2 corresponding to a first state mode M1 and a second state mode M2 of the semiconductor device 400, respectively (S11); setting a same word line access state of a storage unit 42a successively accessing a same word line as the first state mode M1 (S12); and making a charge pump 20 in a first action mode for generating a first output current I1 and a second action mode for generating a second output current I2, according to the first mode enable signal E1 and the second mode enable signal E2, respectively (S13).

[0088] In some embodiments, the method further comprises setting an odd wordline access state of a subsequent access to memory cells 42a on different wordlines to the second state mode M2.

[0089] In some embodiments, the method further comprises setting a standby state of the semiconductor device to the first state mode M1 and setting the charge pump to the first action mode.

[0090] In some embodiments, the method further comprises setting an active state of receiving a read instruction to the second state mode M2 and the subsequent access is a subsequent read operation.

[0091] In some embodiments, the first output current I1 is less than the second output current I2.

[0092] In some embodiments, the method further comprises causing the first action mode to generate a first output voltage V1 and the second action mode to generate a second output voltage V2, and the first output voltage V1 is equal to the second output voltage V2.

[0093] In some embodiments, the step of providing a first mode enable signal E1 and a second mode enable signal E2 comprises outputting the first mode enable signal E1 and the second mode enable signal E2 from a first mode charge pump detection circuit 11 and a second mode charge pump detection circuit 12, respectively, according to the first state mode M1 and the second state mode M2, and selecting one of the first mode enable signal E1 and the second mode enable signal E2 to output to the charge pump 20 by a switch selection circuit 13.

[0094] In some embodiments, the step of causing the charge pump to be in a first action mode for generating a first output current and a second action mode for generating a second output current, respectively, comprises receiving the first mode enable signal E1 by a first sub-charge pump 21 to generate the first output current I1 and receiving the second mode enable signal E2 by a second sub-charge pump 22 to generate the second output current I2.

[0095] By the method of operating the semiconductor device shown in the embodiments of the present application, since Nor flash is to read data in a memory array sequentially, when an internal read operation accesses an area that does not need to switch wordlines, the charge pump can be adjusted to a standby mode, and only when wordlines need to be switched, the charge pump is adjusted to a general active mode to maintain the high voltage and current required by the wordlines. By such an arrangement, the refresh frequency of the charge pump can be greatly reduced, thereby greatly reducing read power consumption.

[0096] Finally, please refer to Figure 6 ,Figure 6 A schematic block diagram of an exemplary electronic system 100 having a memory system 110 according to some embodiments disclosed herein is shown. The electronic system 100 can be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0097] As Figure 6 shown, the electronic system 100 can include at least a memory system 110 having a controller 111 and one or more memories 112, and a host 120. The memory 112 can be the semiconductor device 400 as previously described, and the host 120 can be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device, and in particular, the host 120 can be configured to send data to and receive data from the memory 112.

[0098] According to some embodiments, the controller 111 is coupled to the memory 112 and the host 120, and is configured to control the memory 112, and further, the controller 111 can manage data stored in the memory 112 and communicate with the host 120. In some embodiments, the controller 111 is designed to operate in a low duty cycle environment, which can be a universal serial bus (USB) flash drive or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0099] The controller 111 can communicate with an external device (e.g., the host 120) according to a specific communication protocol. For example, the controller 111 can communicate with the external device through at least one of various interface protocols, such as a Universal Serial Bus (USB) protocol, a Multi Media Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a Peripheral Component Interconnect Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Device Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a FireWire protocol, and the like.

[0100] Some embodiments of the present application provide a memory system having the same advantageous effects as the memory 112 or the semiconductor device 400 described above.

[0101] The semiconductor device and the operating method thereof and the memory system provided by the present application can be set to include a mode detection circuit and a charge pump, and the mode detection circuit is used to provide a first mode enable signal and a second mode enable signal corresponding to a first state mode and a second state mode of the semiconductor device, respectively; the charge pump is used to be in a first operation mode of generating a first output current and a second operation mode of generating a second output current according to the first mode enable signal and the second mode enable signal, respectively; and the first state mode includes a same word line access state of successively accessing storage units on the same word line. When the region accessed by the internal operation does not need to switch the word line, the charge pump can be adjusted to the standby mode, and only when the word line needs to be switched, the charge pump is adjusted to the working mode to maintain the high voltage required by the word line, while the working current of the charge pump and the refresh frequency can also be greatly reduced, so that the read power consumption can be greatly reduced.

[0102] In summary, although the present application has been disclosed with preferred embodiments as above, the preferred embodiments are not intended to limit the present application, and those skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is defined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a mode detection circuit to provide a first mode enable signal and a second mode enable signal corresponding to a first state mode and a second state mode of the semiconductor device, respectively; and a charge pump to be in a first operation mode to generate a first output current and a second operation mode to generate a second output current according to the first mode enable signal and the second mode enable signal, respectively; wherein the first state mode comprises a same word line access state of successively accessing storage cells on a same word line, the second state mode comprises a different word line access state of successively accessing storage cells on different word lines, and the first output current is less than the second output current.

2. The semiconductor device of claim 1, wherein, The first state mode further comprises a standby state, and the first operation mode comprises a standby mode.

3. The semiconductor device of claim 1, wherein, The second state mode comprises a working state of receiving a read instruction, and the successive access is a successive read operation, and the second operation mode comprises a working mode.

4. The semiconductor device of claim 1, wherein, The first operation mode generates a first output voltage, and the second operation mode generates a second output voltage, and the first output voltage is equal to the second output voltage.

5. The semiconductor device of claim 1, wherein, The charge pump operates at a first refresh frequency and a second refresh frequency in the first operation mode and the second operation mode, respectively, and the first refresh frequency is lower than the second refresh frequency.

6. The semiconductor device of claim 1, wherein, The mode detection circuit comprises a first mode charge pump detection circuit and a second mode charge pump detection circuit, and a switch selection circuit; the first mode charge pump detection circuit is to output the first mode enable signal; the second mode charge pump detection circuit is to output the second mode enable signal; the switch selection circuit is to select one of the first mode enable signal and the second mode enable signal to output to the charge pump according to the first state mode and the second state mode, respectively.

7. The semiconductor device of claim 1, wherein, The charge pump comprises a first sub-charge pump and a second sub-charge pump; the first sub-charge pump is in the first operation mode according to the first mode enable signal; the second sub-charge pump is in the second operation mode according to the second mode enable signal.

8. A method of operating a semiconductor device, characterized by, The operation method comprises: providing a first mode enable signal and a second mode enable signal corresponding to a first state mode and a second state mode of the semiconductor device, respectively, setting a same word line access state of successively accessing storage cells on a same word line as the first state mode, and setting a different word line access state of successively accessing storage cells on different word lines as the second state mode; and causing a charge pump to be in a first operation mode to generate a first output current and a second operation mode to generate a second output current according to the first mode enable signal and the second mode enable signal, respectively, and the first output current is less than the second output current.

9. The method of operating a semiconductor device of claim 8, wherein, The operation method further comprises setting a standby state of the semiconductor device as the first state mode, and setting the charge pump in the first operation mode.

10. The method of operating a semiconductor device of claim 8, wherein, The method further includes setting a working state of receiving the read instruction to the second state mode, and the subsequent access is a subsequent read operation.

11. The method of operating a semiconductor device of claim 8, wherein, The method further includes causing the first operation mode to output a first output voltage and causing the second operation mode to output a second output voltage, and the first output voltage is equal to the second output voltage.

12. The method of operating a semiconductor device of claim 8, wherein, The step of providing the first mode enable signal and the second mode enable signal includes outputting the first mode enable signal and the second mode enable signal to the charge pump through a first mode charge pump detection circuit and a second mode charge pump detection circuit, respectively, according to the first state mode and the second state mode.

13. The method of operating a semiconductor device of claim 8, wherein, The step of causing the charge pump to be in the first operation mode to output a first output current and the second operation mode to output a second output current, respectively, includes receiving the first mode enable signal by a first sub-charge pump to output the first output current and receiving the second mode enable signal by a second sub-charge pump to output the second output current.

14. A memory system, comprising: The method further includes: The semiconductor device of any one of claims 1 to 7; and a controller configured to control the semiconductor device.

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