Memory circuit and operating method thereof

Abstract

The embodiment of the invention discloses a memory circuit and an operating method thereof. The memory circuit includes a first memory cell array and a second memory cell array configured to store data. The second memory cell array is configured as a first logic circuit or a second logic circuit in response to the first set of control signals. The first logic circuit is configured to perform a first logic function on the first set of data signals based on the second set of control signals. The second logic circuit is configured to perform a second logic function on the first set of data signals based on the second set of control signals. The second logic function is different from the first logic function. The first set of data signals is a portion of data stored in the first memory cell array. The first memory cell array and the second memory cell array are embedded in the same memory cell array.

Description

Technical Field

[0001] Embodiments of the present application relate to memory circuits and methods of operating the same. Background Art

[0002] Recent developments in the field of artificial intelligence have generated a variety of products and / or applications, including but not limited to speech recognition, image processing, machine learning, natural language processing, etc. Such products and / or applications usually use neural networks to process large amounts of data for learning, training, cognitive computing, etc. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first memory cell array, configured to store data; and a second memory cell array, coupled to the first memory cell array and configured as a first logic circuit or a second logic circuit in response to a first group of control signals, the first logic circuit being configured to perform a first logic function on a first group of data signals based on the second group of control signals, and the second logic circuit being configured to perform a second logic function on the first group of data signals based on the second group of control signals, the second logic function being different from the first logic function, the first group of data signals being part of the data stored in the first memory cell array, wherein the first memory cell array and the second memory cell array are embedded in the same memory cell array.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first memory cell array, configured to store data; a second memory cell array, reconfigured as a first logic circuit or a second logic circuit in response to a first set of control signals, the first logic circuit being configured to perform a first logic function on a first set of data signals based on a second set of control signals, and the second logic circuit being configured to perform a second logic function on the first set of data signals based on the second set of control signals, the second logic function being different from the first logic function, the first set of data signals being part of the data stored in the first memory cell array; and a controller, configured to generate a first set of control signals, and configured to control the first memory cell array and the second memory cell array, wherein the first memory cell array and the second memory cell array are embedded in the same memory cell array.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, the method comprising: writing a first group of control signals into a first group of transistors, thereby setting a logic function of a first memory cell array in the memory circuit, the first group of transistors being part of the memory cell array; performing a write operation of the first memory cell array, performing the write operation comprising: turning on an access transistor group in the first memory cell array, thereby writing a first data signal and a second data signal into corresponding storage nodes of a storage transistor group, the storage transistor group being part of the first memory cell array, the storage transistor group being coupled to a first node, an output node and the first group of transistors; performing a read operation of the memory circuit, the read operation of the memory circuit comprising: setting the first node to a first power supply voltage; pulling the output node to the first power supply voltage or a reference power supply voltage, thereby setting an output signal; setting the first signal at the first node to a reference power supply voltage; and outputting an output signal, the output signal corresponding to a logic function between the first data signal and the second data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of a memory device according to some embodiments.

[0008] Figure 2 is a block diagram of a memory cell array according to some embodiments.

[0009] Figure 3A is a circuit diagram of a memory cell according to some embodiments.

[0010] Figure 3B is a circuit diagram of a memory cell array according to some embodiments.

[0011] Figure 4A is a circuit diagram of a memory circuit according to some embodiments.

[0012] Figure 4B is a table of OR gates that may be used as memory circuits according to some embodiments.

[0013] Figure 4C is a circuit diagram of an OR gate according to some embodiments.

[0014] Figure 4D is a table of AND gates that may be used as memory circuits according to some embodiments.

[0015] Figure 4E is a circuit diagram of an AND gate according to some embodiments.

[0016] Figure 5 According to some embodiments Figure 4A A graph of the corresponding waveforms of the memory circuit.

[0017] Figure 6 is a circuit diagram of a memory circuit according to some embodiments.

[0018] Fig. 7A is a circuit diagram of a memory circuit according to some embodiments.

[0019] Figure 7B is a table of OR gates that may be used as memory circuits according to some embodiments.

[0020] Figure 7C is a circuit diagram of an OR gate according to some embodiments.

[0021] Fig.7D is a table of AND gates that may be used as memory circuits according to some embodiments.

[0022] Fig. 7E is a circuit diagram of an AND gate according to some embodiments.

[0023] Fig. 8A is a circuit diagram of a memory circuit according to some embodiments.

[0024] Figure 8B is a table of OR gates that may be used as memory circuits according to some embodiments.

[0025] Figure 8C is a circuit diagram of an OR gate according to some embodiments.

[0026] Fig.8D is a table of AND gates that may be used as memory circuits according to some embodiments.

[0027] Fig. 8E is a circuit diagram of an AND gate according to some embodiments.

[0028] Fig.8F is a timing diagram of waveforms according to some embodiments.

[0029] Fig. 9A is a circuit diagram of a memory circuit according to some embodiments.

[0030] Fig. 9B is a table of AND gates that may be used as memory circuits according to some embodiments.

[0031] Fig. 10A is a circuit diagram of a memory circuit according to some embodiments.

[0032] Fig. 10B is a table of NOR gates that may be used as memory circuits according to some embodiments.

[0033] Fig. 10C is a circuit diagram of a NOR gate according to some embodiments.

[0034] Fig. 10D is a table of NAND gates that may be used as memory circuits according to some embodiments.

[0035] Fig. 10E is a circuit diagram of a NAND gate according to some embodiments.

[0036] Fig.11A is a circuit diagram of an XOR (exclusive OR) logic gate according to some embodiments.

[0037] Fig. 11B is a circuit diagram of an XOR logic gate according to some embodiments.

[0038] Fig. 12A is a circuit diagram of a full adder circuit according to some embodiments.

[0039] Fig. 12B is a flow chart of a method of operating a circuit according to some embodiments.

[0040] Fig.13 is a circuit diagram of an n-bit adder circuit according to some embodiments.

[0041] Fig.14 is a circuit diagram of a memory circuit according to some embodiments.

[0042] Fig.15 is a cross-sectional view of an integrated circuit 1500 according to some embodiments.

[0043] Fig.16 is a cross-sectional view of an integrated circuit 1600 according to some embodiments.

[0044] Fig.17A is a schematic diagram of a memory device according to some embodiments.

[0045] Fig. 17B is a schematic diagram of a neural network according to some embodiments.

[0046] Fig. 17C is a schematic diagram of an integrated circuit (IC) device according to some embodiments.

[0047] Figure 18A-18B is a flow chart of a method of operating a circuit according to some embodiments. DETAILED DESCRIPTION

[0048] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0049] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0050] According to some embodiments, a memory circuit includes a first memory cell array and a second memory cell array.

[0051] In some embodiments, the first memory cell array is configured to store data.

[0052] In some embodiments, the second memory cell array is configured as a first logic circuit or a second logic circuit in response to the first set of control signals. In some embodiments, the second memory cell array can be reconfigured as a first logic circuit or a second logic circuit in response to the first set of control signals.

[0053] In some embodiments, the first logic circuit is configured to perform a first logic function on the first set of data signals based on the second set of control signals.

[0054] In some embodiments, the second logic circuit is configured to perform a second logic function on the first set of data signals based on a second set of control signals.

[0055] In some embodiments, the second logic function is different from the first logic function.

[0056] In some embodiments, the first set of data signals is part of the data stored in the first memory cell array.

[0057] In some embodiments, the memory circuit further comprises a controller. In some embodiments, the controller is configured to generate a first set of control signals.

[0058] In some embodiments, the controller is further configured to control the first memory cell array and the second memory cell array. In some embodiments, the first memory cell array and the second memory cell array are embedded in the same memory cell array.

[0059] In some embodiments, including the first memory cell array and the second memory cell array in the same memory cell array can reduce the distance between the first memory cell array and the second memory cell array compared to other methods, thereby reducing data loss or degradation between the first memory cell array and the second memory cell array.

[0060] In some embodiments, the first memory cell array and the second memory cell array are contained within the same memory cell array so that the distance between the first memory cell array and the second memory cell array can be reduced, thereby reducing processing time compared to other methods.

[0061] Figure 1 1 is a block diagram of a memory device 100 according to some embodiments. The memory device is an integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuits for other functions outside of the memory device.

[0062] The memory device 100 includes a memory circuit 110, a memory controller 120, and a memory logic circuit 130. The memory circuit 110 includes a memory array 102 and an adder circuit 104.

[0063] Memory controller 120 (also referred to as “controller 120 ”) includes a read word line (RWL) driver 122 a , a write word line (WWL) driver 122 b , a read bit line (RBL) driver 124 a , a write bit line (WBL) driver 124 b , and a control circuit 126 (also referred to as “controller 126 ”).

[0064] In some embodiments, one or more elements of memory controller 120 are included in memory circuit 110 , and / or one or more elements of memory circuit 110 (except memory array 102 ) are included in memory controller 120 .

[0065] In some embodiments, the memory circuit 110 is a memory macro. The macro has a reusable configuration and can be used for IC devices of various types or designs. In some embodiments, the macro is understood to be similar to the architectural hierarchy of modular programming, where a subroutine / routine is called by a main program (or other subprograms) to perform a given computing function. In this case, the IC device uses the macro to perform one or more given functions. Therefore, in this case, the IC device is similar to the main program and the macro is similar to the subroutine / routine in terms of the architectural hierarchy. In some embodiments, the macro is a soft macro. In some embodiments, the macro is a hard macro. In some embodiments, the macro is a soft macro described digitally in register transfer level (RTL) code. In some embodiments, synthesis, placement, and routing have not yet been performed on the macro, so the soft macro can be synthesized, placed, and routed for various process nodes. In some embodiments, the macro is a hard macro digitally described in a binary file format (e.g., a graphic database system II (GDSII) stream format), wherein the binary file format represents the plane geometry of one or more layout diagrams of the macro in a hierarchical form, text labels, other information, etc. In some embodiments, the macro is synthesized, placed, and routed so that the hard macro is specific to a specific process node.

[0066] A memory macro is a macro that includes addressable memory cells to allow data to be written to or read from the memory cells. In some embodiments, the memory macro also includes circuits configured to provide access to the memory cells and / or perform further functions associated with the memory cells. For example, in some embodiments, the memory circuit 110 includes memory cells MC as described herein, which form circuits configured to provide computing in memory (CIM) functions associated with the memory cells MC. The described macro configuration is an example. Other configurations are within the scope of various embodiments.

[0067] The memory circuit 110 includes a memory array 102 coupled to an adder circuit 104 .

[0068] In some embodiments, memory circuit 110 is a memory array. In some embodiments, memory array 102 is a first memory array and adder circuit 104 is a second memory array.

[0069] The memory array 102 includes memory cells MC arranged in a plurality of columns and rows.

[0070] The memory controller 120 is electrically coupled to the memory cell MC and configured to control operations of the memory cell MC, including but not limited to read operations, write operations, etc. The memory controller 120 is electrically coupled to the adder circuit 104 and configured to control operations of the adder circuit 104, including but not limited to initialization operations, read operations, write operations, etc.

[0071] The memory array 102 also includes a plurality of write word lines extending along the rows (eg, Figure 2 ), multiple read word lines extending along the row (such as Figure 2 ), a plurality of write bit lines extending along the columns of memory cells MC (such as Figure 2 ) and a plurality of read bit lines extending along the columns of memory cells MC (such as Figure 2 shown).

[0072] Each memory cell MC is electrically coupled to the memory controller 120 through at least one of a write word line, a read word line, a write bit line, and a read bit line.

[0073] In some example operations, the write or read word line is configured to transmit the address of the memory cell MC to be read, or to transmit the address of the memory cell MC to be written, etc. In at least one embodiment, a group of word lines is configured to perform read word lines and write word lines at the same time. In some embodiments, the write or read bit line is used to transmit data read or written by the memory cell MC indicated by the corresponding word line, etc. In some embodiments, the read bit line and / or the read inverted bit line (not shown) are configured to transmit the data read by the memory cell MC indicated by the corresponding read word line, and the write bit line and / or the write inverted bit line (not shown) are configured to transmit the data to be written to the memory cell MC indicated by the corresponding write word line, or the like.

[0074] Write word lines are generally referred to herein as WWLs, read word lines are generally referred to herein as RWLs, write bit lines are generally referred to herein as WBLs, and read bit lines are generally referred to herein as RBLs. Various numbers of write word lines, read word lines, write bit lines, and / or read bit lines in memory array 102 are within the scope of various embodiments.

[0075] Example memory types of the memory cells MC include, but are not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), spin transfer torque random access memory (STTRAM), floating gate metal oxide semiconductor field effect transistor (FGMOS), spin electronics, etc. In one or more example embodiments described herein, the memory cells MC include DRAM memory cells.

[0076] exist Figure 1In the example configuration, the memory cell MC is a single-port memory cell. In some embodiments, the port of the memory cell is represented by a set of word lines WL and bit lines BL / inverted bit lines BLB (referred to herein as WL / BL / BLB groups), which are configured to provide access to the memory cell in a read operation (i.e., read access) and / or a write operation (i.e., write access). A single-port memory cell has one WL / BL / BLB group, which is configured for read access and write access, but not at the same time. A multi-port memory cell has several WL / BL / BLB groups, each of which is configured for read access only, or for write access only, or for read access and write access. Reference Figure 1-17C An example of a single-port memory cell is described. Other configurations or other numbers of ports of memory cells in the memory array 102 are within the scope of the present disclosure. For example, in some embodiments, reference Figure 1-17C One or more of the single-port memory cells described may be replaced with a corresponding multi-port memory cell.

[0077] The memory array 102 includes a plurality of memory segments. In some embodiments, the memory segments include memory rows, memory columns, banks, etc. A memory row includes a plurality of memory cells coupled to the same read word line RWL or write word line WWL. A memory column (also referred to as a "memory string") includes a plurality of memory cells coupled to the same read bit line RBL and the same write bit line WBL. A bank includes a plurality of memory rows and / or a plurality of memory columns. In at least one embodiment, a bank includes a portion of the memory array 102 having a plurality of memory rows and a plurality of memory columns. In some embodiments, a memory segment includes a plurality of memory banks. Other ways of dividing the memory array 102 into a plurality of memory segments are within the scope of various embodiments.

[0078] Each memory cell MC includes an access portion (e.g., Figure 3A-3B The transistor M1 shown) and the storage portion (eg Figure 3A-3B In some embodiments, each memory cell MC is configured to store a piece of weight data (not shown), and is configured to perform a CIM operation on the weight data and a piece of received data (not marked).

[0079] Examples of CIM operations include, but are not limited to, mathematical operations, logical operations, combinations thereof, and the like. In at least one embodiment, the CIM operation includes one or more multiply-accumulate (MAC) operations. In some embodiments, the CIM operation includes multiplying one or more multi-bit weight values ​​with one or more multi-bit input data values. Other computing portions or circuits configured to perform CIM operations other than multiplication are within the scope of various embodiments. In some embodiments, the output data of the CIM operation is provided to the adder circuit 104 as input data (as data group D4), or is provided to the controller 120 as input data (as data group D1).

[0080] In one or more example embodiments described herein, the memory cell MC is a single bit memory cell, i.e., each memory cell is configured to store a bit of weight data, and calculates a corresponding bit of the output signal based on a CIM operation of the weight data bit and the received data bit. This is an example, and a multi-bit memory cell is within the scope of various embodiments, each memory cell is configured to store more than one bit of weight data, and performs a corresponding CIM operation on the corresponding multi-bit weight data.

[0081] In some embodiments, the memory cell MC is a unit memory cell configured to store one bit of data. In some embodiments, the unit memory cell is also referred to as a bit cell.

[0082] In some embodiments, the memory cell MC is configured to output the data group D1 to the controller 120. In some embodiments, the memory cell MC is configured to receive the data group D1 from the controller 120. In some embodiments, the data group D1 includes a weight group.

[0083] In some embodiments, the memory cell MC is configured to output the control signal group CS1 to the controller 120. In some embodiments, the memory cell MC is configured to receive the control signal group CS1 from the controller 120.

[0084] In some embodiments, the control signal group CS1 includes one or more of an RBL signal, a WBL signal, an RWL signal, or a WWL signal.

[0085] In some embodiments, the memory cell MC is configured to output the data group D4 to the adder circuit 104. In some embodiments, the data group D4 includes at least one of the data signal A or the data signal B (at least Figure 4A ).

[0086] Adder circuit 104 is coupled to memory array 102 and controller 120 .

[0087] Adder circuit 104 is configured to receive data group D4 from memory array 102 and control signal group CS2 from controller 120. In some embodiments, control signal group CS2 includes at least one of control signal C1, control signal C2, or control signal C3 (at least Figure 4A ).

[0088] The adder circuit 104 is configured to output the data group D2 to at least one of the memory array 102 or the controller 120. In some embodiments, the output data group D2 includes the data signal Vo (at least Figure 4A In some embodiments, the adder circuit 104 is configured to perform one or more logic operations / functions on the data group D4 based on the control signal group CS2, thereby generating the output data group D2. In some embodiments, the adder circuit 104 is configured to perform one or more non-volatile logic operations / functions on the data group D4 based on the control signal group CS2, thereby generating the output data group D2.

[0089] Examples of logical operations / functions include, but are not limited to, mathematical operations, logical operations, combinations thereof, etc. In some embodiments, examples of logical operations / functions include AND, NAND, OR, NOR, XOR, NOT, combinations thereof, etc. In some embodiments, examples of logical operations / functions include adders, full adders, half-bit adders, subtractors, multipliers, dividers, combinations thereof, etc.

[0090] In some embodiments, adder circuit 104 has an input coupled to a read bit line RBL or a write bit line WBL to receive output data set D4 from one or more memory cells MC.

[0091] In some embodiments, one or more instances of adder circuit 104 include AND, NAND, OR, NOR, XOR, NOT, etc. In some embodiments, one or more instances of adder circuit 104 include adders, full adders, half-bit adders, subtractors, multipliers, dividers, combinations thereof, etc.

[0092] In some embodiments, the output data group D2 or D4 is provided as input data to another memory macro (not shown) of the memory device 100. In one or more embodiments, the output data group D2 or D4 is output to an external circuit outside the memory device 100, such as a processor as described herein, through one or more I / O circuits (not shown) of the memory controller 120.

[0093] exist Figure 1In the example configuration of FIG. 1 , the controller 120 includes a read word line driver 122 a, a write word line driver 122 b, a read bit line driver 124 a, a write bit line driver 124 b, and a control circuit 126. In at least one embodiment, the controller 120 also includes one or more clock generators for providing clock signals to various components of the memory device 100, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations in the memory device 100.

[0094] The read word line driver 122a reads the word line RWL (eg Figure 2 1 (shown) is coupled to the memory array 102. The read word line driver 122a is configured to decode the row address of the memory cell MC selected to be accessed in the read operation. The read word line driver 122a is configured to provide a voltage to the selected read word line RWL corresponding to the decoded row address, and to provide a different voltage to other unselected read word lines RWL.

[0095] The write word line driver 122b uses the write word line WWL (eg Figure 2 1 ) is coupled to the memory array 102. The write word line driver 122 b is configured to decode the row address of the memory cell MC selected to be accessed in the write operation. The write word line driver 122 b is configured to provide a voltage to the selected write word line WWL corresponding to the decoded row address, and to provide a different voltage to other unselected write word lines WWL.

[0096] The read bit line driver 124a reads the bit line RBL (eg Figure 2 1 and 2. The read bit line driver 124a is coupled to the memory array 102. The read bit line driver 124a is configured to decode the column address of the memory cell MC selected to be accessed in the read operation. The read bit line driver 124a is configured to provide a voltage to the selected read bit line RBL corresponding to the decoded column address, and to provide a different voltage to other unselected read bit lines RBL.

[0097] The write bit line driver 124b receives the write bit line WBL (eg Figure 2 1) is coupled to the memory array 102. The write bit line driver 124b is configured to decode the column address of the memory cell MC selected to be accessed in the write operation. The write bit line driver 124b is configured to provide a voltage to the selected write bit line WBL corresponding to the decoded column address and provide a different voltage to other unselected write bit lines WBL.

[0098] The control circuit 126 is coupled to one or more of the memory cells MC, the adder circuit 104, the read word line driver 122a, the write word line driver 122b, the read bit line driver 124a, the write bit line driver 124b, or the logic circuit 130 to coordinate the operation of the circuits, drivers, and / or buffers in the overall operation of the memory device 100. For example, the control circuit 126 is configured to generate various control signals for controlling the operation of one or more of the memory cells MC, the adder circuit 104, the read word line driver 122a, the write word line driver 122b, the read bit line driver 124a, the write bit line driver 124b, or the logic circuit 130 or other circuits not shown.

[0099] In some embodiments, control circuit 126 is configured to output data group D1 to memory array 102. In some embodiments, control circuit 126 is configured to receive data group D1 from memory array 102.

[0100] In some embodiments, control circuit 126 is configured to output control signal group CS1 to memory array 102. In some embodiments, control circuit 126 is configured to receive control signal group CS1 from memory array 102.

[0101] In some embodiments, the control circuit 126 is configured to output the data set D2 to the adder circuit 104. In some embodiments, the control circuit 126 is configured to receive the data set D2 from the adder circuit 104.

[0102] In some embodiments, the control circuit 126 is configured to output the control signal group CS2 to the adder circuit 104. In some embodiments, the control circuit 126 is configured to receive the control signal group CS2 from the adder circuit 104.

[0103] In some embodiments, control circuit 126 is configured to output data group D3a to logic circuit 130. In some embodiments, control circuit 126 is configured to receive data group D3b from logic circuit 130. In some embodiments, logic circuit 130 may generate data group D3b using data group D3a.

[0104] In some embodiments, the control circuit 126 is configured to output the control signal group CS3a to the logic circuit 130. In some embodiments, the control circuit 126 is configured to receive the control signal group CS3b from the logic circuit 130. In some embodiments, the logic circuit 130 may generate the data group D3b using the control signal group CS3a.

[0105] Logic circuit 130 is coupled to controller 120. In some embodiments, logic circuit 130 is coupled to memory array 102 through controller 120.

[0106] The logic circuit 130 is configured to receive the data group D3 a from the controller 120 and receive the control signal group CS3 a from the controller 120 .

[0107] The logic circuit 130 is configured to output the data group D3 b and the control signal group CS3 b to the controller 120 .

[0108] In some embodiments, the logic circuit 130 includes at least one or more of a central processing unit (CPU), a graphics processing unit (GPU), or a combination thereof. In some embodiments, the logic circuit 130 is configured to perform one or more complex logic operations / functions on the data group D3a based on the control signal group CS3a, thereby generating the output data group D3b. In some embodiments, the one or more complex logic operations / functions performed by the logic circuit 130 include one or more operations not performed by the adder circuit 104.

[0109] Examples of complex logic operations / functions include, but are not limited to, mathematical operations, logic operations, combinations thereof, etc. In some embodiments, examples of complex logic operations / functions include multi-stage AND, NAND, OR, NOR, XOR, NOT, combinations thereof, etc. In some embodiments, examples of complex logic operations / functions include multi-stage adders, full adders, half-bit adders, subtractors, multipliers, dividers, combinations thereof, etc.

[0110] In some embodiments, the memory device 100 is configured to perform near-memory computing (NMC) or one or more CIM operations. In at least one embodiment, an NMC memory device or a CIM memory device (such as the memory device 100) is superior to other methods of moving data back and forth between the memory and the processor because such back-and-forth data movement can be avoided, which is a bottleneck for performance and energy efficiency. Examples of NVM or CIM applications include, but are not limited to, artificial intelligence, image recognition, neural networks for machine learning, etc. In some embodiments, the adder circuit 104 enables the execution of various computational operations implemented and embedded in a memory array (such as the memory circuit 110).

[0111] In some embodiments, by configuring memory circuit 110 to perform one or more CIM operations, the number of transistors in memory circuit 110 may be reduced, thereby reducing the size of memory circuit 110 compared to other approaches.

[0112] In some embodiments, including adder circuit 104 within a memory array (eg, memory circuit 110) may reduce distance DI1 between memory array 102 and adder circuit 104, thereby reducing data loss or degradation between memory array 102 and adder circuit 104 compared to other approaches.

[0113] In some embodiments, including adder circuit 104 in a memory array (e.g., memory circuit 110) reduces the data load on logic circuit 130 compared to other approaches, thereby allowing logic circuit 130 to focus on other operations and / or calculations not performed by adder circuit 104 and reducing processing time and power consumption.

[0114] Figure 2 is a block diagram of a memory cell array 200 according to some embodiments. In some embodiments, the memory cell array 200 is part of an integrated circuit.

[0115] The memory cell array 200 is Figure 1 In some embodiments, each memory cell in the memory cell array 202A is Figure 1 The present invention is an embodiment of the memory cell MC of the memory circuit 110, and thus similar detailed description is omitted.

[0116] The memory cell array 200 includes an array of memory cells 202[1,1], 202[1,2], ..., 202[2,2], ..., 202[M,N] having M rows and N columns (collectively referred to as "memory cell array 202A"), where N is a positive integer corresponding to the number of columns in the memory cell array 202A, and M is a positive integer corresponding to the number of rows in the memory cell array 202A. The cell rows in the memory cell array 202A are arranged along a first direction X. The cell columns in the memory cell array 202A are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. Each memory cell 202[1,1], 202[1,2], ..., 202[2,2], ..., 202[M,N] in the memory cell array 202A is configured to store a corresponding data bit.

[0117] The memory cell array 202A is a dynamic random access memory (DRAM) array including DRAM memory cells. In some embodiments, each memory cell in the memory cell array 202A corresponds to a Figure 3A-3B A 2-transistor (2T) memory cell is shown.

[0118] Other numbers of transistors in each memory cell in the memory cell array 202A are within the scope of the present disclosure. In some embodiments, each memory cell in the memory cell array 202A corresponds to a two-transistor (2T) memory cell with a 1-ferroelectric field effect transistor (FeFET). In some embodiments, each memory cell in the memory cell array 202A corresponds to a three-transistor (3T) memory cell. In some embodiments, each memory cell in the memory cell array 202A corresponds to a four-transistor (4T) memory cell.

[0119] Different types of memory cells in the memory cell array 202A are within the contemplated scope of the present disclosure. For example, in some embodiments, each memory cell in the memory cell array 202A is a static random access memory (SRAM). In some embodiments, each memory cell in the memory cell array 202A corresponds to a ferroelectric resistive random access memory (FeRAM) cell. In some embodiments, each memory cell in the memory cell array 202A corresponds to a magnetoresistive random access memory (MRAM) cell. In some embodiments, each memory cell in the memory cell array 202A corresponds to a resistive random access memory (RRAM) cell. Other configurations of the memory cell 202A array are also within the scope of the present disclosure.

[0120] The memory cell array 200 also includes M write word lines WWL[1], ... WWL[M] (collectively referred to as "write word lines WWL"). Each row 1, ..., M in the memory cell array 202A is associated with a corresponding write word line WWL[1], ..., WWL[M]. Each row of memory cells in the memory cell array 202A is coupled to a corresponding write word line WWL[1], ..., WWL[M]. For example, memory cells 202[1,1], 202[1,2], ..., 202[1,N] in row 1 are coupled to the write word line WWL[1]. Each write word line WWL extends along a first direction X.

[0121] The memory cell array 200 also includes M read word lines RWL[1], ... RWL[M] (collectively referred to as "read word lines RWL"). Each row 1, ..., M in the memory cell array 202A is associated with a corresponding read word line RWL[1], ..., RWL[M]. Each row of memory cells in the memory cell array 202A is coupled to a corresponding read word line RWL[1], ..., RWL[M]. For example, memory cells 202[1,1], 202[1,2], ..., 202[1,N] in row 1 are coupled to the read word line RWL[1]. Each read word line RWL extends along a first direction X.

[0122] The memory cell array 200 also includes N write bit lines WBL[1], ..., WBL[N] (collectively referred to as "write bit lines WBL"). Each column 1, ..., N in the memory cell array 202A is associated with a corresponding write bit line WBL[1], ..., WBL[N]. Each column of memory cells in the memory cell array 202A is coupled to a corresponding write bit line WBL[1], ..., WBL[N]. For example, the memory cells 202[1,1], 202[2,1], ..., 202[M,1] in column 1 are coupled to the write bit line WBL[1]. Each write bit line WBL extends in the second direction Y.

[0123] The memory cell array 200 also includes N read bit lines RBL[1], ..., RBL[N] (collectively referred to as "read bit lines RBL"). Each column 1, ..., N in the memory cell array 202A is associated with a corresponding read bit line RBL[1], ..., RBL[N]. Each column of memory cells in the memory cell array 202A is coupled to a corresponding read bit line RBL[1], ..., RBL[N]. For example, memory cells 202[1,1], 202[2,1], ..., 202[M,1] in column 1 are coupled to the read bit line RBL[1]. Each read bit line RBL extends in the second direction Y.

[0124] Other configurations of the memory cell array 200 are also within the scope of the present disclosure.Different configurations of at least the write bit lines WBL, write word lines WWL, read bit lines RBL, or read word lines RWL in the memory cell array 200 are within the contemplated scope of the present disclosure.

[0125] In some embodiments, memory cell array 200 includes additional write ports (write word lines WWL or write bit lines WBL) and / or read ports (read word lines RWL or read bit lines RBL). In addition, in some embodiments, memory cell array 202A includes multiple groups of memory cells of different types.

[0126] Figure 3A is a circuit diagram of a memory cell 300A according to some embodiments.

[0127] The memory cell 300A is schematically represented Figure 2 The present invention relates to an embodiment of a memory cell in the memory cell array 202A, and thus similar detailed description is omitted.

[0128] and Figure 3A-3B , Figure 4A-4E , Figure 5 , Figure 6 , Figure 7A-7E , Figure 8A-8E , Figure 9A-9B , Figures 10A-10E , Figure 11A-11B , Figure 12A-12B , Fig.13 , Fig.14 , Fig.15 , Fig.16 or Figure 17A-Figure 17C The same or similar components in one or more of the embodiments (as shown below) are given the same reference numerals, and thus their detailed description is omitted. Figure 3A-3B , Figure 4A-4E , Figure 5 , Figure 6 , Figure 7A-7E , Figure 8A-8E , Figure 9A-9B , Figures 10A-10E , Figure 11A-11B , Figure 12A-12B , Fig.13 , Fig.14 , Fig.15 , Fig.16 or Figure 17A-Figure 17C Some of the marking elements in Figure 3A-3B , Figure 4A-4E , Figure 5 , Figure 6 , Figure 7A-7E , Figure 8A-8E , Figure 9A-9B , Figures 10A-10E , Figure 11A-11B , Figure 12A-12B , Fig.13 , Fig.14 , Fig.15 , Fig.16 or Figure 17A-Figure 17C In some embodiments, Figure 3A-3B , Figure 4A-4E , Figure 5 , Figure 6 , Figure 7A-7E , Figure 8A-8E , Figure 9A-9B , Figures 10A-10E , Figure 11A-11B , Figure 12A-12B , Fig.13 , Fig.14 , Fig.15 , Fig.16 or Figure 17A-Figure 17C Including not in Figure 3A-3B , Figure 4A-4E , Figure 5 , Figure 6 , Figure 7A-7E , Figure 8A-8E , Figure 9A-9B , Figures 10A-10E , Figure 11A-11B , Figure 12A-12B , Fig.13 , Fig.14 , Fig.15 , Fig.16 or Figure 17A-Figure 17C Additional elements shown in .

[0129] The memory cell 300A can be used as Figure 2 One or more memory cells in the array of memory cells 202A.

[0130] The memory cell 300A includes a write transistor M1, a read transistor M2, a write word line WWL, a read word line RWL, a write bit line WBL, and a read bit line RBL.

[0131] The write word line WWL corresponds to the write word line among the write word lines WWL[1], ..., WWL[[M]], the read word line RWL corresponds to the read word line among the read word lines RWL[1], ..., RWL[M], the write bit line WBL corresponds to the write bit line among the write bit lines WBL[1], ..., WBL[[N], and the read bit line RBL corresponds to Figure 2 The read bit lines RBL[1], ..., RBL[N] in FIG. 1 , and thus similar detailed description is omitted.

[0132] The write transistor M1 includes a gate terminal coupled to the write word line WWL, a source / drain terminal coupled to the write bit line WBL, and a source / drain terminal coupled to at least a gate terminal of the read transistor M2 through a node ND1. In some embodiments, the node ND1 is a storage node of the read transistor M2. The write transistor M1 is configured to write data in the memory cell 300A. The write transistor M1 is enabled (e.g., turned on) or disabled (e.g., turned off) in response to a write bit line signal on the write bit line WBL.

[0133] The write transistor M1 is shown as a P-type metal oxide semiconductor (PMOS) transistor. In some embodiments, the write transistor M1 is an N-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the write transistor M1 is a transistor type other than a MOS transistor.

[0134] The read transistor M2 includes a source / drain terminal coupled to a read word line RWL, a source / drain terminal coupled to a read bit line RBL, and a gate terminal coupled to the source terminal of the write transistor M1.

[0135] The read transistor M2 is shown as a P-type metal oxide semiconductor (PMOS) transistor. In some embodiments, the read transistor M2 is an NMOS transistor. In some embodiments, the read transistor M2 is a transistor type other than a MOS transistor. In some embodiments, the read transistor M2 is referred to as a ferroelectric field effect transistor (FeFET) device because the read transistor M2 includes a ferroelectric region (at the gate terminal of the read transistor M2) within the gate terminal of the read transistor M2. Fig.141402-1414).

[0136] The write transistor M1 is configured to write data by controlling the voltage of the node ND1 or the gate of the read transistor M2, thereby turning on or off the read transistor M2. In some embodiments, if the write transistor M1 is enabled or turned on, the voltage of the write bit line WBL is configured to control the voltage of the node ND1 or the gate of the read transistor M2. Therefore, in some embodiments, the voltage of the write bit line WBL controls the on or off of the read transistor M2. In some embodiments, the voltage of the write bit line WBL corresponds to the data stored in the memory cell 300A.

[0137] The read transistor M2 is configured to read data stored in the memory cell 300A. In some embodiments, the read transistor M2 is configured to output data stored in the memory cell 300A based on whether the read transistor M2 is turned on or off.

[0138] Other transistor terminals of each of the transistors M1 or M2 of the present application are within the scope of the present disclosure. For example, references to the drain and source of the same transistor in the present disclosure may be changed to the source and drain of the same transistor. Thus, for write transistor M1, references to the drain and source of write transistor M1 may be changed to the source and drain of write transistor M1, respectively. Similarly, for read transistor M2, references to the drain and source of read transistor M2 may be changed to the source and drain of read transistor M2, respectively.

[0139] Other configurations or numbers of transistors in memory cell 300A are within the scope of the present disclosure.

[0140] Figure 3B is a circuit diagram of a memory cell array 300B according to some embodiments.

[0141] The memory cell array 300B is schematically shown Figure 2 The present invention relates to an embodiment of the memory cell array 200, and thus similar detailed description is omitted.

[0142] In some embodiments, the memory cell array 300B incorporates Figure 2 A portion of the memory cell array 200 and Figure 3A For example, in some embodiments, the memory cell array 300B will Figure 3A The memory cell 300A is connected to Figure 2 The two columns and five rows of the memory cell array 200 are grouped together, and thus similar detailed description is omitted.

[0143] Memory cell array 300B includes memory cell array 302A. In some embodiments, memory cell array 302A is similar to Figure 2 The memory cell array 202A is described below, and thus similar detailed description is omitted.

[0144] In some embodiments, the memory cell array 302A includes columns 1 and 2 of the memory cell array 202A, and rows 1, 2, 3, 4, and 5 of the memory cell array 202A, and thus similar detailed descriptions are omitted.

[0145] Each memory cell in the memory cell array 302A is Figure 3A The memory cell 300A is described below, and thus similar detailed description is omitted.

[0146] and Figure 2 Compared with Figure 2 Compared with the read bit line group RBL extending along the second direction Y, Figure 3B The read bit line group RBL in FIG. 1 extends along the first direction X, and thus similar detailed description is omitted.

[0147] and Figure 2 Compared with Figure 2 Compared with the read word line group RWL extending along the first direction X, Figure 3B The read word line group RWL in extends in the second direction Y, so similar detailed description is omitted.

[0148] Other configurations of the memory cell array 300B are also within the scope of the present disclosure.

[0149] Figure 4A is a circuit diagram of a memory circuit 400A according to some embodiments.

[0150] Figure 4B is a table 400B that may be used as an OR gate 400C of the memory circuit 400A, according to some embodiments.

[0151] Figure 4C is a circuit diagram of an OR gate 400C according to some embodiments.

[0152] Figure 4D is a table 400D that may be used as AND gate 400E of memory circuit 400A according to some embodiments.

[0153] Figure 4E is a circuit diagram of an AND gate 400E according to some embodiments.

[0154] The memory circuit 400A is Figure 1 An embodiment of the adder circuit 104 is schematically shown, and thus similar detailed description is omitted.

[0155] The memory circuit 400A can be used as Figure 1 Adder circuit 104. In some embodiments, based on at least one of control signal C1, control signal C2, or control signal C3, memory circuit 400A is configured as OR gate 400C or AND gate 400E.

[0156] The memory circuit 400A includes a transistor N1a, a transistor N1b, a transistor N2a, a transistor N2b, a transistor N3a, a transistor N3b, a transistor N4a, a transistor N4b, a transistor N5a, a transistor N5b, a transistor N6a, a transistor N6b, a transistor N7a, and a transistor N7b.

[0157] In some embodiments, one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are N-type transistors. In some embodiments, one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are NMOS transistors.

[0158] In some embodiments, one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are P-type transistors. In some embodiments, one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are PMOS transistors.

[0159] In some embodiments, one or more of the transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, nanosheet transistors, nanowire transistors, etc. In some embodiments, one or more of the transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are manufactured as part of a front-end-of-line (FEOL) process.

[0160] In some embodiments, one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are thin film transistors (TFTs) having an oxide channel region. In some embodiments, one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are FeFETs or the like and are manufactured as part of a back-end of line (BEOL) process.

[0161] In some embodiments, transistors N1a and N1b are configured as a 2T DRAM cell.

[0162] The source / drain terminal of transistor N1a is configured to receive data signal A. In some embodiments, the drain / source terminal of transistor N1a is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0163] The gate terminal of transistor N1a is configured to receive control signal G1a. In some embodiments, the gate terminal of transistor N1a is coupled to the source of control signal G1a. In some embodiments, the gate terminal of transistor N1a is coupled to a controller, such as Figure 6 In some embodiments, the control signal G1a can be used to control the on / off of the transistor N1a.

[0164] The source / drain terminal of the transistor N1a is configured to output the data signal A in response to the control signal G1a. The source / drain terminal of the transistor N1a is coupled to the gate terminal of the transistor N1b.

[0165] Transistor N1a is configured to write data by controlling the voltage of the gate terminal of transistor N1b, thereby turning on or off transistor N1b. In some embodiments, if transistor N1a is enabled or turned on, the voltage of data signal A is configured to control the voltage of the gate terminal of transistor N1b. Therefore, in some embodiments, the voltage of data signal A controls the turning on or off of transistor N1b. In some embodiments, transistors N1a and N1b are configured as a memory cell, wherein transistor N1a is an access transistor, transistor N1b is a storage transistor, and the voltage of data signal A corresponds to the data stored in transistor N1b.

[0166] In some embodiments, transistor N1b is configured to read data stored therein based on whether transistor N1b is turned on or off. In some embodiments, transistor N1b is configured to output data stored therein based on whether transistor N1b is turned on or off.

[0167] In some embodiments, each of the source / drain terminal of transistor N1b, the source / drain terminal of transistor N2b, the source / drain terminal of transistor N3b, and the source / drain terminal of transistor N4b are coupled together at node 420. In some embodiments, node 420 has a signal VR. In some embodiments, signal VR is equal to power supply voltage VDD. In some embodiments, signal VR is equal to reference power supply voltage VSS.

[0168] In some embodiments, each of the source / drain terminal of transistor N1b, the source / drain terminal of transistor N2b, the source / drain terminal of transistor N3b, the source / drain terminal of transistor N4b, the source / drain terminal of transistor N5b, the source / drain terminal of transistor N6b, and the source / drain terminal of transistor N7b are coupled together at an output node 430. In some embodiments, output node 430 has an output signal Vo.

[0169] In some embodiments, at least one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a, or N7b are configured to set the output signal Vo.

[0170] In some embodiments, transistors N2a and N2b are configured as a 2T DRAM cell.

[0171] The source / drain terminal of transistor N2a is configured to receive data signal A. In some embodiments, the drain / source terminal of transistor N2a is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0172] The gate terminal of transistor N2a is configured to receive control signal G1a. In some embodiments, the gate terminal of transistor N2a is coupled to the source of control signal G1a. In some embodiments, the gate terminal of transistor N2a is coupled to a controller, such as Figure 6 In some embodiments, the control signal G1a can be used to control the on / off of the transistor N2a.

[0173] The source / drain terminal of the transistor N2a is configured to output the data signal A in response to the control signal G1a. The source / drain terminal of the transistor N2a is coupled to the gate terminal of the transistor N2b.

[0174] Transistor N2a is configured to write data by controlling the voltage of the gate terminal of transistor N2b, thereby turning on or off transistor N2b. In some embodiments, if transistor N2a is enabled or turned on, the voltage of data signal A is configured to control the voltage of the gate terminal of transistor N2b. Therefore, in some embodiments, the voltage of data signal A controls the turning on or off of transistor N2b. In some embodiments, transistors N2a and N2b are configured as a memory cell, wherein transistor N2a is an access transistor, transistor N2b is a storage transistor, and the voltage of data signal A corresponds to the data stored in transistor N2b.

[0175] In some embodiments, transistor N2b is configured to read data stored therein based on whether transistor N2b is turned on or off. In some embodiments, transistor N2b is configured to output data stored therein based on whether transistor N2b is turned on or off.

[0176] In some embodiments, transistors N3a and N3b are configured as a 2T DRAM cell.

[0177] The source / drain terminal of transistor N3a is configured to receive data signal B. In some embodiments, the drain / source terminal of transistor N3a is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0178] The gate terminal of transistor N3a is configured to receive control signal G1b. In some embodiments, the gate terminal of transistor N3a is coupled to the source of control signal G1b. In some embodiments, the gate terminal of transistor N3a is coupled to a controller, such as Figure 6 In some embodiments, the control signal G1b can be used to control the on / off of the transistor N3a.

[0179] The source / drain terminal of the transistor N3 a is configured to output the data signal B in response to the control signal G1 b. The source / drain terminal of the transistor N3 a is coupled to the gate terminal of the transistor N3 b.

[0180] Transistor N3a is configured to write data by controlling the voltage of the gate terminal of transistor N3b, thereby turning on or off transistor N3b. In some embodiments, if transistor N3a is enabled or turned on, the voltage of data signal B is configured to control the voltage of the gate terminal of transistor N3b. Therefore, in some embodiments, the voltage of data signal B controls the turning on or off of transistor N3b. In some embodiments, transistors N3a and N3b are configured as a memory cell, wherein transistor N3a is an access transistor, transistor N3b is a storage transistor, and the voltage of data signal B corresponds to the data stored in transistor N3b.

[0181] In some embodiments, transistor N3b is configured to read data stored therein based on whether transistor N3b is turned on or off. In some embodiments, transistor N3b is configured to output data stored therein based on whether transistor N3b is turned on or off.

[0182] In some embodiments, transistors N4a and N4b are configured as a 2T DRAM cell.

[0183] The source / drain terminal of transistor N4a is configured to receive data signal B. In some embodiments, the drain / source terminal of transistor N4a is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0184] The gate terminal of transistor N4a is configured to receive control signal G1b. In some embodiments, the gate terminal of transistor N4a is coupled to the source of control signal G1b. In some embodiments, the gate terminal of transistor N4a is coupled to a controller, such as Figure 6 In some embodiments, the control signal G1b can be used to control the on / off of the transistor N4a.

[0185] The source / drain terminal of the transistor N4a is configured to output the data signal B in response to the control signal G1b. The source / drain terminal of the transistor N4a is coupled to the gate terminal of the transistor N4b.

[0186] Transistor N4a is configured to write data by controlling the voltage of the gate terminal of transistor N4b, thereby turning on or off transistor N4b. In some embodiments, if transistor N4a is enabled or turned on, the voltage of data signal B is configured to control the voltage of the gate terminal of transistor N4b. Therefore, in some embodiments, the voltage of data signal B controls the conduction or cutoff of transistor N4b. In some embodiments, transistors N4a and N4b are configured as a memory cell, wherein transistor N4a is an access transistor, transistor N4b is a storage transistor, and the voltage of data signal B corresponds to the data stored in transistor N4b.

[0187] In some embodiments, transistor N4b is configured to read data stored therein based on whether transistor N4b is turned on or off. In some embodiments, transistor N4b is configured to output data stored therein based on whether transistor N4b is turned on or off.

[0188] In some embodiments, transistors N5a and N5b are configured as a 2T DRAM cell.

[0189] The source / drain terminal of transistor N5a is configured to receive control signal C1. In some embodiments, the source / drain terminal of transistor N5a is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0190] The gate terminal of transistor N5a is configured to receive control signal G2a. In some embodiments, the gate terminal of transistor N5a is coupled to the source of control signal G2a. In some embodiments, the gate terminal of transistor N5a is coupled to a controller, such as Figure 6 In some embodiments, the control signal G2a can be used to control the on / off of the transistor N5a.

[0191] The source / drain terminal of transistor N5a is configured to output the control signal C1 in response to the control signal G2a. The source / drain terminal of transistor N5a is coupled to the gate terminal of transistor N5b.

[0192] Transistor N5a is configured to write data by controlling the voltage of the gate terminal of transistor N5b, thereby turning on or off transistor N5b. In some embodiments, if transistor N5a is enabled or turned on, the voltage of control signal C1 is configured to control the voltage of the gate terminal of transistor N5b. Therefore, in some embodiments, the voltage of control signal C1 controls the turning on or off of transistor N5b. In some embodiments, transistors N5a and N5b are configured as a memory cell, wherein transistor N5a is an access transistor, transistor N5b is a storage transistor, and the voltage of control signal C1 corresponds to the data stored in transistor N5b.

[0193] In some embodiments, transistor N5b is configured to read data stored therein based on whether transistor N5b is turned on or off. In some embodiments, transistor N5b is configured to output data stored therein based on whether transistor N5b is turned on or off.

[0194] In some embodiments, each of the source / drain terminal of transistor N5b, the source / drain terminal of transistor N6b, and the drain-source terminal of transistor N7b are coupled together at node 422. In some embodiments, node 422 has a voltage equal to reference power supply voltage VSS. In some embodiments, the voltage of node 422 is equal to power supply voltage VDD.

[0195] In some embodiments, transistors N6a and N6b are configured as a 2T DRAM cell.

[0196] The source / drain terminal of transistor N6a is configured to receive control signal C2. In some embodiments, the source / drain terminal of transistor N6a is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0197] The gate terminal of transistor N6a is configured to receive control signal G2b. In some embodiments, the gate terminal of transistor N6a is coupled to the source of control signal G2b. In some embodiments, the gate terminal of transistor N6a is coupled to a controller, such as Figure 6 In some embodiments, the control signal G2b can be used to control the on / off of the transistor N6a.

[0198] The source / drain terminal of transistor N6a is configured to output control signal C2 in response to control signal G2b. The source / drain terminal of transistor N6a is coupled to the gate terminal of transistor N6b.

[0199] Transistor N6a is configured to write data by controlling the voltage of the gate terminal of transistor N6b, thereby turning on or off transistor N6b. In some embodiments, if transistor N6a is enabled or turned on, the voltage of control signal C2 is configured to control the voltage of the gate terminal of transistor N6b. Therefore, in some embodiments, the voltage of control signal C2 controls the turning on or off of transistor N6b. In some embodiments, transistors N6a and N6b are configured as a memory cell, wherein transistor N6a is an access transistor, transistor N6b is a storage transistor, and the voltage of control signal C2 corresponds to the data stored in transistor N6b.

[0200] In some embodiments, transistor N6b is configured to read data stored therein based on whether transistor N6b is turned on or off. In some embodiments, transistor N6b is configured to output data stored therein based on whether transistor N6b is turned on or off.

[0201] In some embodiments, transistors N7a and N7b are configured as a 2T DRAM cell.

[0202] The source / drain terminal of transistor N7a is configured to receive control signal C3. In some embodiments, the source / drain terminal of transistor N7a is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0203] The gate terminal of transistor N7a is configured to receive control signal G2c. In some embodiments, the gate terminal of transistor N7a is coupled to the source of control signal G2c. In some embodiments, the gate terminal of transistor N7a is coupled to a controller, such as Figure 6 In some embodiments, the control signal G2c can be used to control the on / off of the transistor N7a.

[0204] The source / drain terminal of transistor N7a is configured to output control signal C3 in response to control signal G2c. The source / drain terminal of transistor N7a is coupled to the gate terminal of transistor N7b.

[0205] Transistor N7a is configured to write data by controlling the voltage of the gate terminal of transistor N7b, thereby turning on or off transistor N7b. In some embodiments, if transistor N7a is enabled or turned on, the voltage of control signal C3 is configured to control the voltage of the gate terminal of transistor N7b. Therefore, in some embodiments, the voltage of control signal C3 controls the turning on or off of transistor N7b. In some embodiments, transistors N7a and N7b are configured as a memory cell, wherein transistor N7a is an access transistor, transistor N7b is a storage transistor, and the voltage of control signal C3 corresponds to the data stored in transistor N7b.

[0206] In some embodiments, transistor N7b is configured to read data stored therein based on whether transistor N7b is turned on or off. In some embodiments, transistor N7b is configured to output data stored therein based on whether transistor N7b is turned on or off.

[0207] Other transistor terminals for one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a or N7b are within the scope of the present disclosure.

[0208] Other numbers of transistors or transistor types for one or more of transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a or N7b are within the scope of the present disclosure.

[0209] Other configurations or numbers of transistors in memory circuit 400A are within the scope of the present disclosure.

[0210] Figure 4B is a table 400B that may be used as an OR gate 400C of the memory circuit 400A, according to some embodiments.

[0211] Table 400B includes values ​​of control signals C1, C2, C3, A, and B and a value of output signal Vo when memory circuit 400A is configured as OR gate 400C. In other words, in some embodiments, memory circuit 400A is configured as OR gate 400C based on the value of at least one of control signal C1, control signal C2, or control signal C3, as shown in table 400B.

[0212] For example, as shown in Table 400B, according to some embodiments, when the control signal C1 is logic low (e.g., logic 0), the control signal C2 is logic low (e.g., logic 0), and the control signal C3 is logic high (e.g., logic 1), the memory circuit 400A is configured as an OR gate 400C. In these embodiments, the control signals A and B can be used as input signals of the OR gate 400C and used to generate an output signal Vo consistent with the output value of the OR gate.

[0213] For example, as shown in table 400B, according to some embodiments, when control signal C1 is logic low (e.g., logic 0), control signal C2 is logic high (e.g., logic 1), and control signal C3 is logic low (e.g., logic 0), memory circuit 400A is configured as OR gate 400C.

[0214] For example, as shown in table 400B, according to some embodiments, when control signal C1 is logic high (e.g., logic 1), control signal C2 is logic low (e.g., logic 0), and control signal C3 is logic low (e.g., logic 0), memory circuit 400A is configured as OR gate 400C.

[0215] In some embodiments, the following Figure 5 A further description of the operation of memory circuit 400A is described in .

[0216] Other configurations or values ​​in table 400B are also within the scope of the present disclosure.

[0217] Figure 4C is a circuit diagram of an OR gate 400C according to some embodiments.

[0218] The OR gate 400C has a first input terminal configured to receive a data signal A and a second input terminal configured to receive a data signal B. The OR gate 400C is configured to generate an output signal Vo based on the control signals A and B.

[0219] In some embodiments, when the values ​​of table 400B are used for control signal C1 , control signal C2 , and control signal C3 , OR gate 400C may be used as memory circuit 400A.

[0220] Other configurations or numbers of terminals in the OR gate 400C are also within the scope of the present disclosure.

[0221] Figure 4D is a table 400D that may be used as AND gate 400E of memory circuit 400A according to some embodiments.

[0222] Table 400D includes values ​​of control signals C1, C2, C3, A, and B and a value of output signal Vo when memory circuit 400A is configured as AND gate 400E. In other words, in some embodiments, memory circuit 400A is configured as AND gate 400E based on the value of at least one of control signal C1, control signal C2, or control signal C3, as shown in table 400D.

[0223] For example, as shown in Table 400D, according to some embodiments, when the control signal C1 is logic high (e.g., logic 1), the control signal C2 is logic high (e.g., logic 1), and the control signal C3 is logic high (e.g., logic 1), the memory circuit 400A is configured as an AND gate 400E. In these embodiments, the control signals A and B can be used as input signals of the gate 400E and used to generate an output signal Vo consistent with the output value of the AND gate.

[0224] Other configurations or values ​​in table 400D are also within the scope of the present disclosure.

[0225] Figure 4E is a circuit diagram of an AND gate 400E according to some embodiments.

[0226] AND gate 400E has a first input terminal configured to receive data signal A and a second input terminal configured to receive data signal B. AND gate 400E is configured to generate output signal Vo based on control signals A and B. AND gate 400E has an output terminal configured to output output signal Vo.

[0227] In some embodiments, when the values ​​of table 400D are used for control signal C1 , control signal C2 , and control signal C3 , AND gate 400E may be used as memory circuit 400A.

[0228] exist Figure 5 The timing diagram of 500 and Fig.18A and Fig.18B Further operations of one or more of memory circuit 400A, table 400B, OR gate 400C, table 400D, or AND gate 400E are described in method 1800 of .

[0229] Other configurations or numbers of terminals in AND gate 400E are also within the scope of the present disclosure.

[0230] Figure 5 According to some embodiments Figure 4A 4 is a graph of a corresponding waveform 500 for the memory circuit 400A.

[0231] In some embodiments, waveform 500 is Figure 4A Examples of the initialization mode, the write mode, and the read mode of the memory circuit 400A.

[0232] Initialization (in Figure 5 The initialization mode is from time T0 and T3, the write mode is from time T3 and T7, and the read mode is from time T7 and T10. Other times for at least one of the initialization mode, the write mode, or the read mode are within the scope of the present disclosure.

[0233] The waveform 500 includes the control signal C1, the control signal G2a, the control signal G1a, the data signal A, the data signal B, the signal VR, and the output signal Vo.

[0234] At time T0, each of control signal C1, control signal G2a, control signal G1a, data signal A, data signal B, signal VR, and output signal Vo is equal to logic 0. In some embodiments, adjacent to one or more of times T0-T8, output signal Vo is electrically floating.

[0235] In response to control signal G2a being equal to logic 0, transistor N5a is turned off, thereby decoupling the source / drain terminal of transistor N5a from the gate terminal of transistor N5b.

[0236] In response to control signal G1a being equal to logic 0, transistor N1a is turned off, thereby decoupling the source / drain terminal of transistor N1a from the gate terminal of transistor N1b. In response to control signal G1a being equal to logic 0, transistor N2a is turned off, thereby decoupling the source / drain terminal of transistor N2a from the gate terminal of transistor N2b.

[0237] At time T1a, control signal C1 transitions to equal logic 1. In some embodiments, control signal C1 transitions to logic 1 to enable the data value to be stored in the gate of transistor N5b.

[0238] At time T1b, control signal G2a transitions to equal logic 1.

[0239] In response to the control signal G2a being equal to logic 1, the transistor N5a is turned on, thereby coupling the source / drain terminal of the transistor N5a to the gate terminal of the transistor N5b and charging or setting the voltage of the gate terminal of the transistor N5b to be equal to logic 1. In response to the voltage of the gate terminal of the transistor N5b being equal to logic 1, the transistor N5b is turned on, thereby coupling the output node 430 to the node 422. In some embodiments, by coupling the output node 430 to the node 422, the output signal of the output node 430 is pulled down to the reference voltage VSS, thereby starting the memory circuit 400A to perform a read operation or a write operation.

[0240] At time T2, control signal G2a transitions to be equal to logic 0. In response to control signal G2a being equal to logic 0, transistor N5a turns off, thereby decoupling the source / drain terminal of transistor N5a and the gate terminal of transistor N5b.

[0241] At time T3, control signal C1 transitions to equal logic 0.

[0242] At time T4, data signal A transitions to equal logic 1. In some embodiments, data signal A transitions to logic 1 to enable data values ​​to be stored in the gates of transistors N1a and N2a.

[0243] At time T5 , control signal G1 a transitions to be equal to logic 1. In some embodiments, by control signal G1 a transitioning to be equal to logic 1, the value of control signal A is written into transistor N1 b and transistor N2 b.

[0244] In response to control signal G1a being equal to logic 1, transistor N1a is turned on, thereby coupling the source / drain terminal of transistor N1a to the gate terminal of transistor N1b and charging or setting the voltage of the gate terminal of transistor N1b equal to logic 1. In response to the voltage of the gate terminal of transistor N1b being equal to logic 1, transistor N1b is turned on, thereby coupling output node 430 to node 422.

[0245] In response to control signal G1a being equal to logic 1, transistor N2a is turned on, thereby coupling the source / drain terminal of transistor N2a to the gate terminal of transistor N2b and charging or setting the voltage of the gate terminal of transistor N2b equal to logic 1. In response to the voltage of the gate terminal of transistor N2b being equal to logic 1, transistor N2b is turned on, thereby coupling output node 430 to node 422.

[0246] At time T6, control signal G1a transitions to be equal to logic 0. In response to control signal G1a being equal to logic 0, transistor N1a is turned off, thereby decoupling the source / drain terminal of transistor N1a and the gate terminal of transistor N1b. In response to control signal G1a being equal to logic 0, transistor N2a is turned off, thereby decoupling the source / drain terminal of transistor N2a and the gate terminal of transistor N1b.

[0247] At time T7, data signal A transitions to equal logic 0.

[0248] At time T8, signal VR transitions to be equal to logic 1 or power supply voltage VDD.

[0249] In some embodiments, at time T8 , transistors N1 b and N2 b are turned on, thereby coupling node 422 and output node 430 together.

[0250] In response to the signal VR being equal to logic 1 or the power supply voltage VDD, and in response to at least one of the transistor N1b or the transistor N2b being turned on, the output signal Vo of the output node 430 is pulled to a high level of the power supply voltage VSS, thereby outputting the value (logic 1) stored in the transistors N1b and N2b during the read operation.

[0251] Although waveform 500 is described for memory circuit 400A and table 400B when control signal C1 is logic high (logic 1), waveform 500 applies to each entry in table 400B and table 400D in a similar manner, and thus similar detailed description is omitted.

[0252] In some embodiments, memory circuit 400A achieves benefits similar to one or more of those discussed herein.

[0253] Other configurations of waveform 500 are also within the scope of the present disclosure.

[0254] Figure 6 is a circuit diagram of a memory circuit 600 according to some embodiments.

[0255] The memory circuit 600 is schematically represented Figure 1 The present invention is a partial embodiment of the memory device 100, and thus similar detailed description is omitted.

[0256] In some embodiments, the memory circuit 600 is Figure 1 The memory array 102, Figure 1 The embodiments of the adder circuit 104 and the controller 120 are described above, and thus similar detailed descriptions are omitted.

[0257] In some embodiments, the memory circuit 600 will Figure 1 The memory array 102, Figure 1 The characteristics of the adder circuit 104 and the controller 120 are Figure 4A The memory circuit 400A and Figure 3B The memory cell array 300B is combined, and thus similar detailed description is omitted.

[0258] The memory circuit 600 includes a memory cell array 602 , an adder circuit 604 , and a controller 606 .

[0259] In some embodiments, memory cell array 602 is similar to Figure 3B The memory cell array 300B, the adder circuit 604 is similar to Figure 4A The memory circuit 400A, the controller 606 is similar to Figure 1 The controller 120 is described below, and thus similar detailed description is omitted.

[0260] like Figure 6 As shown, the source / drain terminals of transistor N1a are connected to the read bit line RBL[1] of the memory cell array 602. In some embodiments, the source / drain terminals of transistor N1a are also coupled to the source / drain terminals of each corresponding transistor in row 1 of the memory cell array 602 through the read bit line RBL[1]. In some embodiments, the source / drain terminals of transistor N1a are also coupled to the source / drain terminals of the corresponding memory cells 302[1,1] and 302[1,2] through the read bit line RBL[1].

[0261] like Figure 6 As shown, the source / drain terminals of transistor N2a are connected to the read bit line RBL[2] of the memory cell array 602. In some embodiments, the source / drain terminals of transistor N2a are also coupled to the source / drain terminals of each corresponding transistor in row 2 of the memory cell array 602 through the read bit line RBL[2]. In some embodiments, the source / drain terminals of transistor N2a are also coupled to the source / drain terminals of the corresponding memory cells 302[2,1] and 302[2,2] through the read bit line RBL[2].

[0262] like Figure 6 As shown, the source / drain terminals of transistor N3a are connected to the read bit line RBL[3] of the memory cell array 602. In some embodiments, the source / drain terminals of transistor N3a are also coupled to the source / drain terminals of each corresponding transistor in row 3 of the memory cell array 602 through the read bit line RBL[3]. In some embodiments, the source / drain terminals of transistor N3a are also coupled to the source / drain terminals of the corresponding memory cells 302[3,1] and 302[3,2] through the read bit line RBL[3].

[0263] like Figure 6 As shown, the source / drain terminals of transistor N4a are connected to the read bit line RBL[4] of the memory cell array 602. In some embodiments, the source / drain terminals of transistor N4a are also coupled to the source / drain terminals of each corresponding transistor in row 4 of the memory cell array 602 through the read bit line RBL[4]. In some embodiments, the source / drain terminals of transistor N4a are also coupled to the source / drain terminals of the corresponding memory cells 302[4,1] and 302[4,2] through the read bit line RBL[4].

[0264] In some embodiments, the source / drain terminal of transistor N5a is coupled to controller 606. In some embodiments, controller 606 is configured to generate and send control signal C1 to transistor N5a.

[0265] In some embodiments, the source / drain terminal of transistor N6a is coupled to controller 606. In some embodiments, controller 606 is configured to generate and send control signal C2 to transistor N6a.

[0266] In some embodiments, the source / drain terminal of transistor N7a is coupled to controller 606. In some embodiments, controller 606 is configured to generate and send control signal C3 to transistor N7a.

[0267] In some embodiments, controller 606 is coupled to one or more of the write word line WWL, the read word line RWL, the write bit line WBL, or the read bit line RBL.

[0268] In some embodiments, the controller 606 is configured to generate a write word line signal for the write word line WWL. In some embodiments, the controller 606 is configured to generate a read word line signal for the read word line RWL. In some embodiments, the controller 606 is configured to generate a write bit line signal for the write bit line WBL. In some embodiments, the controller 606 is configured to generate a read bit line signal for the read bit line RBL.

[0269] In some embodiments, the write word line WWL, the write bit line WBL and the transistors N5a, N6a and N7a of the adder circuit 604 are controlled by a controller 606. In some embodiments, the controller 606 is a FEOL controller or is manufactured by a FEOL process. In some embodiments, the controller is one or more processors, such as Fig. 17C Processor 1732.

[0270] In some embodiments, the read bit line RBL is configured to interact with the controller 606. In some embodiments, the read bit line RBL is also coupled to the adder circuit 604 for writing data to the adder circuit 604 (eg, by using control signals A and B).

[0271] In some embodiments, memory circuit 600 achieves one or more of the benefits discussed herein.

[0272] Other configurations of memory circuit 600 are also within the scope of the present disclosure.

[0273] Fig. 7A is a circuit diagram of a memory circuit 700A according to some embodiments.

[0274] Figure 7B is a table 700B that may be used as an OR gate 700C of the memory circuit 700A, according to some embodiments.

[0275] Figure 7C is a circuit diagram of an OR gate 700C according to some embodiments.

[0276] Fig.7D is a table 700D that may be used as AND gate 700E of memory circuit 700A according to some embodiments.

[0277] Fig. 7E is a circuit diagram of an AND gate 700E according to some embodiments.

[0278] The memory circuit 700A is schematically represented Figure 1 The embodiments of the adder circuit 104 are described above, and thus similar detailed description is omitted.

[0279] The memory circuit 700A can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604. In some embodiments, based on at least one of control signal C1 or control signal C2, memory circuit 700A is configured as OR gate 700C or AND gate 700E.

[0280] The memory circuit 700A is Figure 4A The memory circuit 400A is a variation of the memory circuit 400A, and thus similar detailed description is omitted. Figure 4A Compared with the memory circuit 400A, Fig. 7A Circuit 700A does not include transistor N2a, transistor N2b, transistor N4a, transistor N4b, transistor N7a, or transistor N7b, and thus similar detailed description is omitted.

[0281] The memory circuit 700A includes a transistor N1 a , a transistor N1 b , a transistor N3 a , a transistor N3 b , a transistor N5 a , a transistor N5 b , a transistor N6 a , and a transistor N6 b .

[0282] According to some embodiments, Figure 4A Compared to the memory circuit 400A of FIG. 4 , each of the source / drain terminal of transistor N1 b and the drain / source terminal of transistor N3 b are coupled together at node 720. In some embodiments, node 720 is similar to Figure 4A In some embodiments, the node 720 has a signal VR.

[0283] According to some embodiments, Figure 4A Compared to the memory circuit 400A of FIG. 4 , each of the source / drain terminal of transistor N1 b, the source / drain terminal of transistor N3 b, the source / drain terminal of transistor N5 b, and the source / drain terminal of transistor N6 b are coupled together at output node 730. In some embodiments, output node 730 is similar to Figure 4AThe output node 430 is thus omitted from similar detailed description. In some embodiments, the output node 730 has an output signal Vo.

[0284] According to some embodiments, Figure 4A Compared to memory circuit 400A of FIG. 4 , each of the source / drain terminal of transistor N5 b, the source / drain terminal of transistor N6 b, and the source / drain terminal of transistor N7 b are coupled together at node 722. In some embodiments, node 722 is similar to Figure 4A Node 422, so similar detailed description is omitted.

[0285] In some embodiments, transistor N1a has a width W1. In some embodiments, width W1 is a width of an active region (not shown) of transistor N1a in the first direction X.

[0286] In some embodiments, the transistor N2a has a width W1. In some embodiments, the width W1 is a width of an active region (not shown) of the transistor N2a in the first direction X.

[0287] In some embodiments, the transistor N3a has a width W2. In some embodiments, the width W2 is a width of an active region (not shown) of the transistor N3a in the first direction X.

[0288] In some embodiments, the transistor N5a has a width W3. In some embodiments, the width W3 is a width of an active region (not shown) of the transistor N5a in the first direction X.

[0289] In some embodiments, transistor N6a has a width W4. In some embodiments, width W4 is a width of an active region (not shown) of transistor N6a in the first direction X.

[0290] In some embodiments, width W4 is less than at least one of widths W1, W2, or W3. In some embodiments, width W4 is equal to range R1. In some embodiments, range R1 ranges from about 0.3*W1 to about 0.7*W1. Other ranges or values ​​of range R1 are within the scope of the present disclosure.

[0291] In some embodiments, width W3 is greater than at least one of width W1 or W2. In some embodiments, width W3 is equal to range R2. In some embodiments, range R2 ranges from about 1.3*W1 to about 1.7*W1. Other ranges or values ​​of range R2 are within the scope of the present disclosure.

[0292] In some embodiments, width W1 is equal to width W2. In some embodiments, width W1 is different from width W2. In some embodiments, width W2 is equal to range R3. In some embodiments, range R3 ranges from about 0.9*W1 to about 1.1*W1. Other ranges or values ​​of range R3 are within the scope of the present disclosure.

[0293] In some embodiments, the width W1, W2, W3, or W4 of the corresponding transistor N1a, N3a, N5a, or N6a is related to the corresponding speed and drive strength of the corresponding transistor N1a, N3a, N5a, or N6a. In some embodiments, an increase in the width W1, W2, W3, or W4 of the corresponding transistor N1a, N3a, N5a, or N6a causes the corresponding speed and drive strength of the corresponding transistor N1a, N3a, N5a, or N6a to increase. In some embodiments, a decrease in the width W1, W2, W3, or W4 of the corresponding transistor N1a, N3a, N5a, or N6a causes the corresponding speed and drive strength of the corresponding transistor N1a, N3a, N5a, or N6a to decrease.

[0294] In some embodiments, different speeds and drive strengths allow for the OR function of table 700B and the AND function of table 700D to be implemented by adjusting one or more of the widths W1, W2, W3, or W4 of the corresponding transistors N1a, N3a, N5a, or N6a. Other widths of one or more of the widths W1, W2, W3, or W4 are within the scope of the present disclosure.

[0295] In some embodiments, memory circuit 700A achieves benefits similar to one or more of those discussed herein.

[0296] Other configurations, numbers of transistors, or types of transistors in memory circuit 700A are also within the scope of the present disclosure.

[0297] Figure 7B is a table 700B that may be used as an OR gate 700C of the memory circuit 700A, according to some embodiments.

[0298] Table 700B includes values ​​of control signals C1, C2, A, and B and a value of output signal Vo when memory circuit 700A is configured as OR gate 700C. In other words, in some embodiments, memory circuit 700A is configured as OR gate 700C based on the value of at least one of control signal C1 or control signal C2, as shown in table 700B.

[0299] For example, as shown in Table 700B, according to some embodiments, when the control signal C1 is logic high (e.g., logic 1) and the control signal C2 is logic low (e.g., logic 0), the memory circuit 700A is configured as an OR gate 700C. In these embodiments, the control signals A and B can be used as input signals of the OR gate 700C and used to generate an output signal Vo consistent with the output value of the OR gate.

[0300] Other configurations or values ​​in table 700B are also within the scope of the present disclosure.

[0301] Figure 7C is a circuit diagram of an OR gate 700C according to some embodiments.

[0302] In some embodiments, OR gate 700C is similar to Figure 4C The OR gate 400C is thus similarly described in detail.

[0303] In some embodiments, when the values ​​of table 700B are used for control signal C1 and control signal C2, OR gate 700C may be used as memory circuit 700A.

[0304] Other configurations or numbers of terminals in OR gate 700C are within the scope of the present disclosure.

[0305] Fig.7D is a table 700D that may be used as AND gate 700E of memory circuit 700A according to some embodiments.

[0306] Table 700D includes values ​​of control signals C1, C2, A, and B and a value of output signal Vo when memory circuit 700A is configured as AND gate 700E. In other words, in some embodiments, memory circuit 700A is configured as AND gate 700E based on the value of at least one of control signal C1 or control signal C2, as shown in table 700D.

[0307] For example, as shown in Table 700D, according to some embodiments, when the control signal C1 is logic low (e.g., logic 0) and the control signal C2 is logic high (e.g., logic 1), the memory circuit 700A is configured as an AND gate 700E. In these embodiments, the control signals A and B can be used as input signals of the AND gate 700E and used to generate an output signal Vo consistent with the output value of the AND gate.

[0308] Other configurations or values ​​in Table 700D are also within the scope of the present disclosure.

[0309] Fig. 7E is a circuit diagram of an AND gate 700E according to some embodiments.

[0310] In some embodiments, when the values ​​of table 700D are used for control signal C1 and control signal C2, AND gate 700E may be used as memory circuit 700A.

[0311] Other configurations or numbers of terminals in AND gate 700E are within the scope of the present disclosure.

[0312] Fig. 8A is a circuit diagram of a memory circuit 800A according to some embodiments.

[0313] Figure 8B is a table 800B that may be used as an OR gate 800C of the memory circuit 800A, according to some embodiments.

[0314] Figure 8C is a circuit diagram of an OR gate 800C according to some embodiments.

[0315] Fig.8D is a table 800D that may be used as AND gate 800E of memory circuit 800A, according to some embodiments.

[0316] Fig. 8E is a circuit diagram of an AND gate 800E according to some embodiments.

[0317] The memory circuit 800A is schematically represented Figure 1 The embodiments of the adder circuit 104 are described above, and thus similar detailed description is omitted.

[0318] The memory circuit 800A can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604. In some embodiments, based on at least one of control signal C1 or control signal C2, memory circuit 800A is configured as OR gate 800C or AND gate 800E.

[0319] The memory circuit 800A is Figure 4A The memory circuit 400A is a variation of the memory circuit 400A, and thus similar detailed description is omitted. Figure 4A Compared with the memory circuit 400A, Fig. 8A Circuit 800A does not include transistor N2a, transistor N2b, transistor N4a, transistor N4b, transistor N6a, transistor N6b, transistor N7a, or transistor N7b, and thus similar detailed description is omitted.

[0320] The memory circuit 800A includes a transistor N1 a , a transistor N1 b , a transistor N3 a , a transistor N3 b , a transistor N5 a , and a transistor N5 b .

[0321] and Figure 4ACompared to the memory circuit 400A, node 820 replaces Figure 4A The node 420 of the output node 830 replaces Figure 4A The output node 430 is replaced by node 822 Figure 4A Node 422, so similar detailed description is omitted.

[0322] According to some embodiments, Figure 4A Compared to memory circuit 400A of FIG. 8 , each of the source / drain terminals of transistor N1 b and the source / drain terminals of transistor N3 b are coupled together at node 820. In some embodiments, node 820 has signal VR.

[0323] According to some embodiments, Figure 4A Compared to the memory circuit 400A of FIG. 8 , each of the source / drain terminal of transistor N1b, the source / drain terminal of transistor N3b, and the source / drain terminal of transistor N5b are coupled together at an output node 830. In some embodiments, the output node 830 has an output signal Vo.

[0324] According to some embodiments, Figure 4A Compared to the memory circuit 400A of FIG. 8 , each of the source / drain terminal of transistor N5 b, the source / drain terminal of transistor N6 b, and the source / drain terminal of transistor N7 b are coupled together at node 822. In some embodiments, node 822 has a reference voltage VSS.

[0325] In some embodiments, control signal C1 is equal to voltage V1 or voltage V2. In some embodiments, voltage V1 is different from voltage V2. In some embodiments, voltages V1 and V2 are different from reference power supply voltage VSS. In some embodiments, by voltage V1 being different from voltage V2, the operating voltage of transistor N5a can be adjusted based on voltages V1 and V2, and transistor N5a will be turned on at different speeds for each of voltages V1 or V2. Other values ​​of voltages V1 and V2 are also within the scope of the present disclosure.

[0326] In some embodiments, one or more of transistors N1a or N3a has an operating voltage different from transistor N5a. For example, in some embodiments, by using a control signal C1 having a voltage different from data signal A or B (e.g., VDD or VSS) (e.g., voltage V1 or V2), the operating voltage of transistor N5a can be adjusted, thereby adjusting the memory current through transistors N1b, N3b, or N5b, thereby achieving the OR function of table 800B and the AND function of table 800D.

[0327] Other configurations, numbers of transistors, or types of transistors in memory circuit 800A are also within the scope of the present disclosure.

[0328] Figure 8B is a table 800B that may be used as an OR gate 800C of the memory circuit 800A, according to some embodiments.

[0329] Table 800B includes values ​​of control signals C1, A, and B and values ​​of output signal Vo when memory circuit 800A is configured as OR gate 800C. In some embodiments, as shown in table 800B, when control signal C1 is equal to voltage V1, memory circuit 800A is configured as OR gate 800C.

[0330] For example, as shown in table 800B, according to some embodiments, when control signal C1 is equal to voltage V1, memory circuit 800A is configured as OR gate 800C. In these embodiments, control signals A and B can be used as input signals of OR gate 800C and used to generate output signal Vo consistent with the output value of the OR gate.

[0331] Other configurations or values ​​in table 800B are also within the scope of the present disclosure.

[0332] Figure 8C is a circuit diagram of an OR gate 800C according to some embodiments.

[0333] In some embodiments, OR gate 800C is similar to Figure 4C The OR gate 400C is thus similarly described in detail.

[0334] In some embodiments, when the values ​​of table 800B are used for control signal C1 and control signal C2, OR gate 800C may be used as memory circuit 800A.

[0335] Other configurations or numbers of terminals in OR gate 800C are within the scope of the present disclosure.

[0336] Fig.8D is a table 800D that may be used as AND gate 800E of memory circuit 800A, according to some embodiments.

[0337] Table 800D includes values ​​of control signals C1, C2, A and B and value of output signal Vo when memory circuit 800A is configured as AND gate 800E. In some embodiments, as shown in table 800D, when control signal C1 is equal to voltage V2, memory circuit 800A is configured as AND gate 800E.

[0338] For example, as shown in table 800D, according to some embodiments, when control signal C1 is equal to voltage V2, memory circuit 800A is configured as AND gate 800E. In these embodiments, control signals A and B can be used as input signals of AND gate 800E and used to generate an output signal Vo consistent with the output value of the AND gate.

[0339] Other configurations or values ​​in table 800D are also within the scope of the present disclosure.

[0340] Fig. 8E is a circuit diagram of an AND gate 800E according to some embodiments.

[0341] In some embodiments, when the values ​​of table 800D are used for control signal C1, AND gate 800E may be used as memory circuit 800A.

[0342] Other configurations or numbers of terminals in AND gate 800E are also within the scope of the present disclosure.

[0343] Fig.8F is a timing diagram of waveform 800F according to some embodiments.

[0344] Waveform 800F shows a graph of voltage and corresponding current values ​​for memory circuit 800A.

[0345] Waveform 800F includes voltages V1, V2, and V0. In some embodiments, voltages V1, V2, and V0 are voltages of control signal C1 of memory circuit 800A. In some embodiments, each voltage V1, V2, and V0 is a voltage that can be used to generate a corresponding current I1, I2, and I0.

[0346] Waveform 800F also includes currents I1, I2, and I0. In some embodiments, currents I1, I2, and I0 are the currents of control signal C1 of memory circuit 800A.

[0347] In some embodiments, voltages V0, V1, and V2 are different from one another based on the design of memory circuit 800A. In some embodiments, voltage V0 is a voltage that can be used for a logic 1 or logic high signal.

[0348] In some embodiments, I2 is equal to 1.5*I0, and / or I1 is equal to 0.5*I0.

[0349] In some embodiments, voltage V0 is a voltage that can be used to generate current I0.

[0350] In some embodiments, voltage V1 is a voltage that can be used to generate current I1 .

[0351] In some embodiments, voltage V2 is a voltage that can be used to generate current I2.

[0352] In some embodiments, voltage V2 is greater than voltage V1 and voltage V0.

[0353] In some embodiments, voltage V0 is greater than voltage V1.

[0354] Other configurations or values ​​of the waveforms in waveform 800F are also within the scope of the present disclosure.

[0355] Fig. 9A is a circuit diagram of a memory circuit 900A according to some embodiments.

[0356] Fig. 9B is a table 900B that may be used as an AND gate for memory circuit 900A according to some embodiments.

[0357] The memory circuit 900A is schematically represented Figure 1 The embodiments of the adder circuit 104 are described above, and thus similar detailed description is omitted.

[0358] The memory circuit 900A can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604. In some embodiments, memory circuit 900A is configured as an AND gate.

[0359] The memory circuit 900A is Figure 4A For example, according to some embodiments, the memory circuit 900A is a variation of the memory circuit 400A, and thus similar detailed description is omitted.

[0360] and Figure 4A Compared with the memory circuit 400A, Fig. 9A The circuit 900A does not include transistors N1a, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a and N7b, so similar detailed description is omitted.

[0361] The memory circuit 900A includes a transistor N1d and a transistor N1b.

[0362] In some embodiments, transistor N1d is a variant of transistor N1a, and thus similar detailed description is omitted. Figure 4A Compared with the transistor N1a, the transistor N1d is configured to receive the data signals A and B, and thus similar detailed description is omitted.

[0363] The source / drain terminal of transistor N1d is configured to receive data signal B. In some embodiments, the drain / source terminal of transistor N1d is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0364] The gate terminal of transistor N1d is configured to receive data signal A. In some embodiments, the gate terminal of transistor N1d is coupled to Figure 3B The corresponding read bit line RBL of the memory cell array 300B.

[0365] The source / drain terminal of the transistor N1d is configured to output the data signal B in response to the data signal A. The source / drain terminal of the transistor N1d is coupled to the gate terminal of the transistor N1b.

[0366] Transistor N1d is configured to write data by controlling the voltage of the gate terminal of transistor N1b, thereby turning transistor N1b on or off. In some embodiments, if transistor N1d is enabled or turned on, the voltage of data signal B is configured to control the voltage of the gate terminal of transistor N1b. Therefore, in some embodiments, the voltage of data signal B controls the turning on or off of transistor N1b. In some embodiments, transistors N1d and N1b are configured as a memory cell, wherein transistor N1d is an access transistor, transistor N1b is a storage transistor, and the voltage of data signal B corresponds to the data stored in transistor N1b.

[0367] In some embodiments, transistor N1b is configured to read data stored therein based on whether transistor N1b is turned on or off. In some embodiments, transistor N1b is configured to output data stored therein based on whether transistor N1b is turned on or off.

[0368] The source / drain terminals of transistor N1b are coupled to the power supply voltage VDD.

[0369] In some embodiments, the source / drain terminals of transistor N1b are coupled to output node 430, output load Rload, and reference supply voltage VSS. In some embodiments, output load Rload corresponds to the resistance of one or more conductors or memory cells (similar to memory circuit 900A).

[0370] In some embodiments, memory circuit 900A achieves benefits similar to one or more of those discussed herein.

[0371] Other configurations, numbers of transistors, or types of transistors in memory circuit 900A are also within the scope of the present disclosure.

[0372] Fig. 9B is a table 900B that may be used as an AND gate for memory circuit 900A according to some embodiments.

[0373] Table 900B includes values ​​of data signals A and B and values ​​of output signal Vo. In some embodiments, memory circuit 900A is an AND gate and is configured to output output signal Vo as shown in table 900B.

[0374] In some embodiments, the control signals A and B may be used as input signals of an AND gate similar to AND gate 400E, and the control signals A and B are used to generate an output signal Vo consistent with an output value of the AND gate.

[0375] Other configurations or values ​​in table 900B are also within the scope of the present disclosure.

[0376] Fig. 10A is a circuit diagram of a memory circuit 1000A according to some embodiments.

[0377] Fig. 10B is a table 1000B that may be used as a NOR gate 1000C of the memory circuit 1000A, according to some embodiments.

[0378] Fig. 10C is a circuit diagram of a NOR gate 1000C according to some embodiments.

[0379] Fig. 10D is a table 1000D that may be used as a NAND gate 1000E of the memory circuit 1000A, according to some embodiments.

[0380] Fig.10E is a circuit diagram of a NAND gate 1000E according to some embodiments.

[0381] The memory circuit 1000A is schematically represented Figure 1 The embodiments of the adder circuit 104 are described above, and thus similar detailed description is omitted.

[0382] The memory circuit 1000A can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604. In some embodiments, based on at least one of control signal C1, control signal C2, or control signal C3, memory circuit 1000A is configured as NOR gate 1000C or NAND gate 1000E.

[0383] The memory circuit 1000A is Figure 4A The memory circuit 400A is a variation of the memory circuit 400A, and thus similar detailed description is omitted. Figure 4A Compared with the memory circuit 400A, Fig. 10A The memory circuit 1000A also includes an inverter group 1002, so similar detailed description is omitted.

[0384] and Figure 4ACompared with the memory circuit 400A, Fig. 10A The memory circuit 1000A replaces the memory circuit 1004 of Figure 4A The memory circuit 400A is described above, and thus similar detailed description is omitted.

[0385] The memory circuit 1000A includes a memory circuit 1004 and an inverter group 1002 .

[0386] In some embodiments, memory circuit 1004 is Figure 4A The memory circuit 400A is described above, and thus similar detailed description is omitted.

[0387] In some embodiments, inverter group 1002 includes one or more of inverters 1002a, 1002b, 1002c, or 1002d.

[0388] Inverter 1002a is configured to generate a corresponding inverted data signal A' in response to a corresponding data signal A. In some embodiments, data signal A is inverted from inverted data signal A'.

[0389] The input terminal of the inverter 1002a is connected to the source of the data signal A. In some embodiments, the input terminal of the inverter 1002a is connected to the read bit line RBL. The output terminal of the inverter 1002a is connected to the source / drain of the transistor N1a. The output terminal of the inverter 1002a is configured to output the inverted data signal A' to the source / drain terminal of the transistor N1a. In some embodiments, the operation of the memory circuit 1004 is similar to Figure 4A The memory circuit 400A, but Figure 4A The data signal A of the memory circuit 400A is replaced by the inverted data signal A′ in the memory circuit 1000A, and thus similar detailed description is omitted.

[0390] The inverter 1002 b is configured to generate a corresponding inverted data signal A′ in response to the corresponding data signal A.

[0391] The input terminal of the inverter 1002b is connected to the source of the data signal A. In some embodiments, the input terminal of the inverter 1002b is connected to the read bit line RBL. The output terminal of the inverter 1002b is connected to the source / drain of the transistor N2a. The output terminal of the inverter 1002b is configured to output the inverted data signal A' to the source / drain terminal of the transistor N2a. In some embodiments, the operation of the memory circuit 1004 is similar to Figure 4A The memory circuit 400A, but Figure 4A The data signal A of the memory circuit 400A is replaced by the inverted data signal A′ in the memory circuit 1000A, and thus similar detailed description is omitted.

[0392] Inverter 1002c is configured to generate a corresponding inverted data signal B' in response to a corresponding data signal B. In some embodiments, data signal B is inverted from inverted data signal B'.

[0393] The input terminal of the inverter 1002c is connected to the source of the data signal B. In some embodiments, the input terminal of the inverter 1002c is connected to the read bit line RBL. The output terminal of the inverter 1002c is connected to the source / drain terminal of the transistor N3a. The output terminal of the inverter 1002c is configured to output the inverted data signal B' to the source / drain terminal of the transistor N3a. In some embodiments, the operation of the memory circuit 1004 is similar to Figure 4A The memory circuit 400A, but Figure 4A The data signal B of the memory circuit 400A is replaced by the inverted data signal B′ in the memory circuit 1000A, and thus similar detailed description is omitted.

[0394] Inverter 1002d is configured to generate a corresponding inverted data signal B' in response to a corresponding data signal B.

[0395] The input terminal of the inverter 1002d is connected to the source of the data signal B. In some embodiments, the input terminal of the inverter 1002d is connected to the read bit line RBL. The output terminal of the inverter 1002d is connected to the source / drain of the transistor N4a. The output terminal of the inverter 1002d is configured to output the inverted data signal B' to the source / drain terminal of the transistor N4a. In some embodiments, the operation of the memory circuit 1004 is similar to Figure 4A The memory circuit 400A, but Figure 4A The data signal B of the memory circuit 400A is replaced by the inverted data signal B′ in the memory circuit 1000A, and thus similar detailed description is omitted.

[0396] In some embodiments, by adding the inverter group 1002 to the memory circuit 1004 , the memory circuit 1000A is configured as a NOR gate 1000C or a NAND gate 1000E based on at least one of the control signal C1 , the control signal C2 , or the control signal C3 .

[0397] In some embodiments, memory circuit 1000A achieves benefits similar to one or more of those discussed herein.

[0398] Other configurations, numbers of transistors, or types of transistors in memory circuit 1000A are also within the scope of the present disclosure.

[0399] Fig. 10Bis a table 1000B that may be used as a NOR gate 1000C of the memory circuit 1000A, according to some embodiments.

[0400] Table 1000B includes values ​​of control signals C1, C2, and C3, data signals A and B, inverted data signals A' and B', and output signal Vo when memory circuit 1000A is configured as a NOR gate 1000C. In other words, in some embodiments, memory circuit 1000A is configured as a NOR gate 1000C based on the value of at least one of control signal C1, control signal C2, or control signal C3, as shown in Table 1000B.

[0401] For example, as shown in Table 1000B, according to some embodiments, when the control signal C1 is logic low (e.g., logic 0), the control signal C2 is logic low (e.g., logic 0), and the control signal C3 is logic high (e.g., logic 1), the memory circuit 1000A is configured as a NOR gate 1000C. In these embodiments, the data signals A and B can be used as input signals of the NOR gate 1000C and used to generate an output signal Vo consistent with the output value of the NOR gate.

[0402] For example, as shown in Table 1000B, according to some embodiments, when the control signal C1 is logic low (e.g., logic 0), the control signal C2 is logic high (e.g., logic 1), and the control signal C3 is logic low (e.g., logic 0), the memory circuit 1000A is configured as a NOR gate 1000C.

[0403] For example, as shown in Table 1000B, according to some embodiments, when the control signal C1 is logic high (e.g., logic 1), the control signal C2 is logic low (e.g., logic 0), and the control signal C3 is logic low (e.g., logic 0), the memory circuit 1000A is configured as a NOR gate 1000C.

[0404] Other configurations or values ​​in Table 1000B are also within the scope of the present disclosure.

[0405] Fig. 10C is a circuit diagram of a NOR gate 1000C according to some embodiments.

[0406] In some embodiments, the NOR gate 1000C is similar to Figure 4C The NOR gate 400C is thus similarly described in detail.

[0407] In some embodiments, when the values ​​of table 1000B are used for control signal C1 , control signal C2 , and control signal C3 , NOR gate 1000C may be used as memory circuit 1000A.

[0408] Other configurations or numbers of terminals in NOR gate 1000C are also within the scope of the present disclosure.

[0409] Fig. 10D is a table 1000D that may be used as a NAND gate 1000E of the memory circuit 1000A, according to some embodiments.

[0410] Table 1000D includes values ​​of control signals C1, C2, and C3, data signals A and B, inverted data signals A' and B', and output signal Vo when memory circuit 1000A is configured as NAND gate 1000E. In other words, in some embodiments, memory circuit 1000A is configured as NAND gate 1000E based on the value of at least one of control signal C1, control signal C2, or control signal C3, as shown in table 1000D.

[0411] For example, as shown in Table 1000D, according to some embodiments, when the control signal C1 is logic high (e.g., logic 1), the control signal C2 is logic high (e.g., logic 1), and the control signal C3 is logic high (e.g., logic 1), the memory circuit 1000A is configured as a NAND gate 1000E. In these embodiments, the data signals A and B can be used as input signals of the NAND gate 1000E and used to generate an output signal Vo consistent with the output value of the NAND gate.

[0412] Other configurations or values ​​in Table 1000D are also within the scope of the present disclosure.

[0413] Fig.10E is a circuit diagram of a NAND gate 1000E according to some embodiments.

[0414] In some embodiments, when the values ​​of table 1000D are used for control signal C1 , control signal C2 , and control signal C3 , NAND gate 1000E may be used as memory circuit 1000A.

[0415] Other configurations or numbers of terminals in NAND gate 1000E are within the scope of the present disclosure.

[0416] Fig.11A is a circuit diagram of an XOR logic gate 1100A according to some embodiments.

[0417] XOR logic gate 1100A is schematically represented Figure 1 The embodiments of the adder circuit 104 are described above, and thus similar detailed description is omitted.

[0418] The XOR logic gate 1100A can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604.

[0419] The XOR logic gate 1100A is configured to generate an output signal OUT1 in response to the data signal A and the data signal B.

[0420] XOR logic gate 1100A includes AND gate 1110 , AND gate 1112 , and NOR gate 1114 .

[0421] In some embodiments, when configured as Fig.10E The NOR gate 1000E, NOR gate 1114 is Fig. 10A The memory circuit 1000A is described above, and thus similar detailed description is omitted.

[0422] In some embodiments, when configured as Figure 4E When the AND gate 400E is configured, at least one of the AND gate 1110 or the AND gate 1112 is Figure 4A Therefore, similar detailed description is omitted. In some embodiments, when configured as Fig. 7E When the AND gate 700E is configured, at least one of the AND gate 1110 or the AND gate 1112 is Fig. 7A Therefore, similar detailed description is omitted. In some embodiments, when configured as Fig. 8E When the AND gate 800E is configured, at least one of the AND gate 1110 or the AND gate 1112 is Fig. 8A Therefore, similar detailed description is omitted. In some embodiments, when configured as Figure 8B When AND is formed, at least one of AND gate 1110 or AND gate 1112 is Fig.9A The memory circuit 900A is described below, and thus similar detailed description is omitted.

[0423] AND gate 1110 is configured to generate signal IS1 in response to data signal A and data signal B. In some embodiments, signal IS1 corresponds to an AND operation of data signal B and data signal A.

[0424] A first input terminal of AND gate 1110 is connected to a source of data signal A. A second input terminal of AND gate 1110 is connected to a source of data signal B. In some embodiments, both the first input terminal of AND gate 1110 and the second input terminal of AND gate 1110 are connected to a read bit line RBL.

[0425] A first input terminal of AND gate 1110 is configured to receive data signal A. A second input terminal of AND gate 1110 is configured to receive data signal B.

[0426] The output terminal of the AND gate 1110 is configured to output the signal IS1 to a first input terminal of the NOR gate 1114 .

[0427] NAND gate 1112 is configured to generate signal IS2 in response to data signal A and data signal B. In some embodiments, signal IS2 corresponds to a NAND operation of data signal B and data signal A.

[0428] A first input terminal of NAND gate 1112 is connected to the source of data signal A. A second input terminal of NAND gate 1112 is connected to the source of data signal B. In some embodiments, both the first input terminal of NAND gate 1112 and the second input terminal of NAND gate 1112 are connected to read bit line RBL.

[0429] A first input terminal of the NAND gate 1112 is configured to receive a data signal A. A second input terminal of the NAND gate 1112 is configured to receive a data signal B.

[0430] The output terminal of the NAND gate 1112 is configured to output the signal IS2 to the second input terminal of the NOR gate 1114 .

[0431] NOR gate 1114 is configured to generate output signal OUT1 in response to signal IS1 and signal IS2. In some embodiments, output signal OUT1 corresponds to a NOR operation of signal IS1 and signal IS2. In some embodiments, NOR gate 1114 is a FEOL logic circuit. In some embodiments, AND gate 1110 and NAND gate 1112 are corresponding BEOL logic circuits.

[0432] A first input terminal of the NOR gate 1114 is coupled to the output terminal of the AND gate 1110. A second input terminal of the NOR gate 1114 is coupled to the output terminal of the NAND gate 1112.

[0433] A first input terminal of the NOR gate 1114 is configured to receive a signal IS1. A second input terminal of the NOR gate 1114 is configured to receive a signal IS2.

[0434] The output terminal of the NOR gate 1114 is configured to output a signal OUT1 .

[0435] In some embodiments, XOR logic gate 1100A achieves benefits similar to one or more of those discussed herein.

[0436] Other configurations, numbers of circuits, or transistor types in the XOR logic gate 1100A are also within the scope of the present disclosure.

[0437] Fig. 11B is a circuit diagram of an XOR logic gate 1100B according to some embodiments.

[0438] The XOR logic gate 1100B is Figure 1 An embodiment of the adder circuit 104 is schematically shown, and thus similar detailed description is omitted.

[0439] The XOR logic gate 1100B can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604.

[0440] The XOR logic gate 1100B is configured to generate an output signal OUT2 in response to the data signal A and the data signal B.

[0441] XOR logic gate 1100B includes an OR gate 1120 , a NOR gate 1122 , and an AND gate 1124 .

[0442] In some embodiments, when configured as Fig.10E The NOR gate 1000E, NOR gate 1122 is Fig. 10A The memory circuit 1000A is described above, and thus similar detailed description is omitted.

[0443] In some embodiments, when configured as Figure 4E The OR gate is 400C, the OR gate 1120 is Figure 4A Therefore, similar detailed description is omitted. In some embodiments, when configured as Figure 7C The OR gate is 700C, the OR gate is 1120 Fig. 7A Therefore, similar detailed description is omitted. In some embodiments, when configured as Figure 8C The OR gate is 800C, the OR gate is 1120 Fig. 8A The memory circuit 800A is described above, and thus similar detailed description is omitted.

[0444] In some embodiments, when AND gate 1124 is configured as Figure 4E The AND gate 400E, AND gate 1124 is Figure 4A Memory circuit 400A, therefore similar detailed description is omitted. In some embodiments, when AND gate 1124 is configured as Fig. 7E The AND gate 700E, AND gate 1124 is Fig. 7A Memory circuit 700A, therefore similar detailed description is omitted. In some embodiments, when AND gate 1124 is configured as Fig. 8E The AND gate 800E, AND gate 1124 is Fig. 8A Memory circuit 800A, therefore similar detailed description is omitted. In some embodiments, when configured as Fig. 9B AND gate, AND gate 1124 is Fig.9A The memory circuit 900A is described below, and thus similar detailed description is omitted.

[0445] OR gate 1120 is configured to generate signal IS3 in response to data signal A and data signal B. In some embodiments, signal IS3 corresponds to an OR operation of data signal B and data signal A.

[0446] A first input terminal of the OR gate 1120 is connected to the source of the data signal A. A second input terminal of the OR gate 1120 is connected to the source of the data signal B. In some embodiments, the first input terminal of the OR gate 1120 and the second input terminal of the OR gate 1120 are both connected to the read bit line RBL.

[0447] The first input terminal of the OR gate 1120 is used to receive the data signal A. The second input terminal of the OR gate 1120 is used to receive the data signal B.

[0448] The output terminal of the OR gate 1120 is configured to output the signal IS3 to the first input terminal of the AND gate 1124 .

[0449] NOR gate 1122 is configured to generate signal IS4 in response to data signal A and data signal B. In some embodiments, signal IS4 corresponds to a NOR operation of data signal B and data signal A.

[0450] The first input terminal of the NOR gate 1122 is connected to the source of the data signal A. The second input terminal of the NOR gate 1122 is connected to the source of the data signal B. In some embodiments, the first input terminal of the NOR gate 1122 and the second input terminal of the NOR gate 1122 are both connected to the read bit line RBL.

[0451] The first input terminal of the NOR gate 1122 is used to receive the data signal A. The second input terminal of the NOR gate 1122 is used to receive the data signal B.

[0452] The output terminal of the NOR gate 1122 is configured to output the signal IS4 to the second input terminal of the AND gate 1124 .

[0453] AND gate 1124 is configured to generate output signal OUT2 in response to signal IS3 and signal IS4. In some embodiments, output signal OUT2 corresponds to an AND operation of signal IS3 and signal IS4. In some embodiments, AND gate 1124 is a FEOL logic circuit. In some embodiments, OR gate 1120 and NOR gate 1122 are corresponding BEOL logic circuits.

[0454] A first input terminal of the AND gate 1124 is coupled to the output terminal of the OR gate 1120. A second input terminal of the AND gate 1124 is coupled to the output terminal of the NOR gate 1122.

[0455] A first input terminal of the AND gate 1124 is configured to receive the signal IS3. A second input terminal of the AND gate 1124 is configured to receive the signal IS4.

[0456] The output terminal of the AND gate 1124 is configured to output the output signal OUT2 .

[0457] In some embodiments, XOR logic gate 1100B achieves benefits similar to one or more of those discussed herein.

[0458] Other configurations, numbers of circuits, or transistor types in the XOR logic gate 1100B are also within the scope of the present disclosure.

[0459] Fig. 12A is a circuit diagram of a full adder circuit 1200A according to some embodiments.

[0460] Fig. 12B is a flow chart of a method of operating a circuit according to some embodiments.

[0461] The full adder circuit 1200A is Figure 1 An embodiment of the adder circuit 104 is schematically shown, and thus similar detailed description is omitted.

[0462] The full adder circuit 1200A can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604.

[0463] The full adder circuit 1200A is configured to generate a sum signal Sn and a carry signal CIin in response to a data signal An and a data signal Bn. In some embodiments, the sum signal Sn is the nth bit of the sum signal S. In some embodiments, the data signal An is the nth bit of the data signal A. In some embodiments, the data signal Bn is the nth bit of the data signal B.

[0464] Full adder circuit 1200A includes XOR logic gate 1202 , XOR logic gate 1204 , and circuit 1206 .

[0465] In some embodiments, XOR logic gate 1202 is Fig.11A In some embodiments, the XOR logic gate 1204 is Fig.11A The XOR logic gate 1100A is thus similarly described in detail.

[0466] XOR logic gate 1202 includes AND gate 1210a, NAND gate 1212a, and NOR gate 1214a.

[0467] In some embodiments, AND gate 1210a is Fig.11A AND gate 1110, NAND gate 1212a is Fig.11A The NAND gate 1112 and NOR gate 1214a are shown as Fig.11A The NOR gate 1112 in FIG. 1 is used for the circuit diagram of FIG. 1 , and thus a similar detailed description is omitted.

[0468] AND gate 1210a is configured to generate signal IS1a in response to data signal An and data signal Bn. In some embodiments, signal IS1a corresponds to an AND operation of data signals An / Bn.

[0469] A first input terminal of AND gate 1210a is coupled to a source of data signal An. A second input terminal of AND gate 1210a is coupled to a source of data signal Bn. In some embodiments, a first input terminal of AND gate 1210a and a second output terminal of AND gate 1210b are coupled to a read bit line RBL.

[0470] A first input terminal of the AND gate 1210a is configured to receive a data signal An. A second input terminal of the AND gate 1210a is configured to receive a data signal Bn.

[0471] The output terminal of the AND gate 1210 a is configured to output the signal IS1 a to a first input terminal of the OR gate 1214 a .

[0472] The NAND gate 1212a is configured to generate a signal IS2a in response to the data signal An and the data signal Bn. In some embodiments, the signal IS2a corresponds to a NAND operation of the data signal An / Bn.

[0473] A first input terminal of NAND gate 1212a is coupled to a source of data signal An. A second input terminal of NAND gate 1212b is coupled to a source of data signal Bn. In some embodiments, a first input terminal of NAND gate 1212a and a second output terminal of NAND gate 1212 are coupled to read bit line RBL.

[0474] A first input terminal of the NAND gate 1212a is configured to receive a data signal An. A second input terminal of the NAND gate 1212a is configured to receive a data signal Bn.

[0475] The output terminal of the NAND gate 1212 a is configured to output the signal IS2 a to the second input terminal of the OR gate 1214 a .

[0476] The NOR gate 1214a is configured to generate an output signal OS1a in response to the signal IS1a and the signal IS2a. In some embodiments, the output signal OS1a corresponds to a NOR operation of the signal IS1a and the signal IS2a.

[0477] A first input terminal of the NOR gate 1214a is connected to the output terminal of the AND gate 1210a. A second input terminal of the NOR gate 1214a is coupled to the output terminal of the NAND gate 1212a.

[0478] A first input terminal of the NOR gate 1214a is configured to receive the signal IS1a. A second input terminal of the NOR gate 1214a is configured to receive the signal IS2a.

[0479] The output terminal of the NOR gate 1214a is configured to output the output signal OS1a. The output terminal of the NOR gate 1214a is coupled to the first input terminal of the AND gate 1210b, the first input terminal of the NAND gate 1212b, and the second input terminal of the AND gate 1220.

[0480] XOR logic gate 1204 includes AND gate 1210b, NAND gate 1212b, and NOR gate 1214b.

[0481] In some embodiments, AND gate 1210b is Fig.11A AND gate 1110, NAND gate 1212b is Fig.11A The NAND gate 1112 and NOR gate 1214b are Fig.11A The NOR gate 1112 is shown, and thus a similar detailed description is omitted.

[0482] AND gate 1210b is configured to generate signal IS1b in response to signal OS1a and carry signal CIin-1. In some embodiments, signal IS1b corresponds to an AND operation of signal OS1a and carry signal CIin-1.

[0483] A first input terminal of AND gate 1210b is connected to an output terminal of NOR gate 1214a. A second input terminal of AND gate 1210b is coupled to a source of carry signal CIin-1. In some embodiments, a second input terminal of AND gate 1210b is coupled to an output terminal of OR gate 1224.

[0484] A first input terminal of the AND gate 1210 b is configured to receive the signal OS1 a . A second input terminal of the AND gate 1210 b is configured to receive the carry signal CIin- 1 .

[0485] The output terminal of the AND gate 1210 b is configured to output the signal IS1 b to the first input terminal of the OR gate 1214 b .

[0486] The NAND gate 1212b is configured to generate a signal IS2b in response to the signal OS1a and the carry signal CIin-1. In some embodiments, the signal IS2b corresponds to a NAND operation of the signal OS1a and the carry signal CIin-1.

[0487] A first input terminal of NAND gate 1212b is coupled to an output terminal of NOR gate 1214a. A second input terminal of NAND gate 1212b is coupled to a source of carry signal CIin-1. In some embodiments, a second input terminal of NAND gate 1212b is coupled to an output terminal of OR gate 1224.

[0488] A first input terminal of the NAND gate 1212 b is configured to receive the signal OS1 a . A second input terminal of the NAND gate 1212 b is configured to receive the carry signal CIin- 1 .

[0489] The output terminal of the NAND gate 1212 b is configured to output the signal IS2 b to the second input terminal of the OR gate 1214 b .

[0490] The NOR gate 1214b is configured to generate a sum signal Sn in response to the signal IS1b and the signal IS2b. In some embodiments, the sum signal Sn corresponds to a NOR operation of the signal IS1b and the signal IS2b.

[0491] A first input terminal of NOR gate 1214b is connected to the output terminal of AND gate 1210b. A second input terminal of NOR gate 1214b is coupled to the output terminal of NAND gate 1212b.

[0492] A first input terminal of the NOR gate 1214b is configured to receive the signal IS1b. A second input terminal of the NOR gate 1214b is configured to receive the signal IS2b.

[0493] The output terminal of the NOR gate 1214 b is configured to output the sum signal Sn.

[0494] Circuit 1206 includes AND gate 1220 , AND gate 1222 , and OR gate 1224 .

[0495] In some embodiments, AND gate 1220 is Fig.11A The AND gate 1110 and AND gate 1222 are Fig.11A The AND gate 1100 and OR gate 1224 are Fig. 11B The OR gate 1120 in FIG. 1 is used, and thus similar detailed description is omitted.

[0496] AND gate 1220 is configured to generate signal IS5 in response to signal OS1a and carry signal CIin-1. In some embodiments, signal IS5 corresponds to an AND operation of signal OS1a and carry signal CIin-1.

[0497] The second input terminal of AND gate 1220 is connected to the output terminal of NOR gate 1214a. The first input terminal of AND gate 1220 is coupled to the source of carry signal CIin-1. In some embodiments, the first input terminal of AND gate 1220 is coupled to the output terminal of OR gate 1224.

[0498] The second input terminal of the AND gate 1220 is configured to receive the signal OS1a. The first input terminal of the AND gate 1220 is configured to receive the carry signal CIin-1.

[0499] The output terminal of the AND gate 1220 is configured to output the signal IS5 to a first input terminal of the OR gate 1224 .

[0500] AND gate 1222 is configured to generate signal IS6 in response to data signal An and data signal Bn. In some embodiments, signal IS6 corresponds to an AND operation of data signal An / Bn.

[0501] The first input terminal of AND gate 1222 is connected to the source of data signal An. The second input terminal of AND gate 1222 is connected to the source of data signal Bn. In some embodiments, the first input terminal of AND gate 1222 and the second input terminal of AND gate 1222 are both connected to read bit line RBL.

[0502] A first input terminal of the AND gate 1222 is configured to receive a data signal An. A second input terminal of the AND gate 1222 is configured to receive a data signal Bn.

[0503] The output terminal of the AND gate 1222 is configured to output the signal IS6 to the second input terminal of the OR gate 1224 .

[0504] OR gate 1224 is configured to generate a carry signal CIin in response to signal IS5 and signal IS6. In some embodiments, carry signal CIin corresponds to an OR operation of signal IS5 and signal IS6.

[0505] A first input terminal of the OR gate 1224 is coupled to the output terminal of the AND gate 1220. A second input terminal of the OR gate 1224 is coupled to the output terminal of the AND gate 1222.

[0506] A first input terminal of the OR gate 1224 is configured to receive the signal IS5. A second input terminal of the OR gate 1224 is configured to receive the signal IS6.

[0507] The output terminal of the OR gate 1224 is configured to output a carry signal CIin.

[0508] In some embodiments, the full adder circuit 1200A achieves benefits similar to one or more of those discussed herein.

[0509] Other configurations, numbers of circuits, or transistor types in the full adder circuit 1200A are also within the scope of the present disclosure.

[0510] Fig. 12B is a flow chart of a method 1200B of operating a circuit according to some embodiments.

[0511] In some embodiments, Fig. 12B is a flow chart of a method 1200B of operating a circuit, such as the full adder circuit 1200A.

[0512] In some embodiments, method 1200B uses one or more aspects of full adder circuit 1200A.

[0513] It should be understood that Fig. 12B Additional operations may be performed before, during, and / or after the method 1200B shown, and some other processes may only be briefly described herein. In some embodiments, other operation sequences of method 1200B are within the scope of the present disclosure. Method 1200B includes exemplary operations, but these operations are not necessarily performed in the order shown. According to the spirit and scope of the disclosed embodiments, operations may be appropriately added, replaced, changed in order, and / or eliminated. In some embodiments, one or more operations of method 1200B are not performed.

[0514] In operation 1230 of method 1200B, full adder circuit 1200A performs a setup mode. In some embodiments, the setup mode of method 1200B includes writing each bit of data signals An and Bn. In some embodiments, operation 1230 is performed by a controller (eg, controller 120 or 606).

[0515] In operation 1232 of method 1200B, full adder circuit 1200A executes a calculation mode. In some embodiments, the calculation mode of method 1200B includes writing carry signal CIin-1 to XOR logic gate 1204, reading signal OS1a from XOR logic gate 1202, and writing signal OS1a to XOR logic gate 1204.

[0516] In operation 1234 of method 1200B, full adder circuit 1200A executes a carry mode. In some embodiments, the carry mode of method 1200B includes reading out a carry signal CIin from circuit 1206.

[0517] In some embodiments, the carry mode of method 1200B includes reading the carry signal CIin from circuit 1206 and then returning to operation 1232. In some embodiments, operation 1234 returns to operation 1232 to write the next carry signal CIin to XOR logic gate 1204.

[0518] In operation 1236 of method 1200B, full adder circuit 1200A performs a readout mode. In some embodiments, the readout mode of method 1200B includes outputting a sum signal Sn.

[0519] In some embodiments, operation 1236 is performed after buffering each bit of the sum signal Sn, and then the entire sum signal Sn (eg, each bit in the sum signal Sn) is output simultaneously. In some embodiments, operation 1236 is performed to output the sum signal Sn in a bit-by-bit order.

[0520] By using the method 1200B, the circuit operates to achieve one or more benefits discussed in the present disclosure.

[0521] Although the method 1200B is described above with reference to a single full adder circuit (e.g., full adder circuit 1200A), it should be understood that in some embodiments, the method 1200B is applicable to multiple full adder circuits, such as Fig.13 An n-bit adder circuit 1300 is provided.

[0522] Other operations of method 1200B are within the scope of the present disclosure.

[0523] Fig.13 is a circuit diagram of an n-bit adder circuit 1300 according to some embodiments.

[0524] The N-bit adder circuit 1300 is schematically represented as Figure 1 The embodiments of the adder circuit 104 are described above, and thus similar detailed description is omitted.

[0525] The N-bit adder circuit 1300 can be used as Figure 1 The adder circuit 104 or Figure 6 Adder circuit 604.

[0526] The N-bit adder circuit 1300 is configured to generate an n-bit sum signal Sn and an n-bit carry signal CIn in response to an n-bit data signal An and an n-bit data information Bn. In some embodiments, the sum signal Sn is the nth bit of the sum signal S. In some embodiments, the carry signal CIn is the nth bit of the carry signal CI. In some embodiments, the data signal An is the nth bit of the data signal A. In some embodiments, the data signal Bn is the nth bit of the data signal B.

[0527] The n-bit adder circuit 1300 includes a full adder circuit 1302 , a full adder circuit 1304 , a full adder circuit 1306 , a full adder circuit 1308 , and a full adder circuit 1310 .

[0528] In some embodiments, at least one or more of full adder circuit 1302, full adder circuit 1304, full adder circuit 1306, full adder circuit 1308, or full adder circuit 1310 is Fig. 12A The full adder circuit 1200A is described below, and thus similar detailed description is omitted.

[0529] In some embodiments, at least one or more of full adder circuit 1302, full adder circuit 1304, full adder circuit 1306, full adder circuit 1308, or full adder circuit 1310 operate similarly to Fig. 12B Method 1200B, therefore similar detailed description is omitted.

[0530] Each of full adder circuit 1302, full adder circuit 1304, full adder circuit 1306, full adder circuit 1308, and full adder circuit 1310 are connected together in a cascade fashion.

[0531] In some embodiments, the n-bit adder 1300 is referred to as a “ripple carry adder” because each carry bit (eg, Cn) “ripples” to an adjacent full adder (eg, full adder circuits 1302, 1304, 1306, 1308, or 1310).

[0532] Full adder circuit 1302 is coupled to an input terminal of full adder circuit 1304. Full adder circuit 1302 is configured to receive data signal A0 and data signal B0. Full adder circuit 1302 is configured to generate sum signal S0 and carry signal CI1 in response to data signal A0 and data signal B0. Full adder circuit 1302 is configured to output sum signal S0 and carry signal CI1.

[0533] The full adder circuit 1304 is connected between the output terminal of the full adder circuit 1302 and the input terminal of the full adder circuit 1306. The full adder circuit 1304 is configured to receive the data signal A1, the data signal B1 and the carry signal CI1. The full adder circuit 1304 is configured to generate the sum signal S1 and the carry signal Cl2 in response to the data signal A1, the data signal B1 and the carry signal CI1. The full adder circuit 1304 is configured to output the sum signal S1 and the carry signal CI2.

[0534] The full adder circuit 1306 is connected between the output terminal of the full adder circuit 1304 and the input terminal of the full adder circuit 1308. The full adder circuit 1306 is configured to receive the data signal A2, the data signal B2 and the carry signal CI2. The full adder circuit 1306 is configured to generate the sum signal S2 and the carry signal CI3 in response to the data signal A2, the data signal B2 and the carry signal CI2. The full adder circuit 1306 is configured to output the sum signal S2 and the carry signal CI3.

[0535] The full adder circuit 1308 is connected between the output terminal of the full adder circuit 1306 and the input terminal of the full adder circuit 1310. The full adder circuit 1308 is configured to receive the data signal An-1, the data signal Bn-1 and the carry signal CIn-1. The full adder circuit 1308 is configured to generate the sum signal Sn-1 and the carry signal Cln in response to the data signal An-1, the data signal Bn-1 and the carry signal CIn-1. The full adder circuit 1308 is configured to output the sum signal Sn-1 and the carry signal CIn.

[0536] Full adder circuit 1310 is coupled to the output terminal of full adder circuit 1308. Full adder circuit 1310 is configured to receive data signal An, data signal Bn and carry signal CIn. Full adder circuit 1310 is configured to generate sum signal Sn and carry signal Cln+1 in response to data signal An, data signal Bn and carry signal CIn. Full adder circuit 1310 is configured to output sum signal Sn and carry signal CIn+1.

[0537] In some embodiments, the n-bit adder circuit 1300 achieves benefits similar to one or more of those discussed herein.

[0538] In some embodiments, when the least significant bit (LSB) of the n-bit adder circuit 1300 is in calculation mode (similar to Fig. 12B 1232), the most significant bit (MSB) of the n-bit adder circuit 1300 is in a setting mode (similar to operation 1230 of Table 12B), thereby reducing the idle time of the n-bit adder circuit 1300.

[0539] In some embodiments, in carry mode (similar to Fig. 12B After operation 1234 of the n-bit adder circuit 1300, the LSB is converted to a read mode that directly outputs the output (similar to Fig. 12B Operation 1236), or the LSB of the n-bit adder circuit 1300 is switched to a standby state, thereby preventing unnecessary power consumption.

[0540] In some embodiments, by using n-bit adder circuit 1300 as Figure 1 The adder circuit 104 or Figure 6 The n-bit adder circuit 1300 improves the efficiency of the n-bit adder circuit 1300 by reducing the idle time of the n-bit adder circuit 1300 and saving the power of the n-bit adder circuit 1300. Figure 1 The speed and performance of the memory device 100.

[0541] Other configurations, numbers of circuits, or transistor types in the n-bit adder circuit 1300 are also within the scope of the present disclosure.

[0542] Fig.14 is a circuit diagram of a memory circuit 1400 according to some embodiments.

[0543] The memory circuit 1400 is schematically represented Figure 1 The embodiments of the adder circuit 104 are described above, and thus similar detailed description is omitted.

[0544] The memory circuit 1400 can be used as Figure 1 The adder circuit 104 or Figure 6 In some embodiments, the memory circuit 1400 is configured as an OR gate (similar to Figure 4C OR gate 400C) or AND gate (similar to Figure 4E AND gate 400E).

[0545] The memory circuit 1400 is Figure 4A The memory circuit 400A is a variation of the memory circuit 400A, and thus similar detailed description is omitted. Figure 4A Compared with the memory circuit 400A, Fig.14 The transistor N1c, the transistor N2c, the transistor N3c, the transistor N4c, the transistor N5c, the transistor N6c or the transistor N7c is replaced by Figure 4A The transistors N1b, N2b, N3b, N4b, N5b, N6b, or N7b of the transistors are described above, and thus similar detailed descriptions are omitted.

[0546] The memory circuit 1400 includes a transistor N1a, a transistor N1c, a transistor N2a, a transistor N2c, a transistor N3a, a transistor N3c, a transistor N4a, a transistor N4c, a transistor N5a, a transistor N5c, a transistor N6a, a transistor N6c, a transistor N7a, and a transistor N7c.

[0547] In some embodiments, each of transistors N1c, N2c, N3c, N4c, N5c, N6c, or N7c is a respective ferroelectric field effect transistor (FeFET) device.

[0548] In some embodiments, each of the transistors N1c, N2c, N3c, N4c, N5c, N6c or N7c is a corresponding FeFET device and includes a corresponding ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412 or 1414 located within the corresponding gate terminal of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c or N7c.

[0549] The ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412, or 1414 is configured to have different polarization states based on the corresponding voltage applied to the corresponding gate of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c. The polarization of the ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412, or 1414 determines the conductivity (e.g., low resistance state or high resistance state) of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c, which represents the data stored in the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c.

[0550] Data is stored by programming the ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412, or 1414 to have different polarization states. The different polarization states generate two different threshold voltage states (e.g., Vth), corresponding to logic "1" and logic "0", respectively. Due to the threshold voltage difference, the ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412, or 1414 in the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c is configured to be turned on using a specific gate voltage based on its logic state. In some embodiments, the difference between these gate voltages is called a memory window.

[0551] The binary state of the data stored in the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c is encoded in the polarization of the ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412, or 1414. The polarization direction or value (e.g., +P or -P) of the ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412, or 1414 determines the resistance state (e.g., low or high) of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c. In some embodiments, the low resistance state of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c or N7c corresponds to the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c or N7c being turned on or conducting, and the high resistance state of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c or N7c corresponds to the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c or N7c being turned off or not conducting. In some embodiments, the low resistance state of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c corresponds to a first storage value (e.g., logic "0" or "1"), and the high resistance state of the corresponding transistor N1c, N2c, N3c, N4, N5c, N6c, or N7c corresponds to a second storage value opposite to the first storage value (e.g., logic "1" or "0"). The voltage of the gate or storage node of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c controls the polarization state and the corresponding electric field in the ferroelectric region 1402, 1404, 1406, 1408, 1410, 1412, or 1414 of the corresponding transistor N1c, N2c, N3c, N4c, N5c, N6c, or N7c.

[0552] In some embodiments, memory circuit 1400 achieves benefits similar to one or more of those discussed herein.

[0553] Other configurations, numbers of transistors, or types of transistors in memory circuit 1400 are also within the scope of the present disclosure.

[0554] Fig.15 is a cross-sectional view of an integrated circuit 1500 according to some embodiments.

[0555] IC 1500 is Fig.14 The integrated circuit 1500 is not limited to one or more embodiments of the transistor N1c, transistor N2c, transistor N3c, transistor N4c, transistor N5c, transistor N6c, or transistor N7c, and thus similar detailed descriptions are omitted. In some embodiments, the integrated circuit 1500 includes additional elements that are not shown for ease of illustration.

[0556] Integrated circuit 1500 is shown as a planar transistor; however, other transistors are also within the scope of the present disclosure. In some embodiments, integrated circuit 1500 is a fin field effect transistor (FinFET), a nanosheet transistor, a nanowire transistor, etc. In some embodiments, integrated circuit 1500 is manufactured as part of a front-end of line (FEOL) process. In some embodiments, integrated circuit 1500 is a FeFET, etc., and is manufactured as part of a back-end of line (BEOL) process.

[0557] Integrated circuit 1500 includes substrate 1502. In some embodiments, substrate 1502 is a p-type substrate. In some embodiments, substrate 1502 is an n-type substrate. In some embodiments, substrate 1502 includes: elemental semiconductors, including silicon or germanium in crystalline, polycrystalline or amorphous structures; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe component, wherein the Si and Ge composition changes from one ratio at one position of the gradient SiGe component to another ratio at another position. In some embodiments, alloy SiGe is formed over a silicon substrate. In some embodiments, first substrate 1502 is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epitaxial layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure.

[0558] In some embodiments, the integrated circuit 1500 is a silicon transistor (e.g., having a silicon channel region (not labeled)), and the substrate 1502 has a silicon body or bulk. In some embodiments, the integrated circuit 1500 is an oxide transistor (e.g., having an oxide channel region), and the substrate 1502 includes an oxide semiconductor material, including zinc oxide, cadmium oxide, indium oxide, IGZO, SnO2, TiO2, or a combination thereof.

[0559] Integrated circuit 1500 also includes drain region 1504 and source region 1506 in substrate 1502. In some embodiments, at least a portion of source region 1506 or a portion of drain region 1504 extends over substrate 1502. In some embodiments, source region 1506 and drain region 1504 are embedded in substrate 1502.

[0560] The drain region 1504 is Fig.14The source region 1506 is an embodiment of the drain terminal of the transistor N1c, the transistor N2c, the transistor N3c, the transistor N4c, the transistor N5c, the transistor N6c or the transistor N7c, and thus similar detailed description is omitted. Fig.14 The source terminal of the transistor N1c, the transistor N2c, the transistor N3c, the transistor N4c, the transistor N5c, the transistor N6c or the transistor N7c of the embodiment is described above, and thus similar detailed description is omitted.

[0561] In some embodiments, Fig.15 The drain region 1504 and the source region 1506 are referred to as oxide definition (OD) regions, which define the integrated circuit 1500 or Fig.14 The source or drain diffusion region of the transistor N1c, the transistor N2c, the transistor N3c, the transistor N4c, the transistor N5c, the transistor N6c or the transistor N7c is described above, and thus similar detailed description is omitted.

[0562] In some embodiments, the integrated circuit 1500 is a P-type FeFET transistor, so the substrate 1502 is an N-type region, the drain region 1504 is a P-type active region in which P-type dopants are injected into the substrate 1502, and the source region 1506 is a P-type active region in which P-type dopants are injected into the substrate 1502.

[0563] In some embodiments, the integrated circuit 1500 is an N-type FeFET transistor, so the substrate 1502 is a P-type region, the drain region 1504 is an N-type active region in which N-type dopants are injected into the substrate 1502, and the source region 1506 is an N-type active region in which N-type dopants are injected into the substrate 1502.

[0564] In some embodiments, the N-type dopant includes phosphorus, arsenic, or other suitable N-type dopant. In some embodiments, the P-type dopant includes boron, aluminum, or other suitable P-type dopant.

[0565] Integrated circuit 1500 also includes an insulating layer 1510 on substrate 1502. In some embodiments, insulating layer 1510 is located between drain region 1504 and source region 1506. In some embodiments, insulating layer 1510 is a gate dielectric layer. In some embodiments, insulating layer includes an insulating material including SiO, SiO2, or a combination thereof, etc. In some embodiments, insulating layer 1510 includes a gate oxide, etc.

[0566] Integrated circuit 1500 further includes a metal layer 1512 on insulating layer 1510. In some embodiments, metal layer 1512 includes Cu, TiN, W, or a combination thereof. In some embodiments, metal layer 1512 is a conductive layer including doped polysilicon. In some embodiments, integrated circuit 1500 does not include metal layer 1512.

[0567] Integrated circuit 1500 further includes a ferroelectric layer 1520 on at least conductive layer 1512 or insulating layer 1510. In some embodiments, integrated circuit 1500 does not include metal layer 1512, and ferroelectric layer 1520 is located on insulating layer 1510. Ferroelectric layer 1520 is Fig.14 The embodiments of one or more of the ferroelectric regions 1402, 1404, 1406, 1408, 1410, 1412 or 1414 are described below, and thus similar detailed descriptions are omitted.

[0568] In some embodiments, the ferroelectric layer 1520 includes a ferroelectric material. In some embodiments, the ferroelectric material includes HfO2, HfZrO, HfO, perovskite, SBT, PZT, or a combination thereof.

[0569] The ferroelectric layer 1520 has Fig.15 The polarization state P1 or P2 corresponds to the polarization state P+ or P- in the first direction Y. Therefore, similar detailed description is omitted. The polarization state P1 points to a first direction Y. The polarization state P2 points to a second direction opposite to the first direction Y (eg, negative Y).

[0570] Fig.15 Polarization states P1 and P2 are shown. However, in some embodiments, due to the non-volatility of ferroelectric layer 1520, once the gate voltage V G The polarization state P1 or P2 of the integrated circuit 1500 is set, and the integrated circuit 1500 includes one of the polarization states P1 and P2.

[0571] Ferroelectric layer 1520 generates capacitance in integrated circuit 1500. In addition, MOS transistors of integrated circuit 1500 also have capacitance. In some embodiments, the capacitance of ferroelectric layer 1520 and the capacitance of MOS transistors are matched to operate integrated circuit 1500 in non-volatile mode. In some embodiments, ferroelectric layer 1520 is adjusted based on the thickness T1 of ferroelectric layer 1520. In some embodiments, by changing the thickness T1, integrated circuit 1500 can operate in non-volatile mode or volatile mode.

[0572] In some embodiments, the thickness T1 of the ferroelectric layer 1520 is in a range of about 3 nanometers (nm) to about 50 nm. In some embodiments, as the thickness T1 increases, the ability of the ferroelectric layer 1520 to maintain hysteresis and bistability (e.g., P1 or P2) increases, and the leakage current of the integrated circuit 1500 decreases. In some embodiments, as the thickness T1 decreases, the ability of the ferroelectric layer 1520 to maintain hysteresis and bistability (e.g., P1 or P2) decreases, and the leakage current of the integrated circuit 1500 increases. In some embodiments, the integrated circuit 1500 does not include the insulating layer 1510 and the metal layer 1512, and the ferroelectric layer 1520 is directly located on the substrate 1502. In some embodiments, the integrated circuit 1500 does not include the insulating layer 1510, and the metal layer 1512 is directly located on the substrate 1502.

[0573] Integrated circuit 1500 also includes a gate structure 1530 on ferroelectric layer 1520. Gate structure 1530 includes a conductive material, such as metal or doped polysilicon (also referred to herein as "POLY").

[0574] In some embodiments, integrated circuit 1500 is Figure 4A and Fig.14 In these embodiments, integrated circuit 1500 does not include ferroelectric layer 1520.

[0575] In some embodiments, integrated circuit 1500 achieves benefits similar to one or more of those discussed herein.

[0576] Other configurations, numbers of layers, or other layer types in integrated circuit 1500 are also within the scope of the present disclosure.

[0577] Fig.16 is a cross-sectional view of an integrated circuit 1600 according to some embodiments.

[0578] Integrated circuit 1600 is an embodiment of one or more transistors in memory circuits 400A, 600, 700A, 800A, 900A, 1000A, 1100A, 1100B, 1200A, 1300, or 1400, and thus similar detailed description is omitted. In some embodiments, integrated circuit 1500 includes additional elements that are not shown for ease of illustration.

[0579] The integrated circuit 1600 includes a substrate 1602 , FEOL transistors 1604 a , 1604 b , and 1604 c , an interconnect 1604 , and a BEOL transistor 1610 .

[0580] In some embodiments, substrate 1602 is Fig.15 The substrate 1502 in FIG. 1 is a substrate 1502 in FIG. 1 , and the FEOL transistors 1604a, 1604b, and 1604c are Fig.15 The integrated circuit 1500 is described above, and thus similar detailed description is omitted.

[0581] In some embodiments, at least one of the FEOL transistors 1604a, 1604b, or 1604c is one or more transistors described herein, e.g. Figure 4A and Fig.14 One or more of the transistors N1a, N1b, N2a, N2b, N3a, N3b, N4a, N4b, N5a, N5b, N6a, N6b, N7a or N7b in the circuit are described, and thus similar detailed description is omitted.

[0582] In some embodiments, BEOL transistor 1610 is one or more transistors described herein, such as Fig.14 One or more of the transistor N1c, the transistor N2c, the transistor N3c, the transistor N4c, the transistor N5c, the transistor N6c or the transistor N7c in the embodiment, and thus similar detailed description is omitted.

[0583] Interconnect 1604 is located above FEOL transistors 1604a, 1604b, and 1604c. In some embodiments, interconnect 1604 is located below BEOL transistor 1610. In some embodiments, BEOL transistor 1610 is located within interconnect 1604.

[0584] In some embodiments, the interconnect 1604 includes a plurality of metallization layers M0 , . . . , Mx-1, Mx configured to provide electrical connections between a power source and one or more FEOL transistors 1604 a , 1604 b or 1604 c or BEOL transistor 1610 .

[0585] In some embodiments, the plurality of metallization layers M0, . . . , Mx-1, Mx of the interconnect 1604 are embedded within an insulating layer, such as one or more ILD layers.

[0586] Other configurations and arrangements of the multiple metallization layers M0, ..., Mx-1, Mx metallization layers are within the intended scope of the present disclosure.

[0587] In some embodiments, interconnect 1604 is configured to provide an electrical connection between one or more of FEOL transistors 1604 a , 1604 b , or 1604 c and BEOL transistor 1610 .

[0588] In some embodiments, integrated circuit 1600 achieves benefits similar to one or more of those discussed herein.

[0589] Other configurations, numbers of layers, or other layer types in integrated circuit 1600 are also within the scope of the present disclosure.

[0590] Fig.17A is a schematic diagram of a memory device 1700A according to some embodiments.

[0591] Memory device 1700A includes memory macros 1702, 1704, 1706, 1708 and memory controller 1720. In some embodiments, one or more of memory macros 1702, 1704, 1706, 1708 correspond to memory macro 110, and / or memory controller 1720 corresponds to memory controller 120. In some embodiments, one or more of memory macros 1702, 1704, 1706, 1708 correspond to memory circuit 102, and / or memory controller 1720 corresponds to memory controller 120.

[0592] exist Fig.17A In the example configuration in FIG. 1 , memory controller 1720 is a common memory controller for memory macros 1702, 1704, 1706, 1708. In at least one embodiment, at least one of memory macros 1702, 1704, 1706, 1708 has its own memory controller. The number of four memory macros in memory device 1700A is an example. Other configurations are within the scope of various embodiments.

[0593] The memory macro instructions 1702, 1704, 1706, and 1708 are coupled to each other in sequence, and the output data of the previous memory macro instruction is the input data of the next memory macro. For example, the input data DIN is input to the memory macro 1702. The memory macro 1702 performs one or more CIM operations based on the data signal A and the data signal B stored in the memory macro 1702, and generates the output data DOUT2 as the result of the CIM operation. The output data DOUT2 is provided as the input data DIN4 of the memory macro 1704. The memory macro 1704 performs one or more CIM operations based on the input data DIN4 and one of the data signal A and the data signal B stored in the memory macro 1704, and generates the output data DOUT4 as the result of the CIM operation. The output data DOUT4 is provided as the input data DIN6 of the memory macro 1706. The memory macro 1706 performs one or more CIM operations based on the input data DIN6 and one of the data signal A and the data signal B stored in the memory macro 1706, and generates the output data DOUT6 as the result of the CIM operation. Output data DOUT6 is provided as input data DIN8 of memory macro 1708. Memory macro 1708 performs one or more CIM operations based on input data DIN8 and one of data signal A and data signal B stored in memory macro 1708, and generates output data DOUT as a result of the CIM operation.

[0594] One or more of the input data DIN, DIN4, DIN6, DIN8 corresponds to the data signal A or the data signal B described herein, and / or one or more of the output data DOUT2, DOUT4, DOUT6, DOUT corresponds to the output signal Vo described herein, so similar detailed description is omitted. In at least one embodiment, the configuration of the memory macro instructions 1702, 1704, 1706, 1708 implements a neural network. In at least one embodiment, one or more benefits described herein can be achieved by the memory device 1700A.

[0595] Other configurations or numbers of elements in the memory device 1700A are within the scope of the present disclosure.

[0596] Fig. 17B is a schematic diagram of a neural network 1700B according to some embodiments.

[0597] The neural network 1700B includes a plurality of layers AE, each of which includes a plurality of nodes (or neurons). The nodes in the consecutive layers of the neural network 1700B are connected to each other through a connection matrix or array. For example, the nodes in layers A and B are connected to each other through connections in a matrix 1712, the nodes in layers B and C are connected to each other through connections in a matrix 1714, the nodes in layers C and D are connected to each other through connections in a matrix 1716, and the nodes in layers D and E are connected to each other through connections in a matrix 1718. Layer A is an input layer configured to receive input data 1711. The input data 1711 is propagated from one layer to the next layer through the neural network 1700B via the corresponding connection matrix between the layers. When the data propagates through the neural network 1700B, the data undergoes one or more calculations and is output as output data 1719 from layer E, which is the output layer of the neural network 1700B. Layers B, C, and D between the input layer A and the output layer E are sometimes referred to as hidden layers or intermediate layers. Fig. 17B The number of layers, the number of connection matrices, and the number of nodes in each layer are examples. Other configurations are within the scope of various embodiments. For example, in at least one embodiment, neural network 1700B does not include hidden layers and has an input layer connected to an output layer via a connection matrix. In one or more embodiments, neural network 1700B has one, two, or more than three hidden layers.

[0598] In some embodiments, matrices 1712, 1714, 1716, 1718 are implemented by memory macro instructions 1702, 1704, 1706, 1708 accordingly, input data 1711 corresponds to data signal A or B, and output data 1719 corresponds to output signal Vo, so similar detailed descriptions are omitted. Specifically, in matrix 1712, the connection between a node in layer A and another node in layer B has a corresponding weight. For example, the connection between node A1 and node B1 has a weight W (A1, B1), which corresponds to the weight value stored in the memory array of memory macro 1702. Memory macros 1704, 1706, 1708 are configured in a similar manner. When machine learning is performed using neural network 1700B, weight data W in one or more of memory macros 1702, 1704, 1706, 1708 is updated, for example, by a processor and through memory controller 1720. According to some embodiments, one or more benefits described herein may be achievable in a neural network 1700B that is implemented in whole or in part by one or more memory macros and / or memory devices.

[0599] Other configurations or numbers of elements in neural network 1700B are within the scope of the present disclosure.

[0600] Fig. 17Cis a schematic diagram of an integrated circuit (IC) device 1700C according to some embodiments.

[0601] IC device 1700C is Figure 1 The memory device 100 or Fig.17A The present invention is not limited to embodiments of the memory device 1700A, and thus similar detailed description is omitted.

[0602] IC device 1700C includes one or more hardware processors 1732, one or more memory devices 1734 coupled to processors 1732 via one or more buses 1736. In some embodiments, one or more hardware processors 1732 may be used as Figure 1 The controller 120 or Fig.17A One or more components of the memory controller 1720 are omitted, and thus similar detailed descriptions are omitted. In some embodiments, one or more memory devices 1734 may be used as Figure 1 The memory circuit 102, Figure 1 Memory macro 110 or Fig.17A One or more components in one or more of the memory macros 1702, 1704, 1706, or 1708 in the embodiment of the present invention are described above, and thus similar detailed descriptions are omitted.

[0603] In some embodiments, IC device 1700C includes one or more other circuits, including but not limited to a cellular transceiver, a global positioning system (GPS) receiver, a network interface circuit for one or more of Wi-Fi, USB, Bluetooth, etc. Examples of processor 1732 include but are not limited to a central processing unit (CPU), a multi-core CPU, a neural processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other programmable logic devices, a multimedia processor, an image signal processor (ISP), etc. Examples of memory device 1734 include one or more memory devices and / or memory macros described herein. In at least one embodiment, each processor 1732 is coupled to a corresponding memory device in memory device 1734.

[0604] Because one or more memory devices 1734 are CIM memory devices, various calculations are performed in the memory devices, which reduces the computational workload of the corresponding processor, reduces memory access time, and improves performance. In at least one embodiment, the IC device 1700C is a system on a chip (SOC). In at least one embodiment, the IC device 1700C can achieve one or more benefits described herein.

[0605] Other configurations or numbers of elements in IC device 1700C are within the scope of the present disclosure.

[0606] Figure 18A-18B is a flow chart of a method 1800 of operating a circuit according to some embodiments.

[0607] In some embodiments, Figure 18A-18B is a flow chart of a method 1800 of operating a memory circuit, such as Figure 1 A memory device 100, Figure 2 The memory cell array 200, Figure 3A The memory cell 300A, Figure 3B The memory cell array 300B of Figure 4A The memory circuit 400A of Figure 6 The memory circuit 600, Fig. 7A The memory circuit 700A of Fig. 8A The memory circuit 800A of Fig.8F Waveform 800F, Fig.9A The memory circuit 900A of Fig. 10A The memory circuit 1000A of Fig.11A XOR logic gate 1100A, Fig. 11B XOR logic gate 1100B, Fig. 12A Full adder circuit 1200A, Fig.13 The n-bit adder circuit 1300, Fig.14 The memory circuit 1400, Fig.17A The memory device 1700A, Fig. 17B Neural Networks 1700B or Fig. 17C IC device 1700C.

[0608] In some embodiments, method 1800 uses corresponding Figure 5 One or more aspects of waveform 500.

[0609] It should be understood that Figure 18A-18B Additional operations may be performed before, during, and / or after the method 1800 described in the present disclosure, and some other processes may only be briefly described herein. In some embodiments, other operation sequences of method 1800 are within the scope of the present disclosure. Method 1800 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, replaced, reordered, and / or eliminated, in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of method 1800 are not performed.

[0610] In operation 1802 of method 1800 , a first group of transistors is initialized.

[0611] In some embodiments, the first group of transistors of method 1800 includes at least one of transistors N5a, N5b, N5c, N6a, N6b, N6c, N7a, N7b, or N7c.

[0612] In some embodiments, operations 1802 and 1804 are performed by a controller. In some embodiments, the controller of method 1800 includes at least one of controller 120, 606, or processor 1732.

[0613] In some embodiments, operation 1802 includes at least one of operations 1804 .

[0614] In operation 1804 of method 1800 , a first set of control signals are written to the first set of transistors to set a logic function of the memory circuit.

[0615] In some embodiments, the first set of control signals of method 1800 includes at least one of control signals C1, C2, or C3. In some embodiments, the first set of control signals of method 1800 also includes at least one of control signals G2a, G2b, or G2c.

[0616] In some embodiments, the logical functions of method 1800 include the functions of at least one of tables 400B, 400D, 700B, 700D, 800B, 800D, 900B, 1000B, or 1000D.

[0617] In operation 1806 of method 1800 , a write operation of the memory circuit is performed.

[0618] In some embodiments, operation 1806 is performed by at least one of transistors N1a, N2a, N3a, N4a, or N1d.

[0619] In some embodiments, operation 1806 includes at least one of operations 1808 , 1810 , 1812 , or 1814 .

[0620] In operation 1808 of method 1800 , a data signal is written to the bit line.

[0621] In some embodiments, method 1800 includes writing a data signal to a source line.

[0622] In some embodiments, the data signal of method 1800 includes at least one of data signals A, B, A', B', An, or Bn.

[0623] In some embodiments, the bit line of method 1800 includes at least one of a read bit line RBL or a write bit line WBL.

[0624] In some embodiments, operation 1808 includes writing the data signal to an access transistor group. In some embodiments, the access transistor group of method 1800 includes at least one of transistors N1a, N2a, N3a, N4a, or N1d.

[0625] In some embodiments, operation 1808 includes writing the data signal to an inverter group. In some embodiments, the inverter group of method 1800 includes at least one of inverters 1002a, 1002b, 1002c, or 1002d.

[0626] In some embodiments, operation 1808 is performed by controller 120 , 606 , or processor 1732 .

[0627] In some embodiments, operation 1808 is performed by a driver, such as read bit line driver 124a, write bit line driver 124b, read word line driver 122a, or write word line driver 122b.

[0628] In operation 1810 of method 1800 , the access transistor group is turned on to write a data signal to a storage node of the storage transistor group.

[0629] In some embodiments, operation 1810 further includes turning on the access transistor set in response to the second set of control signals to write the data signal to the storage node of the storage transistor set.

[0630] In some embodiments, the second set of control signals of method 1800 includes at least one of control signals G1a or G1b.

[0631] In some embodiments, the storage transistor group of method 1800 includes at least one of transistors N1b, N2b, N3b, N4b, N1c, N2c, N3c, or N4c.

[0632] In some embodiments, the storage node of the storage transistor set of method 1800 includes at least one respective gate of a respective transistor N1b, N2b, N3b, N4b, N1c, N2c, N3c, or N4c.

[0633] In operation 1812 of method 1800 , the set of access transistors is turned off.

[0634] In some embodiments, operation 1812 further includes turning off the set of access transistors in response to the second set of control signals, thereby decoupling corresponding storage nodes of the set of storage transistors from corresponding bit lines.

[0635] In operation 1814 of method 1800 , a first signal at a first node is set.

[0636] In some embodiments, the first signal of method 1800 includes at least one of the signals VR.

[0637] In some embodiments, the first node of method 1800 includes at least one of nodes 420 , 720 , or 820 .

[0638] In some embodiments, operation 1814 includes setting the first signal of the first node equal to a reference supply voltage VSS.

[0639] In some embodiments, operation 1814 includes setting the first signal of the first node to be electrically floating.

[0640] In some embodiments, operation 1814 is performed by controller 120 , 606 , or processor 1732 .

[0641] In operation 1816 of method 1800 , a read operation of the memory circuit is performed.

[0642] In some embodiments, operation 1816 is performed by at least one of transistors N1b, N2b, N3b, N4b, N1c, N2c, N3c, or N4c.

[0643] In some embodiments, operation 1816 includes at least one of operations 1818 , 1820 , or 1822 .

[0644] In operation 1818 of method 1800 , the first node is pulled toward a first supply voltage.

[0645] In some embodiments, the first supply voltage of method 1800 includes at least one of the supply voltages VDD.

[0646] In some embodiments, operation 1818 includes setting the first signal of the first node equal to the power supply voltage VDD.

[0647] In some embodiments, operation 1818 is performed by controller 120 , 606 , or processor 1732 .

[0648] In operation 1820 of method 1800 , the output node is pulled to a first supply voltage or a reference supply voltage, thereby setting the output signal.

[0649] In some embodiments, the output signals of method 1800 include at least one of the output signals Vo.

[0650] In some embodiments, the output node of method 1800 includes at least one of nodes 430 , 730 , or 830 .

[0651] In some embodiments, operation 1820 is performed by at least one of transistors N1b, N2b, N3b, N4b, N1c, N2c, N3c, N4c, N5b, N5c, N6b, N6c, N7b, or N7c.

[0652] In operation 1822 of method 1800 , a first signal at a first node is set to be electrically floating or equal to a reference supply voltage VSS.

[0653] In some embodiments, operation 1822 includes setting the first signal of the first node equal to a reference power supply voltage VSS.

[0654] In some embodiments, operation 1822 includes setting the first signal of the first node to be electrically floating.

[0655] In some embodiments, operation 1822 is performed by controller 120 , 606 , or processor 1732 .

[0656] In some embodiments, operation 1822 is performed by at least one of transistors N5b, N5c, N6b, N6c, N7b, or N7c.

[0657] In operation 1824 of method 1800, an output signal is output. In some embodiments, the output signal corresponds to a logic function between the first data signal and the second data signal.

[0658] In some embodiments, operation 1824 is performed by at least one of transistors N1b, N2b, N3b, N4b, N1c, N2c, N3c, N4c, N5b, N5c, N6b, N6c, N7b, or N7c.

[0659] By using method 1800, the memory circuit operates to achieve one or more of the benefits discussed in this disclosure.

[0660] Although method 1800 is described above with reference to memory circuit 400A, it should be understood that in some embodiments, method 1800 is applicable to each memory circuit disclosed herein.

[0661] Other operations of method 1800 are within the scope of the present disclosure.

[0662] also, Figure 3A , Figure 3B , Figure 4A , Figure 6 , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A and Fig.14The various PMOS or NMOS transistors shown in the figure are of a specific dopant type (e.g., N-type or P-type) for illustration purposes. The embodiments of the present disclosure are not limited to a specific transistor type. Figure 3A , Figure 3B , Figure 4A , Figure 6 , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A and Fig.14 One or more of the PMOS or NMOS transistors shown in the figure may be replaced with corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also used for illustration. The embodiments of the present disclosure are not limited to specific logic values ​​when the signals are activated and / or deactivated. It is within the scope of the various embodiments to select different logic values. Figure 3A , Figure 3B , Figure 4A , Figure 6 , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A and Fig.14 Selecting a different number of transistors is within the scope of various embodiments.

[0663] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the above benefits. After reading the above description, those skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the attached claims and their equivalents.

[0664] One aspect of the specification relates to a memory circuit. The memory circuit includes a first memory cell array configured to store data and a second memory cell array coupled to the first memory cell array. In some embodiments, in response to a first set of control signals, the second memory cell array is configured as a first logic circuit or a second logic circuit. In some embodiments, the first logic circuit is configured to perform a first logic function on a first set of data signals based on a second set of control signals. In some embodiments, the second logic circuit is configured to perform a second logic function on a first set of data signals based on a second set of control signals. In some embodiments, the second logic function is different from the first logic function. In some embodiments, the first set of data signals is a portion of the data stored in the first memory cell array. In some embodiments, the first memory cell array and the second memory cell array are embedded in the same memory cell array.

[0665] In some embodiments, the second memory cell array includes: a first group of memory cells configured to receive a first group of data signals and a second group of control signals; and a second group of memory cells coupled to the first group of memory cells and configured to receive the first group of control signals and a third group of control signals, wherein the second group of memory cells is configured to control whether the second memory cell array is configured as a first logic circuit or a second logic circuit based on the first group of control signals.

[0666] In some embodiments, each memory cell in the first group of memory cells and each memory cell in the second group of memory cells is a 2-transistor (2T) memory cell.

[0667] In some embodiments, a first group of memory cells includes: a first group of access transistors configured to receive a first group of data signals and a second group of control signals; and a first group of storage transistors coupled to a first node and an output node of a memory circuit; wherein the first group of access transistors is configured to set a first voltage of a first storage node corresponding to each storage transistor in the first group of storage transistors based on the first group of data signals; and in response to the first group of storage transistors being enabled, the first group of storage transistors is configured to set a first state of an output signal of an output node based on the first voltage of the first storage node corresponding to each storage transistor in the first group of storage transistors.

[0668] In some embodiments, the second group of memory cells includes: a second group of access transistors configured to receive the first group of control signals and the third group of control signals; and a second group of storage transistors coupled to the second node and the output node of the memory circuit; wherein the second group of access transistors is configured to set a second voltage of a second storage node corresponding to each storage transistor in the second group of storage transistors based on the first group of control signals; and in response to the second group of storage transistors being enabled, the second group of storage transistors is configured to set a second state of an output signal of the output node based on the second voltage of the second storage node corresponding to each storage transistor in the second group of storage transistors.

[0669] In some embodiments, the first group of access transistors includes: a first transistor, including a first source / drain terminal, a second source / drain terminal and a first gate terminal, the first source / drain terminal of the first transistor is configured to receive a first data signal in the first group of data signals, and the first gate terminal of the first transistor is configured to receive a first control signal in the second group of control signals; and a second transistor, including a first source / drain terminal, a second source / drain terminal and a first gate terminal, the first source / drain terminal of the second transistor is configured to receive a second data signal in the first group of data signals, and the first gate terminal of the second transistor is set to receive a second control signal in the second group of control signals.

[0670] In some embodiments, the first group of storage transistors includes: a third transistor, including a first source / drain terminal, a second source / drain terminal and a first gate terminal, the first gate terminal of the third transistor is coupled to the second source / drain terminal of the first transistor, and is configured to receive a first data signal in the first group of data signals; and a fourth transistor, including a first source / drain terminal, a second source / drain terminal and a first gate terminal, the first gate terminal of the fourth transistor is coupled to the second source / drain terminal of the second transistor, and is configured to receive a second data signal in the first group of data signals; wherein the first source / drain terminal of the third transistor, the first source / drain terminal of the fourth transistor, and each of the output nodes are coupled together; the second source / drain terminal of the third transistor, the second source / drain terminal of the fourth transistor, and each of the first nodes are coupled together.

[0671] In some embodiments, the second group of access transistors includes: a fifth transistor, including a first source / drain terminal, a second source / drain terminal and a first gate terminal, the first source / drain terminal of the fifth transistor being configured to receive a first control signal in the first group of control signals, and the first gate terminal of the fifth transistor being configured to receive a first control signal in the third group of control signals; and a sixth transistor, including a first source / drain terminal, a second source / drain terminal and a first gate terminal, the first source / drain terminal of the sixth transistor being configured to receive a second control signal in the first group of control signals, and the first gate terminal of the sixth transistor being configured to receive the second control signal in the third group of control signals; and a seventh transistor, including a first source / drain terminal, a second source / drain terminal and a first gate terminal, the first source / drain terminal of the seventh transistor being configured to receive a third control signal in the first group of control signals, and the first gate terminal of the seventh transistor being configured to receive a third control signal in the third group of control signals.

[0672] In some embodiments, the second group of storage transistors includes: an eighth transistor, including a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the eighth transistor is coupled to the second source / drain terminal of the fifth transistor, and is configured to receive a first control signal in the first group of control signals; a ninth transistor, including a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the ninth transistor is coupled to the second source / drain terminal of the sixth transistor, and is configured to receive a second control signal in the first group of control signals; a tenth transistor, including a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the ninth transistor is coupled to the second source / drain terminal of the sixth transistor, and is configured to receive a second control signal in the first group of control signals. The first gate terminal of the tenth transistor is coupled to the second source / drain terminal of the seventh transistor and is configured to receive a third control signal in the first group of control signals; wherein the first source / drain terminal of the third transistor, the first source / drain terminal of the fourth transistor, the first source / drain terminal of the eighth transistor, the first source / drain terminal of the ninth transistor, the first source / drain terminal of the tenth transistor and each of the output nodes are coupled together; and the second source / drain terminal of the eighth transistor, the second source / drain terminal of the ninth transistor, the second source / drain terminal of the tenth transistor and each of the second node are coupled together.

[0673] In some embodiments, the first logic circuit is an OR gate, the second logic circuit is an AND gate, the first logic function is an OR function, and the second logic function is an AND function.

[0674] Another aspect of the present specification relates to a memory circuit. In some embodiments, the memory circuit includes a first memory cell array and a second memory cell array configured to store data. In some embodiments, in response to a first set of control signals, the second memory cell array is reconfigured as a first logic circuit or a second logic circuit, and the first logic circuit is configured to perform a first logic function on the first set of data signals based on the second set of control signals. In some embodiments, the second logic circuit is configured to perform a second logic function on the first set of data signals based on the second set of control signals, and the second logic function is different from the first logic function. In some embodiments, the first set of data signals is part of the data stored in the first memory cell array. In some embodiments, the memory circuit also includes a controller, which is configured to generate a first set of control signals and is configured to control the first memory cell array and the second memory cell array. In some embodiments, the first memory cell array and the second memory cell array are embedded in the same memory cell array.

[0675] In some embodiments, the controller includes: a read bit line driver circuit coupled to the first memory cell array and configured to generate a read bit line signal group; and a write bit line driver circuit coupled to the first memory cell array and configured to generate a write bit line signal group.

[0676] In some embodiments, the controller includes: a read word line driver circuit coupled to the first memory cell array and configured to generate a read word line signal group; and a write word line driver circuit coupled to the first memory cell array and configured to generate a write word line signal group.

[0677] In some embodiments, the second memory cell array includes: a first group of memory cells configured to receive a first group of data signals and a second group of control signals; and a second group of memory cells coupled to the first group of memory cells and configured to receive the first group of control signals and a third group of control signals, wherein the second group of memory cells is configured to control whether the second memory cell array is configured as a first logic circuit or a second logic circuit based on the first group of control signals.

[0678] In some embodiments, a first group of memory cells includes: a first group of access transistors configured to receive a first group of data signals and a second group of control signals; and a first group of storage transistors coupled to a first node and an output node of the memory circuit; wherein the first group of access transistors is configured to set a first voltage of a first storage node corresponding to each storage transistor in the first group of storage transistors based on the first group of data signals; and in response to the first group of storage transistors being enabled, the first group of storage transistors is configured to set a first state of an output signal of an output node based on the first voltage of the first storage node corresponding to each storage transistor in the first group of storage transistors.

[0679] In some embodiments, the second group of memory cells includes: a second group of access transistors configured to receive the first group of control signals and the third group of control signals; and a second group of storage transistors coupled to the second node and the output node of the memory circuit; wherein the second group of access transistors is configured to set a second voltage of a second storage node corresponding to each storage transistor of the second group of storage transistors based on the first group of control signals; and in response to the second group of storage transistors being enabled, the second group of storage transistors is configured to set a second state of an output signal of the output node based on the second voltage of the second storage node corresponding to each storage transistor of the second group of storage transistors.

[0680] In some embodiments, the first group of storage transistors is a first group of ferroelectric field effect transistors (FeFETs), each FeFET in the first group of FeFETs includes a first ferroelectric layer; and the second group of storage transistors is a second group of FeFETs, each FeFET in the second group of FeFETs includes a second ferroelectric layer.

[0681] In some embodiments, the first group of access transistors includes a first group of transistors, the first group of transistors having an active area having a first width or a second width in a first direction; the second group of access transistors includes a second group of transistors, the second group of transistors having an active area having a third width or a fourth width in the first direction; and at least one of the first width, the second width, the third width, or the fourth width is different from at least another one of the first width, the second width, the third width, or the fourth width.

[0682] In some embodiments, the first logic circuit is a NOR gate, the second logic circuit is a NAND gate, the first logic function is a NOR function, and the second logic function is a NAND function.

[0683] Another aspect of the present specification relates to a method of operating a memory circuit. In some embodiments, the method includes writing a first set of control signals to a first set of transistors, thereby setting a logic function of a first memory cell array in the memory circuit, the first set of transistors being part of the memory cell array. In some embodiments, the method also includes performing a write operation of the first memory cell array. In some embodiments, performing the write operation includes turning on an access transistor group in the first memory cell array, thereby writing a first data signal and a second data signal to corresponding storage nodes of a storage transistor group, the storage transistor group being part of the first memory cell array, the storage transistor group being coupled to a first node, an output node, and the first set of transistors. In some embodiments, the method also includes performing a read operation of the memory circuit. In some embodiments, performing a read operation of the memory circuit includes setting a first node to a first power supply voltage, pulling an output node to a first power supply voltage or a reference power supply voltage, thereby setting an output signal, setting a first signal at the first node to a reference power supply voltage, and outputting an output signal, the output signal corresponding to a logic function between the first data signal and the second data signal.

[0684] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same benefits thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A memory circuit, comprising: a first memory cell array configured to store data; as well as a second memory cell array, coupled to the first memory cell array and configured as a first logic circuit or a second logic circuit in response to a first set of control signals, the first logic circuit being configured to perform a first logic function on a first set of data signals based on a second set of control signals, and the second logic circuit being configured to perform a second logic function on the first set of data signals based on the second set of control signals, the second logic function being different from the first logic function, the first set of data signals being part of the data stored in the first memory cell array, The first memory cell array and the second memory cell array are embedded in the same memory cell array.

2. The memory circuit according to claim 1, wherein: The second memory cell array comprises: a first group of memory cells configured to receive the first group of data signals and the second group of control signals; and a second group of memory cells coupled to the first group of memory cells and configured to receive the first group of control signals and a third group of control signals, The second group of memory cells is configured to control whether the second memory cell array is configured as the first logic circuit or the second logic circuit based on the first group of control signals.

3. The memory circuit according to claim 2, wherein: The first group of memory cells comprises: a first set of access transistors configured to receive the first set of data signals and the second set of control signals; and a first set of storage transistors coupled to the first node and an output node of the memory circuit; wherein the first set of access transistors is configured to set a first voltage of a corresponding first storage node of each storage transistor in the first set of storage transistors based on the first set of data signals; and In response to the first group of storage transistors being enabled, the first group of storage transistors is configured to set a first state of an output signal of the output node based on a first voltage of the first storage node corresponding to each storage transistor in the first group of storage transistors.

4. The memory circuit according to claim 3, wherein: The second group of memory cells comprises: a second set of access transistors configured to receive the first set of control signals and the third set of control signals; and a second set of storage transistors coupled to a second node and the output node of the memory circuit; wherein the second group of access transistors is configured to set a second voltage of a second storage node corresponding to each storage transistor in the second group of storage transistors based on the first group of control signals; and In response to the second group of storage transistors being enabled, the second group of storage transistors is configured to set a second state of the output signal of the output node based on the second voltage of the second storage node corresponding to each storage transistor in the second group of storage transistors.

5. The memory circuit according to claim 4, wherein: The first set of access transistors includes: a first transistor comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first source / drain terminal of the first transistor being configured to receive a first data signal of the first set of data signals, and the first gate terminal of the first transistor being configured to receive a first control signal of the second set of control signals; and A second transistor includes a first source / drain terminal, a second source / drain terminal and a first gate terminal, wherein the first source / drain terminal of the second transistor is configured to receive a second data signal in the first group of data signals, and the first gate terminal of the second transistor is configured to receive a second control signal in the second group of control signals.

6. The memory circuit according to claim 5, wherein: The first set of storage transistors includes: a third transistor comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the third transistor being coupled to the second source / drain terminal of the first transistor and configured to receive the first data signal of the first set of data signals; and a fourth transistor comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the fourth transistor being coupled to the second source / drain terminal of the second transistor and configured to receive the second data signal of the first set of data signals; wherein each of the first source / drain terminal of the third transistor, the first source / drain terminal of the fourth transistor, and the output node are coupled together; Each of the second source / drain terminal of the third transistor, the second source / drain terminal of the fourth transistor, and the first node are coupled together.

7. The memory circuit according to claim 6, wherein: The second set of access transistors includes: a fifth transistor comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first source / drain terminal of the fifth transistor being configured to receive a first control signal in the first set of control signals, the first gate terminal of the fifth transistor being configured to receive a first control signal in the third set of control signals; and a sixth transistor comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first source / drain terminal of the sixth transistor being configured to receive a second control signal in the first set of control signals, and the first gate terminal of the sixth transistor being configured to receive a second control signal in the third set of control signals; and A seventh transistor comprises a first source / drain terminal, a second source / drain terminal and a first gate terminal, wherein the first source / drain terminal of the seventh transistor is configured to receive a third control signal in the first group of control signals, and the first gate terminal of the seventh transistor is configured to receive a third control signal in the third group of control signals.

8. The memory circuit according to claim 7, wherein: The second set of storage transistors includes: an eighth transistor, comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the eighth transistor being coupled to the second source / drain terminal of the fifth transistor and configured to receive the first control signal of the first set of control signals; a ninth transistor, comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the ninth transistor being coupled to the second source / drain terminal of the sixth transistor and configured to receive the second control signal of the first set of control signals; a tenth transistor comprising a first source / drain terminal, a second source / drain terminal, and a first gate terminal, the first gate terminal of the tenth transistor being coupled to the second source / drain terminal of the seventh transistor and configured to receive the third control signal of the first set of control signals; wherein each of the first source / drain terminal of the third transistor, the first source / drain terminal of the fourth transistor, the first source / drain terminal of the eighth transistor, the first source / drain terminal of the ninth transistor, the first source / drain terminal of the tenth transistor, and the output node are coupled together; and Each of the second source / drain terminal of the eighth transistor, the second source / drain terminal of the ninth transistor, the second source / drain terminal of the tenth transistor, and the second node are coupled together.

9. A memory circuit comprising: a first memory cell array configured to store data; a second memory cell array that is reconfigured into a first logic circuit or a second logic circuit in response to a first set of control signals, the first logic circuit being configured to perform a first logic function on a first set of data signals based on a second set of control signals, and the second logic circuit being configured to perform a second logic function on the first set of data signals based on the second set of control signals, the second logic function being different from the first logic function, the first set of data signals being part of the data stored in the first memory cell array; as well as a controller configured to generate the first set of control signals and configured to control the first memory cell array and the second memory cell array, The first memory cell array and the second memory cell array are embedded in the same memory cell array.

10. A method of operating a memory circuit, the method comprising: writing a first set of control signals to a first set of transistors to set a logic function of a first array of memory cells in the memory circuit, the first set of transistors being part of the array of memory cells; Executing a write operation on the first memory cell array, wherein the write operation comprises: turning on a set of access transistors in the first memory cell array to write a first data signal and a second data signal to respective storage nodes of a set of storage transistors, the set of storage transistors being part of the first memory cell array, the set of storage transistors being coupled to a first node, an output node, and the first set of transistors; Performing a read operation of the memory circuit, the read operation of the memory circuit comprising: setting the first node to a first power supply voltage; pulling the output node to the first power supply voltage or the reference power supply voltage, thereby setting an output signal; setting a first signal at the first node to the reference power supply voltage; and outputting the output signal, the output signal corresponding to the logic function between the first data signal and the second data signal.

Images