Memory circuit and operating method thereof

Abstract

A memory circuit includes a memory array, a first access circuit, and a second access circuit. The memory array may include a plurality of non-volatile memory cells. The non-volatile memory cells may be arranged along a plurality of first access lines and a plurality of second access lines. The first and second access lines may each extend laterally through the memory array. The first access circuit may be physically disposed on a first side of the memory array in a lateral direction. The second access circuit may be physically disposed on a second side of the memory array in the lateral direction. The second side is opposite the first side. The embodiment of the invention also relates to a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array comprising a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are arranged along a plurality of first access lines and a plurality of second access lines, and the first access lines and the second access lines each extend laterally through the memory array; a first access circuit physically disposed at a first side of the memory array in a lateral direction; and a second access circuit physically disposed at a second side of the memory array in a lateral direction, wherein the second side is opposite to the first side; wherein the first access circuit is configured to couple a programming voltage to each nonvolatile memory cell through a corresponding first access line and to provide a first conduction path through a corresponding second access line, and the second access circuit is configured to provide a second conduction path through a corresponding second access line.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory cell coupled between a first access line and a second access line, wherein the first access line and the second access line both extend in a lateral direction; a first access circuit physically disposed at a first side of the memory cell in the lateral direction, wherein the first access circuit comprises a first sub-circuit and a second sub-circuit; and a second access circuit physically disposed at a second side of the memory cell in the lateral direction, the second side being opposite to the first side, wherein the second access circuit comprises a third sub-circuit and a fourth sub-circuit; wherein the first sub-circuit is configured to couple a programming voltage to the memory cell through the first access line, and the second sub-circuit and the third sub-circuit are both configured to provide a corresponding conduction path from the memory cell to ground when the fourth sub-circuit is deactivated.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: activating a first access circuit physically disposed on a first side of a memory array in a lateral direction, wherein the memory array includes a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are arranged along a plurality of first access lines and a plurality of second access lines, and the first access lines and the second access lines both extend through the memory array in the lateral direction; activating a second access circuit physically disposed on a second side of the memory array in the lateral direction, wherein the second side is opposite to the first side; receiving a first current flowing through the memory array; conducting a second current flowing through the first access circuit via a first conduction path; and conducting a third current flowing through the second access circuit via a second conduction path, wherein the first access circuit is configured to couple a programming voltage to each nonvolatile memory cell through a corresponding first access line and provide a first conduction path through a corresponding second access line, and the second access circuit is configured to provide a second conduction path through a corresponding second access line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram illustrating an example of a memory array according to some embodiments.

[0008] Figure 2 An example schematic diagram of a resistive random access memory (RRAM) write operation is shown in accordance with some embodiments.

[0009] Figure 3 An example schematic diagram illustrating double-sided discharge of a resistive random access memory (RRAM) write operation according to some embodiments is shown.

[0010] Figure 4 A method for operating according to some embodiments is shown. Figure 3 Example waveforms of multiple control signals for a memory circuit including multiple access circuits physically disposed on opposite sides of a memory array.

[0011] Figure 5 An example schematic diagram illustrating double-sided discharge of a resistive random access memory (RRAM) write operation according to some embodiments is shown.

[0012] Figure 6 An example schematic diagram illustrating double-sided discharge of a resistive random access memory (RRAM) write operation according to some embodiments is shown.

[0013] Figure 7 An example schematic diagram illustrating double-sided discharge of a resistive random access memory (RRAM) write operation according to some embodiments is shown.

[0014] Figure 8 An example method of fabricating a double-sided discharge memory circuit for resistive random access memory (RRAM) according to some embodiments.

[0015] Fig. 9 A flow chart is shown of an example method for operating a memory device including access circuits physically disposed on opposite sides of a memory array in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0018] A resistive random access memory (RRAM) device may have a resistive material layer sandwiched between two electrodes (e.g., a top electrode or a bottom electrode). The resistance of an RRAM device may be set or reset to low or high, representing a logical "1" or a logical "0," respectively.

[0019] In some embodiments, a "forming" process (or operation) is applied to the RRAM device. The forming process is intended to change the structure of the resistive material layer of the RRAM device, thereby creating a conductive path therein. During the forming process, a forming voltage is applied to the two electrodes of the RRAM device. For example, the bottom electrode is connected to a low voltage Vlow , the top electrode is connected to a high voltage V high . V high -V low The difference in the value of provides a forming voltage. In the "forming" operation, the "forming" voltage is high enough to produce a conductive feature in the resistive material layer. In one example, the conductive feature includes a plurality of conductive filaments to provide a conductive path to turn the resistive material layer "on" or in a low resistance state. The conductive path may be related to the arrangement of oxygen vacancies in the resistive material layer.

[0020] In another embodiment, the formation process includes two steps: a first formation step applies a first (forming) voltage Vf1 to the RRAM device, and a second formation step applies a second (forming) voltage Vf2 to the RRAM device, wherein the second voltage is different from the first voltage. Specifically, in the first formation step, a first voltage is applied to the RRAM device in a first direction (or first polarity). In the second formation step, a second voltage is applied to the RRAM device in a second direction (or second polarity) opposite to the first direction. Therefore, the formation process is also referred to as a bidirectional formation process. The first formation step is also referred to as a forward formation step, and the second formation step is referred to as a reverse formation step. In one embodiment, the amplitude of the first voltage Vf1 is greater than the second voltage Vf2.

[0021] In some embodiments, the RRAM device may undergo multiple set and reset operation cycles (also referred to as set / reset operation cycles), for example, "M" cycles. The initial resistance window may degrade during the cycles.

[0022] The RRAM device can be subjected to a reconstruction operation (or process) to recreate the fuse and recover the RRAM device from resistance degradation, wherein the resistance of the RRAM device is fully or at least partially restored to its initial stage after the "forming" process (in other words, the resistance is improved). The reconstruction process is intended to restore the resistance of the RRAM device. Therefore, the resistance (especially the low resistance) remains a large and stable resistance window for reliable reading.

[0023] In one embodiment, the rebuild process includes applying a rebuild voltage to the RRAM device. The rebuild voltage is applied with a polarity of a set operation. The rebuild voltage is greater than a set voltage of the set operation. In one example, the rebuild voltage is less than a "form" voltage of a "form" operation.

[0024] In another embodiment, the reconstruction process is a bidirectional reconstruction process, comprising two steps: applying a first voltage of a first polarity and a second voltage of a second polarity to the RRAM device. In some embodiments, the set and reset operations can be based on a bipolar switching effect and applied with opposite polarities. In this example, the set operation includes applying a set voltage to the RRAM device with a first polarity, and the reset operation includes applying a reset voltage to the RRAM device with a second polarity. In this case, the first voltage in the first step of the reconstruction process is greater than the set voltage, and the second voltage in the second step of the reconstruction process is greater than the reset voltage. Thereafter, the RRAM device performs normal operation (set and reset), such as the next normal operation (M+1)th cycle.

[0025] When the resistance of the RRAM device needs to be restored from resistance degradation, this process continues by inserting a rebuild process in normal operation. For example, after another number of set / reset operation cycles (such as the Nth cycle), another rebuild process can be applied to the RRAM device to rebuild the fuse and restore the resistance of the RRAM device. Thereafter, the RRAM device performs normal operation (set and reset), such as the next normal operation (N+1)th cycle.

[0026] The rebuild process is inserted into the normal operation of the RRAM device in various modes. In one embodiment, the rebuild process is inserted into the normal operation of the RRAM device in a time mode. The number N0 is predetermined according to the resistance degradation data of the RRAM device. After every N0 set / reset operation cycles, the rebuild process is applied to the RRAM device to rebuild the fuse.

[0027] In another embodiment, the rebuild process is inserted into the normal operation of the RRAM device in a detection mode. Based on the read consistency, stability and / or repeatability, a reference current (also referred to as a predefined read current) of the RRAM device is determined. During normal operation, when the RRAM device is addressed for normal operation, the read current of the RRAM device is captured and compared with the reference current. If the read current is less than the reference current, a rebuild process is applied to the RRAM device to rebuild the fuse.

[0028] In yet another embodiment, the rebuild process is inserted into the normal operation of the RRAM device in a time and detection mode. During normal operation, if the read current is less than the reference current, or when the number of set / reset operation cycles is equal to or greater than a predetermined number N0, the rebuild process is applied to the RRAM device to rebuild the fuse.

[0029] In some embodiments, the voltage or current across a resistive random access memory (RRAM) element (RE) may drop significantly when the bit line (BL) length increases. This phenomenon occurs due to the increase in the size of the BL and source line (SL) metal resistors, resulting in a larger voltage drop (IR drop) between them. The larger IR drop may cause the voltage across the RRAM element to drop, thereby affecting the write window of the memory cell.

[0030] Increasing the bit line (BL) length does result in a degradation in the write performance of resistive random access memory (RRAM) due to factors such as increased resistance and voltage drop along the longer BL. Existing write currents typically flow in a single direction, which may exacerbate the challenges associated with longer BL lengths. To address this issue and enhance the write window, the present disclosure provides a method involving optimizing the direction and distribution of the write current. By carefully controlling the direction and distribution of the write current, the negative effects of longer BL lengths can be mitigated. The method enhances the write window.

[0031] The present invention provides a memory circuit with double-sided discharge for resistive random access memory (RRAM) write operations. Specifically, the present disclosure provides various embodiments of a memory device or circuit including a memory array, a first access circuit, and a second access circuit. The memory array may include a plurality of non-volatile memory cells. In one aspect of the present invention, the non-volatile memory cells may be arranged along a plurality of first access lines and a plurality of second access lines. The first access line and the second access line may each extend through the memory array in a lateral direction. The first access circuit may be physically disposed on a first side of the memory array in a lateral direction. The second access circuit may be physically disposed on a second side of the memory array in a lateral direction. The second side is opposite to the first side. Therefore, the first access circuit may be configured to couple a programming voltage to each non-volatile memory cell through a corresponding first access line, and provide a first conduction path through a corresponding second access line, and the second access circuit may be configured to provide a second conduction path through a corresponding second access line. Therefore, the equivalent resistance of a conduction (e.g., programming or reading) path on any memory cell may be significantly reduced, which may advantageously improve the BL path IR drop.

[0032] Figure 1 1 shows a block diagram of a memory device or circuit 100 according to various embodiments of the present disclosure. Figure 1 In the illustrated embodiment, memory device 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuitry 108, and control logic circuitry 110. Figure 1 Although not shown in FIG. 1 , all components of the memory device 100 may be coupled to each other and to the control logic circuit 110. Figure 1 In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1 Some or all of the components shown in can be integrated together. For example, memory array 102 can include embedded I / O circuits (eg, 108).

[0033] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other storage units) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M Each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3, ... N , each column extends in a second direction (e.g., Y direction). Each row and each column may include one or more conductive (e.g., metal) structures used as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to a voltage or current through the corresponding conductive structure of the column and row. For example, each row may include one or more corresponding word lines (WL), and each column may include one or more corresponding bit lines (BL) and one or more source lines (SL).

[0034] In some embodiments, each memory cell 103 is implemented as an RRAM cell, details of which will be described in detail in Figure 3 However, it should be understood that the memory array 102 may include any of a variety of other non-volatile memory cells, such as spin transfer torque random access memory (STT-RAM) cells, ferroelectric random access memory (FeRAM) cells, magnetoresistive random access memory (MRAM) cells, phase change random access memory (PCRAM) cells, etc., while remaining within the scope of the present disclosure.

[0035] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., WL) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert a conductive structure (e.g., BL and SL) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0036] It should be understood that Figure 1The arrangement of components shown in is for illustration purposes only and does not limit the physical layout of these components. For example, although I / O circuit 108 is shown as being arranged on a first side of memory array 102, according to various embodiments of the present disclosure, I / O circuit 108 may include multiple subcomponents or subcircuits (e.g., one or more driver circuits, one or more pull-down circuits) that are physically arranged on different sides of memory array 102. In addition, these subcomponents may be physically disposed between column decoder 106 and memory array 102. In some embodiments, driver circuits and pull-down circuits may sometimes be referred to as access circuits.

[0037] Figure 2 An example schematic diagram of a resistive random access memory (RRAM) write operation according to some embodiments is shown. In some embodiments, when the bit line (BL) length increases, the voltage or current across the resistive random access memory (RRAM) element (RE) may decrease significantly. This phenomenon is due to the increase in the size of the BL and source line (SL) metal resistors, resulting in a larger voltage drop (IR drop) between them. Figure 2 , Iwrite 202 may represent a write current. RBL 204 and RSL 206 may represent the resistance of the bit line (BL) and the source line (SL), respectively. A large IR drop (e.g., Iwrite*(RBL+RSL)) may result in a reduced voltage across the RRAM element, thereby affecting the write window of the memory cell.

[0038] In the prior art, the driver circuit and the pull-down circuit are usually formed on the same side of the memory array. As the size of the memory array becomes larger (for example, as the number of word lines increases / the length of the bit line increases), the RRAM cells formed away from the driver circuit and the pull-down circuit are usually affected by insufficient programming voltage, which is mainly due to the increase in the voltage (IR) drop along the extended bit line. To this end, some technologies have proposed placing the driver circuit and the pull-down circuit on opposite sides of the memory array. In other words, regardless of the direction of current flow, the programming voltage is applied to one side of the memory array (through the driver circuit), and the resulting current flows to the ground on the other side of the memory array (through the pull-down circuit). However, the electrodes of each RRAM cell are usually coupled to or formed as metal lines. As the size of the technology node is increasingly reduced, the size of these metal lines is also reduced accordingly. Therefore, the metal line (or the corresponding write path) may present a higher resistance, which causes the voltage drop problem to remain unsolved. Therefore, the existing RRAM devices are not completely satisfactory in some aspects.

[0039] Figure 3 Some embodiments of the present disclosure are shown Figure 1An example schematic diagram 300 of a portion of the memory device 100 (hereinafter referred to as “memory circuit 300 ”) is shown. Specifically, Figure 3 An example schematic diagram 300 of double-sided discharge of a resistive random access memory (RRAM) write operation according to some embodiments is shown. As a brief overview, the memory circuit 300 may include a memory array, the memory array including non-volatile memory cells 302, 304, 306, 308, a first access circuit 310, and a second access circuit 320. The first access circuit 310 may be physically disposed on a first side 301a of the memory array in a lateral direction (e.g., Y direction). The second access circuit 320 may be physically disposed on a second side 301b of the memory array in a lateral direction (e.g., Y direction). The second side is opposite to the first side. The memory array 102 is shown implemented as an RRAM cell 200 ( Figure 2 ) of a memory cell (e.g., 103). In some embodiments, the memory circuit 300 may include a control circuit that may include a bit line / source line (BL / SL) decoder and driver 360 and a word line (WL) decoder and driver 370. For illustration purposes, Figure 3 The memory circuit 300 is simplified, therefore, it should be understood that Figure 3 Can be omitted Figure 1 some components of .

[0040] In some embodiments, the memory array may include a plurality of non-volatile memory cells 302, 304, 306, 308. The non-volatile memory cells 302, 304, 306, 308 may be arranged along a plurality of first access lines 305 (e.g., source lines (SL)) and a plurality of second access lines 315 (e.g., bit lines (BL)). The first access lines 305 (e.g., SL) and the second access lines 315 (e.g., BL) each extend through the memory array in a lateral direction (e.g., Y direction). In some embodiments, each non-volatile memory cell 302, 304, 306, 308 may include an access transistor and a resistor coupled in series with each other, wherein the resistor is configured to store at least a data bit. The non-volatile memory cell may retain stored data in the absence of power, while a volatile memory device loses its data storage content when power is lost. The non-volatile memory cell may include any of a variety of non-volatile memory cells, such as a resistive random access memory (RRAM) cell, a spin transfer torque random access memory (STT-RAM) cell, a ferroelectric random access memory (FeRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell, etc., while remaining within the scope of the present disclosure. In some embodiments, the non-volatile memory cell may be configured to be programmed from a first resistance state (e.g., a low resistance state) to a second resistance state (e.g., a high resistance state).

[0041] In some embodiments, the first access circuit 310 (e.g., top MUX) can be physically disposed on the first side 301a of the memory array in a lateral direction (e.g., Y direction). In some embodiments, the first access circuit 310 can be a multiplexer (MUX) for selecting an input from a plurality of inputs and routing it to a single output based on a provided control signal. The first access circuit 310 can be configured to couple a programming voltage to each of the non-volatile memory cells 302, 304, 306, 308 through a corresponding one of the first access lines 305 (e.g., source lines (SL)), and provide a first conduction path 312 (e.g., Iwrite 2) through a corresponding one of the second access lines 315 (e.g., bit lines (BL)). In some embodiments, the first conduction path 312 can extend from the corresponding non-volatile memory cell 302, through the first transistor 322 and the second transistor 324, to the ground (VSS). In some embodiments, the first conduction path 312 can include the first transistor 322 and the second transistor 324. In some embodiments, one source / drain terminal of the first transistor 322 can be connected to the second access line 315 (eg, BL). One source / drain terminal of the second transistor 324 can be connected to ground (eg, VSS). In some embodiments, the first access circuit 310 can include a first sub-circuit and a second sub-circuit.

[0042] In some embodiments, the second access circuit 320 (e.g., bottom MUX) can be physically disposed on the second side 301b of the memory array in a lateral direction (e.g., Y direction). The second side 301b is opposite to the first side 301a. In some embodiments, the second access circuit 320 can be a multiplexer (MUX) for selecting an input from a plurality of inputs based on a provided control signal and routing it to a single output. The second access circuit 320 can be configured to provide a second conduction path 313 (e.g., Iwrite 1) through a corresponding second access line 315. The second conduction path 313 can extend from the corresponding non-volatile memory cell 302, through the third transistor 326, and reach the ground (VSS). The second access circuit may include a third transistor 326. One source / drain terminal of the third transistor 326 may be connected to the second access line 315, and the other source / drain terminal of the third transistor 326 is connected to the ground (VSS). In some embodiments, the second access circuit 320 may include a third subcircuit and a fourth subcircuit.

[0043] In some embodiments, when a programming voltage is applied to the corresponding non-volatile memory cell 302 through one of the first access lines 305, the first to third transistors 322, 324, 326 can be configured to be activated simultaneously. When each non-volatile memory cell is configured to be programmed by a current flowing through the corresponding first access line 305 and the non-volatile memory cell itself, the current (e.g., Iwrite) is configured to be divided into two independent currents (e.g., Iwrite 1 and Iwrite 2) flowing through the first conduction path 312 and the second conduction path 313, respectively. In some embodiments, the second access circuit 320 may include a third subcircuit and a fourth subcircuit. The first subcircuit may be configured to couple the programming voltage to the memory cell through the first access line 305. The second and third subcircuits may each be configured to provide a corresponding conduction path from the memory cell to ground (VSS) while the fourth subcircuit is disabled.

[0044] In some embodiments, the memory circuit 300 may include a control circuit. The control circuit may be a hardware component that may control coupled components (e.g., non-volatile memory cells 302, 304, 306, 308 of the memory array, the first access circuit 310, and / or the second access circuit 320). The control circuit may include a WL decoder and WL driver 370 and a BL / SL decoder and BL / SL driver 360. The WL decoder and WL driver 370 may be a hardware component that may receive a WL address 372 (and an XE signal 374) of the memory circuit 300 and assert a conductive structure (e.g., WL) at the WL address. The BL / SL decoder and BL / SL driver 360 may be a hardware component that may receive a BL / SL address 362 (and a YE signal 364) of the memory circuit 300 and assert a conductive structure (e.g., BL) at the address. The selection of the bit line (BL) and the source line (SL) in the resistive random access memory (RRAM) array can be determined by the YE signal 364 and the BL / SL address 362 signal of BL / SL and the XE signal 374 and the WL address 372 signal of WL. When a cell is selected, the write current flows from the top multiplexer (MUX) through the selected cell, flows from SL to BL, and then discharges to ground on the bottom side (VSS). However, this process is affected by the metal resistors in BL and SL, which causes IR drop. As the number of cells in the array increases, the product of the write current and the sum of the BL and SL resistances (Iwrite*(RBL+RSL)) becomes larger. This larger IR drop reduces the voltage across the RRAM cell, causing the write window to degrade and may affect the reliability and performance of the memory array. The present disclosure provides two independent currents flowing through a first conduction path 312 (e.g., Iwrite 2) and a second conduction path 313 (e.g., Iwrite 3) to reduce the IR drop.

[0045] Figure 4 A method for operating according to some embodiments is shown. Figure 3 Example waveforms 400 of a plurality of control signals for a memory circuit including a plurality of access circuits physically disposed on opposite sides of a memory array.

[0046] The timing waveform 400 of the reset operation in a resistive random access memory (RRAM) can include three different steps. First, the RESET signal 402 rises to start the reset period and activate the pull-down path. Next, the BLE signal 404 rises, selecting the target bit line (BL) and source line (SL) 408, while activating the corresponding top and bottom multiplexers 310, 320. This allows the power supply voltage to pass through the BL or SL, setting the stage for the reset operation. Finally, the XE signal 374 is activated, selecting and enabling the word line (WL) 410. At this point, the reset operation begins, using the current from the power supply to drive the pull-down device and effectively complete the reset process.

[0047] In some embodiments, in a modified waveform for a reset operation in a resistive random access memory (RRAM), a pull-down device may be implemented at the top multiplexer 310. The pull-down device is activated by the same RESET signal used for the reset operation, thereby enabling a discharge path during the reset process. Despite the addition of the device and necessary control logic, the resulting area penalty is very small. This enhancement ensures more efficient discharge during reset, helping to improve the reliability and performance of the RRAM memory system without significantly increasing the overall complexity or footprint of the circuit.

[0048] Figure 5 An example schematic diagram illustrating double-sided discharge of a resistive random access memory (RRAM) write operation according to some embodiments is shown. Figure 5 310, which provides two different conduction paths 312, 313 corresponding to VDD and VSS respectively. This configuration allows for multiple variations of the routing of electrical signals within the circuit, with VDD representing the supply voltage and VSS representing the ground connection. The top MUX 310 plays a vital role in managing the current flow and voltage in the system, providing flexibility and control for the operation of the circuit. By combining these two conduction paths 312, 313, the memory circuit 300 can effectively handle different voltage levels and ensure the normal operation of the integrated circuit.

[0049] Figure 6 An example schematic diagram 600 illustrating double-sided discharge of a resistive random access memory (RRAM) write operation according to some embodiments. Figure 6By introducing an intermediate multiplexer (MUX) 630 (e.g., an additional intermediate side pull-down device) Figure 3 The memory circuit 600 may include non-volatile memory cells 302, 304, 306, 308 of a memory array, a first access circuit 310, a second access circuit 320, and a third access circuit 630. In addition to the additional third access circuit 630, Figure 6 The memory circuit 600 is Figure 3 The third access circuit 630 can expand the available conduction paths within the memory circuit 600.

[0050] In some embodiments, the third access circuit 630 (e.g., middle MUX) can be physically disposed in the middle of the memory array in a lateral direction (e.g., Y direction). The third access circuit 630 can be configured to provide a third conduction path 614 (e.g., Iwrite 3) through a corresponding second access line 315. In some embodiments, the third access circuit 630 can be a multiplexer (MUX) for selecting an input from a plurality of inputs based on a provided control signal and routing it to a single output. The third access circuit 630 can be configured to provide a third conduction path 614 (e.g., Iwrite 3) through a corresponding second access line 315. The third conduction path 614 can extend from the corresponding non-volatile memory cell 302, through the fifth transistor 628, to the ground (VSS). The third access circuit 630 may include a fifth transistor 628. One source / drain terminal of the fifth transistor 628 can be connected to the second access line 315, and the other source / drain terminal of the fifth transistor 626 is connected to the ground (VSS).

[0051] In some embodiments, the first to fifth transistors may be configured to be activated simultaneously when a programming voltage is applied to the corresponding nonvolatile memory cell 302 through one of the first access lines 305. When each nonvolatile memory cell is configured to be programmed by a current flowing through the corresponding first access line 305 and the nonvolatile memory cell itself, the current (e.g., Iwrite) is configured to be separated into three independent currents (e.g., Iwrite 1, Iwrite 2, and Iwrite 3) flowing through the first conduction path 312, the second conduction path 313, and the third conduction path 614, respectively.

[0052] Figure 7An example schematic diagram of double-sided discharge for a resistive random access memory (RRAM) write operation according to some embodiments is shown. The introduction of the memory circuit 300 only results in a small area penalty, making it a practical addition without significantly increasing the overall footprint. In addition, the waveform remains unchanged from the original design and no additional control circuit is required. The method involves dividing the total current Iwrite into two or three paths through BL discharge, thereby reducing the current flowing through the BL, thereby reducing the IR drop on the BL side. As a result, at the same power supply power, the present disclosure achieves a better voltage across the RRAM element due to the reduction in IR drop on the BL side. Even in a 1024-bit line (BL) array 704, the voltage across the RRAM element exceeds the voltage of the original 512-bit line array architecture 702. This advancement allows for larger bank sizes and fewer banks, which helps to better save area by minimizing peripheral circuitry and library requirements.

[0053] By adding an additional pull-down device on the top multiplexer (MUX) side and activating both the top and bottom pull-down devices during a RESET operation, the current can be split into two paths. This division of the current results in a reduction in the total bit line (BL) path IR drop, thereby improving overall performance. The dual-side discharge approach implemented by the device further enhances the write window of the system. As a result of these enhancements, the voltage across the resistive random access memory (RRAM) can be increased by approximately 10% in the case of 512 word lines (WL) and by approximately 18% in the case of 1024 word lines. In addition, the voltage difference between near and far locations of the memory is reduced, contributing to more uniform and reliable operation across the memory array.

[0054] Enhancements made to the bit line (BL) path result in an improved reduction in the IR drop along the path. This improvement translates directly into an increase in the voltage across the resistive element (RE), from about 0.96V to about 1.05V in the case of 512 word lines (WLs). Even with a larger array of 1024 WLs, the worst-case voltage remains at about 0.99V, exceeding the performance of the original 512 WL configuration. In addition, these improvements result in a reduction in the voltage difference between near and far locations of the memory, contributing to a more uniform and reliable voltage distribution across the memory array.

[0055] Figure 8 is an example method of fabricating a memory circuit for double-sided discharge of a resistive random access memory (RRAM) according to some embodiments. In general, method 800 can include fabricating a memory array to avoid the negative effects of longer BL lengths.

[0056] Referring to (802), in some embodiments, a memory array including a plurality of non-volatile memory cells 302, 304, 306, 308 may be provided. In some embodiments, each non-volatile memory cell 302, 304, 306, 308 may include an access transistor and a resistor coupled in series with each other, wherein the resistor is configured to store at least a data bit. A non-volatile memory cell may retain stored data in the absence of power, whereas a volatile memory device loses its data storage contents upon loss of power. The non-volatile memory cell may include any of a variety of non-volatile memory cells, such as a resistive random access memory (RRAM) cell, a spin transfer torque random access memory (STT-RAM) cell, a ferroelectric random access memory (FeRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell, etc., while remaining within the scope of the present disclosure.

[0057] Referring to (804), in some embodiments, a plurality of first access lines 305 and a plurality of second access lines 315 may be formed. The first access lines 305 and the second access lines 315 may each extend through the memory array in a lateral direction (e.g., a Y direction). The nonvolatile memory cells 302, 304, 306, 308 may be arranged along a plurality of first access lines 305 (e.g., source lines (SL)) and a plurality of second access lines 315 (e.g., bit lines (BL)). The first access lines 305 (e.g., SL) and the second access lines 315 (e.g., BL) each extend through the memory array in a lateral direction (e.g., a Y direction).

[0058] Referring to (806), in some embodiments, a first access circuit 310 may be formed that is physically disposed on a first side 301a of the memory array in a lateral direction (e.g., a Y direction). In some embodiments, the first access circuit 310 may be a multiplexer (MUX) for selecting an input from a plurality of inputs and routing it to a single output based on a provided control signal. The first access circuit 310 may be configured to couple a programming voltage to each of the non-volatile memory cells 302, 304, 306, 308 through a corresponding one of the first access lines 305 (e.g., a source line (SL)), and provide a first conduction path 312 (e.g., Iwrite 2) through a corresponding one of the second access lines 315 (e.g., a bit line (BL)).

[0059] Referring to (808), in some embodiments, a second access circuit 320 may be formed that is physically disposed on a second side 301b of the memory array in a lateral direction. The second side 301b is opposite to the first side 301a. In some embodiments, the second access circuit 320 may be a multiplexer (MUX) for selecting an input from a plurality of inputs based on a provided control signal and routing it to a single output. The second access circuit 320 may be configured to provide a second conduction path 313 (e.g., Iwrite 1) through a corresponding second access line 315. In some embodiments, a third access circuit 630 may be formed that is physically disposed in the middle of the memory array in a lateral direction (e.g., Y direction).

[0060] Fig. 9 A flow chart of an example method 900 for operating a memory device including access circuits physically disposed on opposite sides of a memory array according to some embodiments is shown. For example, at least some operations of method 900 may be performed to write / read a memory cell (e.g., 103) based on at least two conduction paths. Therefore, in the following discussion of method 900, the above-mentioned figures (e.g., Figure 1-Figure 7 ) in the reference numerals used in the description. It should be noted that method 900 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 900 may be used in Fig. 9 Additional operations are provided before, during, and after method 900, and some other operations may only be briefly described herein.

[0061] Method 900 begins with operation 902, where a plurality of access circuits physically disposed on opposite sides of a memory array are activated. In some embodiments, a first access circuit (e.g., 310) physically disposed on a first side of the memory array in a lateral direction may be activated. In some embodiments, a second access circuit (e.g., 320) physically disposed on a second side of the memory array in a lateral direction may be activated. The second side may be opposite to the first side. In some embodiments, a memory array (e.g., 300) includes a plurality of memory cells (e.g., RRAM cells 302, 304, 306, 308) arranged in a plurality of columns and a plurality of rows. Along each column, a subset of the memory cells are coupled to each other by bit lines and source lines, each of which may extend in the Y direction; and along each row, another subset of the memory cells are coupled to each other by word lines, which may extend in the X direction.

[0062] In one aspect of the present disclosure (e.g., Figure 3In the embodiment of the present invention, a memory array of a plurality of memory cells is provided with a first access circuit (e.g., 310) physically disposed on a first side 301a of the memory array along the Y direction, and a second access circuit (e.g., 320) physically disposed on a second side 301b of the memory array along the Y direction. In order to access (e.g., program, read) the memory array, a plurality of access circuits may be activated. Specifically, each access circuit may include two sub-circuits, which may be alternately activated based on a logic state to be programmed into a corresponding memory cell. By disposing at least two access circuits on opposite sides of the memory array, each memory cell of the memory array may be programmed / read through at least two conduction paths, which may advantageously reduce equivalent resistance along the conduction paths.

[0063] The method 900 proceeds to operation 904, where a first current flow / voltage may be provided to the memory cell. Continuing with the same example above, each non-volatile memory cell may be configured to be programmed by a current flowing through the corresponding first access line and the non-volatile memory cell itself. The current may be configured to be split into two separate current flows (e.g., a second current flow, a third current flow) flowing through the first conduction path and the second conduction path, respectively. In some embodiments, when a memory cell is selected for programming, the voltage may be a programming voltage (V BL ). Based on the logic state to be programmed, different subcircuits of the access circuit can be activated to couple a programming voltage to the memory cell. When subcircuits 322, 324, and 326 are activated (e.g., to write a logic 0 to a memory cell), a programming voltage can be coupled to the memory cell through its corresponding bit line.

[0064] The method 900 proceeds to operation 906, in which a second current is conducted to flow through the first access circuit via the first conduction path (e.g., Iwrite 2), and operation 908, in which a third current is conducted to flow through the second access circuit via the second conduction path (e.g., Iwrite1). In some embodiments, operations 906 and 909 can be performed simultaneously. Still using the same example described above (when writing a logic 0 to a memory cell), subcircuits 322, 324, and 326 are activated. Thus, a first conduction path (e.g., 312) extending from the corresponding non-volatile memory cell 302 through the first transistor 322 and the second transistor 324 to ground (VSS) can be formed. A second conduction path (e.g., 313) extending from the corresponding non-volatile memory cell 302 through the third transistor 326 to ground (VSS) can be formed. By carefully controlling the direction and distribution of the write current, the negative effects of longer BL lengths (e.g., IR drop) can be mitigated. In some embodiments, method 900 continues with the operation of conducting a fourth current to flow through a third access circuit via a third conduction path (e.g., Iwrite 3). In some embodiments, the third access circuit can be physically disposed in the middle of the memory array in a lateral direction. The third access circuit can be configured to provide a third conduction path through a corresponding second access line.

[0065] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of a value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0066] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of first access lines and a plurality of second access lines, and the first access lines and the second access lines each extend through the memory array in a lateral direction; a first access circuit physically disposed at a first side of the memory array in the lateral direction; and a second access circuit physically disposed at a second side of the memory array in the lateral direction, wherein the second side is opposite to the first side; wherein the first access circuit is configured to couple a programming voltage to each non-volatile memory cell through a corresponding first access line and provide a first conduction path through a corresponding second access line, and the second access circuit is configured to provide a second conduction path through a corresponding second access line.

[0067] In some embodiments, each nonvolatile memory cell includes an access transistor and a resistor coupled in series with each other, wherein the resistor is configured to store at least one data bit.

[0068] In some embodiments, each nonvolatile memory cell includes an access transistor and a capacitor coupled in series with each other, wherein the capacitor is configured to store at least a bit of data.

[0069] In some embodiments, a first conduction path extends from a corresponding nonvolatile memory cell through a first transistor and a second transistor to ground, and a second conduction path extends from a corresponding nonvolatile memory cell through a third transistor to ground.

[0070] In some embodiments, the first access circuit includes a first transistor and a second transistor, and the second access circuit includes a third transistor.

[0071] In some embodiments, the first to third transistors are configured to be simultaneously activated when a programming voltage is applied to the corresponding nonvolatile memory cell through one of the first access lines.

[0072] In some embodiments, one source / drain terminal of the first transistor is connected to the second access line, and one source / drain terminal of the second transistor is grounded.

[0073] In some embodiments, one source / drain terminal of the third transistor is connected to the second access line, and another source / drain terminal of the third transistor is connected to ground.

[0074] In some embodiments, when each nonvolatile memory cell is configured to be programmed by a current flowing through the corresponding first access line and the nonvolatile memory cell itself, the current is configured to be divided into two independent currents flowing through the first conduction path and the second conduction path, respectively.

[0075] In some embodiments, the nonvolatile memory cell is configured to be programmed from a first resistance state to a second resistance state.

[0076] In some embodiments, the memory circuit includes: a third access circuit physically disposed in the middle of the memory array in a lateral direction, wherein the third access circuit is configured to provide a third conduction path through a corresponding second access line.

[0077] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory cell coupled between a first access line and a second access line, wherein the first access line and the second access line both extend in a lateral direction; a first access circuit physically disposed at a first side of the memory cell in the lateral direction, wherein the first access circuit comprises a first sub-circuit and a second sub-circuit; and a second access circuit physically disposed at a second side of the memory cell in the lateral direction, the second side being opposite to the first side, wherein the second access circuit comprises a third sub-circuit and a fourth sub-circuit; wherein the first sub-circuit is configured to couple a programming voltage to the memory cell through the first access line, and the second sub-circuit and the third sub-circuit are both configured to provide a corresponding conduction path from the memory cell to ground when the fourth sub-circuit is deactivated.

[0078] In some embodiments, a memory cell includes an access transistor and a resistor coupled in series with each other, wherein the resistor is configured to store at least a bit of data.

[0079] In some embodiments, a memory cell includes an access transistor and a capacitor coupled in series with each other, wherein the capacitor is configured to store at least a bit of data.

[0080] In some embodiments, the first sub-circuit is configured to provide a first conduction path through the second access line, and the third sub-circuit is configured to provide a second conduction path through the second access line.

[0081] In some embodiments, a first conduction path extends from the memory cell through the first transistor and the second transistor to ground, and a second conduction path extends from the memory cell through the third transistor to ground.

[0082] In some embodiments, the first access circuit includes a first transistor and a second transistor, and the second access circuit includes a third transistor.

[0083] In some embodiments, when a program voltage is applied to corresponding memory cells through a first access line, the first to third transistors are configured to be simultaneously activated.

[0084] According to one aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: activating a first access circuit physically disposed on a first side of a memory array in a lateral direction, wherein the memory array includes a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are arranged along a plurality of first access lines and a plurality of second access lines, and the first access lines and the second access lines both extend through the memory array in the lateral direction; activating a second access circuit physically disposed on a second side of the memory array in the lateral direction, wherein the second side is opposite to the first side; receiving a first current flowing through the memory array; conducting a second current flowing through the first access circuit via a first conduction path; and conducting a third current flowing through the second access circuit via a second conduction path, wherein the first access circuit is configured to couple a programming voltage to each nonvolatile memory cell through a corresponding first access line and provide a first conduction path through a corresponding second access line, and the second access circuit is configured to provide a second conduction path through a corresponding second access line.

[0085] In some embodiments, the method further includes: conducting a fourth current flowing through a third access circuit via a third conduction path, wherein the third access circuit is physically disposed in the middle of the memory array in a lateral direction, wherein the third access circuit is configured to provide a third conduction path through a corresponding second access line.

[0086] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory circuit, comprising: A memory array comprising a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are arranged along a plurality of first access lines and a plurality of second access lines, the first access lines and the second access lines each extending through the memory array in a lateral direction; a first access circuit physically disposed at a first side of the memory array in the lateral direction; and a second access circuit physically disposed on a second side of the memory array in the lateral direction, wherein the second side is opposite to the first side; The first access circuit is configured to couple a programming voltage to each of the nonvolatile memory cells through the corresponding first access line and provide a first conduction path through the corresponding second access line, and the second access circuit is configured to provide a second conduction path through the corresponding second access line.

2. The memory circuit according to claim 1, wherein: Each of the nonvolatile memory cells includes an access transistor and a resistor coupled in series with each other, wherein the resistor is configured to store at least a data bit.

3. The memory circuit according to claim 1, wherein: Each of the nonvolatile memory cells includes an access transistor and a capacitor coupled in series with each other, wherein the capacitor is configured to store at least a data bit.

4. The memory circuit according to claim 1, wherein: The first conduction path extends from the corresponding nonvolatile memory cell through a first transistor and a second transistor to ground, and the second conduction path extends from the corresponding nonvolatile memory cell through a third transistor to ground.

5. The memory circuit according to claim 4, wherein: When the program voltage is applied to the corresponding nonvolatile memory cell through one of the first access lines, the first to third transistors are configured to be activated simultaneously.

6. The memory circuit according to claim 1, wherein: When each of the nonvolatile memory cells is configured to be programmed by a current flowing through the corresponding first access line and the nonvolatile memory cell itself, the current is configured to be split into two independent currents flowing through the first conduction path and the second conduction path, respectively.

7. A memory circuit comprising: a memory cell coupled between a first access line and a second access line, wherein the first access line and the second access line both extend in a lateral direction; a first access circuit physically disposed at a first side of the memory cell in the lateral direction, wherein the first access circuit includes a first sub-circuit and a second sub-circuit; and a second access circuit, physically disposed on a second side of the memory cell in the lateral direction, the second side being opposite to the first side, wherein the second access circuit includes a third sub-circuit and a fourth sub-circuit; The first subcircuit is configured to couple a programming voltage to the memory cell through the first access line, and the second subcircuit and the third subcircuit are both configured to provide a corresponding conduction path from the memory cell to ground when the fourth subcircuit is deactivated.

8. The memory circuit according to claim 7, wherein: The first sub-circuit is configured to provide a first conduction path through the second access line, and the third sub-circuit is arranged to provide a second conduction path through the second access line.

9. The memory circuit according to claim 8, wherein: The first conduction path extends from the memory cell through the first transistor and the second transistor to ground, and the second conduction path extends from the memory cell through the third transistor to ground.

10. A method of operating a memory circuit, comprising: activating a first access circuit physically disposed on a first side of a memory array in a lateral direction, wherein the memory array includes a plurality of nonvolatile memory cells, wherein the nonvolatile memory cells are arranged along a plurality of first access lines and a plurality of second access lines, each of the first access lines and the second access lines extending through the memory array in the lateral direction; activating a second access circuit physically disposed on a second side of the memory array in the lateral direction, wherein the second side is opposite to the first side; receiving a first current flowing through the memory array; conducting a second current through the first access circuit via a first conduction path; and conducting a third current through the second access circuit via a second conduction path, The first access circuit is configured to couple a programming voltage to each of the nonvolatile memory cells through the corresponding first access line and provide the first conduction path through the corresponding second access line, and the second access circuit is configured to provide the second conduction path through the corresponding second access line.

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