Nonvolatile memory device including plurality of page buffers

Abstract

The present disclosure relates to a non-volatile memory device including a plurality of page buffers and a method of operating the same, the memory device including: a memory cell array having a plurality of memory cells; a plurality of page buffers connected to the memory unit; and an enable control circuit configured to divide the page buffers into P groups, sequentially enable L groups among the P groups during an entry period of the operation mode, and adjust a duration of the entry period of the operation mode based on a value of L, where P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0156211, filed on November 13, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a memory device, and more particularly, to a memory device including a plurality of page buffers and an operating method of the memory device. Background Art

[0004] A memory system is a storage device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory systems are divided into volatile memory devices and non-volatile memory devices. A volatile memory device is a memory device in which the stored data is lost when the power is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non-volatile memory device is a memory device in which the stored data is retained even when the power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM, electrically erasable programmable ROM, flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is mainly divided into NOR type memory and NAND type memory.

[0005] The nonvolatile memory device may read or program data through a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a plurality of page buffers connected to the memory cell array through a plurality of bit lines.

[0006] In this case, the plurality of page buffers may each operate as a program driver or a sense amplifier.

[0007] For example, after a program operation starts, a plurality of page buffers may each transmit a voltage corresponding to data to be programmed into a plurality of bit lines.

[0008] Furthermore, after a read operation or a verification operation starts, a plurality of page buffers may each detect data stored in a selected memory cell through a plurality of bit lines. Summary of the invention

[0009] Various embodiments of the present disclosure are directed to providing a memory device and a method of operating the memory device that are capable of optimizing the time taken for an access operation when accessing data in units smaller than a page.

[0010] The technical objectives to be achieved by the embodiments of the present disclosure are not limited to the above objectives, and other objectives not described above can be clearly understood by a person skilled in the art in the art to which the present disclosure belongs from the following description.

[0011] According to an embodiment of the present disclosure, a memory device may include: a memory cell array including a plurality of memory cells; a plurality of page buffers connected to the memory cells; and an enable control circuit configured to divide the page buffers into P groups, sequentially enable L groups among the P groups during an entry time period of an operation mode, and adjust the duration of the entry time period of the operation mode based on the value of L, wherein P may be a natural number greater than or equal to 2, and L may be a natural number greater than or equal to 1 and less than or equal to P.

[0012] According to an embodiment of the present disclosure, a memory device may include: a memory cell array including a plurality of memory cells; a plurality of page buffers connected to the memory cells; and an enable control circuit configured to divide the page buffers into P groups, sequentially enable the P groups during an entry time period of a first operating mode, and simultaneously enable the P groups during an entry time period of a second operating mode, wherein the entry time period of the second operating mode is shorter than the entry time period of the first operating mode, and P may be a natural number greater than or equal to 2.

[0013] According to an embodiment of the present disclosure, an operating method of a memory device including multiple page buffers connected to multiple memory cells may include: dividing the page buffers into P groups; sequentially enabling L groups among the P groups during an entry time period of an operation mode; and adjusting the duration of the entry time period of the operation mode based on the value of L, wherein P may be a natural number greater than or equal to 2, and L may be a natural number greater than or equal to 1 and less than or equal to P.

[0014] According to an embodiment of the present disclosure, an operating method of a memory device including a plurality of page buffers connected to a plurality of memory cells may include: dividing the page buffers into P groups; sequentially enabling the P groups during an entry time period of a first operating mode; and simultaneously enabling the P groups during an entry time period of a second operating mode, wherein the entry time period of the second operating mode is shorter than the entry time period of the first operating mode, and P may be a natural number greater than or equal to 2.

[0015] The present technology can adjust the time taken for access based on the number of page buffers enabled when only some of a plurality of page buffers are enabled and used in order to access data in units smaller than a page.

[0016] Therefore, the time taken for access when only some of the plurality of page buffers are enabled and used in order to access data in units smaller than a page can be optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a diagram for describing an enabling operation of a page buffer in a memory device according to an embodiment of the present disclosure.

[0018] Figure 2 It is used to describe the embodiments according to the present disclosure. Figure 1 FIG. 1 is a diagram of a first embodiment of an enable control circuit among components of a memory device disclosed in FIG.

[0019] Figure 3 Is used to describe Figure 2 Schematic diagram of a signal generating unit among components of an enable control circuit disclosed in .

[0020] Figure 4 Is used to describe Figure 2 Schematic diagram of a first toggle control unit among the components of an enable control circuit disclosed in FIG.

[0021] Figure 5 Is used to describe Figure 2 Schematic diagram of a mode setting unit among the components of the enable control circuit disclosed in .

[0022] Figure 6 Is used to describe Figure 2 Schematic diagram of a second switching control unit among the components of the enabling control circuit disclosed in.

[0023] 7A to 7C Is used to describe Figure 2 Schematic diagram of the operation of the enable control circuit disclosed in .

[0024] Figure 8 It is used to describe the embodiments according to the present disclosure. Figure 1 A diagram of a second embodiment of an enable control circuit among components of a memory device disclosed in FIG.

[0025] Fig. 9 Is used to describe Figure 8 A diagram of a mode selection unit and a mode control unit among components of an enable control circuit disclosed in FIG.

[0026] Fig.10 Is used to describe Figure 8Schematic diagram of a reference signal control unit among the components of the enable control circuit disclosed in .

[0027] Fig.11A and Fig. 11B Is used to describe Figure 8 Schematic diagram of the operation of the enable control circuit disclosed in .

[0028] Fig.12 is a diagram for describing a detailed configuration of a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any one of the disclosed embodiments.

[0030] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0031] In this disclosure, the terms "comprises," "comprising," "includes," and "including" are open ended. As used in the appended claims, these terms specify the presence of the elements described and do not preclude the presence or addition of one or more other elements. The terms in the claims do not preclude the device from including other components (e.g., interface units, circuits, etc.).

[0032] In the present disclosure, various units, circuits, or other components may be described or claimed to be "configured to" perform one or more tasks. In this case, "configured to" is used to represent a structure by indicating that the block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even if the specified block / unit / circuit / component is not currently operating (e.g., not turned on or activated), it can be said that the block / unit / circuit / component is configured to perform a task. The blocks / units / circuit / components expressed using "configured to" include hardware, such as circuits, memories storing executable program instructions to implement operations, etc. In addition, "configured to" may include general structures (e.g., general circuits) that are manipulated by software and / or firmware (e.g., FPGAs or general processors that execute software) to operate in a manner that can perform related tasks. "Configured to" may also include adjusting a manufacturing process (e.g., semiconductor manufacturing equipment) to manufacture a device (e.g., an integrated circuit) that implements or performs one or more tasks.

[0033] As used in this disclosure, the term "circuit" or "logic" refers to all of the following: (a) pure hardware circuit implementations (e.g., implementations of pure analog and / or digital circuits) and (b) combinations of circuits and software (and / or firmware), such as, as applicable: (i) a combination of a processor or (ii) portions of a processor / software (including a digital signal processor), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions, and (c) circuits, such as a microprocessor or a portion of a microprocessor, that require software or firmware for operation even if the software or firmware is not physically present. The definition of "circuit" or "logic" applies to all uses of the term in this application, including in any claims. As a further example, as used in this application, the term "circuit" or "logic" also covers implementations consisting of only a processor (or multiple processors) or a portion of a processor and accompanying software and / or firmware for the processor (or multiple processors). For example, if the term "circuit" or "logic" applies to a particular claim element, an integrated circuit of a memory device is also covered.

[0034] As used herein, the terms "first," "second," "third," etc., are used as labels for nouns following these terms and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" do not necessarily mean that the first value must be written before the second value. In addition, although these terms may be used herein to distinguish various components, these components are not limited by these terms. These terms are used to distinguish one component from another component with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0035] In addition, the term "based on" is used to describe one or more factors that affect the determination. The term does not exclude other factors that may affect the determination. That is, the determination may be based only on these factors, or at least in part on these factors. For example, the phrase "A is determined based on B." Although in this case, B is a factor that affects the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based only on B.

[0036] In this document, an item of data, a data item, a data entry, or an entry of data may be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digital scanned image, a portion of a video or audio signal, metadata, or any other entity that may be represented by a bit sequence. According to an embodiment, a data item may include a discrete object. According to another embodiment, a data item may include an information unit within a transmission data packet between two different components.

[0037] Figure 1 is a diagram for describing an enabling operation of a page buffer in the memory device 150 according to an embodiment of the present disclosure.

[0038] Reference Figure 1 , a memory device 150 according to an embodiment of the present disclosure may include a memory cell array 10 , a plurality of page buffers 20 , an enable control circuit 30 , and a data input and output (input / output) circuit 40 .

[0039] The memory cell array 10 may include a plurality of memory blocks, for example, MEMORY BLOCK<1:6>. Each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells. One memory block may include a plurality of pages.

[0040] A memory block can be understood as a group of nonvolatile memory cells whose data is removed together by an erase operation. Each of the memory blocks may include pages, and from a logical point of view, nonvolatile memory cells are grouped by pages, for example, storing data together during a programming operation, or outputting data together during a read operation. For example, a memory block may include multiple pages. A page may include multiple nonvolatile memory cells.

[0041] From a physical perspective different from a logical perspective such as a program operation or a read operation, one memory block may include a plurality of word lines. One word line may include a plurality of nonvolatile memory cells.

[0042] In this case, according to the number of bits that can be stored or represented in one nonvolatile memory cell, one word line can correspond to at least one page. For example, when a nonvolatile memory cell is a single-layer cell (SLC) storing one bit of data, one word line can correspond to one page. When a nonvolatile memory cell is a double-layer cell (DLC) storing two bits of data, one word line can correspond to two pages. When a nonvolatile memory cell is a triple-layer cell (TLC) storing three bits of data, one word line can correspond to three pages. When a nonvolatile memory cell is a quad-layer cell (QLC) storing four bits of data, one word line can correspond to four pages. In this way, when a nonvolatile memory cell is a multi-layer cell storing five or more bits of data, one word line can correspond to five or more pages.

[0043] The plurality of page buffers 20 may be connected to the plurality of memory cells included in the memory cell array 10 through the plurality of bit lines BL1s, BL2s, BL3s, and BL4s. According to an embodiment, each of the plurality of page buffers 20 may be connected to one or two bit lines.

[0044] The plurality of page buffers 20 may communicate data DATA with the data input / output circuit 40. After programming starts, the plurality of page buffers 20 may receive data DATA to be stored in the plurality of page buffers 20 through the data input / output circuit 40 and the data lines DL. The operation of the page buffers 20 may be responsive to a control circuit (e.g., Fig.12 The page buffer 20 may be controlled by a control signal PBSIGNALS generated by a control logic unit 504 of the control logic unit 504. In particular, the page buffer 20 may be divided into P groups, for example, 4 groups PB1s, PB2s, PB3s, and PB4s. The P groups PB1s, PB2s, PB3s, and PB4s may be enabled in response to the P group enable signal PBEN<1:4>, respectively. The group enable signal PBEN<1:4> is generated by an enable control circuit 30 that may be included in the control logic unit 504. In this case, enabling all P group enable signals PBEN<1:4> may mean enabling all multiple page buffers 20. In addition, enabling all multiple page buffers 20 may mean reading data from the memory cell array 10 or programming data into the memory cell array 10 in units of pages. For reference, the P group enable signal PBEN<1:4> may be included in the control signal PBSIGNALS generated by the control logic unit 504. In this case, P may be a natural number equal to or greater than 2. In the figure, P is 4.

[0045] After the program operation starts, the plurality of page buffers 20 may store data DATA received from the outside (e.g., a memory controller) through the data input / output circuit 40, and may transmit a program enable voltage or a program inhibit voltage to the bit lines BL1s, BL2s, BL3s, and BL4s based on the stored data DATA. For example, the program enable voltage may be a ground voltage VSS. The program inhibit voltage may be a power supply voltage VCORE.

[0046] After the read operation starts, the plurality of page buffers 20 may sense data DATA based on a voltage or current of each of the bit lines BL1s, BL2s, BL3s, and BL4s, and may transmit the sensed data DATA to the data input / output circuit 40 through the data lines DL, where the voltage or current is determined based on a threshold voltage of a memory cell of a selected page.

[0047] After the erase operation starts, the plurality of page buffers 20 may float the bit lines BL1s, BL2s, BL3s, and BL4s, or apply the ground voltage VSS to the bit lines BL1s, BL2s, BL3s, and BL4s.

[0048] The data input / output circuit 40 may include a plurality of input and output buffers receiving data DATA input to the plurality of input and output buffers. After a program operation starts, the data input / output circuit 40 may receive data DATA to be stored from the outside.

[0049] More specifically, the enable control circuit 30 can divide the page buffer 20 into P groups PB1s, PB2s, PB3s and PB4s, and can adjust the time spent enabling each of the P groups PB1s, PB2ss, PB3s and PB4s according to the manner in which the P groups PB1, PB2s, PB3s and PB4s are enabled.

[0050] In the first embodiment, during the entry period of the operation mode, the enable control circuit 30 may sequentially enable only the L groups among the P groups PB1s, PB2s, PB3s, and PB4s. In particular, the enable control circuit 30 may adjust the duration of the entry period of the operation mode based on the value of L. In this case, L may be a natural number equal to or greater than 1 and equal to or less than P.

[0051] When P is 4 and L is 1, during the entry period of the operation mode, the enable control circuit 30 may enable only one group (PB1s, PB2s, PB3s, or PB4s) of the four groups PB1s, PB2s, PB3s, and PB4s. When only one group of the four groups PB1s, PB2s, PB3s, and PB4s is enabled as described above, this may result in a state in which the memory cell array 10 accesses data in units of 1 / 4 pages.

[0052] When P is 4 and L is 2, during the entry period of the operation mode, the enable control circuit 30 may sequentially enable only two of the four groups PB1s, PB2s, PB3s, and PB4s (PB1s and PB2s, PB1s and PB3s, PB1s and PB4s, PB2s and PB3s, or PB3s and PB4s). When only two of the four groups PB1s, PB2s, PB3s, and PB4s are enabled as described above, this may result in a state where the memory cell array 10 accesses data in units of 1 / 2 pages. In this case, the enable control circuit 30 may set the duration of the operation period corresponding to the case where L is 2 to be longer than the duration of the operation period corresponding to the case where L is 1.

[0053] When P is 4 and L is 3, during the entry period of the operation mode, the enable control circuit 30 may sequentially enable only three of the four groups PB1s, PB2s, PB3s, and PB4s (PB1s, PB2s, and PB3s; PB1s, PB3s, and PB4s; or PB2s, PB3s, and PB4s). When only three of the four groups PB1s, PB2s, PB3s, and PB4s are enabled as described above, this may result in a state where the memory cell array 10 accesses data in units of 3 / 4 pages. In this case, the enable control circuit 30 may set the duration of the operation period corresponding to the case where L is 3 to be longer than the duration of the operation period corresponding to the case where L is 2.

[0054] When P is 4 and L is 4, the enable control circuit 30 may set all of the four groups PB1s, PB2s, PB3s, and PB4s to the groups PB1s, PB2s, PB3s, and PB4s, and sequentially enable the groups PB1s, PB2s, PB3s, and PB4s during the entry period of the operation mode. When all of the four groups PB1s, PB2s, PB3s, and PB4s are enabled as described above, this may result in a state in which the memory cell array 10 accesses data in units of one page. In this case, the enable control circuit 30 may set the duration of the operation period corresponding to the case where L is 4 to be longer than the duration of the operation period corresponding to the case where L is 3.

[0055] As described above, in the first embodiment, when only the L group among the P groups PB1s, PB2s, PB3s, and PB4s is selected and the L groups are sequentially enabled during the entry period of the operation mode, the enable control circuit 30 can adjust the time taken to enable each of the L groups based on the size of access data by adjusting the duration of the entry period of the operation period based on the size of L. For example, the enable control circuit 30 can control the time taken to access data of one page to be longer than the time taken to access data of 1 / 2 page.

[0056] For reference, refer to Figures 2 to 7C A detailed embodiment of the enable control circuit 30 in the first embodiment is described.

[0057] In a second embodiment, during an entry time period of a first operating mode, the enable control circuit 30 can sequentially enable P groups PB1s, PB2s, PB3s and PB4s, and during an entry time period of a second operating mode that is shorter than the entry time period of the first operating mode, the P groups PB1s, PB2s, PB3s and PB4s can be simultaneously enabled.

[0058] When P is 4, during the entry time period of the first operation mode, the enable control circuit 30 can sequentially enable the four groups of PB1s, PB2s, PB3s and PB4s, and during the entry time period of the second operation mode, the four groups of PB1s, PB2s, PB3s and PB4s can be enabled simultaneously. In this case, the duration of the entry time period of the second operation mode can be half (1 / 2) of the duration of the entry time period of the first operation mode.

[0059] As described above, in the second embodiment, the enable control circuit 30 can adjust the time spent enabling each of the P groups PB1s, PB2s, PB3s and PB4s according to the type of operation mode by adjusting the method of accessing the P groups PB1s, PB2s, PB3s and PB4s according to the type of operation mode.

[0060] For reference, refer to Figures 8 to 11B A detailed embodiment of the enable control circuit 30 in the second embodiment is described.

[0061] Figure 2 It is used to describe the embodiments according to the present disclosure. Figure 1 FIG. 1 is a diagram of a first embodiment of an enable control circuit 30 among components of a memory device 150 in FIG.

[0062] Reference Figure 2 , refer to Figure 1The enable control circuit 30 in the described first embodiment may include a signal generating unit 301 , a first switching control unit 302 , a mode setting unit 303 and a second switching control unit 304 .

[0063] First, the enable control circuit 30 may divide the page buffer 20 into P groups PB1s, PB2s, PB3s, and PB4s. In addition, the enable control circuit 30 may enter an operation mode for accessing the memory cell array 10, and then may sequentially enable each of the selected L groups among the P groups PB1s, PB2s, PB3s, and PB4s, and then may exit the operation mode. In this case, since L may be a natural number equal to or greater than 1 and equal to or less than P, all of the P groups PB1s, PB2s, PB3s, and PB4s may be sequentially enabled based on the value of L, or only some of the P groups PB1s, PB2s, PB3s, and PB4s may be sequentially enabled.

[0064] According to an embodiment, when P is 4, the enable control circuit 30 may divide the page buffer 20 into four groups PB1s, PB2s, PB3s, and PB4s.

[0065] In this state, when L is 1, the enable control circuit 30 can enter the operation mode, and then can enable only one group (PB1s, PB2s, PB3s or PB4s) of the four groups PB1s, PB2s, PB3s and PB4s during the entry time period of the operation mode, and then can exit the operation mode at the moment when the group enabled for the first time is disabled.

[0066] When L is 2, the enable control circuit 30 may enter the operation mode, and then may sequentially enable only two of the four groups PB1s, PB2s, PB3s, and PB4s (PB1s and PB2s, PB1s and PB3s, PB1s and PB4s, PB2s and PB3s, or PB3s and PB4s) during the entry period of the operation mode, and then may exit the operation mode at the moment when the group enabled for the second time is disabled. In this case, the moment when the group enabled for the second time corresponding to the case where L is 2 is disabled may be a moment later than the moment when the group enabled for the first time corresponding to the case where L is 1 is disabled. That is, the duration of the entry period of the operation mode corresponding to the case where L is 2 may be longer than the duration of the entry period of the operation mode corresponding to the case where L is 1.

[0067] When L is 3, the enable control circuit 30 may enter the operation mode, and then may sequentially enable only three of the four groups PB1s, PB2s, PB3s, and PB4s (PB1s, PB2s, and PB3s; PB1s, PB2s, and PB4s; or PB2s, PB3s, and PB4s) during the entry period of the operation mode, and then may exit the operation mode at the moment when the group enabled for the third time is disabled. In this case, the moment when the group enabled for the third time corresponding to the case where L is 3 is disabled may be a moment later than the moment when the group enabled for the second time corresponding to the case where L is 2 is disabled. That is, the duration of the entry period of the operation mode corresponding to the case where L is 3 may be longer than the duration of the entry period of the operation mode corresponding to the case where L is 2.

[0068] When L is 4, the enable control circuit 30 may enter the operation mode, and then may sequentially enable each of the four groups PB1s, PB2s, PB3s, and PB4s during the entry period of the operation mode, and then may exit the operation mode at the moment when the fourth enabled group is disabled. In this case, the moment when the fourth enabled group corresponding to the case where L is 4 is disabled may be a moment later than the moment when the third enabled group corresponding to the case where L is 3 is disabled. That is, the duration of the entry period of the operation mode corresponding to the case where L is 4 may be longer than the duration of the entry period of the operation mode corresponding to the case where L is 3.

[0069] More specifically, the signal generating unit 301 in the enable control circuit 30 may generate the selection control signal OPC for selecting the value of L in response to the group selection signal SELGP<1:2>.

[0070] According to an embodiment, when P is 4, the signal generating unit 301 may generate a selection control signal OPC for selecting the value of L to be one of 1 to 4.

[0071] In response to the start enable signal STEN and the selection control signal OPC, the first switch control unit 302 in the enable control circuit 30 may sequentially switch the first reference signal to the Lth reference signal among the P reference signals RF<1:4>.

[0072] According to an embodiment, when P is 4 and L is 2, in response to the start enable signal STEN, the first switching control unit 302 may sequentially switch the first reference signal and the second reference signal RF<1:2>. That is, the first switching control unit 302 may switch the first reference signal RF1 in response to the start enable signal STEN, may switch the second reference signal RF2 in response to the switching of the first reference signal RF, and may not switch the third reference signal and the fourth reference signal RF<3:4>.

[0073] According to another embodiment, when P is 4 and L is 3, in response to the start enable signal STEN, the first switch control unit 302 may sequentially switch the first to third reference signals RF<1:3>. That is, the first switch control unit 302 may switch the first reference signal RF1 in response to the start enable signal STEN, may switch the second reference signal RF2 in response to the switching of the first reference signal RF1, may switch the third reference signal RF3 in response to the switching of the second reference signal RF2, and may not switch the fourth reference signal RF4.

[0074] The mode setting unit 303 in the enable control circuit 30 can allow the enable control circuit 30 to enter the operation mode in response to the start enable signal STEN, and can allow the enable control circuit 30 to exit the operation mode in response to switching of the Lth reference signal among the L reference signals RF<1:4>.

[0075] According to an embodiment, the mode setting unit 303 may allow the enable control circuit 30 to enter the operation mode by activating the operation period signal OPSEC in response to the start enable signal STEN. In addition, the mode setting unit 303 may allow the enable control circuit 30 to exit the operation mode by deactivating the operation period signal OPSEC in response to switching of the Lth reference signal among the L reference signals RF<1:4> that are sequentially switched.

[0076] During the entry period of the operation mode, the second switching control unit 304 in the enable control circuit 30 can select the L group enable signal among the P group enable signals PBEN<1:4> in response to the group selection signal SELGP<1:2>. That is, during the activation period of the operation period signal OPSEC, the second switching control unit 304 can select the L group enable signal among the P group enable signals PBEN<1:4> in response to the group selection signal SELGP<1:2>. In this case, it can be seen that among the group selection signals SELGP<1:2>, only the first group selection signal SELGP1 and the inverted signal SELGP1B are directly input to the second switching control unit 304 shown in the figure. However, as described in the aforementioned operation of the signal generating unit 301, based on the logic level of the selection control signal OPC generated in response to the first group selection signal and the second group selection signal SELGP<1:2>, only the first reference signal and the second reference signal RF<1:2> among the four reference signals RF<1:4> may be sequentially switched, or all of the first reference signal to the fourth reference signal RF<1:4> may be sequentially switched. Therefore, both the first group selection signal and the second group selection signal SELGP<1:2> may be considered to participate in the operation of the second switching control unit 304.

[0077] In this case, each of the P group enable signals PBEN<1:4> may be a signal for enabling each of the P groups PB1s, PB2s, PB3s, and PB4s. For example, when the first group enable signal PBEN1 among the P group enable signals PBEN<1:4> is activated, the first group PB1s among the P groups PB1s, PB2s, PB3s, and PB4s may be enabled. As another example, when the third group enable signal PBEN3 among the P group enable signals PBEN<1:4> is activated, the third group PB3s among the P groups PB1s, PB2s, PB3s, and PB4s may be enabled.

[0078] During the entry period of the operation mode, the second switching control unit 304 may switch the selected L group enable signals in response to the first reference signal to the Lth reference signal, respectively. That is, during the activation period of the operation period signal OPSEC, the second switching control unit 304 may switch the selected L group enable signals in response to the first reference signal to the Lth reference signal, respectively.

[0079] According to an embodiment, when P is 4 and L is 2, in response to the group selection signal SELGP<1:2>, the second switching control unit 304 can select two groups of four groups of enable signals PBEN<1:4>, for example, the first group of enable signals and the second group of enable signals PBEN<1:2>, the first group of enable signals and the third group of enable signals PBEN<1, 3>, the first group of enable signals and the fourth group of enable signals PBEN<1, 4>, the second group of enable signals and the third group of enable signals PBEN<2:3>, the second group of enable signals and the fourth group of enable signals PBSEN<2, 4> or the third group of enable signals and the fourth group of enable signals PBSEN<3,4>. In addition, the second switching control unit 304 can switch the two selected enable signals PBEN<1, 2>, PBEN<1, 3>, PBEN<1, 4>, PBEN<2,3>, PBEN<2, 4> or PBEN<3, 4> in response to the first reference signal and the second reference signal RF<1:2> respectively.

[0080] According to another embodiment, when P is 4 and L is 3, in response to the group selection signal SELGP<1:2>, the second switching control unit 304 can select three of the four groups of enable signals PBEN<1:4>, for example, the first group of enable signals to the third group of enable signals PBEN<1:3>, the first group of enable signals, the third group of enable signals and the fourth group of enable information PBEN<1, 3:4>, or the second group of enable signals to the fourth group of enable signals PBEN<2:4>. In addition, the second switching control unit 304 can switch the three groups of enable signals PBEN<1:3>, PBEN<1, 3:4> or PBEN<2:4> that have been selected in response to the first reference signal to the third reference signal RF<1:3>, respectively.

[0081] Figures 3 to 6 Detailed circuit configurations of the signal generating unit 301 , the first switching control unit 302 , the mode setting unit 303 , and the second switching control unit 304 included in the enable control circuit 30 when P is 4 and L is 2 or 4 are shown.

[0082] That is, in Figures 3 to 6 , when L is 2, among the four groups PB1s, PB2s, PB3s and PB4s, the first group PB1s and the second group PB2s are selected as the enable targets, or the third group PB3s and the fourth group PB4s are selected as the enable targets. In addition, when L is 4, all of the four groups PB1s, PB2s, PB3s and PB4s are selected as the enable targets.

[0083] However, Figures 3 to 6 The circuit diagram disclosed in is merely an embodiment and may be reconstructed in different forms according to the designer's choice.

[0084] Figure 3 Is used to describe Figure 2 2 is a diagram of a signal generating unit 301 among the components of the enable control circuit 30 disclosed in FIG.

[0085] Reference Figure 3 , the signal generating unit 301 included in the enable control circuit 30 may include an AND gate AND1 and an inverter IV1 .

[0086] The AND gate AND1 may receive the group selection signal SELGP<1:2> and output a selection control signal OPC.

[0087] The inverter IV1 may output an inversion signal SELGP1B by inverting the first group selection signal SELGP1 .

[0088] According to an embodiment, the first group selection signal SELGP1 may be a signal for selecting the first group PB1s and the second group PB2s as enable targets among the four groups PB1s, PB2s, PB3s, and PB4s.

[0089] The second group selection signal SELGP2 may be a signal for selecting the third group PB3s and the fourth group PB4s as enable targets among the four groups PB1s, PB2s, PB3s, and PB4s.

[0090] According to an embodiment, when the first group selection signal SELGP1 has a logic high level and the second group selection signal SELGP2 has a logic low level, the AND gate AND1 may output the selection control signal OPC having a logic low level, and the inverter IV1 may output the inversion signal SELGP1B having a logic low level. As described above, when the signal generation unit 301 generates the selection control signal OPC having a logic low level, the first group selection signal SELGP1 having a logic high level, and the inversion signal SELGP1B of the first group selection signal SELGP1 having a logic low level, the first group PB1s and the second group PB2s among the four groups PB1s, PB2s, PB3s, and PB4s may be selected as enable targets.

[0091] According to another embodiment, when the first group selection signal SELGP1 has a logic low level and the second group selection signal SELGP2 has a logic high level, the AND gate AND1 may output the selection control signal OPC having a logic low level, and the inverter IV1 may output the inversion signal SELGP1B having a logic high level. As described above, when the signal generating unit 301 generates the selection control signal OPC having a logic low level, the first group selection signal SELGP1 having a logic low level, and the inversion signal SELGP1B of the first group selection signal SELGPS1 having a logic high level, the third group PB3s and the fourth group PB4s among the four groups PB1s, PB2s, PB3s, and PB4s may be selected as enable targets.

[0092] According to another embodiment, when the first group selection signal SELGP1 has a logic high level and the second group selection signal SELGP2 has a logic high level, the AND gate AND1 may output the selection control signal OPC having a logic high level, and the inverter IV1 may output the inversion signal SELGP1B having a logic low level. As described above, when the signal generation unit 301 generates the selection control signal OPC having a logic high level, the first group selection signal SELGP1 having a logic high level, and the inversion signal SELGP1B of the first group selection signal SELGP1 having a logic low level, all of the four groups PB1s, PB2s, PB3s, and PB4s may be selected as enable targets.

[0093] Figure 4 Is used to describe Figure 2 2 is a diagram of a first switching control unit 302 among the components of the enable control circuit 30 disclosed in FIG.

[0094] Reference Figure 4 , the first switching control unit 302 included in the enable control circuit 30 may include P flip-flops (eg, F / F1 , F / F2 , F / F3 , and F / F4 ) connected in a daisy-chain form and an AND gate AND2 .

[0095] As described above, the first switching control unit 302 can select the Lth trigger F / F2 or F / F4 among the P triggers F / F1, F / F2, F / F3 and F / F4 based on the selection control signal OPC, and then can output L reference signals RF<1:2> or RF<1:4> to the output stages of the first to Lth triggers F / F1 and F / F2 or F / F1 to F / F4 in response to the start enable signal STEN applied to the input stage of the first trigger F / F1.

[0096] Specifically, each of the P flip-flops F / F1, F / F2, F / F3, and F / F4 included in the first switching control unit 302 may be a D flip-flop. That is, each of the P flip-flops F / F1, F / F2, F / F3, and F / F4 may output a signal to an output stage of each of the P flip-flops F / F1, F / F2, F / F3, and F / F4 by delaying a signal applied to an input stage in each of the P flip-flops F / F1, F / F2, F / F3, and F / F4. It can be seen that since P is 4 in the above description, the four flip-flops F / F1, F / F2, F / F3, and F / F4 are connected in a daisy chain form in the figure.

[0097] In response to the selection control signal OPC, the AND gate AND2 included in the first switching control unit 302 can select the Lth flip-flop F / F2 or F / F4 among the P flip-flops F / F1, F / F2, F / F3, and F / F4. As described above, L is 2 or 4. Therefore, in response to the selection control signal OPC, the AND gate AND2 can select whether to transmit the signal output from the output stage of the second flip-flop F / F2 to the input stage of the third flip-flop F / F3. The output stage of the second flip-flop F / F2 is set at the second position among the four flip-flops F / F1, F / F2, F / F3, and F / F4. The input stage of the third flip-flop F / F3 is set at the third position among the four flip-flops F / F1, F / F2, F / F3, and F / F4.

[0098] According to an embodiment, when L is 2, the selection control signal OPC may have a logic low level. Therefore, in response to the start enable signal STEN being applied to the input stage of the first flip-flop F / F1 set at the first position among the four flip-flops F / F1, F / F2, F / F3 and F / F4, the first reference signal RF1 may be output to the output stage of the first flip-flop F / F1. In response to the first reference signal RF1 being applied to the input stage of the second flip-flop F / F2, the second reference signal RF2 may be output to the output stage of the second flip-flop F / F2. Thereafter, the second reference signal RF2 may not be transmitted to the input stage of the third flip-flop F / F3 through the AND gate AND2. When L is 2, in response to the start enable signal STEN being switched, the first switching control unit 302 may sequentially switch the first reference signal and the second reference signal RF<1:2>.

[0099] According to another embodiment, when L is 4, the selection control signal OPC may have a logic high level. Therefore, in response to the start enable signal STEN being applied to the input stage of the first flip-flop F / F1 set at the first position, the first reference signal RF1 may be output to the output stage of the first flip-flop F / F1. In response to the first reference signal RF1 being applied to the input stage of the second flip-flop F / F2, the second reference signal RF2 may be output to the output stage of the second flip-flop F / F2. Thereafter, the second reference signal RF2 may be transmitted to the input stage of the third flip-flop F / F3 through the AND gate AND2. As described above, in response to the second reference signal RF2 being applied to the input stage of the third flip-flop F / F3, the third reference signal RF3 may be output to the output stage of the third flip-flop F / F3. In response to the third reference signal RF3 being applied to the input stage of the fourth flip-flop F / F4, the fourth reference signal RF4 may be output to the output stage of the fourth flip-flop F / F4. When L is 4, in response to the start enable signal STEN being switched, the first switching control unit 302 may sequentially switch the first reference signal to the fourth reference signal RF<1:4>.

[0100] Figure 5 Is used to describe Figure 2 2 is a diagram of a mode setting unit 303 among the components of the enable control circuit 30 disclosed in FIG.

[0101] Reference Figure 5 , the mode setting unit 303 included in the enable control circuit 30 may include a first multiplexer (MUX) MUX1 and an activation control unit 3031 .

[0102] As described above, the mode setting unit 303 can allow the enable control circuit 30 to enter the operation mode by activating the operation time period signal OPSEC in response to the start enable signal STEN, and can allow the enable control circuit 30 to exit the operation mode by deactivating the operation time period signal OPSEC in response to the switching of the Lth reference signal among the L reference signals RF<1:4> that are switched sequentially.

[0103] Specifically, MUX1 included in the mode setting unit 303 can select one of the second reference signal RF2 and the fourth reference signal RF4 in response to the selection control signal OPC and output the selected reference signal as the selected signal RFEND. Since L is 2 or 4 in the above description, such operation of MUX1 can be performed.

[0104] The activation control unit 3031 included in the mode setting unit 303 may activate the operation period signal OPSEC in response to the start enable signal STEN, and may deactivate the operation period signal OPSEC in response to the output signal RFEND of the MUX1 .

[0105] According to an embodiment, when L is 2, the selection control signal OPC may have a logic low level. Therefore, the signal RFEND output by MUX1 may be the second reference signal RF2. In this case, the activation control unit 3031 may have a state in which the activation control unit 303 activates the operation period signal OPSEC in response to the start enable signal STEN, and deactivates the operation period signal OPSEC in response to the second reference signal RF2. That is, the mode setting unit 303 may allow the enable control circuit 30 to enter the operation mode in response to the start enable signal STEN, and then may allow the enable control circuit 30 to exit the operation mode in response to the second reference signal RF2.

[0106] According to another embodiment, when L is 4, the selection control signal OPC may have a logic high level. Therefore, the signal RFEND output by MUX1 may be the fourth reference signal RF4. In this case, the activation control unit 3031 may have a state in which the activation control unit 303 activates the operation period signal OPSEC in response to the start enable signal STEN, and deactivates the operation period signal OPSEC in response to the fourth reference signal RF4. That is, the mode setting unit 303 may allow the enable control circuit 30 to enter the operation mode in response to the start enable signal STEN, and may allow the enable control circuit 30 to exit the operation mode in response to the fourth reference signal RF4.

[0107] Figure 6 Is used to describe Figure 2 2 is a diagram of a second switching control unit 304 among the components of the enabling control circuit 30 disclosed in FIG.

[0108] Reference Figure 6 , the second switching control unit 304 included in the enable control circuit 30 may include P MUXs MUX2 , MUX3 , MUX4 , and MUX5 , and P AND gates AND3 , AND4 , AND5 , and AND6 .

[0109] As described above, the second switching control unit 304 can select the L group enable signal among the P group enable signals PBEN<1:4> in response to the group selection signal SELGP<1:2>, and can switch the selected L group enable signal in response to the first reference signal to the Lth reference signal during the entry period of the operation mode, that is, in the state where the operation period signal OPSEC is activated. In this case, it can be seen that among the group selection signals SELGP<1:2>, only the first group selection signal SELGP1 and the inverted signal SELGP1B are directly input to the second switching control unit 304 shown in the figure. However, as described in the aforementioned operation of the signal generating unit 301, based on the logic level of the selection control signal OPC generated in response to the first group selection signal and the second group selection signal SELGP<1:2>, only the first reference signal and the second reference signal RF<1:2> among the four reference signals RF<1:4> can be sequentially switched, or all of the first reference signal to the fourth reference signal RF<1:4> can be sequentially switched. Therefore, both the first group of selection signals and the second group of selection signals SELGP<1:2> can be considered to participate in the operation of the second switching control unit 304 .

[0110] Specifically, the P MUXs MUX2 , MUX3 , MUX4 , and MUX5 and the P AND gates AND3 , AND4 , AND5 , and AND6 included in the second switching control unit 304 may correspond to the P group enable signals PBEN<1:4>, respectively.

[0111] During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the first group PB1 is selected as an enable target due to the first group selection signal and the second group selection signal SELGP<1:2> having a logic high level or having a logic high level and a logic low level, respectively, the MUX2 and the AND gate AND3 set at the first position among the P MUXs MUX2, MUX3, MUX4, and MUX5 and the P AND gates AND3, AND4, AND5, and AND6 may switch the first group enable signal PBEN1 in response to the switching of the first reference signal RF1. During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the first group PB1s is not selected as an enable target due to the first group selection signal SELGP1 having a logic low level, the MUX2 and the AND gate AND3 set at the first position may maintain the logic level of the first group enable signal PBEN1 at a logic low level regardless of whether the first reference signal RF1 is switched. During the exit period of the operation mode in which the operation period signal OPSEC has a logic low level, the MUX2 and the AND gate AND3 set at the first position may maintain the logic level of the first group enable signal PBEN1 at a logic low level.

[0112] During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the second group PB2s is selected as the enable target due to the first group selection signal and the second group selection signal SELGP<1:2> having a logic high level or having a logic high level and a logic low level respectively, the MUX3 and the AND gate AND4 set at the second position among the P MUXs MUX2, MUX3, MUX4 and MUX5 and the P AND gates AND3, AND4, AND5 and AND6 may switch the second group enable signal PBEN2 in response to the switching of the second reference signal RF2. During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the second group PB2s is not selected as the enable target due to the first group selection signal SELGP1 having a logic low level, the MUX3 and the AND gate AND4 set at the second position may maintain the logic level of the second group enable signal PBEN2 at a logic low level regardless of whether the second reference signal RF2 is switched. During the exit period of the operation mode in which the operation period signal OPSEC has a logic low level, the MUX3 and the AND gate AND4 set at the second position may maintain the logic level of the second group enable signal PBEN2 at a logic low level.

[0113] During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the third group PB3s is selected as the enable target due to the inversion signal SELGP1B of the first group selection signal SELGP1 and the second group selection signal SELGP2 having a logic low level and a logic high level, respectively, the MUX4 and the AND gate AND5 set at the third position among the P MUXs MUX2, MUX3, MUX4, and MUX5 and the P AND gates AND3, AND4, AND5, and AND6 may switch the third group enable signal PBEN3 in response to the switching of the third reference signal RF3. During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the third group PB3s is selected as the enable target due to the inversion signal SELGP1B of the first group selection signal SELGP1 and the second group selection signal SELGP2 having a logic high level, the MUX4 and the AND gate AND5 set at the third position may switch the third group enable signal PBEN3 in response to the switching of the third reference signal RF3. During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the third group PB3s is not selected as the enable target because both the inversion signal SELGP1B of the first group selection signal SELGP1 and the second group selection signal SELGP2 have a logic low level, the MUX4 and the AND gate AND5 set at the third position may not switch the third group enable signal PBEN3 because the third reference signal RF3 is not switched. During the exit period of the operation mode in which the operation period signal OPSEC has a logic low level, the MUX4 and the AND gate AND5 set at the third position may maintain the logic level of the third group enable signal PBEN3 at a logic low level.

[0114] During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the fourth group PB4s is selected as the enable target due to the inversion signal SELGP1B of the first group selection signal SELGP1 and the second group selection signal SELGP2 having a logic low level and a logic high level, respectively, the MUX5 and the AND gate AND6 set at the fourth position among the P MUXs MUX2, MUX3, MUX4, and MUX5 and the P AND gates AND3, AND4, AND5, and AND6 may switch the fourth group enable signal PBEN4 in response to the switching of the fourth reference signal RF4. During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the fourth group PB4s is selected as the enable target due to the inversion signal SELGP1B of the first group selection signal SELGP1 and the second group selection signal SELGP2 having a logic high level, the MUX5 and the AND gate AND6 set at the fourth position may switch the fourth group enable signal PBEN4 in response to the switching of the fourth reference signal RF4. During the entry period of the operation mode in which the operation period signal OPSEC has a logic high level, when the fourth group PB4s is not selected as the enable target because both the inversion signal SELGP1B of the first group selection signal SELGP1 and the second group selection signal SELGP2 have a logic low level, since the fourth reference signal RF4 is not switched, the MUX5 and the AND gate AND6 set at the fourth position may not switch the fourth group enable signal PBEN4. During the exit period of the operation mode in which the operation period signal OPSEC has a logic low level, the MUX5 and the AND gate AND6 set at the fourth position may maintain the logic level of the fourth group enable signal PBEN4 at a logic low level.

[0115] 7A to 7C Is used to describe Figure 2 2 is a diagram of the above-described operation of the enable control circuit 30 disclosed in FIG.

[0116] Reference Fig. 7A , describes a situation in which, in the enable control circuit 30 , four groups PB1 , PB2s , PB3s , and PB4s are all selected as enable targets because both the first group selection signal and the second group selection signal SELGP<1:2> have a logic high level.

[0117] Specifically, since both the first group selection signal and the second group selection signal SELGP<1:2> have a logic high level, the selection control signal OPC can have a logic high level. In this state, when the operation period signal OPSEC is activated to a logic high level in response to the start enable signal STEN being switched, the enable control circuit 30 can enter the operation mode.

[0118] During the period in which the operation period signal OPSEC maintains a logic high level, the first to fourth group enable signals PBEN<1:4> may be sequentially switched in response to the first to fourth reference signals RF<1:4> being sequentially switched. The first to fourth groups PB1s, PB2s, PB3s, and PB4s may be sequentially enabled in response to the first to fourth group enable signals PBEN<1:4> being sequentially switched as described above.

[0119] Since the operation period signal OPSEC is disabled to a logic low level in response to switching of the fourth reference signal RF4 (ie, the fourth reference signal among the first to fourth reference signals RF<1:4>), the enable control circuit 30 may exit the operation mode.

[0120] It can be seen that, since the operation period signal OPSEC is activated in response to the switching of the first reference signal RF1 (i.e., the first reference signal among the first reference signal to the fourth reference signal RF<1:4>) as described above, and is deactivated in response to the switching of the fourth reference signal RF4 (i.e., the fourth reference signal among the first reference signal to the fourth reference signal RF<1:4>), the operation period signal OPSEC maintains the state in which the operation period signal OPSEC is activated during the first time t1. In this case, the activation period of the operation period signal OPSEC may refer to the length of the period in which the enable control circuit 30 has entered the operation mode.

[0121] When both the first and second group selection signals SELGP<1:2> have a logic high level, the enable control circuit 30 may enter the operation mode at the first time t1 to sequentially enable all of the first to fourth groups PB1s, PB2s, PB3s, and PB4s.

[0122] Reference Figure 7B , describes a situation in which, in the enable control circuit 30, since the first group selection signal SELGP1 has a logic high level and the second group selection signal SELGP2 has a logic low level, only the first group PB1s and the second group PB2s among the four groups PB1s, PB2s, PB3s and PB4s are selected as enable targets.

[0123] Specifically, because the first group selection signal SELGP1 has a logic high level and the second group selection signal SELGP2 has a logic low level, the selection control signal OPC may have a logic low level. In this state, when the operation period signal OPSEC is activated to a logic high level in response to the start enable signal STEN being switched, the enable control circuit 30 may enter the operation mode.

[0124] During the time period in which the operation period signal OPSEC maintains a logic high level, the first group enable signal and the second group enable signal PBEN<1:2> may be sequentially switched in response to the first reference signal and the second reference signal RF<1:2> being sequentially switched. The first group PB1s and the second group PB2s may be sequentially enabled in response to the first group enable signal and the second group enable signal PBEN<1:2> being sequentially switched as described above.

[0125] When the operation period signal OPSEC is disabled to a logic low level in response to the second reference signal RF2 (ie, the second reference signal among the first to fourth reference signals RF<1:4>) being switched, the enable control circuit 30 may exit the operation mode.

[0126] It can be seen that, as described above, since the operation period signal OPSEC is activated in response to the first reference signal RF1 (i.e., the first reference signal among the first reference signal to the fourth reference signal RF<1:4>) being switched, and is deactivated in response to the second reference signal RF2 (i.e., the second reference signal among the first reference signal to the fourth reference signal RF<1:4>) being switched, the operation period signal OPSEC maintains the state in which the operation period signal OPSEC is activated during the second time t2. In this case, the activation period of the operation period signal OPSEC may refer to the length of the period in which the enable control circuit 30 has entered the operation mode.

[0127] When the first group selection signal SELGP1 has a logic high level and the second group selection signal SELGP2 has a logic low level, the enable control circuit 30 may enter the operation mode at the second time t2 so as to sequentially enable only the first group PB1s and the second group PB2s. In this case, it can be seen that the second time t2 is shorter than Fig. 7A That is, the enable control circuit 30 may control the duration of the second time t2 when the enable control circuit 30 enters the operation mode so as to sequentially enable only two groups PB1s and PB2s among the four groups PB1s, PB2s, PB3s, and PB4s to be shorter than the duration of the first time t1 when the enable control circuit 30 enters the operation mode so as to sequentially enable all of the four groups PB1s, PB2s, PB3s, and PB4s.

[0128] Reference Figure 7C , describes a situation in which, in the enable control circuit 30, when the first group selection signal SELGP1 has a logic low level and the second group selection signal SELGP2 has a logic high level, only the third group PB3s and the fourth group PB4s among the four groups PB1s, PB2s, PB3s and PB4s are selected as enable targets.

[0129] Specifically, since the first group selection signal SELGP1 has a logic low level and the second group selection signal SELGP2 has a logic high level, the selection control signal OPC may have a logic low level. In this state, when the operation period signal OPSEC is activated to a logic high level in response to the start enable signal STEN being switched, the enable control circuit 30 may enter the operation mode.

[0130] During the time period in which the operation period signal OPSEC is maintained at a logic high level, the third group enable signal and the fourth group enable signal PBEN<3:4> may be sequentially switched in response to the first reference signal and the second reference signal RF<1:2> being sequentially switched. The third group PB3s and the fourth group PB4s may be sequentially enabled in response to the third group enable signal and the fourth group enable signal PBEN<3:4> being sequentially switched as described above.

[0131] When the operation period signal OPSEC is disabled to a logic low level in response to the second reference signal RF2 (ie, the second reference signal among the first to fourth reference signals RF<1:4>) being switched, the enable control circuit 30 may exit the operation mode.

[0132] It can be seen that, as described above, since the operation period signal OPSEC is activated in response to the first reference signal RF1 (i.e., the first reference signal among the first reference signal to the fourth reference signal RF<1:4>) being switched, and is deactivated in response to the second reference signal RF2 (i.e., the second reference signal among the first reference signal to the fourth reference signal RF<1:4>) being switched, the operation period signal OPSEC maintains the state in which the operation period signal OPSEC is activated during the second time t2. In this case, the activation period of the operation period signal OPSEC may refer to the length of the period in which the enable control circuit 30 has entered the operation mode.

[0133] When the first group selection signal SELGP1 has a logic low level and the second group selection signal SELGP2 has a logic high level, the enable control circuit 30 can enter the operation mode at the second time t2 so as to sequentially enable only the third group PB3s and the fourth group PB4s. In this case, it can be seen that the second time t2 is shorter than Fig. 7A That is, the enable control circuit 30 can control the duration of the second time t2 when the enable control circuit 30 enters the operation mode so as to sequentially enable only two groups PB3s and PB4s among the four groups PB1s, PB2s, PB3s, and PB4s to be shorter than the duration of the first time t1 when the enable control circuit 30 enters the operation mode so as to sequentially enable all of the four groups PB1s, PB2s, PB3s, and PB4s.

[0134] Figure 8 It is used to describe the embodiments according to the present disclosure. Figure 1 A diagram of a second embodiment of an enable control circuit among components of a memory device disclosed in FIG.

[0135] Reference Figure 8 , have referred to Figure 1 The described enable control circuit 30 having the second embodiment may include a mode selection unit 305 , a mode control unit 306 , and a reference signal control unit 307 .

[0136] The enable control circuit 30 may divide the page buffer 20 into P groups PB1s, PB2s, PB3s, and PB4s. In this case, P may be a natural number equal to or greater than 2.

[0137] The enable control circuit 30 can enter the Figure 1 The first operation mode of the memory cell array 10 may then be sequentially enabled with the P groups PB1s, PB2s, PB3s, and PB4s, and the first operation mode may be exited.

[0138] In addition, the enable control circuit 30 can enter the second operation mode for accessing the memory cell array 10, then can simultaneously enable the P groups PB1s, PB2s, PB3s and PB4s, and can exit the second operation mode. In this case, the duration of the entry time period of the second operation mode can be shorter than the duration of the entry time period of the first operation mode.

[0139] According to an embodiment, when P is 4, the enable control circuit 30 may divide the page buffer 20 into four groups PB1s, PB2s, PB3s, and PB4s.

[0140] Therefore, the enable control circuit 30 can sequentially enable the four groups of PB1s, PB2s, PB3s and PB4s during the entry time period of the first operation mode, and can simultaneously enable the four groups of PB1s, PB2s, PB3s and PB4s during the entry time period of the second operation mode which is shorter than the duration of the entry time period of the first operation mode. In this case, the duration of the entry time period of the second operation mode can be half (1 / 2) of the duration of the entry time period of the first operation mode.

[0141] More specifically, the mode selection unit 305 included in the enable control circuit 30 may generate a mode control signal SELMD or SELMDB for selecting one of the first operation mode and the second operation mode in response to the mode selection signal SELMD.

[0142] The mode control unit 306 included in the enable control circuit 30 may enter the first operation mode in response to the mode control signal SELMD or SELMDB and the start enable signal STEN, and may exit the first operation mode in response to the P reference signals RF<1:4> being sequentially switched.

[0143] According to an embodiment, when P is 4, the mode control unit 306 can enter the first operation mode in response to the mode control signal SELMD or SELMDB, and then can switch the first reference signal RF1 among the reference signals RF<1:4> in response to the start enable signal STEN, can switch the second reference signal RF2 among the reference signals RF<1:4> in response to the switching of the first reference signal RF1, can switch the third reference signal RF3 among the reference signals RF<1:4> in response to the switching of the second reference signal RF2, and can switch the fourth reference signal RF4 among the reference signals <1:4> in response to the switching of the third reference signal RF3.

[0144] The mode control unit 306 may enter the second operation mode in response to the mode control signal SELMD or SELMDB and the start enable signal STEN, and then may exit the second operation mode in response to the first reference signal to the Kth reference signal among the P reference signals RF<1:4> being sequentially switched. In this case, K may be a natural number less than P. As described above, since K is a natural number less than P, the duration of the second operation mode may be shorter than the duration of the first operation mode in any case.

[0145] According to an embodiment, when P is 4 and K is 1, the mode control unit 306 may enter the second operation mode in response to the mode control signal SELMD or SELMDB, and then may switch only the first reference signal RF1 in response to the start enable signal STEN.

[0146] According to another embodiment, when P is 4 and K is 2, the mode control unit 306 can enter the second operation mode in response to the mode control signal SELMD or SELMDB, and then can switch the first reference signal RF1 in response to the start enable signal STEN, can switch the second reference signal RF2 in response to the switching of the first reference signal RF1, and can not switch the third reference signal and the fourth reference signal RF<3:4>.

[0147] According to another embodiment, when P is 4 and K is 3, the mode control unit 306 can enter the second operation mode in response to the mode control signal SELMD or SELMDB, and then can switch the first reference signal RF1 in response to the start enable signal STEN, can switch the second reference signal RF2 in response to the switching of the first reference signal RF1, can switch the third reference signal RF3 in response to the switching of the second reference signal RF2, and can not switch the fourth reference signal RF4.

[0148] In the first operation mode, the reference signal control unit 307 included in the enable control circuit 30 may sequentially switch the P group enable signals PBEN<1:4> in response to the P reference signals RF<1:4> being sequentially switched.

[0149] In this case, each of the P group enable signals PBEN<1:4> may be a signal for enabling each of the P groups PB1s, PB2s, PB3s, and PB4s. For example, when the first group enable signal PBEN1 among the P group enable signals PBEN<1:4> is activated, the first group PB1s among the P groups PB1s, PB2s, PB3s, and PB4s may be enabled. As another example, when the third group enable signal PBEN3 among the P group enable signals PBEN<1:4> is activated, the third group PB3s among the P groups PB1s, PB2s, PB3s, and PB4s may be enabled.

[0150] According to an embodiment, when P is 4, during the entry period of the first operation mode, the reference signal control unit 307 may switch four sets of enable signals PBEN<1:4> in response to the first to fourth reference signals RF<1:4>, respectively.

[0151] In the second operating mode, the reference signal control unit 307 can simultaneously activate the P group enable signal PBEN<1:4> in response to the first reference signal RF1 among the P reference signals RF<1:4> being switched, and can simultaneously deactivate the P group enable signal PBEN<1:4> in response to the switching of the Kth reference signal (for example, one of the reference signals RF<1:3>).

[0152] According to an embodiment, when P is 4 and K is 2, during the entry time period of the second operation mode, the reference signal control unit 307 can simultaneously activate four groups of enable signals PBEN<1:4> in response to the first reference signal RF1 being switched, and can simultaneously deactivate four groups of enable signals PBEN<1:4> in response to the switching of the second reference signal RF2.

[0153] Figures 9 to 11BA detailed circuit configuration of the mode selection unit 305 , the mode control unit 306 , and the reference signal control unit 307 included in the enable control circuit 30 when P is 4 and K is 2 is disclosed.

[0154] However, Figures 9 to 11B The circuit diagram disclosed in is merely an embodiment and may be reconstructed in different forms according to the designer's choice.

[0155] Fig. 9 Is used to describe Figure 8 2 is a diagram of a mode selection unit 305 and a mode control unit 306 among the components of the enable control circuit 30 disclosed in FIG.

[0156] Reference Fig. 9 , the mode selection unit 305 included in the enable control circuit 30 may include an inverter IV2. The inverter IV2 may output an inverted mode selection signal SELMDB by inverting the mode selection signal SELMD.

[0157] According to an embodiment, when the mode selection signal SELMD has a logic high level and the inverted mode selection signal SELMDB has a logic low level, the enable control circuit 30 may enter the first operation mode. Conversely, when the mode selection signal SELMD has a logic low level and the inverted mode selection signal SELMDB has a logic high level, the enable control circuit 30 may enter the second operation mode.

[0158] The mode control unit 306 included in the enable control circuit 30 may include an output selection unit 3061 and an exit control unit 3062 .

[0159] In this case, the output selection unit 3061 may include P flip-flops F / F5 , F / F6 , F / F7 , and F / F8 , and an AND gate AND7 , which are connected in a daisy-chain form.

[0160] In the first operating mode entered by the enable control circuit 30 in response to the mode selection signal SELMD, the output selection unit 3061 can output P reference signals RF<1:4> to the output stages of the first trigger F / F5 to the Pth trigger F / F8 respectively in response to the start enable signal STEN applied to the input stage of the first trigger F / F5.

[0161] In the second operation mode entered by the enable control circuit 30 in response to the mode selection signal SELMD, the output selection unit 3061 can select the Kth flip-flop (for example, one of the flip-flops F / F5 to F / F7) among the P flip-flops F / F5, F / F6, F / F7, and F / F8. In addition, the output selection unit 3061 can output K (one or more) reference signals RF1, RF<1:2>, or RF<1:3> to the output stage of each of the first to Kth flip-flops (F / F5, F / F5 to F / F6, or F / F5 to F / F7) in response to the start enable signal STEN applied to the input stage of the first flip-flop F / F5.

[0162] Specifically, each of the P flip-flops F / F5, F / F6, F / F7, and F / F8 included in the output selection unit 3061 may be a D flip-flop. That is, each of the P flip-flops F / F5, F / F6, F / F7, and F / F8 may delay a signal applied to their input stage and output the signal to their output stage. It can be seen that since P is 4 in the above description, the four flip-flops F / F5, F / F6, F / F7, and F / F8 are connected in a daisy chain in the figure.

[0163] In the second operation mode entered by the enable control circuit 30 in response to the mode selection signal SELMD, the AND gate AND7 included in the output selection unit 3061 can select the Kth flip-flop (for example, one of the flip-flops F / F5 to F / F7) among the P flip-flops F / F5, F / F6, F / F7, and F / F8. Since K is 2 in the above description, the AND gate AND7 can select whether to transmit the signal output from the output stage of the second flip-flop F / F6 to the input stage of the third flip-flop F / F7 in response to the mode selection signal SELMD. The second flip-flop F / F6 is set at the second position among the four flip-flops F / F5, F / F6, F / F7, and F / F8, and the third flip-flop F / F7 is set at the third position among the four flip-flops F / F5, F / F6, F / F7, and F / F8.

[0164] According to an embodiment, when the logic level of the mode selection signal SELMD is set to a logic high level and the control circuit 30 is enabled to enter the first operation mode, in response to the start enable signal STEN being applied to the input stage of the first flip-flop F / F5 set at the first position among the four flip-flops F / F5, F / F6, F / F7, and F / F8, the first reference signal RF1 may be output to the output stage of the first flip-flop F / F5. In response to the first reference signal RF1 being applied to the input stage of the second flip-flop F / F6, the second reference signal RF2 may be output to the output stage of the second flip-flop F / F6. Thereafter, the second reference signal RF2 may be transmitted to the input stage of the third flip-flop F / F7 through the AND gate AND7. As described above, in response to the second reference signal RF2 being applied to the input stage of the third flip-flop F / F7, the third reference signal RF3 may be output to the output stage of the third flip-flop F / F7. In response to the third reference signal RF3 being applied to the input stage of the fourth flip-flop F / F8, the fourth reference signal RF4 may be output to the output stage of the fourth flip-flop F / F8. In the first operation mode, the output selection unit 3061 may sequentially switch the first to fourth reference signals RF<1:4> in response to the start enable signal STEN being switched.

[0165] According to another embodiment, when the logic level of the mode selection signal SELMD is set to a logic low level, the enable control circuit 30 enters the second operation mode, and K is 2, in response to the start enable signal STEN being applied to the input stage of the first flip-flop F / F5 set at the first position, the first reference signal RF1 may be output to the output stage of the first flip-flop F / F5. In response to the first reference signal RF1 being applied to the input stage of the second flip-flop F / F6, the second reference signal RF2 may be output to the output stage of the second flip-flop F / F6. Thereafter, the second reference signal RF2 may not be transmitted to the input stage of the third flip-flop F / F7 through the AND gate AND7. In the second operation mode, when K is 2, the output selection unit 3061 may sequentially switch the first reference signal and the second reference signal RF<1:2> in response to the start enable signal STEN being switched.

[0166] The exit control unit 3062 may include a multiplexer (MUX) MUX6 and an activation control unit 3063. As described above, the exit control unit 3062 may allow the enable control circuit 30 to enter the first operation mode or the second operation mode by activating the operation period signal OPSEC in response to the start enable signal STEN, may allow the enable control circuit 30 to exit the first operation mode in response to switching of the Pth reference signal RF4 among the P reference signals RF<1:4> sequentially switched in the first operation mode, and may allow the enable control circuit 30 to exit the second operation mode in response to switching of the Kth reference signal RF2 among the K reference signals RF<1:2> sequentially switched in the second operation mode.

[0167] Specifically, MUX6 included in the exit control unit 3062 can select one of the second reference signal RF2 and the fourth reference signal RF4 in response to the mode selection signal SELMD and output the selected reference signal as the signal RFEND. Since P is 4 and K is 2 in the above description, such operation of MUX6 can be performed.

[0168] The activation control unit 3063 included in the exit control unit 3062 may activate the operation period signal OPSEC in response to the start enable signal STEN, and may deactivate the operation period signal OPSEC in response to the output signal RFEND of the MUX6.

[0169] According to an embodiment, when the logic level of the mode selection signal SELMD is set to a logic high level and the enable control circuit 30 enters the first operation mode, the signal RFEND output by MUX6 may be the fourth reference signal RF4. In this case, the activation control unit 3063 may be in a state where the activation control unit 306 activates the operation period signal OPSEC in response to the start enable signal STEN and deactivates the operation period signal OPSEC in response to the sixth reference signal RF6. That is, the exit control unit 3062 may allow the enable control circuit 30 to enter the first operation mode in response to the start enable signal STEN, and then may allow the enable control circuit 30 to exit the first operation mode in response to the fourth reference signal RF4.

[0170] According to another embodiment, when the logic level of the mode selection signal SELMD is set to a logic low level and the enable control circuit 30 enters the second operation mode, the signal RFEND output by the MUX6 may be the second reference signal RF2. In this case, the activation control unit 3063 may be in a state where the activation control unit 306 activates the operation period signal OPSEC in response to the start enable signal STEN and deactivates the operation period signal OPSEC in response to the second reference signal RF2. That is, the exit control unit 3062 may allow the enable control circuit 30 to enter the second operation mode in response to the start enable signal STEN, and then may allow the enable control circuit 30 to exit the second operation mode in response to the second reference signal RF2.

[0171] Fig.10 Is used to describe Figure 8 2 is a diagram of a reference signal control unit 307 among the components of the enable control circuit 30 disclosed in FIG.

[0172] Reference Fig.10 The reference signal control unit 307 included in the enable control circuit 30 may include P OR gates OR1 , OR2 , OR3 , and OR4 , and P AND gates AND8 , AND9 , AND10 , and AND11 .

[0173] As described above, when the operation period signal OPSEC maintains a logic high level after the enable control circuit 30 enters the first operation mode in response to the mode selection signal SELMD, the reference signal control unit 307 can sequentially switch the P group enable signal PBEN<1:4> in response to the P reference signals RF<1:4> being sequentially switched.

[0174] When the operation time period signal OPSEC maintains a logic high level after the enable control circuit 30 enters the second operation mode in response to the mode selection signal SELMD, the reference signal control unit 307 can simultaneously activate four groups of enable signals PBEN<1:4> in response to the first reference signal RF1 being switched, and can simultaneously deactivate four groups of enable signals PBEN<1:4> in response to the switching of the second reference signal RF2.

[0175] Specifically, each of the P OR gates OR1 , OR2 , OR3 , and OR4 and each of the P AND gates AND8 , AND9 , AND10 , and AND11 included in the reference signal control unit 307 may correspond to each of the P group enable signals PBEN<1:4>.

[0176] In the first operation mode in which the mode selection signal SELMD has a logic high level and the inverted mode selection signal SELMDB has a logic low level, when the operation period signal OPSEC has a logic high level, the OR gate OR1 and the AND gate AND8 set at the first position among the P OR gates OR1, OR2, OR3, and OR4 and the P AND gates AND8, AND9, AND10, and AND11 may switch the first group enable signal PBEN1 in response to the switching of the first reference signal RF1. In addition, in the second operation mode in which the mode selection signal SELMD has a logic low level and the inverted mode selection signal SELMDB has a logic high level, when the operation period signal OPSEC has a logic high level, regardless of whether the first reference signal RF1 is switched, the OR gate OR1 and the AND gate AND8 set at the first position may maintain the logic level of the first group enable signal PBEN1 at a logic high level. Furthermore, during the exit period of the first operation mode or the second operation mode where the operation period signal OPSEC has a logic low level, the OR gate OR1 and the AND gate AND8 set at the first position may maintain the logic level of the first group enable signal PBEN1 at a logic low level.

[0177] In the first operation mode in which the mode selection signal SELMD has a logic high level and the inverted mode selection signal SELMDB has a logic low level, when the operation period signal OPSEC has a logic high level, the OR gate OR2 and the AND gate AND9 set at the second position among the P OR gates OR1, OR2, OR3, and OR4 and the P AND gates AND8, AND9, AND10, and AND11 can switch the second group enable signal PBEN2 in response to the switching of the second reference signal RF2. In addition, in the second operation mode in which the mode selection signal SELMD has a logic low level and the inverted mode selection signal SELMDB has a logic high level, when the operation period signal OPSEC has a logic high level, regardless of whether the second reference signal RF2 is switched, the OR gate OR2 and the AND gate AND9 set at the second position can maintain the logic level of the second group enable signal PBEN2 at a logic high level. Furthermore, during the exit period of the first operation mode or the second operation mode where the operation period signal OPSEC has a logic low level, the OR gate OR2 and the AND gate AND9 set at the second position may maintain the logic level of the second group enable signal PBEN2 at a logic low level.

[0178] In the first operation mode in which the mode selection signal SELMD has a logic high level and the inverted mode selection signal SELMDB has a logic low level, when the operation period signal OPSEC has a logic high level, the OR gate OR3 and the AND gate AND10 set at the third position among the P OR gates OR1, OR2, OR3, and OR4 and the P AND gates AND8, AND9, AND10, and AND11 may switch the third group enable signal PBEN3 in response to the switching of the third reference signal RF3. In addition, in the second operation mode in which the mode selection signal SELMD has a logic low level and the inverted mode selection signal SELMDB has a logic high level, when the operation period signal OPSEC has a logic high level, regardless of whether the third reference signal RF3 is switched, the OR gate OR3 and the AND gate AND10 set at the third position may maintain the logic level of the third group enable signal PBEN3 at a logic high level. Furthermore, during the exit period of the first operation mode or the second operation mode where the operation period signal OPSEC has a logic low level, the OR gate OR3 and the AND gate AND10 set at the third position may maintain the logic level of the third group enable signal PBEN3 at a logic low level.

[0179] In the first operation mode in which the mode selection signal SELMD has a logic high level and the inverted mode selection signal SELMDB has a logic low level, when the operation period signal OPSEC has a logic high level, the OR gate OR4 and the AND gate AND11 at the fourth position set in the P OR gates OR1, OR2, OR3, and OR4 and the P AND gates AND8, AND9, AND10, and AND11 may switch the fourth group enable signal PBEN4 in response to the switching of the fourth reference signal RF4. In addition, in the second operation mode in which the mode selection signal SELMD has a logic low level and the inverted mode selection signal SELMDB has a logic high level, when the operation period signal OPSEC has a logic high level, regardless of whether the fourth reference signal RF4 is switched, the OR gate OR4 and the AND gate AND11 set in the fourth position may maintain the logic level of the fourth group enable signal PBEN4 at a logic high level. Furthermore, during the exit period of the first operation mode or the second operation mode where the operation period signal OPSEC has a logic low level, the OR gate OR4 and the AND gate AND11 set at the fourth position may maintain the logic level of the fourth group enable signal PBEN4 at a logic low level.

[0180] Fig.11A and Fig. 11B Is used to describe Figure 8 Schematic diagram of the operation of the enable control circuit 30 disclosed in FIG.

[0181] Reference Fig.11A , describes a case where the enable control circuit 30 enters the first operation mode because the mode selection signal SELMD has a logic high level in the enable control circuit 30 .

[0182] Specifically, when the operation period signal OPSEC is activated to a logic high level in response to the start enable signal STEN being switched because the mode selection signal SELMD has a logic high level, the enable control circuit 30 may enter the first operation mode. During the period in which the operation period signal OPSEC maintains a logic high level, the first to fourth group enable signals PBEN<1:4> may be sequentially switched in response to the first to fourth reference signals RF<1:4> being sequentially switched. The first to fourth groups PB1s, PB2s, PB3s, and PB4s may be sequentially enabled in response to the first to fourth group enable signals PBEN<1:4> being sequentially switched as described above.

[0183] When the operation period signal OPSEC is disabled to a logic low level in response to switching of the fourth reference signal RF4 (ie, the fourth reference signal among the first to fourth reference signals RF<1:4>), the enable control circuit 30 may exit the first operation mode.

[0184] It can be seen that, as described above, since the operation period signal OPSEC is activated in response to the first reference signal RF1 of the first reference signal to the fourth reference signal RF<1:4>, and is deactivated in response to the switching of the fourth reference signal RF4 of the first reference signal to the fourth reference signal RF<1:4>, the operation period signal OPSEC maintains the state in which the operation period signal OPSEC is activated during the third time t3. In this case, the activation period of the operation period signal OPSEC may refer to the length of the period in which the enable control circuit 30 has entered the first operation mode.

[0185] When the mode selection signal SELMD has a logic high level, the enable control circuit 30 may enter the first operation mode at the third time t3 to sequentially enable all of the first to fourth groups PB1s, PB2s, PB3s, and PB4s.

[0186] Reference Fig. 11B , describes a case where the control circuit 30 is enabled to enter the second operation mode because the mode selection signal SELMD has a logic low level.

[0187] Specifically, when the operation period signal OPSEC is activated to a logic high level in response to the start enable signal STEN being switched because the mode selection signal SELMD has a logic low level, the enable control circuit 30 may enter the second operation mode.

[0188] In response to the operation period signal OPSEC being activated to a logic high level, all of the first to fourth group enable signals PBEN<1:4> may be simultaneously activated to a logic high level. As described above, in response to the first to fourth group enable signals PBEN<1:4> being activated to a logic high level, the first to fourth groups PB1s, PB2s, PB3s, and PB4s may be simultaneously enabled.

[0189] During the period in which the operation period signal OPSEC maintains a logic high level, the first reference signal and the second reference signal RF<1:2> may be sequentially switched. When the operation period signal OPSEC is disabled to a logic low level in response to the second reference signal RF2 being switched, the enable control circuit 30 may exit the second operation mode.

[0190] As described above, in response to the operation period signal OPSEC being deactivated to a logic low level, all of the first to fourth group enable signals PBEN<1:4> may be simultaneously deactivated to a logic low level. As described above, in response to the first to fourth group enable signals PBEN<1:4> being deactivated to a logic low level, the first to fourth groups PB1s, PB2s, PB3s, and PB4s may be simultaneously disabled.

[0191] When the mode selection signal SELMD has a logic low level, the enable control circuit 30 can enter the second operation mode within the fourth time t4 so as to simultaneously enable the first to fourth groups PB1s, PB2s, PB3s and PB4s. In this case, it can be seen that the fourth time t4 is shorter than Fig.11A That is, the enable control circuit 30 may control the enable control circuit 30 to enter the second operation mode to simultaneously enable all of the four groups PB1s, PB2s, PB3s, and PB4s, and the duration of the fourth time t4 is shorter than the duration of the third time t3 when the enable control circuit 30 enters the first operation mode to sequentially enable all of the four groups PB1s, PB2s, PB3s, and PB4s.

[0192] Fig.12 is a diagram for describing a detailed configuration of a memory device according to an embodiment of the present disclosure.

[0193] Reference Fig.12, the memory device according to the embodiment of the present disclosure may include a memory cell array 10 and a controller 202. The controller 202 may include a control circuit unit 509 and a control logic unit 504. In addition, the control circuit unit 509 may include a plurality of page buffers 20, a check unit 503, a data input / output circuit 40, a voltage supply circuit 506, and an address decoder 507. In addition, the control logic unit 504 may include an enable control circuit 30.

[0194] The memory cell array 10 may include a plurality of memory blocks MEMORY BLOCK<1:6>. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the control circuit unit 509 through row lines DSL<1:2>, WL<1:n>, and SSL<1:2> and bit lines BL1s, BL2s, BL3s, and BL4s. Each of the plurality of memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells.

[0195] The row lines DSL<1:2>, WL<1:n>, and SSL<1:2> may include one or more source select lines SSL<1:2>, a plurality of word lines WL<1:n>, and one or more drain select lines DSL<1:2>.

[0196] The control logic unit 504 may be connected to the address decoder 507 , the voltage supply circuit 506 , the plurality of page buffers 20 , the data input / output circuit 40 , and the check unit 503 included in the control circuit unit 509 .

[0197] The control circuit unit 509 may be connected to the memory cell array 10, and may be configured to perform a programming operation on a selected region of the memory cell array 10. The control circuit unit 509 may drive the memory cell array 10. For example, the control circuit unit 509 may apply various operating voltages to the row lines DSL<1:2>, WL<1:n>, and SSL<1:2>, and the bit lines BL1s, BL2s, BL3s, and BL4s, or may discharge the voltages that have been applied to the row lines DSL<1:2>, WL<1:n>, and SSL<1:2>, and the bit lines BL1s, BL2s, BL3s, and BL4s. The control circuit unit 509 may perform a programming operation on the programming unit in response to the control of the control logic unit 504. In particular, the control circuit unit 509 may selectively enable a plurality of groups PB1, PB2s, PB3s, and PB4s included in the plurality of page buffers 20 in response to the group enable signal PBEN<1:4> generated by the control logic unit 504.

[0198] The voltage supply circuit 506 of the control circuit unit 509 may be configured to generate a plurality of operating voltages Vop by utilizing a power supply voltage supplied from the outside. The voltage supply circuit 506 may operate in response to the control of the control logic unit 504. In an embodiment, the voltage supply circuit 506 may generate an internal power supply voltage by adjusting an external power supply voltage. In an embodiment, the voltage supply circuit 506 may generate a plurality of operating voltages Vop by utilizing an external power supply voltage or an internal power supply voltage. The voltage supply circuit 506 may include a plurality of pumping capacitors that receive an internal power supply voltage to generate a plurality of operating voltages Vop having various voltage levels, and may generate a plurality of operating voltages Vop by selectively activating a plurality of pumping capacitors in response to the control of the control logic unit 504. The generated plurality of operating voltages Vop may be supplied to the memory cell array 10 through the address decoder 507. For example, the voltage supply circuit 506 may adjust the level and supply time of the operating voltage Vop in response to a generation control signal OP_SIG generated by the control logic unit 504.

[0199] The address decoder 507 of the control circuit unit 509 may be connected to the memory cell array 10 through the row lines DSL<1:2>, WL<1:n>, SSL<1:2>, and CSL.

[0200] The address decoder 507 may be configured to operate in response to the control of the control logic unit 504. The address decoder 507 may receive the address RADD from the control logic unit 504.

[0201] The address decoder 507 may be configured to decode the block address in the received address RADD. The address decoder 507 may select at least one of the memory blocks MEMORY BLOCK<1:6> based on the decoded block address. The address decoder 507 may be configured to decode the row address in the received address RADD. The address decoder 507 may select at least one of the word lines of the selected memory block based on the decoded row address. The address decoder 507 may apply the operating voltage Vop supplied by the voltage supply circuit 506 to the selected word line.

[0202] You can refer to Figure 1 The plurality of page buffers 20 and the data input / output circuit 40 included in the control circuit unit 509 will be described.

[0203] After the read operation or the verification operation starts, the inspection unit 503 of the control circuit unit 509 may generate a reference current in response to the detection reference signal VRYBIT generated by the control logic unit 504, and may compare the sensing voltage VPB received from the plurality of page buffers 20 with the reference voltage generated by the reference current. In addition, the inspection unit 503 may generate a pass signal PASS or a fail signal FAIL based on the result of the comparison, and may output the pass signal PASS or the fail signal FAIL to the control logic unit 504. For example, when the voltage level of the sensing voltage VPB is greater than or equal to the reference voltage, the inspection unit 503 may output the pass signal PASS to the control logic unit 504. When the voltage level of the sensing voltage VPB is less than the reference voltage, the inspection unit 503 may output the fail signal FAIL to the control logic unit 504.

[0204] The control logic unit 504 may be connected to the address decoder 507, the voltage supply circuit 506, the plurality of page buffers 20, the data input / output circuit 40, and the inspection unit 503 included in the control circuit unit 509. The control logic unit 504 may be configured to control the overall operation of the memory device. The control logic unit 504 may operate in response to a command CMD transmitted from an external device.

[0205] The control logic unit 504 may control the control circuit unit 509 by generating various signals in response to the command CMD and the address ADDR. For example, the control logic unit 504 may generate an operation signal OP_SIG, an address RADD, a read and write circuit control signal PBSIGNALS, and a detection reference signal VRYBIT in response to the command CMD and the address ADDR. The control logic unit 504 may output the operation signal OP_SIG to the voltage supply circuit 506, may output the address RADD to the address decoder 507, may output the read and write control signal PBSIGNALS to the page buffer 20, and may output the detection reference signal VRYBIT to the inspection unit 503. In addition, the control logic unit 504 may determine whether the verification operation is passed or failed in response to the pass signal PASS or the fail signal FAIL output by the inspection unit 503. In particular, the control logic unit 504 may include an enable control circuit 30. Therefore, the read and write circuit control signal PBSIGNALS applied from the control logic unit 504 to the page buffer 20 may include a P group enable signal PBEN<1:4>. In this case, reference may be made to Figures 1 to 11B The detailed configuration and operation of the enable control circuit 30 will be described.

[0206] It is obvious to those skilled in the art that the embodiments of the present disclosure are not limited to the above embodiments and drawings, and the embodiments may be replaced, modified, and changed in various ways without departing from the technical spirit of the present disclosure.

[0207] For example, the location and type of logic gates shown in the above embodiments must be implemented differently depending on the polarity of the input signal. Furthermore, these embodiments may be combined to form other embodiments.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells; a plurality of page buffers connected to the memory unit; as well as Enable control circuit: Divide the page buffer into P groups, sequentially enabling the L group among the P groups during an entry period of the operation mode, and The duration of the entry time period of the operation mode is adjusted based on the value of L, Wherein, P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.

2. The memory device according to claim 1, wherein: The enabling control circuit comprises: a signal generating unit that generates a selection control signal for selecting a value of L in response to the group selection signal; a first switching control unit, in response to a start enable signal and the selection control signal, sequentially switching a first reference signal to an Lth reference signal among the P reference signals; a mode setting unit that enters the operation mode in response to the start enable signal and exits the operation mode in response to switching of the Lth reference signal; and a second switching control unit that selects an L group enable signal from among P group enable signals for respectively enabling the P groups in response to the group selection signal during an entry time period of the operation mode, and switches the selected L group enable signal in response to the first reference signal to the Lth reference signal, respectively.

3. The memory device according to claim 2, wherein: The first switching control unit includes P triggers, which selects the Lth trigger among the P triggers in response to the selection control signal, and outputs L reference signals to the output stages of the first trigger to the Lth trigger among the P triggers in response to the start enable signal applied to the input stage of the first trigger.

4. The memory device according to claim 2, wherein: The mode setting unit: activating an operation period signal in response to the start enable signal, and In response to switching of an Lth reference signal among the sequentially switched L reference signals, the operation period signal is deactivated.

5. The memory device according to claim 4, wherein: The second switching control unit: During an activation period of the operation period signal, selecting L group enable signals corresponding to the group selection signal among the P group enable signals, and The L groups of enable signals are sequentially switched in response to the sequentially switched L reference signals, respectively.

6. A memory device comprising: a memory cell array comprising a plurality of memory cells; a plurality of page buffers connected to the memory unit; as well as Enable control circuit: Divide the page buffer into P groups, sequentially enabling the P groups during an entry period of the first operation mode, and simultaneously enabling the P groups during an entry period of the second operation mode, The time period for entering the second operation mode is shorter than the time period for entering the first operation mode, and P is a natural number greater than or equal to 2.

7. The memory device according to claim 6, wherein: The enabling control circuit comprises: a mode selection unit that generates a mode control signal for selecting one of the first operation mode and the second operation mode in response to a mode selection signal; a mode control unit that, in response to the mode control signal and the start enable signal, exits the first operation mode in response to P reference signals being sequentially switched after entering the first operation mode, and exits the second operation mode in response to first to Kth reference signals among the P reference signals being sequentially switched after entering the second operation mode; and a reference signal control unit that sequentially switches P group enable signals for respectively enabling the P groups in response to the P reference signals being sequentially switched in the first operation mode, simultaneously activates the P group enable signals in response to a first reference signal among the P reference signals being switched in the second operation mode, and simultaneously deactivates the P group enable signals in response to switching of the Kth reference signal, Here, K is a natural number less than P.

8. The memory device according to claim 7, wherein: The mode control unit comprises: an output selection unit comprising P flip-flops, wherein the output selection unit outputs the P reference signals to the output stages of the first to P-th flip-flops respectively in response to a start enable signal applied to an input stage of the first flip-flop in a first operation mode entered by the mode control unit in response to the mode control signal, selects a K-th flip-flop among the P flip-flops in a second operation mode, and outputs K reference signals among the P reference signals to the output stages of the first to K-th flip-flops among the P flip-flops respectively in response to the start enable signal applied to the input stage of the first flip-flop; and an exit control unit, allowing the mode control unit to enter the first operation mode or the second operation mode in response to the start enable signal, allowing the mode control unit to exit the first operation mode in response to the Pth reference signal being output in the first operation mode, and allowing the mode control unit to exit the second operation mode in response to the Kth reference signal being output in the second operation mode.

9. A method for operating a memory device, the memory device comprising a plurality of page buffers connected to a plurality of memory cells, the method comprising: Dividing the page buffer into P groups; sequentially enabling the L group among the P groups during an entry period of an operation mode; as well as The duration of the entry time period of the operation mode is adjusted based on the value of L, Wherein, P is a natural number greater than or equal to 2, and L is a natural number greater than or equal to 1 and less than or equal to P.

10. The operating method according to claim 9, wherein sequentially enabling the L groups comprises: generating a selection control signal for selecting a value of L in response to the group selection signal and the P reference signals; In response to a start enable signal and the selection control signal, sequentially switching a first reference signal to an Lth reference signal among the P reference signals; as well as During an entry period of the operation mode, an L group enable signal is selected among P group enable signals for respectively enabling the P groups in response to the group selection signal, and the selected L group enable signals are switched in response to the first reference signal to the Lth reference signal, respectively.

11. The operating method according to claim 10, wherein: Sequentially enabling the L groups further comprises: The operation mode is entered in response to the start enable signal, and the operation mode is exited in response to the switching of the Lth reference signal.

12. The operating method according to claim 11, wherein: Sequentially switching the first reference signal to the Lth reference signal includes: In response to the selection control signal, selecting the Lth flip-flop among the P flip-flops, and In response to a start enable signal applied to an input stage of the first flip-flop, L reference signals are output to output stages of first to L-th flip-flops among the P flip-flops, respectively.

13. The operating method according to claim 10, wherein: Adjusting the duration of the entry time period of the operation mode includes: entering the operation mode by activating an operation period signal in response to the start enable signal, and The operation mode is exited by deactivating the operation period signal in response to switching of the Lth reference signal.

14. The operating method according to claim 13, wherein: Select L group enable signals include: selecting L group enable signals corresponding to the group selection signal among the P group enable signals during an activation period of the operation period signal, and In response to the sequentially switched L reference signals, the L groups of enable signals are sequentially switched.

15. A method for operating a memory device, the memory device comprising a plurality of page buffers connected to a plurality of memory cells, the method comprising: Dividing the page buffer into P groups; sequentially enabling the P groups during an entry period of a first operating mode; as well as simultaneously enabling the P groups during an entry period of the second operation mode, The time period for entering the second operation mode is shorter than the time period for entering the first operation mode, and P is a natural number greater than or equal to 2.

16. The operating method according to claim 15, further comprising: generating a mode control signal for selecting one of the first operation mode and the second operation mode in response to a mode selection signal; as well as in response to the mode control signal and the start enable signal, exiting the first operation mode in response to P reference signals being sequentially switched after entering the first operation mode, and exiting the second operation mode in response to first to Kth reference signals among the P reference signals being sequentially switched after entering the second operation mode, Here, K is a natural number less than P.

17. The operating method according to claim 16, wherein: Sequentially enabling the P groups includes sequentially switching P group enable signals for respectively enabling the P groups in response to the P reference signals being sequentially switched in the first operation mode.

18. The operating method according to claim 17, wherein: Also enabled include: activating the P groups of enable signals simultaneously in response to a first reference signal among the P reference signals being switched in the second operation mode; and The P groups of enable signals are simultaneously deactivated in response to switching of a Kth reference signal among the P reference signals in the second operation mode.

19. The operating method according to claim 18, wherein: Exiting the first operation mode and exiting the second operation mode include: outputting the P reference signals to the output stages of the first to Pth flip-flops, respectively, in response to a start enable signal applied to an input stage of a first flip-flop in a first operation mode in response to the mode control signal, In the second operation mode, a Kth flip-flop is selected among the P flip-flops, outputting K reference signals among the P reference signals to output stages of first to Kth flip-flops among the P flip-flops, respectively, in response to a start enable signal applied to an input stage of the first flip-flop, and The first operation mode or the second operation mode is entered in response to the start enable signal.

20. The operating method according to claim 19, wherein: Exiting the first operation mode and exiting the second operation mode further include: exiting the first operation mode in response to a Pth reference signal being output in the first operation mode, and The second operation mode is exited in response to the Kth reference signal being output in the second operation mode.

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