Memory reference array repairing method and device and medium

Abstract

The invention discloses a memory reference array repairing method, a memory reference array repairing device and a medium, relates to the technical field of memories, is used for repairing a memory failure reference array, and provides the memory reference array repairing method aiming at the problem that a scheme for repairing the failure reference array is lacked at present. Address information of a reference array is pre-configured in a register in advance, so that when the resistance state of a memory is overturned due to sudden high temperature, a magnetic field, vibration and the like in an external environment, high resistance state writing can be carried out on a full address of the reference array through the pre-configured address information of the reference array; and the repair work of the failed reference array is realized. When the resistance state of the reference array using the MTJ bit is overturned due to the influence of external factors such as sudden high temperature, magnetic field and vibration, the full-address high-resistance state of the reference array can be recovered through rewriting operation, and the requirement of memory resistance value reference in a scene with temperature change is better met.

Description

Technical Field

[0001] The present application relates to the field of memory, and in particular to a memory reference array repair method, device and medium. Background Art

[0002] The bit of MRAM usually includes a magnetic tunnel junction (MTJ) and one or more field effect transistors (MOSFET). The reading of information in a single MTJ depends on the difference between the parallel resistance Rp and the antiparallel resistance Rap. An MRAM composed of an MTJ array has certain statistical distribution standards for Rp and Rap (the Rp and Rap distribution curves do not overlap), and it is necessary to determine the appropriate reference resistance to accurately determine the storage information in the bit.

[0003] MRAM: Magnetoresistive Random Access Memory, is a non-volatile magnetic random access memory.

[0004] When the temperature changes, the resistance value of Rap will change accordingly, so a reference resistor whose resistance value can also change with the temperature is needed to ensure that the MRAM can be read out normally with a certain read window. At this time, the MTJ array can also be used as a reference, and the MTJ array can be written to a high-resistance state (also called 1 state or AP state, corresponding to the resistance value Rap), and the target reference resistance value can be achieved by connecting it in series and parallel with other resistors.

[0005] However, when a short-term high temperature condition occurs (such as the chip welding process), or when affected by a magnetic field, the AP state of the reference MTJ array has a certain probability of flipping to a low resistance state (also called 0 state or P state, corresponding to the resistance value Rp). At this time, the reference fails and the MRAM can no longer perform normal read and write operations. Currently, technicians are mostly working on preventing the occurrence of MTJ flipping, and there is no repair solution after the reference array fails.

[0006] Therefore, technicians in this field are in urgent need of a memory reference array repair method to repair a failed memory reference array to ensure normal reading and writing functions of the memory. Summary of the invention

[0007] The purpose of the present application is to provide a memory reference array repair method, device and medium to solve the problem of repairing a failed reference array of a memory to ensure the normal reading and writing functions of the memory.

[0008] In order to solve the above technical problems, the present application provides a memory reference array repair method, comprising:

[0009] Obtaining pre-configured reference array address information from a register;

[0010] According to the reference array address information, write a high impedance state into each bit of the reference array;

[0011] After the reference array is fully addressed and written into the high-impedance state, it indicates that the memory is operating normally.

[0012] On the other hand, writing a high impedance state into each element of the reference array according to the reference array address information includes:

[0013] According to the reference array address information, each element of the reference array is traversed, and a high impedance state is written into each element with the highest write voltage.

[0014] On the other hand, writing a high impedance state into each element of the reference array according to the reference array address information includes:

[0015] Read the resistance state of each bit of the reference array according to the reference array address information, and determine the bit with a low resistance state as the target bit;

[0016] Writes a high-impedance state to the target bit.

[0017] On the other hand, writing a high impedance state into each element of the reference array according to the reference array address information includes:

[0018] Traversing each element of the reference array and writing a high impedance state into each element with a preset write voltage;

[0019] Read the resistance state of each bit that is written into the high-resistance state this time, and determine the bit that fails to be written into the high-resistance state as the target bit;

[0020] Raising the voltage level of the preset write voltage and writing a high impedance state into each target bit with the new preset write voltage;

[0021] Repeat the steps of reading the resistance state of each bit that is written into the high-resistance state this time, and determining the bit that fails to be written into the high-resistance state as the target bit, until no target bit appears.

[0022] On the other hand, it also includes:

[0023] Count the number of times the high impedance state is repeatedly written to the reference array;

[0024] If the number of repeated writes exceeds a preset threshold and there is still a newly determined target bit, an error message including the address of the latest determined target bit is returned.

[0025] On the other hand, after the reference array is fully written to the high impedance state, indicating that the memory is working normally includes:

[0026] After the writing of the full address of the reference array into the high-impedance state is completed, the specified flag bit in the register is set to indicate that the memory enters the normal working mode.

[0027] On the other hand, the repair method is executed every time the memory is powered on and the voltage is stable.

[0028] In order to solve the above technical problems, the present application also provides a memory reference array repair device, comprising:

[0029] An address acquisition module, used for acquiring pre-configured reference array address information from a register;

[0030] A resistance state writing module, used for writing a high resistance state into each element of the reference array according to the reference array address information;

[0031] The recovery indication module is used to indicate that the memory operates normally after all addresses of the reference array are written into the high-impedance state.

[0032] In order to solve the above technical problems, the present application also provides a memory reference array repair device, comprising:

[0033] Memory for storing computer programs;

[0034] A processor is used to implement the steps of the memory reference array repair method as described above when executing a computer program.

[0035] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the memory reference array repair method as described above are implemented.

[0036] The present application provides a method for repairing a memory reference array. By pre-configuring the address information of the reference array in a register, when the memory is flipped in resistance state due to sudden high temperature, magnetic field, vibration, etc. in the external environment, the pre-configured reference array address information can be used to write the full address of the reference array in a high-resistance state to achieve the repair of the failed reference array. When the repair work is completed, the reference array can be restored to a normal resistance state, and the memory can correctly distinguish between high resistance and low resistance states to meet the needs of its normal read and write functions. The present application provides a repair solution when the memory reference array fails, so that when the reference array using MTJ bits is flipped in resistance state due to external factors such as sudden high temperature, magnetic field, and vibration, the full address high-resistance state of the reference array can also be restored through a rewrite operation, which better meets the needs of memory resistance reference in scenarios with temperature changes.

[0037] The memory reference array repair device and computer-readable storage medium provided in the present application correspond to the above method and have the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 This is a structural schematic diagram of a common memory read circuit;

[0040] Figure 2 A flowchart of a memory reference array repair method provided by the present invention;

[0041] Figure 3 A flowchart of a memory power-on and repair process provided by the present invention;

[0042] Figure 4 A structural diagram of a memory reference array repair device provided by the present invention;

[0043] Figure 5 A structural diagram of another memory reference array repair device provided by the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] The core of this application is to provide a memory reference array repair method, device and medium.

[0046] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0047] At present, in order to ensure that the memory can still have a certain read window in an environment with a significant temperature difference, a reference array is often constructed by using bits composed of magnetic tunnel junctions (MTJs).

[0048] A memory read circuit structure using MTJ reference is shown in FIG. Figure 1 As shown, it includes: a reading circuit part and a reference circuit part.

[0049] Among them, the reference circuit part includes multiple bits and a poly (a type of resistor) resistor with a resistance value of 1 / 2Rp (corresponding to the resistance value of the low resistance state); each bit includes an MTJ and a field effect transistor (MOSFET) connected in series; multiple bits are connected in parallel and in series with the poly resistor to form a reference array, and an intermediate state reference with a resistance value of 1 / 2 (Rap+Rp) is obtained as the initial state.

[0050] It should be noted that the multiple bits in the memory read circuit are divided into normal bits and reference bits. Figure 1 In the example, the input signal at the control terminal (i.e., the GATE terminal of the MOSFET) of the normal bit is WL (WL <0> ~WL <1023> ), in practical applications, 1024 normal bits are generally set; the input signal at the GATE end of the reference bit is ref_wl (ref_wl <0> ~ref_wl <3> ), generally two groups of reference bits are set, each group includes two reference bits in parallel; when data is read, the two reference bits of the same group are connected in parallel, and only one normal bit is selected at the data end (IREAD).

[0051] Before the memory chip leaves the factory, all MTJs in the reference array need to be set to a high-resistance state (AP state). At this time, the resistance value of the reference array is normal. When the actual user uses the memory chip, since the use of the memory chip usually requires welding, the memory chip will be exposed to high temperature during welding, causing the temperature to rise sharply in a short period of time. At this time, one or several MTJs in the reference array that are in a high-resistance state may flip to a low-resistance state (P state), and part of the reference may be offset. This offset reference will cause the read window of the memory chip to be lost or non-existent, affecting the normal read and write functions of the memory. Similarly, other external factors including magnetic fields and vibrations may also cause some MTJs in the reference array to flip, which in turn causes the reference to fail and affects the normal read and write of the memory.

[0052] To solve the above problems, the present application provides a memory reference array repair method, such as Figure 2 As shown, including:

[0053] S11: Obtain pre-configured reference array address information from a register.

[0054] S12: Writing a high impedance state into each bit of the reference array according to the reference array address information.

[0055] S13: After all addresses of the reference array are written into the high-impedance state, the memory is instructed to work normally.

[0056] It is easy to know that the register in step S11 can be a register in the memory chip (if any), or a separately set register, which is used to store the preset reference array address information. The reference array address information records the address corresponding to each bit in the reference array or the start address and end address corresponding to all bits in the reference array, which is used to implement data writing to the reference array (i.e., writing of "1" and "0", which correspond to high impedance state and low impedance state respectively).

[0057] As for step S12, it can be known from the above that all MTJs of the reference array should be in a high impedance state under normal circumstances. Therefore, the step implements the repair of the MTJ resistance state flip by rewriting all addresses of the reference array in a high impedance state.

[0058] It should also be noted that the high-impedance writing of the reference array does not require changing the original structure of the memory chip. The manufacturer itself needs to write a high-impedance state to all bits of the reference array before the memory chip leaves the factory, that is, the existing memory chip structure itself already supports high-impedance writing of the entire address of the reference array. However, the write permission for the reference array is generally not open to the user, so the above method can be implemented through a program or script pre-configured in the memory chip. On the one hand, it reduces unnecessary permission opening to users and avoids the impact of user misoperation on the normal use of the memory chip; on the other hand, it can also effectively reduce the implementation cost of users to repair the failed reference array, making the repair of the failed reference array of the memory simpler and easier to implement.

[0059] In addition, the present application does not restrict how to perform high-impedance writing to the reference array in step S12. The writing may be performed by address traversal, or may be performed starting from a specified address, specified sequence, specified jump method, etc. The number of times of writing may be only one time or may be repeated multiple times, and this embodiment does not restrict this.

[0060] As for step S13, it is easy to know that this method is a method for repairing a failed reference array, and the reference array is one of the necessary conditions for the memory to realize normal read and write functions. Therefore, when the failed reference array is repaired by executing the above method, the memory needs to suspend the normal read and write functions, that is, enter another mode different from the normal working mode, which can be called the repair mode. When the above method flow is executed and the failed reference array is repaired, the memory needs to be switched back to the normal working mode.

[0061] As for how to instruct the memory to work normally in step S13, this embodiment does not limit it either. It can be implemented by generating and sending specific instructions to the memory, or as a possible implementation scheme provided in this embodiment, step S13 is specifically:

[0062] After the writing of the full address of the reference array into the high-impedance state is completed, the specified flag bit in the register is set to indicate that the memory enters the normal working mode.

[0063] The designated flag bit in this embodiment is the flag bit of the register to determine the current working mode. In the implementation scheme currently provided, the working mode of the memory can be divided into a normal working mode and a repair mode, so it can be realized in the simplest way through a binary number, 0 and 1 respectively represent the normal working mode and the repair mode of the memory. However, it should also be noted that this embodiment does not limit the designated flag bit to only represent the normal working mode and the repair mode of the memory through a binary number. If there are other working modes required for the memory in actual applications, other methods can also be used to achieve the setting of the designated flag bit.

[0064] The present application provides a method for repairing a memory reference array. When the reference array in the memory fails due to a resistance state flip caused by external factors, a high-resistance state is written into the reference array to ensure that the full address of the reference array remains in a high-resistance state, so as to restore the resistance reference function of the reference array and enable the memory to normally implement the read and write functions. In addition, this method does not need to change the original architecture of the memory, is simple to implement, and does not affect the implementation of other functions of the memory. It is well adapted to the use of MTJ as a bit element to adapt to the needs of the memory in scenarios with significant temperature differences. Even if the MTJ has a resistance state flip due to external factors, it can be repaired by this method, so that the application range of the MTJ reference array is wider and the reliability is higher.

[0065] On the other hand, for the implementation method of writing a high impedance state into the reference array which is not specifically limited in the above embodiment, this embodiment provides a possible implementation method, and the above step S12 is specifically as follows:

[0066] S12-A: According to the reference array address information, traverse each element of the reference array, and write a high impedance state into each element with the highest write voltage.

[0067] As can be seen from the above, the normal resistance reference function of the reference array is based on the premise that the resistance state of each MTJ is in a high resistance state, and the repair method provided by the present application is the process of rewriting the MTJ that has been flipped into a low resistance state due to external factors back to a high resistance state. Therefore, the success rate of writing a high resistance state to the reference array directly affects the effect of the present method on repairing the failed reference array.

[0068] It should be noted that when writing a high-resistance state to the reference array, the selection of the write voltage will affect the success rate of writing the high-resistance state to a certain extent. Generally speaking, within a reasonable range, the higher the write voltage, the higher the success rate of writing the high-resistance state. The highest write voltage mentioned in this embodiment is the write voltage of the maximum voltage level that can be achieved under the premise of the allowable range of the electrical parameters of the memory. Therefore, it is not difficult to see that an implementation scheme provided in this embodiment is a preferred scheme from the perspective of improving the success rate of writing the high-resistance state of the reference array. By setting the highest write voltage, the highest write success rate is guaranteed in the single high-resistance state writing process of the reference array.

[0069] Furthermore, in addition to increasing the voltage level of the write voltage, the reliability of the modification effect of the method can also be effectively improved by repeatedly performing high-resistance write.

[0070] However, it should be noted that although the high voltage level write voltage has the characteristic of high success rate of high impedance write, there are also some other problems, such as high write voltage will affect the service life of related electrical components in the memory. Specifically, when the memory is written in high impedance state through low level write voltage, it can support more write times before being damaged compared with high write voltage.

[0071] In the implementation scheme provided in the above embodiment, for writing high-resistance state into the reference array, the simplest implementation scheme is to write high-resistance state into all bits in the reference array to ensure that the reference array is in high-resistance state at all addresses after the high-resistance state is written. However, it is easy to understand that when the reference array is flipped due to external factors, usually only the MTJ resistance state of one or several bits is flipped. Therefore, performing traversal writing of the full address will lead to the problem of invalid writing, that is, writing high-resistance state to bits that were originally in high-resistance state. On the one hand, this invalid writing will affect the overall efficiency of the repair method to a certain extent. On the other hand, when the high-resistance state is written at the highest write voltage in the above embodiment, it will cause unnecessary loss to the life of the electrical components.

[0072] Based on the above, the present application also provides another preferred implementation scheme for writing in step S12, which specifically includes:

[0073] S121-B: Read the resistance state of each bit of the reference array according to the reference array address information, and determine that the bit with a low resistance state is the target bit;

[0074] S122-B: Write high impedance to the target bit.

[0075] It should be noted that most existing memory architectures also support reading data from a reference array. For example, after writing a high-impedance state to the reference array, whether the writing is successful is determined by reading data from the reference array. If the data of all addresses in the reference array are "1" (i.e., corresponding to a high-impedance state), it indicates that the reference array has been repaired successfully.

[0076] Correspondingly, it can be seen from the above that in actual applications, the resistance state flipping of the failed reference array often occurs on one or several bits, and the possibility of the resistance state flipping of all bits is almost negligible. Therefore, this embodiment determines the address where the stored data is "0" by reading the data stored in the reference array, and the corresponding bit is also the target bit to be repaired, and the subsequent high-resistance write step is performed on this part of the target bits.

[0077] This embodiment reads the data in the reference array to screen out the target bits with flipped resistance states, so that in the subsequent high-resistance write, targeted write operations can be performed. On the one hand, invalid writes can be prevented from affecting the efficiency of the overall repair process, and on the other hand, invalid writes can be prevented from wasting bits, which is beneficial to improving the overall service life of the memory.

[0078] Furthermore, in combination with the implementation schemes of writing the reference array into a high impedance state provided in the above two embodiments, this embodiment also provides another preferred implementation scheme, in which the above step S12 is specifically as follows:

[0079] S121-C: traverse each element of the reference array, and write a high impedance state into each element with a preset write voltage;

[0080] S122-C: Read the resistance state of each bit that is written into the high-resistance state this time, and determine the bit that fails to be written into the high-resistance state as the target bit;

[0081] S123-C: increasing the voltage level of the preset write voltage, and writing a high impedance state into each target bit with the new preset write voltage;

[0082] S124-C: Repeat step S122-C until no target bit appears.

[0083] It should be noted that the preset write voltage can pre-include multiple levels of write voltages. When the first high-impedance write is performed in step S121-C, the write is first performed with the lowest level of write voltage. After the first high-impedance write step is completed, the data in the reference array is read to determine whether there are any bits that failed to be written. If so, it is determined to be the target bit for the next high-impedance write. Then, in the next high-impedance write process, the level of the write voltage is increased, and the target bit is re-written in the high-impedance state. The judgment of whether the write is successful is repeated again, that is, whether a new target bit is generated. If so, the level of the write voltage is increased again and the writing is repeated until the entire address of the reference array is in the high-impedance state, that is, no new target bit appears.

[0084] Exemplarily, this embodiment further illustrates the preferred solution provided by this embodiment in combination with a possible practical application scenario:

[0085] There are four voltage levels, namely, the first, second, third and fourth, as the adoptable write voltages, and the voltage levels are increased from the first write voltage to the fourth write voltage. When the high-resistance state is written for the first time, the first write voltage with the lowest voltage level is used; if a target bit that fails to be written is found after reading the reference array data, the target bit is rewritten in the high-resistance state through the second write voltage; if the target bit still appears, the third write voltage is used to write in the high-resistance state for the third time; if no new target bit is determined after the third write in the high-resistance state is completed, it is considered that the full address of the reference array has been repaired to the high-resistance state, and the method is completed, and the fourth write voltage does not need to participate in this repair process.

[0086] In addition, it should be noted that, as can be seen from the above, the resistance state flipping usually occurs in some bits in the reference array, and the determination of these bits can be achieved by reading the reference array data. Therefore, during the first high-resistance state writing in step S121-C of this embodiment, the target bit to be written can also be determined by data reading, and the above is only a possible implementation scheme.

[0087] The preferred solution provided in this embodiment uses a step voltage writing method to write the high-resistance state of the reference array; on the one hand, the repeated writing and the method of increasing the writing voltage each time can effectively ensure the success rate of writing the high-resistance state and ensure the repair effect on the reference array; on the other hand, the step-by-step increased writing voltage can also minimize the impact of the high-resistance writing on the life of the reference array. If the low voltage level can be written successfully, there is no need to use a high writing voltage, and the loss of bits is smaller; therefore, this solution is a preferred solution that comprehensively considers the writing success rate and the service life of the reference array, and can better meet the general needs in actual memory application scenarios.

[0088] On the other hand, the above embodiments do not limit the time when the repair method provided by the present application is executed. The user may trigger the above method based on instructions at any time after determining that the reference array has failed, or may trigger the above repair method by pre-setting a cycle or according to a certain law or rule. The present application does not limit this, and the user may freely select a suitable triggering method according to actual needs.

[0089] Based on this, this embodiment provides a possible implementation scheme of the trigger logic:

[0090] The repair method is executed each time the memory is powered on and the voltage is stable.

[0091] It should be noted that the memory needs to be powered on for use, and operations such as reading the reference array and writing in a high-impedance state also need to be based on the memory chip being powered on, so the above repair method must occur after the memory is powered on.

[0092] The memory power-on and repair process can be as follows: Figure 3 As shown: after the chip is powered on, the digital logic control module of the chip sends a power-on signal to the low dropout regulator (LDO) regulator, and the LDO is powered on at this time; after the LDO is powered on, the LDO returns an instruction to the digital logic control module to inform that the power-on is complete (in other scenarios, the LDO is also used to send a reset signal and a clock signal OSC_CLK to the digital logic control module); after receiving the feedback from the LDO, the digital logic control module sends an instruction (READY signal) to the reset write module (i.e., a digital module used to implement high-impedance writing of the reference array); the reset write module obtains the reference array address information from the register, sends a write enable, write data and write address to the write drive circuit, and writes the reference array in a high-impedance state through the write drive circuit, so that the full address of the reference array is in a high-impedance state; after the full address of the reference array is written in a high-impedance state, the specified flag bit is set to indicate that the memory can start working normally, and the memory power-on and repair process ends.

[0093] Furthermore, because random flipping caused by external factors rarely occurs during the normal operation of the memory chip, the reference array is no longer prone to failure after the memory chip is powered on and starts working normally. Therefore, setting the reference array repair process at the beginning of the memory chip power-on can effectively repair the flipping problem that may occur in the reference array and provide support for the normal operation of the subsequent memory chip. And because the reference array failure problem rarely occurs after the memory is powered on and works normally, it is usually not necessary to repeat the repair in the subsequent application of the memory. Special circumstances can be triggered by user instructions.

[0094] The reason why the repair method needs to wait for the voltage to stabilize is that the repair method also involves steps such as writing a high impedance state to the reference array, and a stable working voltage can ensure the reliability of repairing the failed reference array. In summary, the preferred solution provided by this embodiment is to automatically execute the repair method of the above embodiment at the beginning of each memory chip power-on and after the voltage stabilizes, so as to solve the possible reference array failure problem.

[0095] In addition, as to how to determine whether the voltage of the memory chip is stable after it is powered on, it is considered that the power-on process is usually a non-instantaneous process. If the memory chip is normal, the voltage of the memory chip will tend to be stable after a period of time after it is powered on. Therefore, the currently commonly used solution is to wait for a preset time, after which the voltage of the memory chip can be considered stable.

[0096] This embodiment provides a logic for triggering the above-mentioned repair method. Whenever the memory is powered on and the voltage is stable, the above-mentioned repair method is triggered, and the reference array bits that have flipped are written in a high-resistance state to repair the failed reference array. The repair process occurs at the beginning of the memory power-on, and after the repair is completed, it will indicate that the memory is working normally. Since the resistance state flip problem rarely occurs again when the memory is working normally, the repair process will not be automatically performed again, and the subsequent use of the memory will not be affected. This embodiment provides an automatic execution logic of a repair method, which can automatically repair the failed reference array without the need for additional user manipulation, while only reducing the impact on the memory application.

[0097] In the above embodiment, a memory reference array repair method is described in detail, and the present application also provides a corresponding embodiment of a memory reference array repair device. It should be noted that the present application describes the embodiments of the device part from two perspectives, one is based on the functional module perspective, and the other is based on the hardware perspective.

[0098] Based on the functional module perspective, such as Figure 4 As shown, this embodiment provides a memory reference array repair device, including:

[0099] An address acquisition module 21, used to acquire pre-configured reference array address information from a register;

[0100] The resistance state writing module 22 is used to write a high resistance state into each element of the reference array according to the reference array address information;

[0101] The recovery instruction module 23 is used to instruct the memory to work normally after the writing of all addresses of the reference array into the high-impedance state is completed.

[0102] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0103] Figure 5 A structural diagram of a memory reference array repair device provided in another embodiment of the present application, such as Figure 5 As shown, a memory reference array repair device comprises: a memory 30, for storing a computer program;

[0104] The processor 31 is used to implement the steps of a memory reference array repair method in the above embodiment when executing a computer program.

[0105] Among them, the processor 31 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 31 can be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 31 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 31 may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 31 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0106] The memory 30 may include one or more computer-readable storage media, which may be non-transitory. The memory 30 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 30 is at least used to store the following computer program 301, wherein, after the computer program is loaded and executed by the processor 31, it can implement the relevant steps of a memory reference array repair method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 30 may also include an operating system 302 and data 303, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 302 may include Windows, Unix, Linux, etc. Data 303 may include but is not limited to a memory reference array repair method, etc.

[0107] In some embodiments, a memory reference array repair device may further include a display screen 32 , an input / output interface 33 , a communication interface 34 , a power supply 35 , and a communication bus 36 .

[0108] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation on a memory reference array repair device, and may include more or fewer components than those shown in the figure.

[0109] A memory reference array repair device provided in an embodiment of the present application includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a memory reference array repair method.

[0110] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps recorded in the above method embodiment are implemented.

[0111] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0112] The above is a detailed introduction to a memory reference array repair method, device and medium provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can refer to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0113] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A memory reference array repair method, characterized in that: include: Obtaining pre-configured reference array address information from a register; Writing a high impedance state into each element of the reference array according to the reference array address information; After the reference array is fully written into the high impedance state, the memory is instructed to operate normally.

2. The memory reference array repair method according to claim 1, characterized in that: Writing a high impedance state into each element of the reference array according to the reference array address information comprises: According to the reference array address information, each bit cell of the reference array is traversed, and a high impedance state is written into each bit cell with a highest write voltage.

3. The memory reference array repair method according to claim 1, characterized in that: Writing a high impedance state into each element of the reference array according to the reference array address information comprises: Reading the resistance state of each bit of the reference array according to the reference array address information, and determining that the bit whose resistance state is a low resistance state is a target bit; A high impedance state is written into the target bit.

4. The memory reference array repair method according to claim 1, characterized in that: Writing a high impedance state into each element of the reference array according to the reference array address information comprises: Traversing each bit cell of the reference array, and writing a high impedance state into each bit cell with a preset write voltage; Read the resistance state of each bit that is written into the high-resistance state this time, and determine the bit that fails to be written into the high-resistance state as the target bit; Increasing the voltage level of the preset write voltage, and writing a high impedance state into each of the target bits with the new preset write voltage; Repeat the steps of reading the resistance state of each bit that is written into the high-resistance state this time and determining the bit that fails to be written into the high-resistance state as the target bit until no target bit appears.

5. The memory reference array repair method according to claim 4, characterized in that: Also includes: Counting the number of times the high impedance state is repeatedly written to the reference array; If the number of repeated writes exceeds a preset threshold and there is still a newly determined target bit, an error message including the latest determined target bit address is returned.

6. The memory reference array repair method according to claim 1, characterized in that: After all addresses of the reference array are written into the high impedance state, indicating that the memory works normally includes: After the reference array full address is written into the high impedance state, a designated flag bit in the register is set to indicate that the memory enters a normal working mode.

7. The memory reference array repair method according to any one of claims 1 to 6, characterized in that: The repair method is executed each time the memory is powered on and the voltage is stable.

8. A memory reference array repair device, characterized in that: include: An address acquisition module, used for acquiring pre-configured reference array address information from a register; A resistance state writing module, used for writing a high resistance state into each element of the reference array according to the reference array address information; The recovery instruction module is used to instruct the memory to work normally after the reference array is fully written into the high-impedance state.

9. A memory reference array repair device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the memory reference array repair method as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the memory reference array repair method according to any one of claims 1 to 7 are implemented.

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