A memory reference array repair method, device and medium

Abstract

The application discloses a memory reference array repair method, device and medium, relates to the technical field of memory, and is used for repairing a failed memory reference array. In view of the problem that there is no scheme for repairing a failed reference array at present, the application provides a memory reference array repair method. Address information of a reference array is preconfigured in a register in advance. When a memory is caused to have a resistance state flip due to sudden high temperature, a magnetic field, vibration and other conditions of an external environment, the preconfigured address information of the reference array can be used to perform high-resistance state writing on all addresses of the reference array, so that the repair work on the failed reference array is realized. When a reference array using an MTJ bit is affected by sudden high temperature, a magnetic field, vibration and other external factors to have a resistance state flip, the all-address high-resistance state of the reference array can also be restored through a rewriting operation, so that the reference array can better adapt to the requirement of the resistance value reference of the memory in a scene where temperature changes exist.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory, in particular to a memory reference array repair method, device and medium. BACKGROUND

[0002] The bit of MRAM usually includes 1 magnetic tunnel junction (MTJ) and 1 or more MOSFETs. The reading of information in a single MTJ depends on the difference between the parallel state resistance Rp and the anti-parallel state resistance Rap, and a MRAM composed of an MTJ array has a certain statistical distribution standard of Rp and Rap (the Rp and Rap distribution curves do not overlap), and a suitable reference resistance needs to be determined to accurately determine the storage information in the bit.

[0003] MRAM: Magnetoresistive Random Access Memory, is a non-volatile magnetic random access memory.

[0004] When the temperature changes, the resistance value of Rap will change accordingly, so a reference resistance whose resistance value can also change with temperature is needed to ensure that MRAM has a certain read window for normal reading. At this time, an MTJ array can also be selected as a reference, and the MTJ array is written as a high resistance state (also called 1 state or AP state, corresponding to resistance value Rap), and is connected in series and parallel with other resistances to achieve the target reference resistance.

[0005] However, when there is a short-term high-temperature situation (such as the welding process of a chip), or when affected by a magnetic field, the AP state of the reference MTJ array has a certain probability of flipping to a low resistance state (also called 0 state or P state, corresponding to resistance value Rp), at which time the reference is invalid, and MRAM cannot perform normal read and write operations. At present, technical personnel are mainly engaged in preventing the occurrence of MTJ flipping, and there is no repair scheme after the reference array fails.

[0006] Therefore, the technical personnel in the field now urgently need a memory reference array repair method to repair the failed reference array of the memory to ensure the normal read and write function of the memory. SUMMARY

[0007] The purpose of the present application is to provide a memory reference array repair method, device and medium to solve the problem of repairing the failed reference array of the memory to ensure the normal read and write function of the memory.

[0008] To solve the above technical problems, the present application provides a memory reference array repair method, comprising:

[0009] obtaining pre-configured reference array address information from a register;

[0010] writing high resistance state into each bit of the reference array according to the reference array address information;

[0011] after the writing of high resistance state into all addresses of the reference array is completed, instructing the memory to work normally.

[0012] In another aspect, the writing of high resistance state into each bit of the reference array according to the reference array address information comprises:

[0013] traversing each bit of the reference array according to the reference array address information, and writing high resistance state into each bit with the highest write voltage.

[0014] In another aspect, the writing of high resistance state into each bit of the reference array according to the reference array address information comprises:

[0015] reading resistance state of each bit of the reference array according to the reference array address information, and determining the bit with low resistance state as a target bit;

[0016] writing high resistance state into the target bit.

[0017] In another aspect, the writing of high resistance state into each bit of the reference array according to the reference array address information comprises:

[0018] traversing each bit of the reference array, and writing high resistance state into each bit with a preset write voltage;

[0019] reading resistance state of each bit written with high resistance state this time, and determining the bit with failed writing of high resistance state as a target bit;

[0020] increasing voltage level of the preset write voltage, and writing high resistance state into each target bit with the new preset write voltage;

[0021] repeating the step of reading resistance state of each bit written with high resistance state this time, and determining the bit with failed writing of high resistance state as a target bit, until no target bit appears.

[0022] In another aspect, the method further comprises:

[0023] counting the number of times of writing high resistance state into the reference array repeatedly;

[0024] if the number of times of repeated writing exceeds a preset threshold, and there still exists a newly determined target bit, returning error information including address of the latest determined target bit.

[0025] In another aspect, after the writing of high resistance state into all addresses of the reference array is completed, instructing the memory to work normally comprises:

[0026] After the high resistance state writing of the full address of the reference array is completed, the specified flag bit in the register is set to indicate that the memory enters the normal working mode.

[0027] In another aspect, the repair method is executed each time the memory is powered on and the voltage is stable.

[0028] To solve the above technical problems, the application further provides a memory reference array repair device, comprising:

[0029] An address acquisition module is configured to acquire the preconfigured reference array address information from the register;

[0030] A resistance state writing module is configured to write the high resistance state into each bit of the reference array according to the reference array address information;

[0031] A recovery indication module is configured to indicate the memory to work normally after the high resistance state writing of the full address of the reference array is completed.

[0032] To solve the above technical problems, the application further provides a memory reference array repair device, comprising:

[0033] A memory is configured to store a computer program;

[0034] A processor is configured to execute the computer program to implement the steps of the memory reference array repair method.

[0035] To solve the above technical problems, the application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the memory reference array repair method.

[0036] The memory reference array repair method provided by the application can write the high resistance state into the full address of the reference array through the preconfigured reference array address information when the memory resistance state is reversed due to sudden high temperature, magnetic field, vibration and other external factors, so as to repair the failed reference array. After the repair is completed, the reference array can be restored to the normal resistance state, and the memory can correctly distinguish the high resistance state and the low resistance state, so as to meet the needs of the normal read-write function. The application provides a repair scheme for the failed memory reference array, so that when the reference array using MTJ bits is affected by sudden high temperature, magnetic field, vibration and other external factors, the full address high resistance state of the reference array can be restored through the rewriting operation, which better adapts to the needs of the memory resistance reference in the scene with temperature change.

[0037] The memory reference array repair device and the computer readable storage medium provided by the application correspond to the above method and have the same effect. Attached Figure Description

[0038] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a common memory read circuit.

[0040] Figure 2 A flowchart of a memory reference array repair method provided by the present invention;

[0041] Figure 3 A flowchart of the power-on and repair process of a memory is provided for this invention;

[0042] Figure 4 A structural diagram of a memory reference array repair device provided by the present invention;

[0043] Figure 5 This is a structural diagram of another memory reference array repair device provided by the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0045] The core of this application is to provide a method, apparatus, and medium for repairing a memory reference array.

[0046] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Currently, in order to ensure that the memory can still be read out in environments with significant temperature changes, a reference array composed of bits consisting of magnetic tunnel junctions (MTJs) is often used.

[0048] The structure of a memory read circuit using an MTJ reference is as follows: Figure 1 As shown, it includes: a read circuit section and a reference circuit section.

[0049] The reference circuit part includes a plurality of bits and a poly resistor with a resistance of 1 / 2Rp(corresponding to the resistance of the low resistance state); each bit includes an MTJ and a MOSFET in series; the plurality of bits are connected in parallel with the poly resistor in series to form a reference array, and an intermediate state reference with a resistance of 1 / 2(Rap+Rp) is obtained as an initial state.

[0050] It should be noted that the plurality of bits in the memory reading circuit are divided into normal bits and reference bits. Figure 1 In the normal bits, the input signal at the control end (i.e., the GATE end of the MOSFET) is WL (WL<0>~WL<1023>), and in practical applications, 1024 normal bits are generally provided; the input signal at the GATE end of the reference bits is ref_wl (ref_wl<0>~ref_wl<3>), and generally, two groups of reference bits are provided, each group including two reference bits connected in parallel; during data reading, the two reference bits in the same group are connected in parallel, and only one normal bit is enabled at the data end (IREAD).

[0051] Before the memory chip is shipped, all the MTJs in the reference array need to be set to the high resistance state (AP state), at which time the resistance of the reference array is normal. However, when the memory chip is used by the actual user, the memory chip is usually soldered, and the memory chip is exposed to high temperature during soldering, which causes the temperature to rise sharply in a short time. At this time, one or more MTJs in the reference array that are in the high resistance state may flip to the low resistance state (P state), and part of the reference may be offset, which may cause the read window of the memory chip to be lost or not to exist, affecting the normal read and write function of the memory. Similarly, other external factors such as magnetic field and vibration may also cause some MTJs in the reference array to flip, thereby causing the reference to fail and affecting the normal read and write of the memory.

[0052] To solve the above problems, the application provides a memory reference array repair method, as shown in Figure 2 , which includes the following steps.

[0053] S11: Obtain the preconfigured reference array address information from the register.

[0054] S12: Write the high resistance state into each bit of the reference array according to the reference array address information.

[0055] S13: After the high resistance state is written into all the bits of the reference array, instruct the memory to work normally.

[0056] It is easy to know that the register in step S11 can be a register in the memory chip (if any) or a register set up additionally for storing the pre-set reference array address information. The reference array address information records the address corresponding to each bit in the reference array or the start address and the end address corresponding to all bits in the reference array, for realizing data writing (i.e. writing of "1" and "0", corresponding to high resistance state and low resistance state respectively) to the reference array.

[0057] For step S12, as known from the above, the reference array is normally in a high resistance state of all MTJs. Therefore, step S12 realizes the repair of the MTJ resistance state flip by rewriting the high resistance state to all addresses of the reference array.

[0058] It is also to be noted that the realization of the high resistance state writing to the reference array does not need to change the original structure of the memory chip. The manufacturer needs to write the high resistance state to all bits of the reference array before the memory chip is shipped from the factory, that is, the existing memory chip structure itself already supports the high resistance state writing to all addresses of the reference array. However, the write permission to the reference array is generally not open to the user, so the above method can be realized by a program or script pre-configured in the memory chip. On the one hand, it reduces unnecessary permission opening to the user and avoids the influence of the user's misoperation on the normal use of the memory chip; on the other hand, it can effectively reduce the implementation cost of the user to realize the repair of the failed reference array, making the repair work of the failed reference array of the memory more simple and easy to realize.

[0059] In addition, the present application does not limit how the high resistance state is written to the reference array in step S12. It can be written by address traversal, or it can be written from a specified address, a specified order, a specified jump mode, etc. The number of times of writing can be only once or repeated multiple times, which is not limited in the embodiment.

[0060] For step S13, it is easy to know that the method is a repair method for a failed reference array, and the reference array is one of the necessary conditions for the memory to realize normal read and write functions. Therefore, when the repair of the failed reference array is realized by executing the above method, the memory needs to suspend the normal read and write functions, that is, to enter another mode different from the normal working mode, which can be called repair mode. When the above method flow is executed and the failed reference array is repaired, the memory needs to be switched back to the normal working mode,

[0061] As to how to indicate the normal working of the memory in step S13, the embodiment is not limited in particular. The specific indication can be achieved by generating and sending specific instructions to the memory, or in a possible implementation provided by the embodiment, step S13 is specifically:

[0062] After the high-resistance state writing of the full address of the reference array is completed, the specified flag bit in the register is set to indicate that the memory enters the normal working mode.

[0063] The specified flag bit in the embodiment is a flag bit for determining the current working mode of the register. In the currently provided implementation, the working mode of the memory can be divided into a normal working mode and a repair mode, so the simplest way is to use a binary number, 0 and 1 respectively representing the normal working mode and the repair mode of the memory. However, it should be noted that the embodiment does not limit the specified flag bit to represent the normal working mode and the repair mode of the memory by a binary number only. If there are other working modes of the memory in actual application, the setting of the specified flag bit can also be achieved by other ways.

[0064] The reference array repair method provided by the application can ensure that the full address of the reference array still maintains a high-resistance state by writing a high-resistance state into the reference array when the reference array in the memory fails due to the resistance state inversion caused by external factors, so as to restore the resistance reference function of the reference array and enable the memory to normally implement the read-write function. In addition, the method does not need to change the original architecture of the memory, is simple to implement, and will not affect the implementation of other functions of the memory. Moreover, the method is well adapted to the use of MTJ as a bit to meet the needs of the memory in a scenario with obvious temperature difference changes. Even if the MTJ resistance state inverts due to external factors, the method can repair it, so that the application range of the MTJ reference array is wider and the reliability is higher.

[0065] On the other hand, for the implementation of writing a high-resistance state into the reference array which is not limited in the above embodiment, the embodiment provides a possible implementation, and step S12 is specifically:

[0066] S12-A: According to the reference array address information, traverse each bit of the reference array, and write a high-resistance state into each bit with the highest write voltage.

[0067] As can be seen from the above, the normal resistance reference function of the reference array is based on the premise that the resistance state of each MTJ is a high-resistance state, and the repair method provided by the application is to write back the MTJ inverted to a low-resistance state by external factors to a high-resistance state. Therefore, the success rate of writing a high-resistance state into the reference array directly affects the repair effect of the method on the failed reference array.

[0068] It should be noted that, when writing the high resistance state to the reference array, the selection of the write voltage will affect the success rate of writing the high resistance state to a certain extent. Generally speaking, within a reasonable range, the higher the write voltage, the higher the success rate of writing the high resistance state. The highest write voltage mentioned in the embodiment is the maximum voltage level write voltage that can be achieved under the premise that the electrical parameters of the memory are allowed. Therefore, it is not difficult to see that the embodiment provided in the embodiment is a preferred solution from the perspective of improving the success rate of writing the high resistance state of the reference array. By setting the highest write voltage, the highest write success rate is ensured in the single high resistance state writing process of the reference array.

[0069] Further, in addition to increasing the voltage level of the write voltage, repeatedly writing the high resistance state can also effectively improve the reliability of the modification effect of the method.

[0070] However, it should be noted that although the high voltage level write voltage has the characteristic of high success rate of writing the high resistance state, it also has some other problems, for example, the high write voltage will affect the service life of the related electrical elements in the memory. Specifically, that is, when the memory writes the high resistance state by a low-level write voltage, it can support more write times before being damaged compared to a high write voltage.

[0071] In the embodiment provided in the above embodiment, for writing the high resistance state to the reference array, the simplest implementation is to write the high resistance state to all bits in the reference array to ensure that the reference array is full address high resistance state after the high resistance state is written. However, it is easy to understand that when the reference array is flipped due to external factors, usually only one or a few bits of the MTJ resistance state are flipped. Therefore, the full address traversal write will cause the problem of invalid write, that is, writing the high resistance state to the bit which is originally high resistance state. This invalid write will affect the overall efficiency of the repair method to a certain extent, and on the other hand, when the above embodiment writes the high resistance state with the highest write voltage, it will cause unnecessary damage to the service life of the electrical elements.

[0072] Based on the above, the application also provides another preferred implementation scheme for writing in step S12, which specifically includes:

[0073] S121-B: According to the reference array address information, read the resistance state of each bit of the reference array, and determine that the bit with low resistance state as the target bit;

[0074] S122-B: Write the high resistance state to the target bit.

[0075] It should be noted that the existing memory architecture also supports data reading in the reference array, for example, after the above-mentioned writing of the high resistance state to the reference array is completed, whether the writing is successful is determined by reading the data in the reference array. If the data of all addresses in the reference array is "1" (i.e. corresponding to the high resistance state), it means that the reference array is repaired successfully.

[0076] Accordingly, as known from the above, in actual application, the resistance state flip of the failed reference array often occurs in one or several bits, and the possibility of resistance state flip of all bits is almost negligible. Therefore, the embodiment determines the address of the stored data as "0" by reading the data stored in the reference array, and the corresponding bit is the target bit that needs to be repaired. The subsequent high resistance state writing step is performed on the target bit.

[0077] The embodiment filters out the target bit with resistance state flip by reading the data in the reference array, so that targeted writing operation can be performed in the subsequent high resistance state writing. On the one hand, it can avoid the influence of invalid writing on the efficiency of the overall repair process, and on the other hand, it can avoid the damage of invalid writing to the bit, which is beneficial to improve the service life of the memory as a whole.

[0078] Further, in combination with the above two embodiments of writing the high resistance state to the reference array, the embodiment also provides another preferred embodiment, and the step S12 is specifically:

[0079] S121-C: traversing each bit of the reference array, and writing a high resistance state to each bit with a preset writing voltage;

[0080] S122-C: reading the resistance state of each bit written with the high resistance state this time, and determining the bit with failed writing of the high resistance state as a target bit;

[0081] S123-C: improving the voltage level of the preset writing voltage, and writing a high resistance state to each target bit with a new preset writing voltage;

[0082] S124-C: repeating step S122-C until no target bit appears.

[0083] It should be noted that the preset write voltage can include multiple levels of write voltage in advance, and when the first high resistance state write is performed in step S121-C, the write is first performed with the lowest level of write voltage; after the first high resistance state write step is completed, the data in the reference array is read, and it is determined whether there is a failed bit; if so, it is determined as the target bit for the next high resistance state write; then, in the next high resistance state write process, the level of the write voltage is increased, and the target bit is re-written in the high resistance state; the judgment of whether the write is successful is repeated again, that is, it is determined whether a new target bit is generated; if so, the level of the write voltage is increased again to repeat the write, until the reference array full address is in the high resistance state, that is, no new target bit appears.

[0084] For example, the preferred scheme provided by the embodiment is further described in combination with a possible actual application scenario:

[0085] The first, second, third and fourth levels of voltage are preset as the write voltage that can be used, and the voltage levels are sequentially increased from the first write voltage to the fourth write voltage. When the high resistance state write is performed for the first time, the first write voltage with the lowest voltage level is used; if it is found after reading the data in the reference array that there is a target bit that fails to be written, the target bit is re-written in the high resistance state by using the second write voltage; if there is still a target bit, the third write voltage is used to perform the third write in the high resistance state; if no new target bit is determined after the third write in the high resistance state is completed, it is considered that the reference array full address has been repaired to the high resistance state, and the fourth write voltage does not need to participate in the repair process.

[0086] In addition, it should be noted that, as known from the above, the resistance state reversal usually occurs in part of the bits in the reference array, and the determination of these bits can be achieved by reading the data in the reference array. Therefore, in the first high resistance state write in step S121-C of the embodiment, the target bit for the write can also be determined by reading the data, and the above is only one possible implementation scheme.

[0087] The preferred scheme provided by the embodiment uses the stepped voltage write method to perform the write in the high resistance state of the reference array. On the one hand, the repeated write and the increase of the write voltage each time can effectively ensure the success rate of the write in the high resistance state and ensure the repair effect on the reference array; on the other hand, the stepped increase of the write voltage can also reduce the impact of the write in the high resistance state on the service life of the reference array as much as possible, and the low voltage level can be written successfully without using a high write voltage, and the bit loss is smaller. Therefore, the scheme is a preferred scheme that comprehensively considers the write success rate and the service life of the reference array, and can better meet the general needs in the actual memory application scenario.

[0088] On the other hand, the time at which the repair method provided in the present application is executed is not limited in the above embodiments. The method can be triggered by a user based on an instruction at any time after the reference array is determined to be invalid, or the method can be triggered by a pre-set period or according to certain rules, and the present application does not limit the triggering mode, which can be freely selected according to actual needs.

[0089] Based on this, the present embodiment provides a possible implementation of a triggering logic:

[0090] The repair method is executed each time the memory is powered on and the voltage is stable.

[0091] It should be noted that the memory needs to be powered on, and operations such as reading the reference array and writing in the high resistance state also need to be based on the power-on of the memory chip, so the above repair method must occur after the memory is powered on.

[0092] The power-on and repair process of the memory can be as shown in Figure 3 After the chip is powered on, the digital logic control module of the chip sends a power-on signal to the low dropout regulator (LDO) stabilizer, and the LDO is powered on at this time. After the LDO is powered on, the LDO returns an instruction to the digital logic control module, indicating that the power-on is complete (in other scenarios, the LDO is also used to send a reset signal and a clock signal OSC CLK to the digital logic control module). After receiving the feedback from the LDO, the digital logic control module sends an instruction (READY signal) to the reset write module (i.e., the digital module for implementing high resistance state writing of the reference array). The reset write module obtains the reference array address information from the register and sends write enable, write data and write address to the write drive circuit, and performs high resistance state writing on the reference array through the write drive circuit, so that all addresses of the reference array are in the high resistance state. After the high resistance state writing of all addresses of the reference array is completed, a specified flag bit is set, indicating that the memory can start normal work, and the power-on and repair process of the memory is completed.

[0093] Further, because random flipping caused by external factors rarely occurs during normal operation of the memory chip, the reference array is not easily invalid after the memory chip is normally powered on and starts working, so setting the repair process of the reference array at the beginning of the power-on of the memory chip can effectively repair the flipping problem that may occur in the reference array, and provide support for the subsequent normal work of the memory chip. And because the memory is normally powered on and works, the reference array invalid problem rarely occurs, so it is usually not necessary to repeatedly repair in the subsequent application of the memory, and in special cases, the user instruction triggering mode can be adopted.

[0094] The reason for waiting for the voltage to be stable before performing the repair method is that the repair method involves writing a high resistance state to the reference array, and only a stable working voltage can ensure the reliability of the repair of the failed reference array. In summary, the preferred solution provided in this embodiment is to automatically perform the repair method of the above embodiment at the beginning of each power-on of the memory chip and after the voltage is stable, so as to solve the possible failure of the reference array.

[0095] In addition, as to how to determine whether the voltage is stable after the memory chip is powered on, it is considered that the power-on process is usually a non-instantaneous process. In the normal case of the memory chip, the voltage will tend to be stable after the memory chip is powered on for a period of time. Therefore, the commonly used solution is to wait for a preset time, and then it is considered that the voltage of the memory chip is stable.

[0096] The embodiment provides a logic for triggering the above repair method. When the memory is powered on and the voltage is stable, the above repair method is triggered. The flipped reference array bit is written in a high resistance state to repair the failed reference array. The repair process occurs at the beginning of the power-on of the memory, and after the repair is completed, the memory is instructed to work normally. Subsequently, because the resistance state flipping problem rarely occurs again when the memory is working normally, the repair process will not be automatically performed again, and the subsequent use of the memory will not be affected. The embodiment provides an automatic execution logic of the repair method, which can automatically repair the failed reference array without additional user operation, and can reduce the impact on the application of the memory.

[0097] In the above embodiment, a memory reference array repair method is described in detail, and the present application also provides an embodiment of a memory reference array repair device. It should be noted that the embodiment of the device part is described from two angles, one is based on the functional module, and the other is based on the hardware.

[0098] Based on the functional module, as shown in Figure 4 The embodiment provides a memory reference array repair device, which comprises:

[0099] The address acquisition module 21 is configured to acquire the preconfigured reference array address information from the register.

[0100] The resistance state writing module 22 is configured to write a high resistance state into each bit of the reference array according to the reference array address information.

[0101] The recovery instruction module 23 is configured to instruct the memory to work normally after the writing of the high resistance state into all addresses of the reference array is completed.

[0102] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part are described in the description of the embodiments of the method part, and will not be described here.

[0103] Figure 5 A structural diagram of a memory reference array repair device provided for another embodiment of the present application is shown in FIG. 3. The memory reference array repair device includes a memory 30 for storing a computer program. Figure 5

[0104] A processor 31 is configured to implement the steps of the memory reference array repair method according to any one of the above embodiments when executing the computer program.

[0105] The processor 31 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 31 can be implemented in at least one of a hardware form of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), etc. The processor 31 can also include a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also known as a Central Processing Unit (CPU). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 31 can be integrated with a Graphics Processing Unit (GPU) for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 31 can also include an Artificial Intelligence (AI) processor for processing machine learning-related computing operations.

[0106] ​The memory 30 can include one or more computer-readable storage media that can be non-transitory. The memory 30 can also include high-speed random access memory and nonvolatile, computer-readable storage media such as one or more magnetic disk storage devices, flash memory devices. In this embodiment, the memory 30 is at least used to store the following computer program 301, wherein the computer program is loaded and executed by the processor 31, and can realize the related steps of the memory reference array repair method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 30 can also include an operating system 302 and data 303, etc., and the storage mode can be temporary storage or permanent storage. The operating system 302 can include Windows, Unix, Linux, etc. The data 303 can include but is not limited to a memory reference array repair method, etc.

[0107] In some embodiments, the memory reference array repair apparatus can further include a display screen 32, an input / output interface 33, a communication interface 34, a power supply 35, and a communication bus 36.

[0108] Those skilled in the art can understand that, Figure 5 The structure shown in the figure does not constitute a limitation on the memory reference array repair apparatus, and can include more or fewer components than those shown in the figure.

[0109] The memory reference array repair apparatus provided by the embodiments of the present application includes a memory and a processor, and the processor can realize the following method when executing the program stored in the memory: a memory reference array repair method.

[0110] Finally, the present application also provides an embodiment of a computer-readable storage medium. The computer-readable storage medium stores a computer program, and the computer program is executed by the processor to realize the steps recorded in the above method embodiments.

[0111] It can be understood that if the method in the above embodiments is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and executes all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0112] The memory reference array repair method, device and medium provided by the present application are described in detail above. The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be understood by referring to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be understood by referring to the method part. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, the present application can be improved and modified, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0113] It should also be noted that in the present specification, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A memory reference array repair method, characterized by, The reference array comprises a plurality of bits and a poly resistor with a resistance of 1 / 2Rp; each bit comprises an MTJ and a field effect transistor connected in series; the plurality of bits are connected in parallel and connected in series with the poly resistor to form the reference array, so that an intermediate state reference with a resistance of 1 / 2(Rap+Rp) is obtained as an initial state; The method comprises: obtaining preconfigured reference array address information from a register; iterating through each bit of the reference array and writing a high resistance state into each bit at a preset write voltage; reading the resistance state of each bit written with the high resistance state this time to determine the bit as a target bit if the writing of the high resistance state fails; increasing the voltage level of the preset write voltage and writing the high resistance state into each target bit at a new preset write voltage; repeating the step of reading the resistance state of each bit written with the high resistance state this time to determine the bit as a target bit if the writing of the high resistance state fails until no target bit appears; after the writing of the high resistance state into all addresses of the reference array is completed, instructing the memory to work normally.

2. The memory reference array repair method of claim 1, wherein, Further comprising: counting the number of times of repeatedly writing the high resistance state into the reference array; if the number of times of repeatedly writing exceeds a preset threshold and there still exists a newly determined target bit, returning error information including the address of the latest determined target bit.

3. The memory reference array repair method of claim 1, wherein, The step of instructing the memory to work normally after the writing of the high resistance state into all addresses of the reference array is completed comprises: after the writing of the high resistance state into all addresses of the reference array is completed, setting a specified flag bit in the register to instruct the memory to enter a normal working mode.

4. The memory reference array repair method of any one of claims 1 to 3, wherein, The repair method is executed each time the memory is powered on and the voltage is stable.

5. A memory reference array repair apparatus, characterized by, The reference array comprises a plurality of bits and a poly resistor with a resistance of 1 / 2Rp; each bit comprises an MTJ and a field effect transistor connected in series; the plurality of bits are connected in parallel and connected in series with the poly resistor to form the reference array, so that an intermediate state reference with a resistance of 1 / 2(Rap+Rp) is obtained as an initial state; the device comprises: an address obtaining module configured to obtain preconfigured reference array address information from a register; a resistance state writing module configured to iterate through each bit of the reference array and write a high resistance state into each bit at a preset write voltage; read the resistance state of each bit written with the high resistance state this time to determine the bit as a target bit if the writing of the high resistance state fails; increase the voltage level of the preset write voltage and write the high resistance state into each target bit at a new preset write voltage; repeat the step of reading the resistance state of each bit written with the high resistance state this time to determine the bit as a target bit if the writing of the high resistance state fails until no target bit appears; a recovery instruction module configured to instruct the memory to work normally after the writing of the high resistance state into all addresses of the reference array is completed.

6. A memory reference array repair apparatus, characterized by, comprises: a memory configured to store a computer program; a processor configured to execute the computer program to implement the steps of the memory reference array repair method according to any one of claims 1 to 4.

7. A computer readable storage medium characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the memory reference array repairing method in any one of claims 1 to 4.

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