Programmable fuse trimming circuit and method

Abstract

The application provides a programmable fuse trimming circuit and method, and a fuse array circuit, which comprises a plurality of fuse unit modules and an end bit fuse module, each of the fuse unit modules comprises a fuse; a fuse programming control circuit receives an external input signal through a chip pin, controls the working mode of the circuit according to the external input signal, reads the fuse state information from the fuse unit module in a fuse state reading mode, pre-trims the fuses in the fuse unit module in a pre-trimming mode, executes a trimming operation on the fuses in the corresponding fuse unit module in an official trimming mode, and burns the fuses in the end bit fuse module after the trimming operation is completed. After the fuses are read and the fuses to be trimmed are determined through pre-trimming, the official trimming is performed according to the external input trimming code, and the fuses in the end bit fuse module are burned after the official trimming is completed. The chip circuit cannot be trimmed again, the misburning phenomenon is effectively prevented, and the trimming time and cost are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular to a programmable fuse trimming circuit and method. BACKGROUND

[0002] In the process of integrated circuit wafer fabrication, it is inevitable to be affected by process fluctuation and packaging process, thereby causing deviation of circuit parameters from design target value, and finally the precision of parameters cannot be completely guaranteed, and even the overall performance index of the chip will be affected. In addition, with the increasing requirement of users on the performance index of small-sized integrated circuits, the high-precision challenge faced by integrated circuits is becoming increasingly obvious. Therefore, the trimming scheme for each parameter of the chip has been gradually valued.

[0003] The trimming techniques used in the current chip production process include laser trimming, PAD trimming and in-circuit trimming. Laser trimming is to burn the metal fuse of the chip before packaging through laser technology; PAD trimming is also to burn the metal fuse of the chip before packaging through a probe; and in-circuit trimming is to burn the fuse by inputting trimming code on the external pin to control the internal circuit to generate a large current after packaging. Laser trimming has good precision, but cannot avoid the influence of packaging; PAD trimming needs to design a special trimming PAD in the chip for probe testing, which occupies a large chip area; and in-circuit trimming is performed after packaging, saves the area by inputting trimming code through the existing chip pin without the need to increase additional PAD port, and can avoid the influence of dicing and packaging on the chip, and is a trimming method with high precision at present. However, at present, with the increasing requirement of chip precision and the increasing number of trimming bits, repeated trimming is needed, which leads to the phenomenon of incorrect trimming, and the trimming time also increases with the increase of the number of trimming bits, thereby increasing the cost of the chip. SUMMARY

[0004] Based on the above description, the present application provides an in-circuit trimming scheme with low cost, programmability and high reliability.

[0005] A programmable fuse trimming circuit comprises: a fuse array circuit comprising a plurality of fuse cell modules and an end bit fuse module, each fuse cell module comprising a fuse; and a fuse programming control circuit connected to the fuse array circuit and receiving an external input signal through a chip pin, for entering a fuse state reading mode, a pre-trimming mode and a formal trimming mode according to the external input signal; reading fuse state information from the fuse cell modules in the fuse state reading mode; pre-trimming the fuses in the fuse cell modules in the pre-trimming mode; performing a fuse trimming operation on the fuses in the corresponding fuse cell modules in the formal trimming mode, and burning the fuse in the end bit fuse module after the fuse trimming operation is completed.

[0006] Further, the fuse burning control circuit comprises a mode control module, a data read-write module, a storage module, an analog module, an address information detection module and a burning module; the mode control module is connected with the data read-write module, the address information detection module and the burning module respectively, the data read-write module is connected with the storage module, the storage module is connected with the analog module and the burning module respectively, and the address information detection module is connected with the burning module; the mode control module receives an external input signal through a chip pin and controls to enter a fuse state reading mode, a pre-adjustment mode and an official adjustment mode according to the external input signal; the address information detection module is used for generating a fuse address control signal and outputting the fuse address control signal to the fuse unit module for conduction operation in the fuse state reading mode and the official adjustment mode; the data read-write module is used for storing fuse state information of the fuse unit module in the storage module in the fuse state reading mode and storing pre-adjustment data information in the storage module in the pre-adjustment mode; the analog module is used for receiving the fuse state information from the storage module, performing parameter testing according to the pre-adjustment data information and the fuse state information in the pre-adjustment mode, obtaining a parameter testing result, determining a fuse to be adjusted according to the parameter testing result, and storing fuse address information of the fuse to be adjusted in the storage module; and the burning module is used for generating a burning current control signal according to the fuse address information of the fuse to be adjusted in the storage module and outputting the burning current control signal in the official adjustment mode; and the fuse array circuit performs adjustment operation on the fuse to be adjusted according to the burning current control signal and the fuse address control signal.

[0007] Further, the fuse array circuit further comprises a second PMOS tube, and each fuse unit module further comprises an NMOS tube; a source of the second PMOS tube is connected with a power supply voltage, a drain of the second PMOS tube is connected with a first end of a fuse, and a gate of the second PMOS tube is connected with a read fuse information operation signal; in the fuse unit module, a source of the NMOS tube is connected with ground, a gate of the NMOS tube is connected with a fuse address control signal, and a drain of the NMOS tube is connected with a second end of the fuse; the fuse array circuit is provided with a fuse state output end connected with the first end of the fuse and used for outputting fuse state information.

[0008] Further, the programmable fuse adjustment circuit further comprises a clock generation module, and the mode control module comprises a counter unit and a counting end detection unit; in the fuse state reading mode, the counter unit starts to work, and the counting end detection unit is used for detecting a counting state of the counter unit according to an output end signal of the counter unit and outputting a counting end signal and a read fuse information operation signal according to a counting state detection result; in the fuse state reading mode, the address information detection module generates a fuse address control signal according to the output end signal of the counter unit, the data read-write module is used for reading fuse state information of the fuse unit module according to the counting end signal, and the clock generation module generates a first internal clock signal according to the output end signal of the counter unit; and the storage module latches the fuse state information read by the data read-write module according to the first internal clock signal.

[0009] Further, the external input signal comprises an external data signal; the mode control module further comprises a shift register, a read pulse detection unit, a data flow unit, an addressing unit and an inverter; the shift register receives the external data signal and stores the data information of the external data signal as data information of the shift register; the external data signal comprises an unlock input signal, and the shift register stores the unlock input signal as unlock data; the read pulse detection unit is configured to generate first and second unlock pulse signals which do not overlap with each other based on the unlock data of the shift register; the data flow unit is configured to perform latch unlocking according to the first unlock pulse signal; the addressing unit is configured to perform latch unlocking according to the second unlock pulse signal; the inverter inverts the count end signal output by the count end detection unit to form a count end inverse signal; in the pre-adjustment mode, the external data signal received by the shift register comprises pre-adjustment input data, the pre-adjustment input data enters the data flow unit and is processed by the data flow unit to form pre-adjustment data information, and the pre-adjustment input data enters the addressing unit and is processed by the addressing unit to form pre-adjustment address information; the data read-write module reads the pre-adjustment data information formed by the data flow unit according to the count end inverse signal; the clock generation module processes the pre-adjustment address information formed by the addressing unit to generate a second internal clock signal; and the storage module latches the pre-adjustment data information read by the data read-write module according to the second internal clock signal.

[0010] Further, the burn-in module includes a burn-in pulse detection unit, a combinational logic unit, a timing logic unit and a burn-in current generation unit; in the formal trimming mode, the external data signal received by the shift register includes first trimming input data and second trimming input data, the first trimming input data enters the data flow unit and forms the first trimming control signal after being processed by the data flow unit; the first trimming input data enters the addressing unit and forms the second trimming control signal after being processed by the addressing unit; the second trimming input data enters the data flow unit and forms the third trimming control signal after being processed by the data flow unit; the second trimming input data enters the addressing unit and forms the fourth trimming control signal after being processed by the addressing unit; in the formal trimming mode, the burn-in pulse detection unit generates the trimming start control signal according to the first trimming control signal and the second trimming control signal, the timing logic unit generates the reset signal of the count end detection unit according to the third trimming control signal and the fourth trimming control signal, and the counter unit is started according to the reset signal of the count end detection unit; in the formal trimming mode, the address information detection module generates the fuse address control signal to the fuse unit module according to the output signal of the counter unit, and generates the fuse address detection information to the combinational logic unit; the combinational logic unit performs logical processing according to the fuse address detection information and the to-be-trimmed fuse address information stored in the storage module to output the fuse address selection signal; the burn-in current generation unit generates the burn-in current control signal according to the trimming start control signal and the fuse address selection signal; and the fuse array circuit performs the fuse burn-out operation according to the burn-in current control signal.

[0011] Further, the burn-in current generation unit includes a fourth AND gate and a seventh NAND gate; the first input end of the fourth AND gate receives the fuse address selection signal; the second input end of the fourth AND gate receives the trimming start control signal; the output end of the fourth AND gate outputs the second burn-in large current control signal; the first input end of the seventh NAND gate receives the trimming start control signal; the second input end of the seventh NAND gate receives the count end signal output by the count end detection unit; the output end of the seventh NAND gate outputs the first burn-in large current control signal; the fuse array circuit includes an eighth NAND gate and a first PMOS transistor; the first burn-in large current control signal enters the eighth NAND gate after being inverted at the first input end of the eighth NAND gate; the second burn-in large current control signal enters the second input end of the eighth NAND gate; the output end of the eighth NAND gate outputs the fuse burn-out operation control signal; the gate of the first PMOS transistor is connected to the output end of the eighth NAND gate, the source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the fuse unit module.

[0012] Further, the clock generating module comprises a clock generating circuit, a third NAND gate, a fourth NAND gate, a sixth NAND gate and a decoder; the clock generating circuit is connected to the output signal of the counter unit, and the output of the clock generating circuit is connected to the second input of the fourth NAND gate; the first input of the fourth NAND gate is connected to the count end signal, and the output of the fourth NAND gate is connected to the second input of the sixth NAND gate; the first input of the third NAND gate is connected to the output of the decoder, the second input of the third NAND gate is connected to the count end inverse signal, and the output of the third NAND gate is connected to the first input of the sixth NAND gate; the output of the sixth NAND gate is connected to the storage module; the input of the decoder is connected to the addressing unit, and in the pre-trimming mode, the decoder processes the pre-trimming address information formed by the addressing unit to form a decoding signal output to the third NAND gate, and the second internal clock signal is output to the storage module through the sixth NAND gate.

[0013] Further, the data read-write module comprises a first NAND gate, a second NAND gate and a fifth NAND gate; the first input of the first NAND gate is connected to the fuse state output of the fuse array circuit, the second input of the first NAND gate is connected to the count end signal, and the output of the first NAND gate is connected to the first input of the fifth NAND gate; the second input of the second NAND gate is connected to the output of the inverter, the output of the second NAND gate is connected to the second input of the fifth NAND gate, and the output of the fifth NAND gate is connected to the storage module; the first input of the second NAND gate is connected to the data flow unit, and in the pre-trimming mode, the pre-trimming data information formed by the data flow unit is output to the first input of the second NAND gate, and then output to the storage module through the output of the fifth NAND gate.

[0014] The application provides a programmable fuse trimming method using the programmable fuse trimming circuit, which comprises the following steps: A1, initializing the programmable fuse trimming circuit; A2, the fuse programming control circuit obtains the external input signal about reading the fuse state information through the chip pin, controls to enter the fuse state reading mode, and reads the fuse state information from the fuse unit module; A3, the fuse programming control circuit obtains the external input signal about pre-trimming the fuse through the chip pin, controls to enter the pre-trimming mode, performs parameter test on the chip circuit, and determines the fuse to be trimmed according to the parameter test result; A4, the fuse programming control circuit obtains the external input signal about trimming the fuse through the chip pin, controls to enter the formal trimming mode, and performs the fuse trimming operation on the fuse to be trimmed; and A5, after the fuse trimming operation is completed, the fuse in the end bit fuse module is burned out.

[0015] The beneficial technical effect of the present application is that the present application inputs external signals through chip pins, and performs programming of the fuses according to the external signals, reads the fuse information, determines the to-be-adjusted fuses, and then performs formal adjustment according to the external input adjustment code. In addition, after the adjustment of the to-be-adjusted fuses is completed, the fuses in the end bit fuse module are burned out, and the circuit cannot enter the adjustment mode again. The phenomenon of false adjustment is effectively prevented, the adjustment time and cost are reduced, and the reliability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 and Figure 2 A circuit diagram of a specific embodiment of the programmable fuse adjustment circuit is provided for the present application.

[0017] Figure 3 A module schematic diagram of the programmable fuse adjustment circuit is provided for the present application.

[0018] Figure 4 A step flow chart of the programmable fuse adjustment method is provided for the present application.

[0019] Figure 5 A circuit initialization and end timing diagram of the programmable fuse adjustment circuit is provided for the present application.

[0020] Figure 6 A whole adjustment timing diagram of a specific embodiment of the programmable fuse adjustment circuit is provided for the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0022] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0023] The present application will be further described below with reference to the accompanying drawings and specific embodiments, but not as a limitation of the present application.

[0024] Reference Figures 1-3The application provides a programmable fuse trimming circuit, which comprises a fuse array circuit 1, a fuse burning control circuit 2 and a fuse array circuit 1.

[0025] The application inputs external signals through chip pins, performs programmable trimming on fuses according to the external signals, reads the state information of the fuses, performs pre-trimming on the fuses, and performs formal trimming on the fuses according to the external input trimming code after determining the fuses to be trimmed, thereby effectively preventing the phenomenon of incorrect burning, reducing the burning time, reducing the cost, and improving the reliability.

[0026] Specifically, as shown in the figure, the fuse array circuit 1 comprises N fuse unit modules 11-1 to 11-N. Figure 1 Each fuse unit module has one fuse fuse. The fuse fuse1 of the first fuse unit module 11-1 and the fuse fuseN of the Nth fuse unit module 11-N.

[0027] Referring to Figure 2 and Figure 3, further, the fuse burning control circuit 2 includes a mode control module 21, a data read-write module 22, a storage module 23, an analog module 24, an address information detection module 25 and a burning module 26; the mode control module 21 is connected with the data read-write module 22, the address information detection module 25 and the burning module 26 respectively, the data read-write module 22 is connected with the storage module 23, the storage module 23 is connected with the analog module 24 and the burning module 26 respectively, and the address information detection module 25 is connected with the burning module 26; the mode control module 21 receives external input signals through chip pins, controls to enter a fuse state reading mode, a pre-trimming mode and an official trimming mode according to the external input signals; the address information detection module 25 is used for generating a fuse address control signal Con_add and outputting the fuse address control signal Con_add to the fuse unit module for conduction operation in the fuse state reading mode and the official trimming mode; the data read-write module 22 is used for storing fuse state information Fuse_DATA of the fuse unit module in the storage module 23 in the fuse state reading mode, and storing pre-trimming data information Pre_trim_DATA in the storage module 23 in the pre-trimming mode; the analog module 24 is used for receiving the fuse state information Fuse_DATA from the storage module 23, performing parameter testing according to the pre-trimming data information Pre_trim_DATA and the fuse state information Fuse_DATA in the pre-trimming mode, obtaining a parameter testing result, determining a fuse to be trimmed according to the parameter testing result, and storing fuse address information of the fuse to be trimmed in the storage module 23; and the burning module 26 is used for generating a trimming current control signal output according to the fuse address information of the fuse to be trimmed in the storage module 23 in the official trimming mode; the fuse array circuit 1 performs trimming operation on the fuse to be trimmed according to the trimming current control signal and the fuse address control signal Con_add.

[0028] The present application multiplexes reading fuse information, pre-trimming and official trimming, for example, the mode control module 21 controls the circuit to enter three operation modes, the information of the three modes is stored in the storage module 23, reading fuse information and official trimming are multiplexed in the address information detection module 25, reading fuse information and pre-trimming are multiplexed in the data read-write module 22, the structure is simple, the reusability is high, the circuit occupation area is reduced, the chip cost is reduced, the integration is facilitated, and the fuse burning is effectively prevented.

[0029] Further, the fuse array circuit 1 further comprises a second PMOS PM2, and each fuse cell module further comprises an NMOS NM; the source of the second PMOS PM2 is connected to a power supply voltage VIN, the drain of the second PMOS PM2 is connected to a first end of a fuse, and the gate of the second PMOS PM2 is connected to a read fuse information operation signal Read_sel; in the fuse cell module, the source of the NMOS is connected to ground, the gate of the NMOS is connected to a fuse address control signal Con_add, and the drain of the NMOS is connected to a second end of the fuse; the fuse array circuit 1 is provided with a fuse state output end connected to the first end of the fuse, for outputting fuse state information Fuse_DATA.

[0030] Each fuse cell module has an NMOS, for example Figure 1 In the embodiment, the NMOS NM-1 of the first fuse cell module 11-1 and the NMOS NM-N of the Nth fuse cell module 11-N. The address information detection module 25 sends a fuse address control signal Con_add to the gate of the NMOS, for example, Con_add1 to the gate of the NMOS NM-1 of the first fuse cell module 11-1, and Con_addN to the gate of the NMOS NM-N of the Nth fuse cell module 11-N. If the second PMOS PM2 is turned on, the corresponding NMOS is turned on when the fuse address control signal Con_add is high, and the power supply voltage VIN is applied to the corresponding fuse to form a read current Iread. At this time, the fuse state output end outputs the fuse state information Fuse_DATA of the fuse.

[0031] Specifically, each fuse cell module further comprises a first buffer, the gate of the NMOS is connected to the output end of the first buffer, and the input end of the first buffer is connected to the fuse address control signal. The fuse address control signal is buffered by the first buffer before entering the NMOS, reducing the impact on the NMOS and protecting the NMOS. For example Figure 1 In the embodiment, the first buffer 111-1 of the first fuse cell module 11-1 and the first buffer 111-N of the Nth fuse cell module 11-N. Specifically, the fuse state output end is connected to a second buffer 12, and the fuse state information Fuse_DATA of the fuse is buffered before being output, for protecting the fuse programming control circuit 2.

[0032] Further, the programmable fuse trimming circuit further comprises a clock generation module 27, the mode control module 21 comprises a counter unit 211 and a count end detection unit 212; in the fuse state reading mode, the counter unit 211 starts to work, and the count end detection unit 212 is used for detecting the counting state of the counter unit 211 according to the output signal of the counter unit 211, outputting a count end signal Con1 and a fuse information reading operation signal Read_sel according to the count state detection result; in the fuse state reading mode, the address information detection module 25 generates a fuse address control signal Con_add according to the output signal of the counter unit 211, the data read-write module 22 is used for reading the fuse state information Fuse_DATA of the fuse unit module according to the count end signal Con1, and the clock generation module 27 generates a first internal clock signal according to the output signal of the counter unit 211; the storage module 23 latches the fuse state information Fuse_DATA read by the data read-write module 22 according to the first internal clock signal.

[0033] The gate of the second PMOS tube PM2 is connected to the fuse information reading operation signal Read_sel, and the second PMOS tube PM2 is turned on at a low level, so that the fuse information reading operation signal Read_sel is at a low level only when the fuse information is read after power-up, and is at a high level at other times. The high level makes the second PMOS tube not conduct, that is, no fuse state information reading operation is performed.

[0034] Further, the external input signals include an external data signal SDA; the mode control module 21 further includes a shift register 213, a read pulse detection unit 214, a data flow unit, an addressing unit and an inverter INV; the shift register 213 receives the external data signal SDA and stores the data information of the shift register; the external data signal SDA contains an unlocking input signal, and the shift register stores the unlocking input signal as unlocking data; the read pulse detection unit 214 is configured to generate first and second unlocking pulse signals C1 and C2 that do not overlap each other based on the unlocking data of the shift register 213; the data flow unit is configured to perform latch unlocking according to the first unlocking pulse signal C1; the addressing unit is configured to perform latch unlocking according to the second unlocking pulse signal C2; the inverter INV inverts the count end signal Con1 output by the count end detection unit 212 to form a count end inverse signal Con2; in the pre-trimming mode, the external data signal SDA received by the shift register 213 includes pre-trimming input data, the pre-trimming input data enters the data flow unit and is processed by the data flow unit to form pre-trimming data information Pre_trimDATA, and the pre-trimming input data enters the addressing unit and is processed by the addressing unit to form pre-trimming address information; the data read-write module 22 reads the pre-trimming data information Pre_trimDATA formed by the data flow unit according to the count end inverse signal Con2; the clock generation module 27 processes the pre-trimming address information formed by the addressing unit to generate a second internal clock signal; and the storage module 23 latches the pre-trimming data information Pre_trimDATA read by the data read-write module 22 according to the second internal clock signal.

[0035] Specifically, the data flow unit and the addressing unit each have a latch, and therefore the data flow unit needs to perform latch unlocking according to the first unlocking pulse signal C1, and the addressing unit needs to perform latch unlocking according to the second unlocking pulse signal C2, so as to obtain the data information of the shift register.

[0036] Specifically, the external input signals include an external clock signal SCL and an external data signal SDA. In addition, specifically, the mode control module 21 further includes a system reset unit 28. The fuse programming control circuit 2 further receives an external power-on end signal POK through a chip pin. The input end of the system reset unit 28 receives the external clock signal SCL, the external data signal SDA and the power-on end signal POK. The output end of the system reset unit 28 is connected to the third input end of the shift register 213 and the second input end of the read pulse detection unit 214. The output end of the system reset unit 28 outputs a system reset signal RESET to the shift register 213 and the read pulse detection unit 214 respectively.

[0037] The first input terminal of the shift register 213 is connected with the external clock signal SCL, and the second input terminal of the shift register 213 is connected with the external data signal SDA.

[0038] The first input terminal of the read pulse detection unit 214 is connected with the external clock signal SCL.

[0039] Specifically, the data flow unit comprises a first AND gate AND1 and a data flow circuit 2151. The first input terminal of the first AND gate AND1 is connected with the first output terminal of the shift register 213, the second input terminal of the first AND gate AND1 is connected with the second output terminal of the shift register 213, and the output terminal of the first AND gate AND1 is connected with the first input terminal of the data flow circuit 2151.

[0040] The output terminal of the data flow circuit 2151 is connected with the input terminal of the data read-write module 22. Specifically, refer to Figure 2 The first output terminal of the data flow circuit 2151 is connected with the first input terminal of a second NAND gate NAND2. The first output terminal of the data flow circuit 2151 is used for outputting the pre-trim data information Pre_trim DATA.

[0041] Specifically, the second input terminal of the data flow circuit 2151 is connected with the external clock signal SCL, and the third input terminal of the data flow circuit 2151 is connected with the power-on end signal POK.

[0042] Specifically, the second input terminal of the first AND gate AND1 is also connected with the first output terminal of the read pulse detection unit 214, which is used for obtaining the first unlock pulse signal C1.

[0043] Specifically, the addressing unit comprises a second AND gate AND2 and an addressing circuit 2161. The first input terminal of the second AND gate AND2 is connected with the third output terminal of the shift register 213. The second input terminal of the second AND gate AND2 is connected with the second output terminal of the read pulse detection unit 214, which is used for obtaining the second unlock pulse signal C2. The output terminal of the second AND gate AND2 is connected with the first input terminal of the addressing circuit 2161. The second input terminal of the addressing circuit 2161 is connected with the external clock signal SCL, and the third input terminal of the addressing circuit 2161 is connected with the power-on end signal POK.

[0044] The fourth output terminal of the shift register 213 is connected with the third input terminal of the read pulse detection unit 214.

[0045] Specifically, the data flow circuit and the addressing circuit have a latch.

[0046] Further, the burn-in module 26 comprises a burn-in pulse detection unit 261, a combination logic unit 262, a timing logic unit 263 and a burn-in current generation unit; in the formal trimming mode, the external data signal SDA received by the shift register comprises first trimming input data and second trimming input data, the first trimming input data enters the data flow unit and forms the first trimming control signal after being processed by the data flow unit; the first trimming input data enters the addressing unit and forms the second trimming control signal after being processed by the addressing unit; the second trimming input data enters the data flow unit and forms the third trimming control signal after being processed by the data flow unit; the second trimming input data enters the addressing unit and forms the fourth trimming control signal after being processed by the addressing unit; in the formal trimming mode, the burn-in pulse detection unit 261 generates the trimming start control signal according to the first trimming control signal and the second trimming control signal, the timing logic unit 263 generates the reset signal RN of the count end detection unit according to the third trimming control signal and the fourth trimming control signal, and the count end detection unit 212 starts the counter unit 211 according to the reset signal RN of the count end detection unit; in the formal trimming mode, the address information detection module 25 generates the fuse address control signal Con_add to the fuse unit module according to the output signal of the counter unit, and generates the fuse address detection information Fuse_ADD to the combination logic unit 262; the combination logic unit 262 performs logical processing on the fuse address detection information Fuse_ADD and the to-be-trimmed fuse address information stored in the storage module to output the fuse address selection signal; the burn-in current generation unit generates the burn-in current control signal according to the trimming start control signal and the fuse address selection signal; and the fuse array circuit 1 performs the fuse burn-out operation according to the burn-in current control signal.

[0047] Specifically, the second output end of the data flow circuit 2151 is connected to the first input end of the timing logic unit 263, and the second output end of the addressing circuit 2161 is connected to the second input end of the timing logic unit 263.

[0048] Specifically, the third output end of the data flow circuit 2151 is connected to the first input end of the burn-in pulse detection unit 261, and the third output end of the addressing circuit 2161 is connected to the second input end of the burn-in pulse detection unit 261.

[0049] The first output end of the address information detection module 25 is connected to the first input end of the combination logic unit 262, and outputs the fuse address detection information Fuse_ADD to the combination logic unit 262; and the second output end of the address information detection module 25 is connected to the fuse array circuit, and outputs the fuse address control signal Con_add to the fuse array circuit.

[0050] Further, the trimming current generating unit comprises a fourth AND gate AND4 and a seventh NAND gate NAND7; the first input end of the fourth AND gate AND4 receives a fuse address selection signal; the second input end of the fourth AND gate AND4 receives a trimming start control signal; the output end of the fourth AND gate AND4 outputs a second trimming large current control signal Con2_trim; the first input end of the seventh NAND gate NAND7 receives the trimming start control signal; the second input end of the seventh NAND gate NAND7 receives a count end signal Con1 output by the count end detection unit 212; the output end of the seventh NAND gate NAND7 outputs a first trimming large current control signal Con1_trim; the fuse array circuit comprises an eighth NAND gate 13 and a first PMOS transistor PM1; the first trimming large current control signal Con1_trim is input into the eighth NAND gate 13 after being inverted at the first input end of the eighth NAND gate 13; the second trimming large current control signal Con2_trim is input into the second input end of the eighth NAND gate 13; the output end of the eighth NAND gate 13 outputs a fuse trimming operation control signal Trim_sel; the gate of the first PMOS transistor PM1 is connected to the output end of the eighth NAND gate 13, the source of the first PMOS transistor PM1 is connected to a power supply voltage VIN, and the drain of the first PMOS transistor PM1 is connected to the fuse unit module.

[0051] Specifically, when the first PMOS transistor PM1 is turned on, the fuse address control signal Con_add is at a high level, corresponding NMOS transistors are turned on, the power supply voltage VIN is applied to the corresponding fuses through the first PMOS transistor PM1, and a trimming large current Itrim is formed to perform a fuse blowing operation.

[0052] Further, the clock generating module 27 comprises a clock generating circuit 271, a third NAND gate NAND3, a fourth NAND gate NAND4, a sixth NAND gate NAND6 and a decoder 272; the clock generating circuit 271 is connected to the output end signal of the counter unit 211, and the output end of the clock generating circuit 271 is connected to the second input end of the fourth NAND gate NAND4; the first input end of the fourth NAND gate NAND4 is connected to the count end signal Con1, and the output end of the fourth NAND gate NAND4 is connected to the second input end of the sixth NAND gate NAND6; the first input end of the third NAND gate NAND3 is connected to the output end of the decoder 272, the second input end of the third NAND gate NAND3 is connected to the count end inverted signal Con2, and the output end of the third NAND gate NAND3 is connected to the first input end of the sixth NAND gate NAND6; the output end of the sixth NAND gate NAND6 is connected to the storage module 23; the input end of the decoder 272 is connected to the addressing unit, in the pre-trimming mode, the decoder 272 processes the pre-trimming address information formed by the addressing unit to form a decoding signal output to the third NAND gate NAND3, and the second internal clock signal is output to the storage module 23 after passing through the sixth NAND gate NAND6.

[0053] Specifically, the first output terminal of the addressing circuit 2161 is connected to the input terminal of the decoder 272.

[0054] Further, the data read-write module 22 comprises a first NAND gate NAND1, a second NAND gate NAND2 and a fifth NAND gate NAND5; the first input terminal of the first NAND gate NAND1 is connected to the fuse state output terminal of the fuse array circuit 1, the second input terminal of the first NAND gate NAND1 is connected to the count end signal Con1, and the output terminal of the first NAND gate NAND1 is connected to the first input terminal of the fifth NAND gate NAND5; the second input terminal of the second NAND gate NAND2 is connected to the output terminal of the inverter INV, the output terminal of the second NAND gate NAND2 is connected to the second input terminal of the fifth NAND gate NAND5, and the output terminal of the fifth NAND gate NAND5 is connected to the storage module 23; the first input terminal of the second NAND gate NAND2 is connected to the data stream unit, and in the pre-trimming mode, the pre-trimming data information Pre_trim DATA formed by the data stream unit is output to the first input terminal of the second NAND gate NAND2 and then output to the storage module 23 through the output terminal of the fifth NAND gate NAND5.

[0055] Specifically, the mode control module 21 comprises a third AND gate AND3. The first input terminal of the third AND gate AND3 is connected to the count end signal Con1, the second input terminal of the third AND gate AND3 is connected to the power-on end signal POK, and the output terminal of the third AND gate AND3 is connected to the input terminal of the calculator unit 211.

[0056] The first input terminal of the count end detection unit 212 is connected to the output terminal of the calculator unit 211, and the input terminal of the clock generation circuit 271 is connected to the output terminal of the calculator unit 211. The input terminal of the address information detection module 25 is connected to the output terminal of the calculator unit 211.

[0057] The second input terminal of the count end detection unit 212 is connected to the external clock signal SCL, the third input terminal of the count end detection unit 212 is connected to the power-on end signal POK, and the fourth input terminal of the count end detection unit 212 is connected to the reset signal RN of the count end detection unit, i.e. connected to the output terminal of the timing logic unit 263.

[0058] The first output terminal of the count end detection unit 212 outputs the count end signal Con1, and the count end inverted signal Con2 is output after being inverted by the inverter INV. The second output terminal of the count end detection unit 212 outputs the read fuse information operation signal Read_sel, i.e. connected to the gate of the second PMOS transistor. The third output terminal of the count end detection unit 212 is connected to the second input terminal of the seventh NAND gate NAND7.

[0059] Specifically, the first input end of the storage module 23 is connected to the output end of the fifth NAND gate NAND5, the second input end of the storage module 23 is connected to the output end of the sixth NAND gate NAND6, the signal output by the sixth NAND gate NAND6 becomes the clock signal CLK of the storage module 23, the first internal clock signal in the fuse state reading mode, and the second internal clock signal in the pre-adjustment mode. The third input end of the storage module 23 is connected to the power-on end signal POK.

[0060] Referring to Figure 4 The application also provides a programmable fuse adjustment method using the programmable fuse adjustment circuit, characterized in that the method comprises the following steps: step A1, initializing the programmable fuse adjustment circuit after power-on; step A2, the fuse programming control circuit obtains the external input signal about reading the fuse state information through the chip pin, controls to enter the fuse state reading mode, and reads the fuse state information from the fuse cell module; step A3, the fuse programming control circuit obtains the external input signal about pre-adjusting the fuse through the chip pin, controls to enter the pre-adjustment mode, performs parameter testing on the chip circuit, and determines the fuse to be adjusted according to the parameter testing result; step A4, the fuse programming control circuit obtains the external input signal about adjusting the fuse through the chip pin, controls to enter the formal adjustment mode, and performs the fuse adjustment operation on the fuse to be adjusted; and step A5, after the fuse adjustment operation is completed, the fuse in the end bit fuse module is burned out.

[0061] Specifically, the fuse state information represents the fuse on-off information.

[0062] As an embodiment of the application, the specific application principle is as follows.

[0063] The input end of the fuse programming control circuit is connected to the output end of the power-on reset module, the external pin 1 and the external pin 2, the output end of the power-on reset module, the external pin 1 and the external pin 2 respectively provide the power-on end signal POK, the clock signal SCL and the data signal SDA. Through the fuse programming control circuit of the application, the fuse state information of each bit of fuse can be read and any bit of fuse can be burned.

[0064] After the end of the power-on of the circuit, the fuse state information is read, and the analog module tests whether the chip circuit meets the requirements. If yes, the fuse in the end-position fuse module is burned out. As an embodiment of the present application, the end-position fuse module is the fuse cell module after the N fuse cell modules, i.e. the fuse of the last fuse cell module. If no, the pre-adjustment stage is entered. In the pre-adjustment stage, each fuse is pre-fused and tested by repeating the four steps of circuit initialization, data stream unit and addressing unit unlocking, input row data encoding (the data stream unit pre-adjustment data information obtained by the storage module) and input column data encoding (the first internal clock signal formed by the address information obtained by the addressing unit received by the storage module), until the test result meets the requirements, and then the formal adjustment is entered. The formal adjustment includes two parts of adjustment start control signal effective and fuse address scanning chain (i.e. fuse address detection information) effective. When the adjustment start control signal and the fuse address detection information are effective at the same time, the corresponding bit fuse can be burned out.

[0065] Referring to Figure 5 In step A1, during the period when the SCL pin keeps high level, the SDA pin inputs a falling edge to enter the initialization; during the period when the SCL pin keeps high level, the SDA pin inputs a rising edge to end the circuit state. After the circuit enters the initialization, the output signal of the system reset unit changes from low to high, at this time, the shift register and the read pulse detection unit can work normally.

[0066] After the input of the circuit initialization encoding, the shift register can output the serial data input by the SDA pin in parallel. The parallel output data can be used as the data information of the data stream circuit and the address information of the addressing circuit. The data stream circuit and the addressing circuit both have latches, therefore, when the above data information and address information are written into the data stream circuit and the addressing circuit respectively, the latches in the data stream circuit and the addressing circuit need to be unlocked first.

[0067] The latch unlocking process is as follows. After the input circuit is initialized, a set of specific unlocking codes is input to SDA, so that the read pulse detection unit outputs two non-overlapping first and second unlocking pulse signals C1 and C2. The first unlocking pulse signal C1 is input to the first AND gate AND1 and then to the data flow circuit. The first unlocking pulse signal C1 generated by the read pulse detection unit controls whether the data flow circuit can read the data information of the shift register. When the first unlocking pulse signal C1 is high, the data flow circuit can read the data information. At this time, the data flow circuit reads the eight-bit parallel data information, and then outputs and latches the eight-bit parallel data information until the next first unlocking pulse signal C1 appears and the data information is read again. The second unlocking pulse signal C2 is input to the second AND gate AND2 and then to the addressing circuit. The second unlocking pulse signal C2 generated by the read pulse detection unit controls whether the addressing circuit can read the data information of the shift register to obtain address information. When the second unlocking pulse signal C2 is high, the addressing circuit can read the data information of the shift register to obtain address information. At this time, the addressing circuit reads the data information of the shift register to obtain address information, and then outputs and latches the address information until the second unlocking pulse signal C2 appears and the address information is read again. This is the latch unlocking process.

[0068] The latch unlocking of the data flow circuit and the addressing circuit can read the external data signal SDA input from the chip pin. The external data signal SDA is output in parallel through the shift register and then input to the data flow circuit and the addressing circuit, serving as the data information of the data flow circuit (as the fuse row information) and the address signal of the addressing circuit (as the fuse column information).

[0069] The overall trimming timing diagram is shown in Figure 6 and includes three parts: reading fuse information, pre-trimming, and formal trimming.

[0070] In the fuse state reading mode, the counter unit starts to work after the power-up is finished, at this time, the count end signal Conl is high level and the count end inverse signal Con2 is low level. After the count end is detected, the count end signal Conl changes from high to low, so that the RESET signal of the counter unit is invalid, thereby ending the counting. When the counter unit is working, the first NAND gate NANDl can read the fuse state information Fuse_DATA, and then the fuse state information Fuse_DATA is used as the data information of the storage module. At the same time, the output of the counter unit is given to the clock generating circuit 271, which is internally composed of a decoder and a combination logic circuit, to generate the first internal clock signal in the fuse information reading mode. At this time, the fourth NAND gate NAND4 can read the first internal clock signal, and then the first internal clock signal is used as the clock signal CLK of the storage module. When the data information and the clock information of the storage module are valid at the same time, a bit latch can be uniquely determined, the data information is transmitted to the latch of the storage module and is latched, and then the fuse state information Fuse_DATA can be read into the simulation module. After the counter unit stops working, the data information and the clock signal CLK of the storage module are invalid, the fuse information reading is ended, and the fuse state reading mode is ended.

[0071] In the pre-adjustment mode, when the fuse is pre-adjusted, the counter unit has stopped working, so the count end signal Conl is low level and the count end inverse signal Con2 is high level.

[0072] After the data information (fuse row information) of the data flow circuit is processed by the data flow, the pre-adjustment data information is obtained. At this time, the second NAND gate NAND2 can read the pre-adjustment data information, and then the pre-adjustment data information is used as the data information of the storage module. The second internal clock signal obtained by processing the address information latched by the addressing circuit and then processing by the decoder is read by the third NAND gate NAND3, and then the second internal clock signal is used as the clock signal CLK of the storage module. When the fuse row and column information are valid at the same time, that is, when the data information and the clock signal CLK of the memory unit are valid at the same time, a bit latch can be uniquely determined, the data information is transmitted to the latch and is latched, the pre-adjustment of the fuse is completed, and then the information (pre-adjustment data information) is given to the simulation module. Finally, whether the parameters meet the requirements after the pre-adjustment of the fuse is tested. If the parameters do not meet the requirements, the process is repeated until the parameters meet the requirements, and the pre-adjustment is ended.

[0073] In the formal adjustment mode, the counter starts to work again, so the count end signal Conl is high level and the count end inverse signal Con2 is low level.

[0074] After the pre-adjustment mode ends, the fuse that needs to be truly adjusted, i.e. the fuse to be adjusted, is determined and output by the storage module as an input signal of the combination logic unit, and the high effective signal represents that the fuse needs to be blown, and the low effective signal represents that the fuse does not need to be blown. During the formal adjustment, the SDA inputs a specific code (the first adjustment input data), which is processed by the data flow circuit and the addressing circuit, and then is input to the burn pulse detection unit, and a high-level control signal is output, which indicates that the formal adjustment is entered; then the SDA inputs another specific code (the second adjustment input data), which is processed by the data flow circuit and the addressing circuit, and then is input to the timing logic circuit, and a reset signal RN of the count end detection unit is generated, so that the count end signal Con1 outputs a high level, and the counter unit starts working again. At this time, the other output end of the count end detection unit, i.e. the second output end, and the output end of the burn pulse detection unit are processed by the seventh NAND gate NAND7, and then a low effective signal Con1_trim is output; at the same time, the output end signal of the counter unit is processed by the address information detection module, and then fuse address detection information Fuse_add is output. The fuse address detection information Fuse_add and the output of the storage module, i.e. the fuse address information to be adjusted, are processed by logic, and then a fuse bit that needs to be truly blown, i.e. a fuse address selection signal, is output. The signal is processed by the fourth AND gate AND4, and then Con2_trim is output. The high level of Con2_trim represents that the fuse bit is blown, and the low level of Con2_trim represents that the fuse bit is not blown. Con1_trim and Con2_trim are input to the fuse array circuit, and the fuse burn current is controlled. Finally, after the fuse adjustment is completed, a specific code is input through the chip pin (at this time, the external data signal is the end bit fuse adjustment input data), and the end bit fuse is blown. After the fuse bit is blown, the chip circuit cannot enter the adjustment mode again.

[0075] The above merely describes the preferred embodiments of the present application, and does not limit the embodiments and protection scope of the present application. It should be recognized by those skilled in the art that any equivalent replacement and obvious change based on the content of the present application should be included in the protection scope of the present application.

Claims

1. A programmable fuse trimming circuit, characterized in that, include: A fuse array circuit includes multiple fuse unit modules and an end-position fuse module, each of the fuse unit modules including a fuse; A fuse programming control circuit is connected to the fuse array circuit and receives external input signals through chip pins. It is used to: enter a fuse status reading mode, a pre-adjustment mode, and a formal adjustment mode based on the external input signals; read fuse status information from the fuse unit modules in the fuse status reading mode; perform pre-adjustment on the fuses in the fuse unit modules in the pre-adjustment mode; perform fuse adjustment operations on the corresponding fuse unit modules in the formal adjustment mode; and burn the fuse in the end-position fuse module after the fuse adjustment operation is completed. The fuse programming control circuit includes a mode control module, a data read / write module, a storage module, an analog module, an address information detection module, and a programming module; the mode control module is connected to the data read / write module, the address information detection module, and the programming module respectively; the data read / write module is connected to the storage module; the storage module is connected to the analog module and the programming module respectively; and the address information detection module is connected to the programming module. The programmable fuse adjustment circuit also includes a clock generation module, and the mode control module includes a counter unit and a counting end detection unit. In the fuse status reading mode, the counter unit starts working, and the counting end detection unit is used to: detect the counting status of the counter unit according to the output signal of the counter unit, and output the counting end signal and the fuse information reading operation signal according to the counting status detection result; In the fuse status reading mode, the address information detection module generates a fuse address control signal based on the output signal of the counter unit, the data read / write module reads the fuse status information of the fuse unit module based on the count end signal, and the clock generation module generates a first internal clock signal based on the output signal of the counter unit. The storage module latches the fuse status information read by the data read / write module according to the first internal clock signal.

2. The programmable fuse trimming circuit as described in claim 1, characterized in that, The mode control module receives external input signals through the chip pins and controls the entry into fuse status reading mode, pre-adjustment mode and formal adjustment mode according to the external input signals. The address information detection module is used to generate a fuse address control signal in the fuse status reading mode and the formal adjustment mode and output it to the fuse unit module for conduction operation. The data read / write module is used to: read the fuse status information of the fuse unit module in the fuse status reading mode and store it in the storage module; and read the pre-adjustment data information in the pre-adjustment mode and store it in the storage module. The simulation module is used to: receive the fuse status information from the storage module, and perform parameter testing according to the pre-troubleshooting data information and the fuse status information in the pre-troubleshooting mode, obtain the parameter test results, determine the fuse to be repaired according to the parameter test results, and the storage module latches the address information of the fuse to be repaired. The programming module is used to: generate a programming current control signal output according to the address information of the fuse to be tuned in the storage module in the formal tuning mode; The fuse array circuit performs adjustment operations on the fuse to be adjusted according to the adjustment current control signal and the fuse address control signal.

3. The programmable fuse trimming circuit as described in claim 2, characterized in that, The fuse array circuit further includes a second PMOS transistor, and each fuse unit module further includes an NMOS transistor; The source of the second PMOS transistor is connected to the power supply voltage, the drain of the second PMOS transistor is connected to the first end of the fuse, and the gate of the second PMOS transistor is connected to the fuse information read operation signal. In the fuse unit module, the source of the NMOS transistor is grounded, the gate of the NMOS transistor is connected to the fuse address control signal, and the drain of the NMOS transistor is connected to the second end of the fuse. The fuse array circuit is provided with a fuse status output terminal, which is connected to the first end of the fuse and is used to output fuse status information.

4. The programmable fuse trimming circuit as described in claim 3, characterized in that, The external input signal includes an external data signal; the mode control module further includes a shift register, a read pulse detection unit, a data stream unit, an addressing unit, and an inverter; the shift register is used to receive the external data signal and store it as data information in the shift register; The external data signal includes an unlock input signal, and the shift register stores the unlock input signal as unlock data; The read pulse detection unit is used to generate a first unlock pulse signal and a second unlock pulse signal that do not overlap based on the unlock data of the shift register; The data stream unit is used to unlock the latch according to the first unlock pulse signal; The addressing unit is used to unlock the latch according to the second unlocking pulse signal; The inverter inverts the count end signal output by the count end detection unit to form a count end inverted signal; In the pre-adjustment mode, the external data signal received by the shift register includes pre-adjustment input data. After entering the data stream unit, the pre-adjustment input data is processed by the data stream unit to form pre-adjustment data information. After entering the addressing unit, the pre-adjustment input data is processed by the addressing unit to form pre-adjustment address information. The data read / write module reads the pre-adjustment data information generated by the data stream unit according to the count end inversion signal; The clock generation module processes the pre-adjusted address information formed by the addressing unit to generate a second internal clock signal; The storage module latches the pre-adjustment data information read by the data read / write module according to the second internal clock signal.

5. The programmable fuse trimming circuit as described in claim 4, characterized in that, The programming module includes a programming pulse detection unit, a combinational logic unit, a timing logic unit, and a programming current generation unit; In the formal tuning mode, the external data signal received by the shift register includes a first tuning input data and a second tuning input data. The first tuning input data enters the data stream unit and is processed by the data stream unit to form a first tuning control signal; the first tuning input data enters the addressing unit and is processed by the addressing unit to form a second tuning control signal; the second tuning input data enters the data stream unit and is processed by the data stream unit to form a third tuning control signal; the second tuning input data enters the addressing unit and is processed by the addressing unit to form a fourth tuning control signal. In the formal adjustment mode, the programming pulse detection unit generates an adjustment start control signal according to the first adjustment control signal and the second adjustment control signal, the timing logic unit generates a reset signal for the count end detection unit according to the third adjustment control signal and the fourth adjustment control signal, and the count end detection unit starts the counter unit according to the reset signal of the count end detection unit. In the formal adjustment mode, the address information detection module generates a fuse address control signal to the fuse unit module based on the output signal of the counter unit, and generates fuse address detection information to the combinational logic unit. The combinational logic unit performs logic processing based on the fuse address detection information and the fuse address information to be repaired stored in the storage module, and outputs a fuse address selection signal. The adjustment current generating unit generates an adjustment current control signal based on the adjustment start control signal and the fuse address selection signal. The fuse array circuit performs fuse burning operation according to the burning current control signal.

6. The programmable fuse trimming circuit as described in claim 5, characterized in that, The current generating unit includes a fourth AND gate and a seventh NAND gate; The first input terminal of the fourth AND gate receives the fuse address selection signal; The second input terminal of the fourth AND gate receives the adjustment start control signal; The output terminal of the fourth AND gate outputs a second high-current control signal. The first input terminal of the seventh NAND gate receives the adjustment start control signal; The second input terminal of the seventh NAND gate receives the count end signal output by the count end detection unit; The output of the seventh NAND gate outputs the first high-current control signal. The fuse array circuit includes an eighth NAND gate and a first PMOS transistor; The first high-current control signal is inverted at the first input of the eighth NAND gate and then enters the eighth NAND gate. The second high-current control signal is input to the second input terminal of the eighth NAND gate; The output terminal of the eighth NAND gate outputs a fuse burning operation control signal; The gate of the first PMOS transistor is connected to the output terminal of the eighth NAND gate, the source of the first PMOS transistor is connected to the power supply voltage, and the drain of the first PMOS transistor is connected to the fuse unit module.

7. A programmable fuse trimming circuit as described in claim 5, characterized in that, The clock generation module includes a clock generation circuit, a third NAND gate, a fourth NAND gate, a sixth NAND gate, and a decoder; The clock generation circuit is connected to the output signal of the counter unit, and the output of the clock generation circuit is connected to the second input of the fourth NAND gate. The first input terminal of the fourth NAND gate is connected to the counting end signal, and the output terminal of the fourth NAND gate is connected to the second input terminal of the sixth NAND gate; The first input terminal of the third NAND gate is connected to the output terminal of the decoder, the second input terminal of the third NAND gate is connected to the counting end inverted signal, and the output terminal of the third NAND gate is connected to the first input terminal of the sixth NAND gate. The output of the sixth NAND gate is connected to the storage module; The input terminal of the decoder is connected to the addressing unit. In the pre-adjustment mode, the decoder processes the pre-adjustment address information formed by the addressing unit to form a decoded signal, which is output to the third NAND gate. After passing through the sixth NAND gate, the second internal clock signal is output to the storage module.

8. A programmable fuse trimming circuit as described in claim 4, characterized in that, The data read / write module includes a first NAND gate, a second NAND gate, and a fifth NAND gate; The first input terminal of the first NAND gate is connected to the fuse status output terminal of the fuse array circuit, the second input terminal of the first NAND gate is connected to the counting end signal, and the output terminal of the first NAND gate is connected to the first input terminal of the fifth NAND gate. The second input terminal of the second NAND gate is connected to the output terminal of the inverter, the output terminal of the second NAND gate is connected to the second input terminal of the fifth NAND gate, and the output terminal of the fifth NAND gate is connected to the storage module. The first input terminal of the second NAND gate is connected to the data stream unit. In the pre-adjustment mode, the pre-adjustment data information generated by the data stream unit is output to the first input terminal of the second NAND gate, and then to the storage module via the output terminal of the fifth NAND gate.

9. A method for adjusting a programmable fuse, characterized in that, The programmable fuse trimming circuit as described in any one of claims 1-8 is characterized by comprising: Step A1: Power on and initialize the programmable fuse trimming circuit; Step A2: The fuse programming control circuit obtains an external input signal about reading fuse status information through the chip pin, controls the entry into fuse status reading mode, and reads fuse status information from the fuse unit module; Step A3: The fuse programming control circuit obtains external input signals about the pre-tune fuse through the chip pins, controls the entry into the pre-tune mode, performs parameter testing on the chip circuit, and determines the fuse to be repaired based on the parameter test results. Step A4: The fuse programming control circuit obtains external input signals about the trimmed fuse through the chip pins, controls the entry into the formal trimming mode, and performs fuse trimming operation on the fuse to be trimmed. Step A5: After the fuse adjustment operation is completed, burn the fuse in the end position fuse module.

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