Transistor and preparation method thereof
By removing impurities generated by the reaction of the first etching gas and the etching barrier layer during the etching process, and using different etching gases under different etching conditions, the problem of poor etching uniformity is solved and the appearance and electrical yield of the transistor is improved.
Patent Information
- Application Number
- CN202411947360.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-05-13
AI Technical Summary
During the etching process, impurities are generated due to the reaction of CF4 gas with the etching barrier layer, resulting in poor etching uniformity, which affects the appearance and electrical yield of the transistor.
The second dielectric layer is patterned by using the first etching gas to remove impurities generated by the reaction of the first etching gas and the etching barrier layer, and subjecting each film layer to targeted treatment with different etching gases under different etching conditions to form an ohmic contact groove.
Improves the uniformity of etching, enhances the appearance and electrical yield of the transistor, and saves the use of photoresist.
Smart Images
Figure CN119993836A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of power electronic devices, and in particular to a transistor and a method for preparing the same. Background Art
[0002] A transistor is a semiconductor device.
[0003] The related art provides a transistor, including a buffer layer, a channel layer, a barrier layer, a first dielectric layer, an etch barrier layer, and a second dielectric layer. The buffer layer, the channel layer, the barrier layer, the first dielectric layer, the etch barrier layer, and the second dielectric layer are stacked in sequence, and an ohmic contact groove is formed by etching the second dielectric layer, the etch barrier layer, the first dielectric layer, the barrier layer, and the channel layer.
[0004] In the related art, multiple etchings are performed on the transistor. During the etching process, the reaction of CF4 gas with the etching barrier layer will precipitate impurities, causing the next etching to slow down or terminate, resulting in poor etching uniformity, and ultimately affecting the appearance and electrical yield of the transistor. Summary of the invention
[0005] The embodiment of the present disclosure provides a transistor and a method for manufacturing the same, which ensures uniformity of etching and improves the appearance and electrical yield of the transistor. The technical solution is as follows:
[0006] A method for manufacturing a transistor, the method comprising:
[0007] A buffer layer, a channel layer, a barrier layer, a first dielectric layer, an etching stop layer and a second dielectric layer are sequentially formed;
[0008] Under a first etching condition, patterning the second dielectric layer using a first etching gas;
[0009] removing impurities generated by the reaction between the first etching gas and the etching stop layer during the patterning process of the second dielectric layer;
[0010] Under the second etching condition, patterning the etching stop layer using a second etching gas;
[0011] Under a third etching condition, patterning the first dielectric layer using the first etching gas;
[0012] Under the fourth etching condition, the second dielectric layer is used as a hard mask, and the second etching gas is used to perform patterning on the channel layer and the barrier layer to form an ohmic contact groove.
[0013] Optionally, the first dielectric layer is a MOSiN layer with a thickness of 50-60 nm, and the second dielectric layer includes a stacked MOSiN sublayer with a thickness of 4-6 nm and a LPSiN sublayer with a thickness of 250-350 nm.
[0014] Optionally, the first etching gas includes: CF4 and O2;
[0015] The first etching condition includes:
[0016] The CF4 flow rate is 40-60 sccm, the O2 flow rate is 20-50 sccm, the pressure is 2-5 mT, the source power is 140-160 W, the bias power is 70-90 W, and the etching time is 390-410 S.
[0017] Optionally, removing impurities generated by the reaction between the first etching gas and the etching stop layer during the patterning process of the second dielectric layer includes:
[0018] The transistor is immersed in a solution of HCl and H2O in a ratio of 1:1 to 3:1 for 4 to 6 minutes;
[0019] After soaking, the transistor is rinsed and dried.
[0020] Optionally, the second etching gas includes Cl2 and BCl3;
[0021] The second etching condition includes:
[0022] The Cl2 flow rate is 3-10 sccm, the BCl3 flow rate is 30-40 sccm, the pressure is 2-5 mT, the source power is 70-90 W, the bias power is 5-15 W, and the etching time is 90-110 S.
[0023] Optionally, the first etching gas includes: CF4 and O2;
[0024] The third etching condition includes:
[0025] The CF4 flow rate is 40-60 sccm, the O2 flow rate is 20-50 sccm, the pressure is 2-5 mT, the source power is 140-160 W, the bias power is 70-90 W, and the etching time is 60-80 S.
[0026] Optionally, the second etching gas includes Cl2 and BCl3;
[0027] The fourth etching condition includes:
[0028] The Cl2 flow rate is 3-10 sccm, the BCl3 flow rate is 30-40 sccm, the pressure is 2-5 mT, the source power is 70-90 W, the bias power is 5-15 W, and the etching time is 520-540 S.
[0029] Optionally, the etching stop layer is an Al2O3 layer with a thickness of 1 to 5 nm.
[0030] Optionally, the method further comprises:
[0031] Coating a layer of photoresist on the surface of the second dielectric layer;
[0032] Using a mask plate to block and expose the photoresist;
[0033] The exposed photoresist is developed to form a photoresist mask.
[0034] Optionally, the transistor is manufactured using any of the methods described above.
[0035] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0036] In the disclosed embodiment, by coordinating the first etching gas and the second etching gas under the first etching condition, the second etching condition, the third etching condition and the fourth etching condition, different film layers of the transistor are patterned to form ohmic contact grooves that can be used for the source and drain. The above-mentioned patterning process is more targeted at etching each film layer, which can improve the etching efficiency. At the same time, in the process of patterning the second dielectric layer, the first etching gas and the etching barrier layer react to produce impurities. By removing the above-mentioned impurities, the above-mentioned impurities are prevented from depositing and affecting the subsequent patterning steps, and the etching caused by impurities is prevented from slowing down or stopping the etching, thereby improving the etching uniformity, and thus improving the appearance and electrical yield of the transistor. In addition, the second dielectric layer is used as a hard mask to pattern the channel layer and the barrier layer. On the one hand, it can save the deposition, exposure, development and cleaning steps of the photoresist, and on the other hand, it can better perform the etching of the channel layer and the barrier layer to form an ohmic contact groove. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0038] Figure 1 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure;
[0039] Figure 2 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure;
[0040] Figure 3 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0041] Figure 4 This is a partial enlarged view of the epitaxial wafer after etching is completed.
[0042] The reference numerals are as follows:
[0043] 10: epitaxial structure;
[0044] 100: substrate; 101: buffer layer; 102: channel layer; 103: barrier layer; 104: first dielectric layer; 105: etching stop layer; 106: second dielectric layer;
[0045] 1061: MOSiN sublayer; 1062: LPSiN sublayer;
[0046] 201: Ohmic contact groove;
[0047] A: The angle between the first dielectric layer and the substrate surface after etching; B: The angle between the channel layer and the barrier layer and the substrate surface. DETAILED DESCRIPTION
[0048] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0049] Figure 1 is a flow chart of a transistor manufacturing method provided by an embodiment of the present disclosure. Figure 1 The method steps include:
[0050] S11, sequentially fabricating a buffer layer, a channel layer, a barrier layer, a first dielectric layer, an etching stop layer and a second dielectric layer.
[0051] Among them, the buffer layer can be a GaN buffer layer, the channel layer can be a GaN channel layer, the barrier layer can be an AlGaN barrier layer, the first dielectric layer can be a MOSiN layer with a thickness of 50 to 60 nm, the etch stop layer can be an Al2O3 layer with a thickness of 1 to 5 nm, and the second dielectric layer includes a stacked MOSiN sublayer with a thickness of 4 to 6 nm and a LPSiN sublayer with a thickness of 250 to 350 nm.
[0052] Among them, MOSiN refers to a SiN layer grown by a Metal-Organic Chemical Vapor Deposition (MOCVD) process, and LPSiN refers to a SiN layer grown by a Low Pressure Chemical Vapor Deposition (LPCVD) process.
[0053] S12, under a first etching condition, using a first etching gas to perform patterning on the second dielectric layer.
[0054] S13, removing impurities generated by the reaction between the first etching gas and the etching stop layer during the patterning process of the second dielectric layer.
[0055] S14, under a second etching condition, using a second etching gas to perform patterning on the etching stop layer.
[0056] S15. Under a third etching condition, the first etching gas is used to perform patterning on the first dielectric layer.
[0057] S16. Under the fourth etching condition, the second dielectric layer is used as a hard mask, and the second etching gas is used to perform patterning on the channel layer and the barrier layer to form an ohmic contact groove.
[0058] In the disclosed embodiment, the first etching condition, the second etching condition, the third etching condition and the fourth etching condition are different. The first etching gas is different from the second etching gas. This design is more targeted at etching each film layer and can improve etching efficiency.
[0059] In other embodiments, the first etching condition, the second etching condition, the third etching condition and the fourth etching condition may also be partially or completely the same. The first etching gas is the same as the second etching gas.
[0060] The ohmic contact groove is formed by etching four times in steps S12, S14 to S16, that is, each etching completes a section of the groove; the number of the grooves is two, corresponding to the source and the drain respectively.
[0061] In the disclosed embodiment, by coordinating the first etching gas and the second etching gas under the first etching condition, the second etching condition, the third etching condition and the fourth etching condition, different film layers of the transistor are patterned to form ohmic contact grooves that can be used for the source and drain. The above-mentioned patterning process is more targeted at etching each film layer, which can improve the etching efficiency. At the same time, in the process of patterning the second dielectric layer, the first etching gas and the etching barrier layer react to produce impurities. By removing the above-mentioned impurities, the above-mentioned impurities are prevented from depositing and affecting the subsequent patterning steps, and the etching caused by impurities is prevented from slowing down or stopping the etching, thereby improving the etching uniformity, and thus improving the appearance and electrical yield of the transistor. In addition, the second dielectric layer is used as a hard mask to pattern the channel layer and the barrier layer. On the one hand, it can save the deposition, exposure, development and cleaning steps of the photoresist, and on the other hand, it can better perform the etching of the channel layer and the barrier layer to form an ohmic contact groove.
[0062] Figure 2 is a flow chart of another transistor manufacturing method provided by an embodiment of the present disclosure. Figure 2 The method steps include:
[0063] S21. Forming a buffer layer, a channel layer, and a barrier layer in sequence on the substrate to form an epitaxial structure.
[0064] The substrate may be any one of a sapphire substrate, a Si substrate, a SiC substrate and the like.
[0065] Exemplarily, the substrate is a Si substrate.
[0066] In one example, step S21 includes:
[0067] The first step is to form a buffer layer on the substrate.
[0068] In the embodiment of the present disclosure, the buffer layer may be a buffer layer grown by MOCVD.
[0069] In the embodiment of the present disclosure, the buffer layer may be a GaN buffer layer.
[0070] In the second step, a channel layer is formed on the buffer layer.
[0071] In the embodiment of the present disclosure, the channel layer may be a channel layer grown by MOCVD.
[0072] In the embodiment of the present disclosure, the channel layer may be a GaN channel layer.
[0073] The third step is to form a barrier layer on the channel layer.
[0074] In the embodiment of the present disclosure, the barrier layer may be a barrier layer grown by MOCVD.
[0075] In the embodiment of the present disclosure, the barrier layer may be an AlGaN barrier layer, and the thickness may be 20 to 50 nm.
[0076] S22, sequentially fabricating a first dielectric layer, an etching stop layer, and a second dielectric layer on the epitaxial structure to form an epitaxial wafer.
[0077] In one example, step S22 includes:
[0078] In the first step, a first dielectric layer is formed on the barrier layer.
[0079] In the embodiment of the present disclosure, the first dielectric layer may be a first dielectric layer grown by MOCVD.
[0080] In the disclosed embodiment, the first dielectric layer may be a MOSiN layer with a thickness of 50 to 60 nm. The MOSiN layer as the first dielectric layer may be used as a gate dielectric to serve as a back-end gate field plate. The first dielectric layer may be of the above thickness so that it is not too thin to affect the protective effect on the epitaxial structure, nor too thick to cause the overall thickness of the transistor.
[0081] Exemplarily, the first dielectric layer is a MOSiN layer with a thickness of 55 nm.
[0082] The second step is to form an etching stop layer on the first dielectric layer.
[0083] In the embodiment of the present disclosure, the etch stop layer may be an etch stop layer grown by MOCVD.
[0084] In the embodiment of the present disclosure, the etch barrier layer can be an Al2O3 layer with a thickness of 1 to 5 nm. The Al2O3 layer is corrosion-resistant and can be used as an etch barrier layer for the gate. It has no blocking effect during the etching of the source and drain grooves and will increase the difficulty of etching. The etch barrier layer using the above thickness will not be too thin to fail to play a blocking role during the etching process, causing over-etching, nor will it be too thick to cause the transistor as a whole to be too thick.
[0085] Exemplarily, the etching stop layer is an Al2O3 layer with a thickness of 3 nm.
[0086] The third step is to form a second dielectric layer on the etching stop layer.
[0087] In the disclosed embodiment, the second dielectric layer includes a stacked MOSiN sublayer with a thickness of 4-6 nm and a LPSiN sublayer with a thickness of 250-350 nm, wherein the MOSiN sublayer is grown by MOCVD and the LPSiN sublayer is grown by LPCVD.
[0088] Among them, the MOSiN sublayer can prevent oxidation of the etch barrier layer, and the LPSiN sublayer can serve for the back-end gate field plate; the MOSiN sublayer and the LPSiN sublayer adopt the above thicknesses so that they are not too thin to affect the protection effect on the epitaxial structure, nor too thick to cause the overall thickness of the transistor.
[0089] In other examples, the MOSiN sublayer may not exist on the Al2O3.
[0090] Exemplarily, the second dielectric layer includes a stacked MOSiN sublayer with a thickness of 5 nm and a LPSiN sublayer with a thickness of 300 nm.
[0091] S23, making a photoresist mask on the second dielectric layer.
[0092] In one example, step S23 includes:
[0093] In the first step, a layer of photoresist is coated on the surface of the second dielectric layer.
[0094] The second step is to use a mask to block and expose the photoresist.
[0095] The third step is to develop the exposed photoresist to form a photoresist mask with a specific shape.
[0096] In the disclosed embodiment, a photoresist is fabricated to form a mask layer for use as a mask in subsequent etching steps.
[0097] It should be noted that subsequent etchings can share a mask and finally remove the photoresist mask before step S28; or after each etching step is completed, the photoresist mask can be removed and then remade (except for step S28 using a hard mask).
[0098] S24, under the first etching condition, using the first etching gas to over-etch the second dielectric layer.
[0099] In the disclosed embodiment, inductively coupled plasma etching (ICP) is used to over-etch the second dielectric layer.
[0100] In the embodiment of the present disclosure, the first etching gas includes: CF4 and O2.
[0101] In the embodiment of the present disclosure, the first etching condition includes:
[0102] The CF4 flow rate can be 40-60 sccm, the O2 flow rate can be 20-50 sccm, the pressure can be 2-5 mT, the source power can be 140-160 W, the bias power can be 70-90 W, and the etching time can be 390-410 S.
[0103] Among them, source power refers to the power source power applied to the upper electrode in the plasma etcher, and bias power is applied to the lower electrode, which is mainly used to adjust the bombardment capacity.
[0104] In the embodiment of the present disclosure, the etching conditions described above are adopted to allow CF4 to react quickly with the dielectric layer, and the addition of O2 can adjust the etching angle and provide better uniformity of the overall etching.
[0105] Exemplarily, the CF4 flow rate is 50 sccm, the O2 flow rate is 35 sccm, the pressure is 3.5 mT, the source power is 150 W, the bias power is 80 W, and the etching time is 400 S.
[0106] S25, removing impurities generated by the reaction between the first etching gas and the etching stop layer during the patterning process of the second dielectric layer.
[0107] In one example, step S25 includes:
[0108] In the first step, the transistor is immersed in a solution of HCl and H2O in a mixing ratio of 1:1 to 3:1 for 4 to 6 minutes.
[0109] Exemplarily, the transistor is immersed in a solution of HCl and H2O in a mixing ratio of 1:1 for 5 minutes.
[0110] The second step is to rinse and dry the transistor after soaking.
[0111] In the disclosed embodiment, the epitaxial wafer can be cleaned to remove the byproducts containing AlF3 or ALF generated by the reaction of CF4 and Al2O3 etching barrier layer after the second dielectric layer is etched, so as to improve the etching uniformity.
[0112] S26, under the second etching condition, using the second etching gas to etch the etching stop layer.
[0113] In the embodiment of the present disclosure, ICP is used to etch the etch stop layer.
[0114] In the embodiment of the present disclosure, the second etching gas includes Cl2 and BCl3.
[0115] In the embodiment of the present disclosure, the second etching condition includes:
[0116] The Cl2 flow rate can be 3-10 sccm, the BCl3 flow rate can be 30-40 sccm, the pressure can be 2-5 mT, the source power can be 70-90 W, the bias power can be 5-15 W, and the etching time can be 90-110 S.
[0117] In the embodiment of the present disclosure, under the above conditions, the Cl element can react quickly with the Al2O3 etch barrier layer, thereby accelerating the etching rate of the etch barrier layer and achieving better etching uniformity.
[0118] Exemplarily, the Cl2 flow rate is 5 sccm, the BCl3 flow rate is 35 sccm, the pressure is 3 mT, the source power is 80 W, the bias power is 10 W, and the etching time is 100 S.
[0119] S27. Under a third etching condition, the first etching gas is used to etch the first dielectric layer.
[0120] In the embodiment of the present disclosure, ICP is used to etch the first dielectric layer.
[0121] In the embodiment of the present disclosure, the first etching gas includes: CF4 and O2.
[0122] In the embodiment of the present disclosure, the third etching condition includes:
[0123] The CF4 flow rate can be 40-60 sccm, the O2 flow rate can be 20-50 sccm, the pressure can be 2-5 mT, the source power can be 140-160 W, the bias power can be 70-90 W, and the etching time can be 60-80 S.
[0124] In the embodiment of the present disclosure, under the above conditions, CF4 can react quickly with the first dielectric layer, the addition of O2 can adjust the etching angle, and the overall etching uniformity is better.
[0125] Exemplarily, the CF4 flow rate is 50 sccm, the O2 flow rate is 35 sccm, the pressure is 3.5 mT, the source power is 150 W, the bias power is 80 W, and the etching time is 70 S.
[0126] S28. Under the fourth etching condition, the second dielectric layer is used as a hard mask, and the second etching gas is used to etch the channel layer and the barrier layer to form an ohmic contact groove.
[0127] In this step, the hard mask here is different from the photoresist mask (compared to the photoresist mask, the hard mask is harder). Using the second dielectric layer as the hard mask can save the steps of deposition, exposure, development and cleaning of the photoresist on the one hand, and on the other hand, it can better etch the channel layer and the barrier layer to form an ohmic contact groove.
[0128] In the embodiment of the present disclosure, ICP is used to etch the channel layer and the barrier layer to form an ohmic contact groove.
[0129] In the disclosed embodiment, the second etching gas includes Cl2 and BCl3;
[0130] In the embodiment of the present disclosure, the fourth etching condition includes:
[0131] The Cl2 flow rate can be 3-10 sccm, the BCl3 flow rate can be 30-40 sccm, the pressure can be 2-5 mT, the source power can be 70-90 W, the bias power can be 5-15 W, and the etching time can be 520-540 S.
[0132] In the embodiment of the present disclosure, the etching method described above can accelerate the etching rate of the channel layer and the barrier layer, and the etching uniformity is better.
[0133] Exemplarily, the Cl2 flow rate is 5 sccm, the BCl3 flow rate is 35 sccm, the pressure is 3 mT, the source power is 80 W, the bias power is 10 W, and the etching time is 530 S.
[0134] Optionally, the method may further include: manufacturing a source electrode and a drain electrode, wherein the source electrode and the drain electrode are connected to the channel layer through two ohmic contact grooves.
[0135] Optionally, the method further includes: manufacturing a gate, and the gate may be located on the second dielectric layer.
[0136] Figure 3 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 3 The transistor includes: an epitaxial structure 10 , a first dielectric layer 104 , an etching stop layer 105 and a second dielectric layer 106 .
[0137] Among them, the epitaxial structure 10 includes a buffer layer 101, a channel layer 102 and a barrier layer 103 stacked in sequence; a first dielectric layer 104, an etch stop layer 105 and a second dielectric layer 106 are stacked in sequence on the barrier layer 103, and an ohmic contact groove 201 is provided on the transistor, the ohmic contact groove 201 passes through the second dielectric layer 106, the etch stop layer 105, the first dielectric layer 104 and the barrier layer 103, and the bottom of the ohmic contact groove 201 is located in the channel layer 102.
[0138] In the embodiment of the present disclosure, the transistor further includes: a substrate 100 .
[0139] In the embodiment of the present disclosure, a buffer layer 101 , a channel layer 102 , a barrier layer 103 , a first dielectric layer 104 , an etch stop layer 105 , and a second dielectric layer 106 are sequentially stacked on a substrate 100 .
[0140] In the embodiment of the present disclosure, the substrate 100 may be any one of substrates such as a sapphire substrate, a Si substrate, and a SiC substrate, and the embodiment of the present disclosure does not limit the material of the substrate 100.
[0141] Exemplarily, the substrate 100 is a Si substrate. Si has good electrical conductivity and thermal conductivity, which can ensure that the chip has good heat dissipation. Si is also easy to process and has a low manufacturing cost.
[0142] In the embodiment of the present disclosure, the size of the substrate 100 may be 4 inches, 6 inches, 8 inches, or 12 inches.
[0143] Exemplarily, the size of substrate 100 is 4 inches.
[0144] Of course, in other embodiments, the transistor may not have a substrate, and the present disclosure is not limited to this.
[0145] In the embodiment of the present disclosure, the buffer layer 101 may be a GaN buffer layer.
[0146] In the embodiment of the present disclosure, the channel layer 102 may be a GaN channel layer.
[0147] In the embodiment of the present disclosure, the barrier layer 103 may be an AlGaN barrier layer, and the thickness may be 20-50 nm.
[0148] In the embodiment of the present disclosure, the thickness of the barrier layer 103 may be 20-50 nm.
[0149] Exemplarily, the thickness of the barrier layer 103 is 35 nm.
[0150] In the embodiment of the present disclosure, the first dielectric layer 104 can be a MOSiN layer with a thickness of 50 to 60 nm. The MOSiN layer as the first dielectric layer can be used as a gate dielectric to serve the back-end gate field plate. The first dielectric layer using the above thickness will not be too thin to affect the protection effect on the epitaxial structure, nor will it be too thick to cause the overall thickness of the transistor.
[0151] Exemplarily, the first dielectric layer 104 is a MOSiN layer with a thickness of 55 nm.
[0152] In the embodiment of the present disclosure, the etch barrier layer 105 can be an Al2O3 layer with a thickness of 1 to 5 nm. The Al2O3 layer is corrosion-resistant and can be used as an etch barrier layer for the gate. It has no blocking effect during the etching of the source and drain grooves and will increase the difficulty of etching. The etch barrier layer using the above thickness will not be too thin to fail to play a blocking role during the etching process, causing over-etching, nor will it be too thick to cause the transistor as a whole to be too thick.
[0153] Exemplarily, the etching stop layer 105 is an Al 2 O 3 layer with a thickness of 3 nm.
[0154] In the disclosed embodiment, the second dielectric layer 106 includes a stacked MOSiN sublayer 1061 with a thickness of 4 to 6 nm and a LPSiN sublayer 1062 with a thickness of 250 to 350 nm. The MOSiN sublayer can prevent oxidation of the etching barrier layer, and the LPSiN sublayer can serve as a back-end gate field plate; the MOSiN sublayer and the LPSiN sublayer adopt the above thicknesses so that they are not too thin to affect the protection effect on the epitaxial structure, nor too thick to cause the overall thickness of the transistor.
[0155] Exemplarily, the second dielectric layer 106 includes a stacked MOSiN sublayer 1061 with a thickness of 5 nm and a LPSiN sublayer 1062 with a thickness of 300 nm.
[0156] Figure 4 This is a partial enlarged picture of the epitaxial wafer after etching. Figure 4 As shown, the etched morphology of the epitaxial wafer is relatively smooth.
[0157] In the embodiments of the present disclosure, observation was performed using a transmission electron microscope (TEM).
[0158] In the embodiment of the present disclosure, the angle A between the first dielectric layer 104 and the surface of the substrate 100 after etching is 20.2°, and the angle B between the channel layer 102 and the barrier layer 103 and the surface of the substrate 100 is 35°. The etching morphology is relatively flat, and the etching uniformity is improved, thereby improving the appearance and electrical yield of the transistor.
[0159] During the transistor manufacturing process, Energy Dispersive X-ray spectroscopy (EDX) was used to verify that there were indeed AlF3 or ALF byproducts on the surface after CF4 came into contact with Al2O3. Therefore, dry etching and wet cleaning were combined. CF4 gas was used to dry-etch the upper dielectric layer until it came into contact with Al2O3, and then a wet solution (dilute HCl solution) was used to clean off the byproducts on the surface. Dry etching was then used to further clean the surface. The final etching morphology was smooth. For example, the angle A between the first dielectric layer and the substrate surface after etching was 20°, and the angle B between the channel layer and the barrier layer and the substrate surface was 35°.
[0160] The transistor manufactured by the embodiment of the present disclosure is suitable for normally-off and normally-on GaN HEMT devices, and is also suitable for etching AlN (1-5nm) and other Al-containing compounds.
[0161] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A method for preparing a transistor, characterized in that: The transistor preparation method comprises: A buffer layer, a channel layer, a barrier layer, a first dielectric layer, an etching stop layer and a second dielectric layer are sequentially formed; Under a first etching condition, patterning the second dielectric layer using a first etching gas; removing impurities generated by the reaction between the first etching gas and the etching stop layer during the patterning process of the second dielectric layer; Under the second etching condition, patterning the etching stop layer using a second etching gas; Under a third etching condition, patterning the first dielectric layer using the first etching gas; Under the fourth etching condition, the second dielectric layer is used as a hard mask, and the second etching gas is used to perform patterning on the channel layer and the barrier layer to form an ohmic contact groove.
2. The transistor manufacturing method according to claim 1, characterized in that: The first dielectric layer is a MOSiN layer with a thickness of 50-60 nm, and the second dielectric layer includes a stacked MOSiN sublayer with a thickness of 4-6 nm and a LPSiN sublayer with a thickness of 250-350 nm.
3. The transistor manufacturing method according to claim 1 or 2, characterized in that: The first etching gas includes: CF4 and O2; The first etching condition includes: The CF4 flow rate is 40-60 sccm, the O2 flow rate is 20-50 sccm, the pressure is 2-5 mT, the source power is 140-160 W, the bias power is 70-90 W, and the etching time is 390-410 S.
4. The transistor manufacturing method according to claim 1 or 2, characterized in that: Removing impurities generated by the reaction between the first etching gas and the etching stop layer during the patterning process of the second dielectric layer, comprising: The transistor is immersed in a solution of HCl and H2O in a mixing ratio of 1:1 to 3:1 for 4 to 6 minutes; After soaking, the transistor is rinsed and dried.
5. The transistor manufacturing method according to claim 1 or 2, characterized in that: The second etching gas includes Cl2 and BCl3; The second etching condition includes: The Cl2 flow rate is 3-10 sccm, the BCl3 flow rate is 30-40 sccm, the pressure is 2-5 mT, the source power is 70-90 W, the bias power is 5-15 W, and the etching time is 90-110 S.
6. The transistor manufacturing method according to claim 1 or 2, characterized in that: The first etching gas includes: CF4 and O2; The third etching condition includes: The CF4 flow rate is 40-60 sccm, the O2 flow rate is 20-50 sccm, the pressure is 2-5 mT, the source power is 140-160 W, the bias power is 70-90 W, and the etching time is 60-80 S.
7. The transistor manufacturing method according to claim 1 or 2, characterized in that: The second etching gas includes Cl2 and BCl3; The fourth etching condition includes: The Cl2 flow rate is 3-10 sccm, the BCl3 flow rate is 30-40 sccm, the pressure is 2-5 mT, the source power is 70-90 W, the bias power is 5-15 W, and the etching time is 520-540 S.
8. The transistor manufacturing method according to claim 1 or 2, characterized in that: The etching stop layer is an Al2O3 layer with a thickness of 1 to 5 nm.
9. The transistor manufacturing method according to claim 1 or 2, characterized in that: The method further comprises: Coating a layer of photoresist on the surface of the second dielectric layer; Using a mask plate to block and expose the photoresist; The exposed photoresist is developed to form a photoresist mask.
10. A transistor, characterized in that: The transistor is manufactured by the method according to any one of claims 1 to 9.