TGV Substrate Integrated Packaging Method and Packaging Structure

Abstract

A TGV substrate integrated packaging method and a packaging structure provided by the present application relate to the technical field of semiconductor packaging. The TGV substrate integrated packaging method includes: The first substrate is a glass substrate. The first substrate includes a first surface and a second surface which are oppositely arranged; a chip is mounted on the first surface, and a plastic package body covering the chip is formed. The second surface is ground and thinned. A first through hole corresponding to the position of the electrode on the chip is formed on the second surface. A first groove is formed on the second surface; the first groove communicates with the first through holes on different corresponding chips. A second through hole is formed on the second surface; the second through hole corresponds to the position of the first through hole and communicates with it; the second through hole extends at least axially to the first through hole to expose the electrode. A first metal layer is formed in the first through hole, the second through hole and the first groove; the first metal layer is electrically connected to the electrode. This method is beneficial to improving the packaging efficiency and quality and reducing the risk of glass substrate hidden cracks.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method and a packaging structure for integrated packaging of a TGV substrate. Background Art

[0002] TGV is an abbreviation for "Through Glass Via", which means perforating through glass. Due to the self - characteristic that the glass substrate is prone to cracking, in order to reduce the risk of chipping, the existing TGV glass substrate is usually relatively thick, which affects the overall packaging thickness. Moreover, due to the relatively thick thickness of the glass substrate, the perforations made thereon are deeper, and the depth - to - diameter ratio of the holes is relatively large, making it easy to generate voids when filling with metal, which affects the packaging quality. Summary of the Invention

[0003] The purpose of the present invention is to provide a method and a packaging structure for integrated packaging of a TGV substrate, which can reduce the packaging thickness of the glass substrate, reduce the risk of chipping of the glass substrate, and improve the packaging quality and reliability.

[0004] In a first aspect, the present invention provides a method for integrated packaging of a TGV substrate, including:

[0005] Providing a first substrate; the first substrate is a glass substrate; the first substrate includes a first surface and a second surface which are oppositely arranged; the first surface is mounted with a chip and a plastic package body covering the chip is formed;

[0006] Grinding and thinning the second surface of the first substrate;

[0007] Forming a first through - hole on the second surface; the position of the first through - hole corresponds to the position of the electrode on the chip;

[0008] Forming a first groove on the second surface; the first groove communicates with the first through - holes corresponding to different chips;

[0009] Forming a second through - hole on the second surface; the second through - hole corresponds to and communicates with the first through - hole; the second through - hole extends at least axially to the first through - hole to expose the electrode;

[0010] Forming a first metal layer in the first through - hole, the second through - hole and the first groove; the first metal layer is electrically connected to the electrode.

[0011] In an optional embodiment, the step of providing the first substrate includes:

[0012] A bonding layer is formed between the first substrate and the chip; wherein, a functional area is further provided on the side of the chip where the electrodes are provided, the bonding layer covers the surface of the side of the chip with the electrodes, and an opening is left at a position corresponding to the functional area.

[0013] In an alternative embodiment, in the step of forming the first through-hole on the second surface, the first through-hole penetrates through the first substrate;

[0014] In the step of forming the second through-hole on the second surface, the second through-hole penetrates through the bonding layer.

[0015] In an alternative embodiment, the step of forming the first through-hole on the second surface includes:

[0016] Irradiating a first area on the second surface with a first laser; the first area corresponds to the position of the electrodes;

[0017] Etching the first area to form the first through-hole;

[0018] The step of forming the first groove on the second surface includes:

[0019] Irradiating a second area on the second surface with a second laser; the second area is used to connect the first through-holes corresponding to different chips;

[0020] Etching the second area to form the first groove; the depth of the first groove is less than the depth of the first through-hole.

[0021] In an alternative embodiment, the step of irradiating the first area on the second surface with a first laser and etching the first area to form the first through-hole includes:

[0022] Irradiating the first area on the second surface with a first laser; etching the first area to form a prefabricated groove;

[0023] Irradiating the bottom of the prefabricated groove with a third laser; etching the bottom of the prefabricated groove to form a through-groove penetrating through the first substrate, and the diameter of the through-groove is smaller than the diameter of the prefabricated groove;

[0024] The through-groove and the prefabricated groove together form the first through-hole.

[0025] In an alternative embodiment, the step of forming the second through-hole on the second surface includes:

[0026] Removing the bonding layer corresponding to the electrodes by dry etching to form a second through-hole communicating with the first through-hole on the bonding layer.

[0027] In an alternative embodiment, the step of forming a first metal layer in the first through hole, the second through hole, and the first groove includes:

[0028] Forming a first metal layer integrally on the second surface, and filling the first metal layer into the first through hole, the second through hole, and the first groove;

[0029] Grinding the first metal layer to expose the second surface of the first substrate; wherein, the surfaces of the first metal layer in the first through hole, the second through hole, and the first groove are flush with the second surface respectively.

[0030] In an alternative embodiment, it further includes:

[0031] Mounting a second substrate on the second surface;

[0032] Opening a third through hole and a second groove in the second substrate;

[0033] Filling a second metal layer in the third through hole and the second groove; the second metal layer is electrically connected to the first metal layer.

[0034] In an alternative embodiment, it further includes:

[0035] Forming a solder mask layer covering the second surface; opening a first window in the solder mask layer;

[0036] Filling a third metal layer in the first window to form a solder pad; the solder pad is electrically connected to the first metal layer;

[0037] Forming bumps on the solder pad.

[0038] In a second aspect, the present invention provides a packaging structure prepared by using the TGV substrate integrated packaging method according to any one of the foregoing embodiments.

[0039] The beneficial effects of the TGV substrate integrated packaging method and the packaging structure provided by the embodiments of the present invention include:

[0040] First, form a plastic package on one side of the glass substrate, and then grind the glass substrate. During the grinding process, the plastic package can play a supporting and buffering role, and grinding the entire intact glass substrate can significantly reduce the risk of chipping. After grinding the glass substrate, form the first through-hole, the first groove, and the second through-hole, which can reduce the risk of chipping, thin the thickness of the glass substrate, and achieve ultra-thin packaging. The first through-hole formed in this way has a smaller depth-to-diameter ratio, better metal filling performance, is not prone to generating voids, and has a better bonding force between the metal and the glass substrate. Secondly, by opening the first groove on the glass substrate, the metal in the first groove is used for wiring of the circuit layer to achieve chip interconnection. Opening the first groove is beneficial to improving the bonding force between the metal and the glass substrate, preventing structural delamination, and improving the packaging quality. In addition, metal filling can be completed at one time in the first through-hole, the first groove, and the second through-hole, with higher process efficiency and better bonding force, which is beneficial to improving the packaging efficiency and packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0042] Figure 1 Schematic diagram of the structure for preparing the adhesive layer in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0043] Figure 2 Schematic diagram of the structure for separating the wafer into single chips in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0044] Figure 3 Schematic diagram of the structure for mounting the chip to the first substrate in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0045] Figure 4 Schematic diagram of the structure for forming the plastic package in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0046] Figure 5 Schematic diagram of the structure for forming the buffer groove in the plastic package in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0047] Figure 6 Schematic diagram of the structure for thinning the first substrate in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0048] Figure 7Schematic diagram of forming a first through hole and a first groove in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0049] Figure 8 Another schematic diagram of forming a first through hole in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0050] Figure 9 Schematic diagram of forming a second through hole in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0051] Figure 10 Schematic diagram of forming a first metal layer in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0052] Figure 11 Another schematic diagram of a chip in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0053] Figure 12 For Figure 11 Partial enlarged schematic diagram at position A in

[0054] Figure 13 Schematic diagram of forming a solder mask layer and bumps in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0055] Figure 14 Schematic diagram of forming multi-layer wiring in the TGV substrate integrated packaging method provided by the embodiment of the present invention;

[0056] Figure 15 Schematic diagram of forming double-sided mounting in the TGV substrate integrated packaging method provided by the embodiment of the present invention.

[0057] Icon: 110 - First substrate; 111 - First surface; 112 - Second surface; 113 - First through hole; 114 - Prefabricated groove; 115 - Through groove; 116 - First groove; 120 - Chip; 121 - Electrode; 1211 - Micro bump; 1213 - Metal bonding layer; 122 - Functional area; 130 - Adhesive layer; 131 - Opening; 133 - Second through hole; 140 - Wafer; 150 - Encapsulant; 151 - Buffer groove; 152 - Buffer block; 160 - First metal layer; 161 - Electrical connection post; 162 - Wiring layer; 170 - Solder mask layer; 171 - Pad; 172 - Bump; 180 - Second substrate; 181 - Second metal layer; 190 - Conductive post; 191 - Connection pad. Detailed implementation manners

[0058] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention generally described and illustrated in the drawings herein can be arranged and designed in a variety of different configurations.

[0059] Therefore, the detailed description of the embodiments of the present invention provided in the drawings below is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0060] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0061] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the inventive product is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0062] In addition, the terms "horizontal", "vertical", "overhanging", etc. do not mean that the components are required to be absolutely horizontal or overhanging, but may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but may be slightly inclined.

[0063] In the description of the present invention, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "installed", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0064] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0065] The TGV substrate integrated packaging method and packaging structure proposed in the embodiments of the present invention can realize the packaging of ultra-thin glass substrates, reduce the risk of hidden cracks in the glass substrate, and help improve the packaging quality and packaging efficiency.

[0066] The TGV substrate integrated packaging method generally includes the following packaging processes:

[0067] S1. Provide a first substrate 110, which is a glass substrate. The first substrate 110 includes a first surface 111 and a second surface 112 that are opposite to each other. A chip 120 is mounted on the first surface 111, and a plastic package 150 covering the chip 120 is formed.

[0068] S2, grinding and thinning the second surface 112 of the first substrate 110.

[0069] It can be understood that during the grinding process, the plastic encapsulation body 150 first formed in step S1 can play a supporting and buffering role, and the overall grinding of the complete glass substrate can greatly reduce the risk of cracking. After grinding and thinning, the packaging of ultra-thin glass substrates can be achieved, greatly reducing the packaging height. It is worth noting that if the glass substrate is perforated first and then ground, this method will greatly increase the risk of hidden cracks in the glass substrate. Since the local strength of the glass substrate is weakened after perforation, grinding the entire substrate will cause the glass substrate to break. Therefore, in this embodiment, the entire substrate is first ground and thinned before the subsequent perforation process. The overall grinding thickness can be flexibly set according to actual needs.

[0070] S3 , forming a first through hole 113 on the second surface 112 ; the position of the first through hole 113 corresponds to the position of the electrode 121 on the chip 120 .

[0071] S4, forming a first groove 116 on the second surface 112; the first groove 116 is connected to the first through hole 113 on the corresponding different chips 120. The first groove 116 is used to fill the first metal layer 160 as a wiring layer 162 to achieve electrical connection between different chips 120, that is, to achieve interconnection between the chips 120.

[0072] S5. Form a second through-hole 133 on the second surface 112; the second through-hole 133 corresponds to and communicates with the position of the first through-hole 113; the second through-hole 133 extends at least axially to the first through-hole 113 to expose the electrode 121. Optionally, the first through-hole 113 and the second through-hole 133 are coaxially arranged, and the first through-hole 113 and the second through-hole 133 are used to fill the first metal layer 160 as the electrical connection column 161. One end of the electrical connection column 161 is electrically connected to the electrode 121, and the other end is electrically connected to the wiring layer 162. That is, the electrical connection column 161 is used to realize the electrical connection between the electrode 121 and the wiring layer 162 on the chip 120.

[0073] S6. Form a first metal layer 160 in the first through-hole 113, the second through-hole 133 and the first groove 116; the first metal layer 160 is electrically connected to the electrode 121. In this embodiment, since the metal filling can be completed at one time in the first through-hole 113, the first groove 116 and the second through-hole 133, that is, the electrical connection column 161 and the wiring layer 162 can be formed at one time, improving the process efficiency and the bonding force, and the electrical connection is more reliable.

[0074] Moreover, after grinding the glass substrate, the first through-hole 113 and the second through-hole 133 are formed. The first through-hole 113 and the second through-hole 133 have a smaller depth-to-diameter ratio, which is beneficial to improving the density of subsequent metal filling, reducing the risk of voids formed by insufficient filling, and further improving the bonding force between the first metal layer 160 and the first substrate 110.

[0075] S7. Form a solder mask layer 170 covering the second surface 112. The solder mask layer 170 plays a protective role for the second surface 112 of the glass substrate and the wiring layer 162, etc. Open a first window in the solder mask layer 170, and fill the third metal layer in the first window to form a solder pad 171. The solder pad 171 is electrically connected to the first metal layer 160. Form a bump 172 on the solder pad 171. Complete the packaging process.

[0076] Optionally, in step S1, the step of providing the first substrate 110 includes:

[0077] Combined with Figure 1 , form an adhesive layer 130 between the first substrate 110 and the chip 120; wherein, the chip 120 is further provided with a functional area 122 on the side with the electrode 121. The adhesive layer 130 covers the surface of the chip 120 on the side with the electrode 121 and leaves an opening 131 at the position corresponding to the functional area 122. The chip 120 can be a radio frequency chip 120, a filter chip 120 or other types of chips 120, which are not specifically limited here.

[0078] Optionally, an adhesive layer 130 is coated on the wafer 140, and the adhesive layer 130 is made of a photosensitive material. An opening 131 exposing the functional area 122 is formed on the adhesive layer 130 through a photolithography process. It can be understood that, except for the functional area 122, other parts of the surface of the chip 120 where the functional area 122 is provided are covered by the adhesive layer 130, and the electrodes 121 of the chip 120 are also covered by the adhesive layer 130.

[0079] Combined with Figure 2 , techniques such as cutting the wafer 140 with a metal blade or laser cutting are used to separate the entire wafer 140 into single chips 120. Each chip 120 is covered with an adhesive layer 130.

[0080] Combined with Figure 3 , the side of the single chip 120 covered with the adhesive layer 130 is mounted on the first substrate 110. The adhesive layer 130 can fix the chip 120 on the first substrate 110, and the adhesive layer 130 can isolate and protect the adjacent electrodes 121. The adhesive layer 130 is made of an insulating material. On the same first substrate 110, chips 120 of different types, models, and size specifications can be mounted, and multiple chips 120 can be integrated and packaged together, making the functions of the packaged product more abundant. Figure 3 The situation where 3 different chips 120 are mounted on the first substrate 110 is shown in

[0081] It should be noted that the process of coating the adhesive layer 130 on the surface of the wafer 140 not only facilitates subsequent chip mounting but also improves the problem in traditional technologies that due to the large size of the chip 120, the bottom filling adhesive has poor filling performance and it is difficult to enter between the electrodes 121 of the chip 120. The packaging process of this embodiment can omit the dispensing process of the bottom filling adhesive, the process is simpler, the structural reliability is better, and the packaging efficiency is higher.

[0082] In some other embodiments, the adhesive layer 130 can also be first coated on the first substrate 110, openings are made at positions corresponding to the functional areas 122 of the chip 120, and then the chip 120 is mounted on the first substrate 110, which is not specifically limited here.

[0083] Combined with Figure 4 , a plastic package 150 is formed on the side of the first substrate 110 where the chip 120 is mounted. The plastic package 150 encapsulates all the chips 120 on the first substrate 110, playing a role in protection and structural reinforcement. And the plastic package 150 plays a role in support and buffering in the subsequent process of grinding the first substrate 110, reducing the risk of cracking of the first substrate 110.

[0084] Combined with Figure 5, Optionally, a buffer groove 151 is formed on the side of the encapsulation body 150 away from the first substrate 110, and a buffer block 152 can be filled in the buffer groove 151. The formation of the buffer groove 151 can play a role in releasing stress and relieve the warping deformation of the structure caused by the encapsulation stress. The setting of the buffer block 152 can improve the buffer performance and play a better buffering and supporting role in the subsequent grinding process. The buffer block 152 can be made of one or more of metal, ceramic, silicon oxide, and epoxy resin. The number of the buffer grooves 151 can be one or more, and the cross-sectional shape and distribution position of the buffer grooves 151 can be flexibly set according to the actual situation. For example, the buffer groove 151 can be formed at the position corresponding to the first through hole 113 and the first groove 116, and no specific limitation is made here.

[0085] Alternatively, the buffer groove 151 may not be filled with material and remain an empty groove structure. It can also play a buffering role and improve the heat dissipation performance at the same time.

[0086] Combined with Figure 6 , in step S2, the first substrate 110 is ground and thinned. During the grinding process, the first substrate 110 is placed upward, and the encapsulation body 150 plays a supporting and buffering role, which can reduce the risk of chipping. The grinding thickness can be designed according to actual needs. In this embodiment, after grinding, the thickness of the first substrate 110 can reach below 20 um, preferably below 10 um, greatly reducing the thickness of the first substrate 110 and the overall packaging height, and realizing ultra-thin packaging.

[0087] It should be noted that in this embodiment, the grinding process is advanced to before the via-hole process. At this time, the glass substrate is a complete whole, and compared with the glass substrate that has completed local through holes, the risk of chipping can be greatly reduced.

[0088] Combined with Figure 7 , in step S3, the first through hole 113 penetrates the first substrate 110, and the first through hole 113 extends from the second surface 112 of the first substrate 110 to the bonding layer 130 at the electrode 121.

[0089] Optionally, the first region of the second surface 112 is irradiated with the first laser; the first region corresponds to the position of the electrode 121. The first region on the first substrate 110 is induced to be modified by laser irradiation, and then the first region is etched to form the first through hole 113. Among them, the first substrate 110 is etched by a wet etching process. The first region irradiated by the laser corrodes faster than other regions not irradiated by the laser, and thus the first through hole 113 can be quickly etched on the first substrate 110.

[0090] In this step, the bonding layer 130 plays a protective role for the electrode 121, and the etching solution will not remove the bonding layer 130 and cause damage to the electrode 121.

[0091] Optionally, the first through-hole 113 is a cylindrical straight hole, that is, on the axis of the first through-hole 113, its diameter remains unchanged. During subsequent metal filling, the flow resistance of the metal liquid is lower, the filling performance is better, effectively avoiding situations such as voids, the bonding force between the metal layer and the glass substrate is better, and the electrical conductivity is better. It is easy to understand that since the first substrate 110 has been thinned, the depth of the first through-hole 113 is relatively small, the metal filling performance is better, the electrical connection path is shorter, the transmission signal loss is lower, and the transmission speed is faster.

[0092] Optionally, the first through-hole 113 can be formed by etching once or by etching in multiple steps. The cross-sectional shape of the first through-hole 113 can be circular, or triangular, quadrilateral, elliptical, pentagonal, hexagonal or any other shape. The cross-section of the first through-hole 113 can be consistent in the axial direction, or can be gradually changed. Or it can be designed that one end cross-section of the first through-hole 113 is large and the other end cross-section is small. The first through-hole 113 can be a tapered hole, an X-shaped hole, an L-shaped hole, a wavy hole, a stepped hole, etc., which are not specifically limited here.

[0093] Optionally, in combination with Figure 8 , in some embodiments, the first region of the second surface 112 is irradiated with the first laser; the first region is etched to form a prefabricated groove 114. The depth of the prefabricated groove 114 is less than the thickness of the first substrate 110. The bottom of the prefabricated groove 114 is irradiated with the third laser; the bottom of the prefabricated groove 114 is etched to form a through groove 115 penetrating the first substrate 110, and the diameter of the through groove 115 is less than or equal to the diameter of the prefabricated groove 114. The through groove 115 can be a straight hole or a tapered hole, etc. The through groove 115 terminates at the bonding layer 130 at the electrode 121, that is, the through groove 115 exposes the bonding layer 130. The through groove 115 and the prefabricated groove 114 together form the first through-hole 113.

[0094] In the step of forming the through groove 115, the prefabricated groove 114 can be widened or deepened, or the prefabricated groove 114 can be widened and deepened at the same time. The design of the stepped hole is beneficial to increasing the contact area between the metal layer and the glass substrate, thereby improving the bonding property between the metal layer and the glass substrate, and the electrical performance is better. And adopting the step-by-step multiple hole forming process is beneficial to controlling the hole opening accuracy, adjusting the alignment error with the electrode 121, and preventing the problem of reducing the electrical conductivity or electrical connection failure caused by the deviation of the hole opening position. And adopting multiple hole forming, the depth of each hole forming is smaller, and it is not easy to cause chipping. It should be noted that in the multiple hole forming process, the roughness of the hole wall of the first through-hole 113 increases and the adhesion increases, which is beneficial to improving the bonding force between the hole wall of the first through-hole 113 and the metal layer.

[0095] Among them, the first laser and the third laser can be different lasers, and the etching solutions in the multiple via-forming processes can be the same or different, which are not specifically limited here.

[0096] It should be noted that if the prefabricated groove 114 is formed in advance, when the first groove 116 is opened, the first groove 116 communicates with the prefabricated groove 114, so that when the first metal layer 160 is formed subsequently, the metal cross-sectional area at the corner where the electrical connection column 161 and the wiring layer 162 are connected is larger, and the electrical connection performance and bonding property are better. Of course, in some embodiments, the prefabricated groove 114 and the first groove 116 can be carried out synchronously and completed in one process step to improve the process efficiency. Optionally, the depth of the prefabricated groove 114 is the same as the depth of the first groove 116. In some other embodiments, the depth of the prefabricated groove 114 and the depth of the first groove 116 can also be different, which are not specifically limited here.

[0097] In step S4, the first groove 116 is formed. Optionally, the second region of the second surface 112 is irradiated with the second laser; the second region is used to communicate the first through holes 113 corresponding to different chips 120. The second region is etched to form the first groove 116; the depth of the first groove 116 is less than the depth of the first through hole 113.

[0098] It can be understood that after the second laser irradiates, the second region of the first substrate 110 is induced to be modified, and then the second region is etched with the etching solution to form the first groove 116. The second laser and the first laser can be different, and the used etching solutions can also be different, but the principles of laser-induced modification and etching the modified part with the etching solution to remove are similar, which will not be elaborated here.

[0099] Since the first groove 116 is formed and the wiring layer 162 is disposed in the first groove 116, the glass substrate can protect the wiring layer 162. In addition, the setting of the first groove 116 reduces the overall packaging thickness. And compared with directly forming the wiring layer 162 on the second surface 112, the solution in this embodiment increases the contact area between the wiring layer 162 and the glass substrate, which is beneficial to improving the bonding property between the wiring layer 162 and the glass substrate and better protecting the wiring layer 162.

[0100] Optionally, after the first through hole 113 and the first groove 116 are formed, the hole wall of the first through hole 113 and the groove wall of the first groove 116 can be roughened to increase the bonding force between the subsequent metal layer and the glass substrate and prevent structural delamination.

[0101] Combined Figure 9 , optionally, the step S5 of forming the second through hole 133 from the second surface 112 includes:

[0102] The dry etching method is used to remove the bonding layer 130 corresponding to the electrode 121, so as to form a second through hole 133 communicating with the first through hole 113 on the bonding layer 130. Optionally, the dry etching of the product can be carried out by using a plasma etching process, and the bonding layer 130 at the electrode 121 of the chip 120 is etched away to expose the electrode 121. After the plasma etching process, the second surface 112 of the glass substrate is cleaner, and the bonding force between the glass substrate and the metal layer can be further increased.

[0103] It is easy to understand that during the step of forming the second through hole 133, the aperture of the first through hole 113 can be appropriately enlarged, and the purpose of cleaning the hole wall of the first through hole 113 can be achieved, which is beneficial to improving the bonding force between the subsequent glass substrate and the metal layer.

[0104] Of course, it is not limited to this. The opening method of the second through hole 133 can also adopt laser opening, wet etching or other process methods, which are not specifically limited here.

[0105] Combined with Figure 10 , in step S6, a first metal layer 160 is formed on the whole second surface 112, and the first metal layer 160 is filled into the first through hole 113, the second through hole 133 and the first groove 116. The first metal layer 160 is ground to expose the second surface 112 of the first substrate 110; wherein, the surfaces of the first metal layer 160 in the first through hole 113, the second through hole 133 and the first groove 116 are respectively flush with the second surface 112.

[0106] Optionally, the PVD is used to sputter the metal layer on the whole surface, and then the whole surface is electroplated to fill the second through hole 133, the first through hole 113 and the first groove 116 with metal all at once. In this way, the process efficiency is high, and the first metal layer 160 is formed at one time, and the electrical connection performance and bonding property are better. Then, the metal layer on the second surface 112 is thinned by a thinning process until all the metal outside the first groove 116 is removed, that is, the glass substrate is exposed. The thinning process includes but is not limited to grinding, etching, etc. It can be understood that the metal in the first through hole 113, the second through hole 133 and the first groove 116 is left after grinding; and the surfaces of the metal in the second through hole 133 and the first groove 116 are flush with the second surface 112 of the first substrate 110. In this way, the production of the electrical connection column 161 and the wiring layer 162 is completed.

[0107] Combined with Figure 11 and Figure 12, Optionally, a roughened surface may be formed on the electrode 121 of the chip 120 by micro-etching. The roughened surface can be regarded as having a micro-groove or micro-bump 1211 structure formed on the surface of the electrode 121. A metal bonding layer 1213 is formed on the roughened surface. The metal bonding layer 1213 can be made of metals such as titanium, tungsten, nickel, etc. In this way, when the first metal layer 160 is formed by subsequent electroplating, it is beneficial to improve the electrical connection performance and bonding force between the first metal layer 160 and the electrode 121.

[0108] Bond Figure 13 , In step S7, a solder mask layer 170 covering the second surface 112 is formed; a first window is opened in the solder mask layer 170; a third metal layer is filled in the first window to form a solder pad 171; the solder pad 171 is electrically connected to the first metal layer 160; and bumps 172 are formed on the solder pad 171.

[0109] Optionally, the solder mask layer 170 is formed on the entire second surface 112 by a photolithography process. The solder mask layer 170 protects the first substrate 110 and the first metal layer 160 flush with the surface of the first substrate 110. The positions of the bumps 172 are defined on the solder mask layer 170, and then the solder pads 171 under the bumps 172 are fabricated by a chemical plating process, and then the bumps 172 are formed on the solder pads 171 by processes such as printing or ball placement. Thus, the electrode 121 of the chip 120 is guided from the inside to the surface of the first substrate 110.

[0110] Optionally, bond Figure 14 , In some embodiments, in order to increase the density of input and output pins and improve the product integration performance, multiple wiring layers 162 are provided to meet more line interconnections. For example, a first wiring layer 162 is formed on the first substrate 110, a second wiring layer 162 is formed on the second substrate 180, and the second wiring layer 162 is electrically connected to the first wiring layer 162.

[0111] Optionally, after the solder mask layer 170 and the solder pads 171 under the bumps 172 are formed, a second substrate 180 is mounted on the second surface 112 of the first substrate 110. The second substrate 180 can be made of glass, ceramic, silicon substrate, etc. Taking the glass substrate as an example for the second substrate 180. The second substrate 180 is bonded or keyed to the first substrate 110. Third through-holes and second grooves are opened in the second substrate 180. The manufacturing process of the third through-holes is similar to that of the first through-holes 113. After laser-induced modification, the third through-holes are formed by wet etching. The positions of the third through-holes correspond to the positions of the solder pads 171 on the first substrate 110. The preparation process of the second grooves is similar to that of the first grooves 116 described above and will not be elaborated here.

[0112] The second metal layer 181 is filled in the third through-hole and the second groove to form the second wiring layer 162; the second metal layer 181 is electrically connected to the first metal layer 160. The second metal layer 181 adopts sputtering and electroplating processes, and its formation principle is similar to that of the first metal layer 160. The second metal layer 181 in the third through-hole and the second groove can also be formed in one step to improve the packaging efficiency. A solder mask layer 170 is formed on the side of the second substrate 180 away from the first substrate 110, and pads 171 are formed on the solder mask layer 170, and bumps 172 are fabricated on the pads 171.

[0113] Optionally, in some embodiments, in combination with Figure 15 , two structures formed by steps S1 to S7 can also be mounted together to form a structure similar to a double-sided package, further improving the integration degree of the packaging structure. It should be noted that when two above-mentioned packaging structures are stacked together, the bumps 172 on one first substrate 110 are bonded to the bumps 172 on the other first substrate 110. Of course, the preparation process of the bumps 172 on one of the first substrates 110 can also be omitted, and the bumps 172 on one first substrate 110 are bonded to the pads 171 on the other first substrate 110.

[0114] Optionally, if it is necessary to electrically connect two stacked packaging structures to other modules, connection pads 191 can be reserved on at least one of the two first substrates 110 to achieve electrical connection with other external modules.

[0115] Alternatively, the connection pads 191 can also be led out from the slots of the plastic package 150. For example, slots are opened on the plastic package 150 and electroplated metal is used to form conductive posts 190. The conductive posts 190 are connected to the first metal layer 160 on either side, or are electrically connected to the first metal layers 160 on both sides respectively. Connection pads 191 electrically connected to the conductive posts 190 are formed on the surface of the plastic package 150. The connection pads 191 can be provided on either side of the plastic packages 150 on both sides, or connection pads 191 are provided on the surfaces of the plastic packages 150 on both sides.

[0116] An embodiment of the present invention also provides a packaging structure prepared by using the TGV substrate integrated packaging method in any one of the foregoing embodiments.

[0117] In summary, the TGV substrate integrated packaging method and packaging structure provided by the embodiments of the present invention have the following beneficial effects, including:

[0118] First, a plastic package 150 is formed on one side of the glass substrate, and then the glass substrate is ground. During the grinding process, the plastic package 150 can play a role in support and buffering, and grinding the entire intact glass substrate can significantly reduce the risk of chipping. After grinding the glass substrate, the first through hole 113, the first groove 116, and the second through hole 133 are formed to reduce the risk of chipping, reduce the thickness of the glass substrate, and achieve ultra-thin packaging. The first through hole 113 formed in this way has a smaller depth-to-diameter ratio, better metal filling performance, is not prone to generating voids, and has a better bonding force between the metal and the glass substrate. Secondly, by forming the first groove 116 on the glass substrate, the metal in the first groove 116 is used for wiring of the circuit layer to achieve the interconnection of the chip 120. Forming the first groove 116 is beneficial to improving the bonding force between the metal and the glass substrate, preventing structural delamination, and improving the packaging quality. In addition, the metal filling can be completed at one time in the first through hole 113, the first groove 116, and the second through hole 133, with higher process efficiency and better bonding force, which is beneficial to improving the packaging efficiency and packaging quality. Moreover, the packaging structure provided in this embodiment can integrate a variety of different chips 120 together, improve the packaging integration degree, enhance the product performance, and enrich the product functions.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; any modifications, equivalent replacements, improvements, etc. should be included in the protection scope of the present invention.

Claims

1. A method for integrating and packaging a TGV substrate, characterized in that, Comprising: Providing a first substrate; the first substrate is a glass substrate; the first substrate includes a first surface and a second surface disposed opposite to each other; the first surface is mounted with chips and is formed with a plastic package covering the chips; wherein, the electrodes of the chips are roughened by micro-etching to form a roughened surface, and a metal bonding layer is formed on the roughened surface; Opening a buffer groove on the side of the plastic package away from the first substrate, and filling a buffer block in the buffer groove; Grinding and thinning the second surface of the first substrate to achieve the encapsulation of the ultra-thin glass substrate; First forming a first through-hole on the second surface; the position of the first through-hole corresponds to the position of the electrodes on the chips; then forming a first groove on the second surface; the first groove communicates with the first through-holes on different corresponding chips; Forming a second through-hole on the second surface; the second through-hole corresponds to and communicates with the position of the first through-hole; the second through-hole extends at least axially to the first through-hole to expose the electrodes; Forming a first metal layer on the second surface as a whole, and the first metal layer is filled into the first through-hole, the second through-hole and the first groove; grinding the first metal layer to expose the second surface of the first substrate; wherein, the surfaces of the first metal layer in the first through-hole, the second through-hole and the first groove are respectively flush with the second surface; The step of providing the first substrate includes: Forming an adhesive layer between the first substrate and the chips; wherein, a functional area is further provided on the side of the chips where the electrodes are provided, the adhesive layer covers the surface of the side of the chips where the electrodes are provided, and an opening is left at the position corresponding to the functional area; The adhesive layer is used to protect the electrodes and prevent damage to the electrodes when forming the first through-hole.

2. The TGV substrate integrated packaging method according to claim 1, wherein In the step of forming the first through-hole on the second surface, the first through-hole penetrates the first substrate; In the step of forming the second through-hole on the second surface, the second through-hole penetrates the adhesive layer.

3. The TGV substrate integrated packaging method according to claim 1, wherein The step of forming the first through-hole on the second surface includes: Irradiating a first area of the second surface with a first laser; the first area corresponds to the position of the electrodes; Etching the first area to form the first through-hole; The step of forming the first groove on the second surface includes: Irradiating a second area of the second surface with a second laser; the second area is used to communicate the first through-holes between different corresponding chips; Etching the second area to form the first groove; the depth of the first groove is less than the depth of the first through-hole.

4. The TGV substrate integrated packaging method according to claim 3, characterized in that, Irradiating a first area of the second surface with a first laser; the step of etching the first area to form the first through-hole includes: Irradiating a first area of the second surface with a first laser; etching the first area to form a preformed groove; Irradiating the bottom of the preformed groove with a third laser; etching the bottom of the preformed groove to form a through-groove penetrating the first substrate, and the diameter of the through-groove is smaller than the diameter of the preformed groove; The through-groove and the preformed groove together form the first through-hole.

5. The TGV substrate integrated packaging method according to claim 1, characterized in that, The step of forming a second through-hole on the second surface includes: Using dry etching to remove the bonding layer corresponding to the electrode, so as to form a second through-hole communicating with the first through-hole on the bonding layer.

6. The TGV substrate integrated packaging method according to claim 1, characterized in that, It further includes: Mounting a second substrate on the second surface; Opening a third through-hole and a second groove on the second substrate; Filling a second metal layer in the third through-hole and the second groove; the second metal layer is electrically connected to the first metal layer.

7. The TGV substrate integrated packaging method according to any one of claims 1 to 6, characterized in that It further includes: Forming a solder mask layer covering the second surface; Opening a first window on the solder mask layer; Filling a third metal layer in the first window to form a solder pad; the solder pad is electrically connected to the first metal layer; Forming bumps on the solder pad.

8. An encapsulation structure, characterized in that, Prepared by using the TGV substrate integrated packaging method described in any one of claims 1 to 7.

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