Manufacturing method of semiconductor device and semiconductor device
By filling the protective layer between the chips during the semiconductor device manufacturing process, the side walls of the chip are protected from wear and tear, the chip damage problem is solved, the product yield and performance are improved, and the cost is reduced.
Patent Information
- Application Number
- CN202411978562.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-05-13
AI Technical Summary
During the manufacturing process of semiconductor devices, the grinding process causes uncontrollable damage to the side walls of the chip, affecting the electrical performance of the device and reducing product yield.
By having spaced grooves between adjacent first chips and filling the protective layer in these grooves, the side walls of the chip are protected from damage. The chip is then thinned and the protective layer is removed, and the stacked structure is finally cut to obtain the semiconductor device.
It effectively reduces chip damage, improves product yield and semiconductor device performance, and reduces manufacturing costs.
Smart Images
Figure CN119993846A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art
[0002] In the application process of integrated circuits, the performance of various devices will be affected by the manufacturing process. Because of the different processing techniques between the layers of materials during the manufacturing process, it is easy to cause damage to some materials, which in turn affects the electrical performance of the device.
[0003] In current semiconductor devices, in the chip thinning process, grinding and chemical mechanical polishing (CMP) are usually used to thin the chip. When the space between chips is large, the grinding wheel will damage the side wall of the chip. The damage is uncontrollable and difficult to repair in subsequent process steps, which reduces the product yield, increases costs, and further reduces the performance of semiconductor devices. Summary of the invention
[0004] The main technical problem solved by the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device, which can effectively reduce damage to the chip, improve product yield, thereby improving the performance of the semiconductor device and reducing costs.
[0005] To solve the above technical problems, a technical solution adopted in the present application is: providing a method for manufacturing a semiconductor device, comprising: providing a stacking structure, wherein the stacking structure includes a first semiconductor and a plurality of first chips, the plurality of first chips are bonded on the first semiconductor, and there are spacing grooves between adjacent first chips; forming a protective layer, wherein the protective layer fills the spacing grooves; performing thinning processing on the first chips in the stacking structure, and removing the remaining protective layer.
[0006] In one embodiment of the present application, the forming of the protective layer includes: filling the spacing groove with a protective material to form a protective layer; wherein, in a direction perpendicular to the surface of the first semiconductor, the thickness of the protective layer is greater than the thickness of the first chip, so that the protective layer covers the side wall of the first chip and the second surface of the first chip.
[0007] In one embodiment of the present application, the material of the protective layer is organic or inorganic, wherein the decomposition temperature corresponding to the thermal stability of the protective layer is greater than 400° C., and the tensile strength corresponding to the mechanical strength of the protective layer is greater than 80 MPa.
[0008] In one embodiment of the present application, the thinning process is performed on the first chip in the stacked structure, and the remaining protective layer is removed, including: performing a thinning process on the first chip from the second surface of the first chip to thin the first chip to a target thickness; and removing the remaining protective layer in the spacing groove.
[0009] In an embodiment of the present application, after removing the protective layer remaining in the spacing groove, the method further includes: filling the spacing groove with a filling layer, wherein the filling layer is used to protect the first chip.
[0010] In one embodiment of the present application, it further includes: performing a cutting process on the stacked structure in the area where the spacing groove is located to obtain a semiconductor device; wherein each of the semiconductor devices includes one of the first chips.
[0011] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a semiconductor device, comprising: a second chip; a first chip, wherein the first chip is bonded to the second chip to obtain a semiconductor device; wherein the semiconductor device is a stacked structure obtained by bonding a plurality of the first chips and a second chip on a first semiconductor, and then filling the spacing grooves between the first chips with a protective layer, thinning the first chips and removing the protective layer, and then performing a cutting process on the stacked structure.
[0012] In an embodiment of the present application, the second chip is at least a portion of the first semiconductor divided after cutting, wherein a first dielectric layer is further formed on the first surface of the second chip, and a first bonding structure is formed in the first dielectric layer.
[0013] In one embodiment of the present application, a second dielectric layer is further formed on the first surface of the first chip, and a second bonding structure is formed in the second dielectric layer, wherein the first chip is bonded to the first bonding structure corresponding to the second chip through the second bonding structure to obtain the semiconductor device.
[0014] In an embodiment of the present application, a metal trace is further formed on the second surface of the first chip, and the first chip is coupled to an external device through the metal trace.
[0015] Different from the prior art, the manufacturing method of the semiconductor device provided in the present application includes: providing a stacking structure, wherein the stacking structure includes a first semiconductor and a plurality of first chips, the plurality of first chips are bonded on the first semiconductor, and there are spacing grooves between adjacent first chips; forming a protective layer, wherein the protective layer fills the spacing grooves; performing a thinning process on the first chips in the stacking structure, and removing the remaining protective layer. That is, in the present application, before performing a thinning process on the plurality of first chips in the stacking structure, a protective layer is filled in the spacing grooves between the first chips, so that during the thinning process of the first chip, the edge and sidewall of the first chip are protected by the protective layer without causing damage, and the structural integrity of the first chip is effectively protected, which can effectively reduce damage to the chip, improve product yield, and thereby improve the performance of the semiconductor device and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:
[0017] Figure 1 It is a flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application;
[0018] Figure 2 is a structural schematic diagram of the first embodiment of the stacking structure in the present application;
[0019] Figure 3 is a structural schematic diagram of a second embodiment of a stacking structure in the present application;
[0020] Figure 4 It is a structural schematic diagram of an embodiment of forming a protective layer in the present application;
[0021] Figure 5 is a schematic diagram of the structure of thinning the first chip in the present application;
[0022] Figure 6 It is a structural schematic diagram of an embodiment of removing the protective layer in the present application;
[0023] Figure 7 It is a structural schematic diagram of an embodiment of cutting a stacked structure in the present application.
[0024] In the drawings, a first semiconductor 100, a second chip 110, a first surface 101 of the first semiconductor, a first chip 200, a bonding groove 210, a first surface 201 of the first chip, a second surface 202 of the first chip, a first dielectric layer 300, a first bonding structure 310, a second dielectric layer 400, a second bonding structure 410, a protective layer 500, a thickness T1 of the protective layer 500, and a thickness T2 of the first chip 200. DETAILED DESCRIPTION
[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0026] The terms "first" and "second" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically limited. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back ...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.
[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0028] The present application is described in detail below with reference to the accompanying drawings and embodiments.
[0029] In current semiconductor devices, in advanced packaging processes, the chip usually needs to be thinned again after die to wafer bonding (D2W). That is, in the chip thinning process, a common method is to thin the chip by grinding and chemical mechanical polishing (CMP) after chip to wafer bonding (C2W). The profile of the ground chip is optimized by adjusting the grinding feed speed, grinding wheel mesh, etc.; when the space between chips is large, such as the space is greater than 100um, the grinding wheel will damage the side wall of the chip. The damage is uncontrollable and difficult to repair in the subsequent process, which reduces the product yield, increases the cost, and further reduces the performance of the semiconductor device.
[0030] Therefore, a method for manufacturing a semiconductor device is provided to effectively protect the structural integrity of a first chip, which can effectively reduce damage to the chip, improve product yield, and further improve the performance of the semiconductor device and reduce costs.
[0031] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a semiconductor device in the present application.
[0032] like Figure 1 As shown, the semiconductor device manufacturing method of the present application comprises the following steps:
[0033] S10. Provide a stacking structure, wherein the stacking structure includes a first semiconductor and a plurality of first chips, the plurality of first chips are bonded on the first semiconductor, and spacing grooves exist between adjacent first chips.
[0034] Among them, the stacking structure is a structure in which at least two semiconductor structures are stacked together, such as wafers and chips stacked together; the wafer is a wafer commonly used in the semiconductor field; the first semiconductor can be a wafer, a chip, a packaging substrate, a transfer board, etc., the first chip refers to a part of the wafer after cutting, and can be a carrier of a miniaturized circuit structure; the spacing groove refers to the gap between the first chip and the adjacent first chip, that is, there is a gap between the first chips after bonding, which serves as a spacing groove.
[0035] Specifically, a first semiconductor and a plurality of first chips are provided, and the plurality of first chips are bonded on the first semiconductor, and the plurality of first chips are spaced apart on the first semiconductor, so that a spacing groove exists between each first chip and other adjacent first chips.
[0036] S20, forming a protection layer, wherein the protection layer fills the spacing grooves.
[0037] The protection layer refers to a material layer for protecting the first chip, and is used to protect the first chip during the thinning process of the first chip after bonding.
[0038] Specifically, after multiple first chips are bonded on the first semiconductor, there are spacing grooves between adjacent first chips. In order to avoid damage to the side walls of the first chips during the grinding process, protective material is filled in the spacing grooves to form a protective layer to protect the side walls of the first chips from damage.
[0039] S30, performing a thinning process on the first chip in the stacked structure, and removing the remaining protection layer.
[0040] The thinning process refers to performing a thickness reduction operation on the first chip, ie, a grinding process or chemical mechanical polishing (CMP) to reduce the thickness of the first chip.
[0041] Specifically, after the protective layer is filled in the spacing grooves between the first chips, a grinding process or chemical mechanical polishing (CMP) is used to perform a thinning process on the second side of the bonded first chip to reduce the thickness of the first chip, and after the thinning process is completed, the protective layer remaining in the spacing grooves is removed.
[0042] In this embodiment, after multiple first chips are bonded on the first semiconductor, a protective layer is formed in the spacing grooves between adjacent first chips to protect the side walls of the first chips from being damaged during the thinning process of the bonded first chips, thereby effectively reducing damage to the chips, improving product yield, and thereby improving the performance of semiconductor devices and reducing costs.
[0043] In some embodiments, a stacked structure is provided.
[0044] First, a first semiconductor 100 is provided.
[0045] Among them, the first semiconductor 100 can be any suitable substrate known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).
[0046] Then, a plurality of first chips 200 are provided, and then the plurality of first chips 200 are bonded to the first semiconductor 100 to obtain a stacked structure.
[0047] See also Figure 2 , Figure 2 It is a structural schematic diagram of the first embodiment of the stacking structure in this application.
[0048] like Figure 2 As shown, the first semiconductor 100 is divided into a plurality of second chips 110 , and then a first chip 200 is bonded on each second chip 110 , and there are spacing grooves 210 between adjacent first chips.
[0049] It is understandable that the initial thickness of the first chip 200 is smaller than the thickness of the first semiconductor 100 , that is, the first chip 200 may be obtained after thinning, and the thinning of the first chip 200 after bonding is the second thinning process.
[0050] In some embodiments, a dielectric layer is further formed in the stacked structure.
[0051] See also Figure 3 , Figure 3 It is a structural schematic diagram of the second embodiment of the stacking structure in this application.
[0052] like Figure 3 As shown, the first semiconductor 100 is divided into a plurality of second chip regions 110, wherein the first surface 101 of the first semiconductor 100 further forms a first dielectric layer 300, and a first bonding structure 310 is formed in the first dielectric layer 300. A plurality of first chips 200 are provided, a second dielectric layer 400 is formed on the first surface 201 of the first chip 200, and a second bonding structure 410 is formed in the second dielectric layer 400.
[0053] Among them, each first chip 200 is bonded to the first bonding structure 310 corresponding to the second chip area 110 through the second bonding structure 410, thereby obtaining a stacked structure; that is, multiple first chips 200 are bonded to the first semiconductor 100 in the stacked structure, and there are bonding grooves 210 between adjacent first chips 200; it can be understood that the second chip area is a functional area divided on the first semiconductor 100, and after subsequent cutting, the cut second chip area is used as the second chip.
[0054] In some embodiments, the first semiconductor 100 may include a first substrate (not shown in the drawings) and a first dielectric layer 300, that is, the first bonding structure 310 is also formed in the first dielectric layer 300 of the first semiconductor 100; the first chip 200 may include a second substrate (not shown in the drawings) and a second dielectric layer 400, that is, the second bonding structure 410 is formed in the second dielectric layer 400 of the first chip.
[0055] In some embodiments, a conductive structure may also be formed in the first chip 200, that is, a circuit structure in the first chip is formed; a conductive structure may also be formed in the first semiconductor 100, that is, a circuit structure in the second chip 110 is formed, and the conductive structure may be coupled to the corresponding bonding structure, and may be coupled to an external device through the conductive structure; for example, a first conductive structure (not shown in the drawings) is formed in the second chip of the first semiconductor, the first conductive structure is coupled to the first bonding structure, a second conductive structure is formed in the first chip 200, the second conductive structure is coupled to the second bonding structure, and the first bonding structure is bonded to the second bonding structure, so that the second chip 110 is coupled to the first chip 200 through the first conductive structure, the first bonding structure, the second bonding structure, and the second conductive structure.
[0056] In some embodiments, a through-silicon via (TSV) process may be used to form a through-hole structure (not shown in the drawings) in the first chip 200 , and the conductive structure may be exposed by using the through-hole structure to couple with an external device.
[0057] Next, a protective layer is formed.
[0058] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming a protective layer in the present application.
[0059] like Figure 4 As shown, in Figure 3 On the basis of the above, a protective material is filled in the spacing groove 210 to form a protective layer 500 . The spacing groove 210 is filled with the protective layer 500 , and the protective layer 500 covers the sidewall of the first chip 200 .
[0060] Among them, the protective material of the protective layer 500 can be organic or inorganic, wherein the decomposition temperature corresponding to the thermal stability of the protective layer 500 is greater than 400°C, and the tensile strength corresponding to the mechanical strength of the protective layer 500 is greater than 80MPa, such as PI (Polyimide) photoresist (polyimide), PR (Photoresist) photoresist (benzene ring polymer), temporary bonding glue, etc., wherein PI photoresist refers to a photoresist with polyimide (Polyimide) as the main component, and its molecular structure contains a polyimide skeleton; PR photoresist refers to a photoresist with photopolymer as the main component, such as a styrene-based substance, whose molecular chain contains double bonds, and after being irradiated with ultraviolet light, a photopolymerization reaction occurs. Compared with the oxide layer and other filling layers that are filled in the spacing groove 210 and have electrical properties, the protective layer 500 in the present application is mainly used to prevent the grinding process from causing damage to the side wall of the first chip 200. It has good filling properties and will not cause air gap problems when filling the spacing groove 210 due to the larger depth and width of the spacing groove 210 like the oxide layer and other filling layers.
[0061] In some embodiments, the protective layer 500 also covers the second surface 202 of the first chip 200 , that is, in a direction perpendicular to the surface of the first semiconductor 100 , the thickness T1 of the protective layer 500 is greater than the thickness T2 of the first chip 200 , so that the protective layer 500 covers the side walls of the first chip 200 and the second surface 202 of the first chip 200 .
[0062] Then, a thinning process is performed on the first chip in the stacked structure.
[0063] See also Figure 5 , Figure 5 It is a schematic diagram of the structure of thinning the first chip in this application.
[0064] like Figure 5 As shown, in Figure 4 On the basis of, a thinning process is performed on the first chip 200 in the stacked structure.
[0065] The thinning process may be performed by grinding or chemical mechanical polishing (CMP).
[0066] Specifically, a thinning process is performed on the first chip 200 from the second surface of the first chip 200 to reduce the thickness of the first chip 200 to a target thickness.
[0067] In the present embodiment, there is a spacing groove between the first chip and the first chip after bonding, and a protective layer is filled in the spacing groove, so that during the thinning process of the first chip, the protective layer can effectively protect the first chip, so that the side wall of the first chip will not be damaged, thereby improving the product yield, thereby improving the performance of the semiconductor device and reducing the cost.
[0068] Then, remove the remaining protective layer.
[0069] See also Figure 6 , Figure 6 It is a structural schematic diagram of an embodiment of removing the protective layer in the present application.
[0070] like Figure 6 As shown, in Figure 5 On the basis of the above, the residual protection layer 500 in the spacing groove 210 is removed, so that the spacing groove 210 appears again.
[0071] It is understandable that the protective layer 500 may be removed by etching, such as wet etching or dry etching, or by other types of removal methods, as long as the residual protective layer 500 in the spacing groove 210 can be removed.
[0072] In some embodiments, after removing the remaining protection layer 500 in the spacing groove 210 , metal traces (not shown) may be formed on the second surface 202 of the first chip 200 , thereby coupling the first chip to an external device through the metal traces.
[0073] Specifically, exposure, development, etching and other operations are performed on the second surface 202 of the first chip 200, and then the etched area on the second surface 202 of the first chip 200 is filled with metal wiring, which can be subsequently coupled to external devices through the metal wiring.
[0074] In some embodiments, after removing the protective layer 500 remaining in the spacing groove 210, a filling layer (not shown in the figure) may also be filled in the spacing groove 210. The filling layer is used to protect the first chip 200, isolate the first chip 200 from the influence of the external environment, and improve the reliability and anti-interference capability of the first chip 200.
[0075] In some embodiments, after removing the remaining protective layer, the stacked structure may be cut to obtain a semiconductor device.
[0076] See also Figure 7 , Figure 7 It is a structural schematic diagram of an embodiment of cutting a stacked structure in the present application.
[0077] like Figure 7As shown, in Figure 6 On the basis of this, a cutting process is performed on the stacked structure in the area where the spacing groove 210 is located to obtain a semiconductor device.
[0078] Among them, because a plurality of first chips 200 are bonded to the first semiconductor 100, and the first chips 200 are generally used individually, the stacked structure needs to be cut into semiconductor devices corresponding to the individual first chips 200. The cutting process can be performed after the spacing grooves 210 between adjacent first chips 200 are filled with a filling layer (not shown in the figure), or the cutting process can be performed directly without filling the spacing grooves 210 between adjacent first chips 200 with a filling layer.
[0079] Specifically, taking the example of performing a cutting process after filling a filling layer in the spacing grooves 210 between adjacent first chips 200, after removing the remaining protective layer in the spacing grooves 210, a plurality of first chips 200 are exposed on the first semiconductor 100 of the stacked structure, and there are spacing grooves 210 between adjacent first chips 200, and the spacing grooves 210 between adjacent first chips 200 are filled with a filling layer (not marked in the figure), and the stacked structure is cut in the area where the spacing grooves 210 are located, and then individual semiconductor devices are cut out, and each semiconductor device includes a first chip 200 and a second chip 110 divided by the first semiconductor 100, and in parallel with the surface of the first semiconductor 100 In the direction, the width of a first chip 200 can be less than, equal to or greater than the width of a second chip 110 divided by the first semiconductor 100. Further, in the direction parallel to the surface of the first semiconductor 100, the width of a first chip 200 is less than the width of a second chip 110 divided by the first semiconductor 100, that is, a step is formed between a first chip 200 and a second chip 110 divided by the first semiconductor 100, and a filling layer after cutting is retained at the step at the edge of a first chip 200; specifically, the stacked structure is cut from the second side of the first semiconductor 100 to obtain a bonding structure of the cut second chip area and the first chip, and the cut second chip area is used as the second chip.
[0080] In some embodiments, the individual semiconductor devices obtained by cutting may be packaged to obtain complete semiconductor devices that can be used.
[0081] In this embodiment, after multiple first chips are bonded to the first semiconductor, a protective layer is formed in the spacing grooves between adjacent first chips to protect the side walls of the first chips from being damaged during the thinning process of the bonded first chips, thereby effectively reducing damage to the chips. Furthermore, when the stacked structure is cut into semiconductor devices corresponding to a single first chip, the structural integrity of the semiconductor device is ensured, the product yield is improved, and the performance of the semiconductor device is improved, thereby reducing costs.
[0082] The present application also provides a semiconductor device, which is formed by the manufacturing method of the semiconductor device, referring to Figure 2-7 .
[0083] The semiconductor device includes a second chip 110 and a first chip 200 , and the first chip 200 and the second chip 110 are bonded.
[0084] Among them, the semiconductor device is obtained by bonding multiple first chips 200 and a second chip 110 on a first semiconductor 100 to obtain a stacked structure, filling a protective layer 500 in the spacing grooves 210 between the first chips 200, thinning the first chips 200 and removing the protective layer 500, and then cutting the stacked structure.
[0085] In some embodiments, the second chip 110 is at least a portion of the first semiconductor 100 divided after cutting, that is, the second chip area of the first semiconductor 100 after cutting serves as the second chip 110, wherein a first dielectric layer 300 is also formed on the first surface 101 of the second chip 110, a first bonding structure 310 is formed in the first dielectric layer 300, and the second chip 110 is coupled to the first bonding structure.
[0086] In some embodiments, a second dielectric layer 400 is further formed on the first surface 201 of the first chip 200 , and a second bonding structure 410 is formed in the second dielectric layer 400 , wherein the first chip 200 is bonded to the first bonding structure 310 corresponding to the second chip 110 through the second bonding structure 410 to obtain a semiconductor device.
[0087] In some embodiments, metal traces (not shown in the drawings) are further formed on the second surface 202 of the first chip 200 , and the first chip 200 is coupled to external devices through the metal traces.
[0088] In some embodiments, in a direction parallel to the surface of the first semiconductor 100, the width of the first chip 200 is smaller than the width of the second chip 110, that is, a step is formed between the first chip 200 and the second chip 110. Furthermore, a filling layer is formed on the step at the edge of the first chip 200, and the filling layer is the filling layer retained after the protective layer 500 is removed and the stacked structure is cut.
[0089] In this embodiment, after multiple first chips are bonded to the first semiconductor, a protective layer is formed in the spacing grooves between adjacent first chips to protect the side walls of the first chips from being damaged during the thinning process of the bonded first chips, thereby effectively reducing damage to the chips. Furthermore, when the stacked structure is cut into semiconductor devices corresponding to a single first chip, the structural integrity of the semiconductor device is ensured, the product yield is improved, and the performance of the semiconductor device is improved, thereby reducing costs.
[0090] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: A stacking structure is provided, wherein the stacking structure comprises a first semiconductor and a plurality of first chips, the plurality of first chips are bonded on the first semiconductor, and there are spacing grooves between adjacent first chips; forming a protective layer, wherein the protective layer fills the spacing groove; The first chip in the stacked structure is thinned and the remaining protection layer is removed.
2. The manufacturing method according to claim 1, characterized in that: The forming of the protective layer comprises: Filling the spacing groove with a protective material to form a protective layer; Wherein, in a direction perpendicular to the first semiconductor surface, the thickness of the protection layer is greater than the thickness of the first chip, so that the protection layer covers the side wall of the first chip and the second surface of the first chip.
3. The manufacturing method according to claim 1 or 2, characterized in that: The material of the protective layer is organic or inorganic, wherein the decomposition temperature corresponding to the thermal stability of the protective layer is greater than 400° C., and the tensile strength corresponding to the mechanical strength of the protective layer is greater than 80 MPa.
4. The manufacturing method according to claim 1, characterized in that: The thinning process is performed on the first chip in the stacked structure, and the remaining protective layer is removed, comprising: performing a thinning process on the first chip from the second surface of the first chip to thin the first chip to a target thickness; The protective layer remaining in the spacing groove is removed.
5. The manufacturing method according to claim 4, characterized in that: After removing the protective layer remaining in the spacing groove, the method further includes: A filling layer is filled in the spacing groove, and the filling layer is used to protect the first chip.
6. The manufacturing method according to claim 5, characterized in that: Also includes: Performing a cutting process on the stacked structure in the area where the spacing groove is located to obtain a semiconductor device; Each of the semiconductor devices includes a first chip.
7. A semiconductor device, characterized in that: include: The second chip; A first chip, wherein the first chip is bonded to the second chip to obtain a semiconductor device; Among them, the semiconductor device is obtained by bonding multiple first chips and the second chip area on the first semiconductor to obtain a stacked structure, filling the spacing grooves between the first chips with a protective layer, thinning the first chips and removing the protective layer, and then performing a cutting process on the stacked structure.
8. The semiconductor device according to claim 7, characterized in that The second chip is at least a portion of the first semiconductor after being cut, wherein a first dielectric layer is further formed on the first surface of the second chip, and a first bonding structure is formed in the first dielectric layer.
9. The semiconductor device according to claim 8, characterized in that A second dielectric layer is also formed on the first surface of the first chip, and a second bonding structure is formed in the second dielectric layer, wherein the first chip is bonded to the first bonding structure corresponding to the second chip through the second bonding structure to obtain the semiconductor device.
10. The semiconductor device according to claim 7, wherein: A metal trace is also formed on the second surface of the first chip, and the first chip is coupled to an external device through the metal trace.