Semiconductor device and manufacturing method thereof
By forming openings in the interlayer dielectric layer of the integrated circuit and depositing a copper nitride layer, filling the metal material and heating and decomposing it to form an air gap, the problem of increasing parasitic capacitance in the integrated circuit is solved, the chip processing speed is improved, and high integration and low process complexity are maintained.
Patent Information
- Application Number
- CN202311504685.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-13
- Publication Date
- 2025-05-13
AI Technical Summary
In integrated circuit manufacturing, as the chip feature size decreases and the integration level increases, the number of metal wiring layers in the electrical interconnect structure increases, and the interconnect density increases, resulting in a significant impact on resistance and parasitic capacitance, which in turn increases RC delay, crosstalk noise and chip power consumption, and reduces processing speed.
By forming an opening in the interlayer dielectric layer and depositing a copper nitride layer on the inner surface of the opening, filling the metal material, forming an electrically connected metal layer through a planarization process, and finally heating decomposes the copper nitride layer to form an air gap to reduce parasitic capacitance.
The parasitic capacitance between the electrically connected metal parts and between the electrically connected metal parts and the substrate is effectively reduced, the RC delay is reduced, the electron migration rate is increased, the chip processing speed is improved, and the influence of increasing process complexity and chip integration is avoided.
Smart Images
Figure CN119993904A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] With the advancement of integrated circuit technology, the chip feature size is constantly shrinking, and the chip integration is constantly improving. In the electrical interconnection structure set on the substrate, the number of metal wiring layers is increasing, and the interconnection density is increasing, so that the resistance of the electrical interconnection structure is increasing. The influence of the parasitic capacitance formed between the electrically connected metal parts and between the electrically connected metal parts and the conductive structure (such as the gate of the MOS transistor) in the surface area of the substrate can no longer be ignored. It is specifically reflected in the increase of resistance-capacitance (RC) delay, crosstalk noise and chip power consumption, which ultimately leads to a decrease in chip processing speed. In order to shorten the RC delay and increase the chip processing speed, a low-k (dielectric constant) dielectric layer is usually used as an isolation medium to reduce the parasitic capacitance. In addition, the industry has also proposed a method for forming an air gap on the substrate. Since the dielectric constant of the air gap is very low, the parasitic capacitance can also be reduced by forming an air gap.
[0003] In order to form an air gap on a substrate, one method is to first form a groove with a large aspect ratio on the surface of an interlayer dielectric layer or a conductive layer, and then deposit a dielectric material by a chemical vapor deposition process. By controlling the deposition process, the dielectric material is suspended to cover the groove to form an air gap in the groove. However, the size and shape of the air gap formed by this method are not easy to control, and the groove needs to be specially made, which significantly increases the complexity of the process. Another method for forming an air gap is to first form a groove on the surface of an interlayer dielectric layer or a conductive layer and fill the groove with a sacrificial material. During a subsequent process, the sacrificial material is removed to form an air gap at the groove position. However, in this method, the planar area occupied by the groove to be filled with the sacrificial material is usually large, which is not conducive to improving the chip integration. Summary of the invention
[0004] In order to form an air gap on a substrate to reduce parasitic capacitance without significantly increasing process complexity and avoiding affecting chip integration, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device.
[0005] In one aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
[0006] A semiconductor structure is provided, the semiconductor structure comprising a lower conductive layer formed on a substrate and an interlayer dielectric layer located above the lower conductive layer;
[0007] An opening is formed in the interlayer dielectric layer, wherein the lower conductive layer and the opening have at least a partially overlapping area in a top view;
[0008] Depositing a copper nitride layer on the inner surface of the opening;
[0009] Depositing a metal material so that the metal material fills the opening and covers the interlayer dielectric layer;
[0010] Performing a planarization process to remove the metal material outside the opening, and the remaining metal material forms an electrical connection metal layer located in the opening; and
[0011] The copper nitride layer is heated to decompose the copper nitride layer into copper and nitrogen, so that an air gap is formed between the sidewall of the electrical connection metal layer and the interlayer dielectric layer in the opening.
[0012] Optionally, before performing the planarization process, the manufacturing method further comprises: performing thermal annealing, wherein an annealing temperature of the thermal annealing is lower than a temperature at which the copper nitride layer decomposes.
[0013] Optionally, when heating the copper nitride layer, a heating source is located above the copper nitride layer.
[0014] Optionally, when the copper nitride layer is heated to decompose the copper nitride layer into copper and nitrogen, the heating temperature is 200°C to 500°C or 200°C to 300°C or 300°C to 450°C.
[0015] Optionally, the thickness of the copper nitride layer is less than 20% or 15% or 10% of the maximum width of the opening; or, the thickness of the copper nitride layer is 2 nm to 20 mm.
[0016] Optionally, before forming the copper nitride layer, a barrier layer is formed on the inner surface of the opening, wherein the copper nitride layer is formed on the surface of the barrier layer.
[0017] Optionally, the barrier layer is a TiN / Ti layer or a TaN / Ta layer.
[0018] In another aspect, the present invention provides a semiconductor device, comprising:
[0019] A semiconductor structure, the semiconductor structure comprising a lower conductive layer formed on a substrate and an interlayer dielectric layer located above the lower conductive layer, the lower conductive layer and the opening having at least a partially overlapping area in a top view; and
[0020] An electrical connection metal layer fills the opening, and an air gap exists between a side wall of the electrical connection metal layer and the interlayer dielectric layer in the opening.
[0021] Optionally, the opening is a through hole penetrating the interlayer dielectric layer, and the electrically connected metal layer is electrically connected to the underlying conductive layer through the through hole; or, the opening includes a groove formed on the upper portion of the interlayer dielectric layer and a through hole penetrating the interlayer dielectric layer from the bottom surface of the groove, and the electrically connected metal layer is electrically connected to the underlying conductive layer through the through hole.
[0022] Optionally, the width of the air gap is smaller than 20% or 15% or 10% of the maximum width of the opening; or, the width of the air gap is 2 nm to 20 mm.
[0023] Optionally, the semiconductor device further includes:
[0024] A barrier layer covers the inner surface of the opening, and the air gap is formed between the side wall of the electrical connection metal layer and the barrier layer.
[0025] Optionally, there is a copper film and / or copper particles between the sidewall of the electrical connection metal layer and the barrier layer.
[0026] Optionally, in the above manufacturing method or semiconductor device, the barrier layer is a TiN / Ti stack or a TaN / Ta stack.
[0027] Optionally, in the above manufacturing method or semiconductor device, the electrical connection metal layer includes at least one of copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, cobalt, copper alloy, tungsten alloy, or aluminum alloy.
[0028] In the manufacturing method of the semiconductor device provided by the present invention, an opening having at least a partial overlapping area with the lower conductive layer in a top view is formed in the interlayer dielectric layer, and then a copper nitride layer is deposited on the inner surface of the opening and filled with metal material. After a flattening process, the remaining metal material is located in the opening to form an electrically connected metal layer, and then the copper nitride layer is heated to decompose the copper nitride layer into copper and nitrogen, so that in the opening, an air gap is formed between the side wall of the electrically connected metal layer and the interlayer dielectric layer, and the air gap helps to reduce the parasitic capacitance between the electrically connected metal parts located on both sides of the air gap and between the electrically connected metal parts and the conductive parts (such as the gate of the MOS tube) in the surface area of the substrate, reduce RC delay, increase the electron migration rate, and improve the chip processing speed. In addition, the manufacturing method does not need to form additional grooves, and will not significantly increase the process complexity. The copper nitride layer is prepared by a deposition process, and the thickness of the film can be well controlled, that is, the width of the air gap can be well controlled, so that the air gap width is small, does not affect the overall structure of the device, and does not increase the area of the device due to the setting of the air gap, so it does not affect the component density and chip integration.
[0029] In the semiconductor device provided by the present invention, an air gap is provided between the side wall of the electrically connected metal layer formed in the opening of the interlayer dielectric layer and the interlayer dielectric layer. The air gap helps to reduce the parasitic capacitance between the electrically connected metal parts located on both sides of the air gap and between the electrically connected metal parts and the conductive parts in the surface area of the substrate, thereby helping to reduce RC delay, increase the electron migration rate, and improve the chip processing speed without affecting the component density and chip integration. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0031] FIG. 2A to FIG. 2E is a schematic cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0032] The semiconductor device and the method for manufacturing the same of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the accompanying drawings is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.
[0033] By reducing the dielectric constant of the capacitor dielectric layer, the capacitance of the corresponding capacitor can be reduced. In the manufacturing process of semiconductor devices, a low-k dielectric layer and / or an air gap is used as a capacitor dielectric layer to reduce the parasitic capacitance formed between the electrically connected metal parts and between the electrically connected metal parts and the gate of the MOS tube, which helps to improve chip performance. The embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device. The manufacturing method can form an air gap on a substrate, which helps to reduce the parasitic capacitance, and, compared with the existing method, does not significantly increase the process complexity and basically does not affect the chip integration. The following is combined with Figure 1 as well as FIG. 2A to FIG. 2E A method for manufacturing a semiconductor device according to an embodiment of the present invention is described.
[0034] Reference Figure 1 and Figure 2AIn the manufacturing method, step S1 includes: providing a semiconductor structure, the semiconductor structure includes a lower conductive layer 100 formed on a substrate and an interlayer dielectric layer 110 located above the lower conductive layer 100. It is worth noting that the lower conductive layer 100 and the upper interlayer dielectric layer 110 may be in direct contact, or there may be one or more other dielectric layers between the lower conductive layer 100 and the upper interlayer dielectric layer 110, such as silicon oxide, silicon nitride, SiON, etc. Step S2 includes: forming an opening 101 in the interlayer dielectric layer 110, and the lower conductive layer 100 and the opening 101 have at least a partially overlapping area in a top view. Figure 2A The substrate is not shown.
[0035] The semiconductor structure is a structure based on a substrate after some device manufacturing steps (such as deposition, etching, ion implantation, etc.) have been completed. The substrate may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), etc. As an example, the substrate is a silicon wafer. In one embodiment, the semiconductor structure is a structure that has completed the semiconductor front-end process but has not yet undergone the back-end process, wherein electronic components such as MOS transistors are formed on the surface area of the substrate, and the lower conductive layer 100 is, for example, a polysilicon layer or a metal layer constituting the gate of the MOS transistor. However, it is not limited to this. As an example, in this embodiment, the semiconductor structure has completed the semiconductor front-end process and part of the back-end process, wherein electronic components are formed on the surface of the substrate, and at least one electrically connected metal layer has been formed on the substrate, and the lower conductive layer 100 is one of the electrically connected metal layers.
[0036] The interlayer dielectric layer 110 is used to form isolation between the lower conductive layer 100 and the electrical connection metal layer to be formed when an electrical connection metal layer is formed on the lower conductive layer 100. The material of the interlayer dielectric layer 110 can be selected as required. In order to reduce the parasitic capacitance in the semiconductor device, the interlayer dielectric layer 110 preferably includes a low-k dielectric material. As an example, the interlayer dielectric layer 110 includes silicon oxide.
[0037] like Figure 2A As shown, through step S2, the opening 101 formed in the interlayer dielectric layer 110 exposes at least a portion of the underlying conductive layer 100, and after a conductive material is subsequently formed in the opening 101, the conductive material is electrically connected to the underlying conductive layer 100 to form an interconnection.
[0038] The opening 101 may be formed in the interlayer dielectric layer 110 by a patterning process, and the shape of the opening 101 may be different according to the structure of the electrically connected metal layer to be formed in the opening 101. As an example, the opening 101 is a through hole penetrating the interlayer dielectric layer 110, and the through hole exposes a partial area of the underlying conductive layer 100. The present invention is not limited thereto. In another embodiment, the opening 101 includes a groove formed in the upper part of the interlayer dielectric layer 110 and a through hole penetrating the interlayer dielectric layer 110 from the bottom surface of the groove, and the through hole exposes a partial area of the underlying conductive layer 100, and the groove, for example, extends in a plane parallel to the surface of the substrate to form a pattern.
[0039] Reference Figure 1 and Figure 2B In the manufacturing method, step S3 includes: depositing a copper nitride layer 130 on the inner surface of the opening 101 .
[0040] The copper nitride layer 130 is used to form an air gap between the sidewall of the electrical connection metal layer subsequently formed in the opening 101 and the interlayer dielectric layer 110. In this embodiment, before depositing the copper nitride layer 130, a barrier layer 120 is first formed along the top surface of the interlayer dielectric layer 110 and the inner surface of the opening 101. The barrier layer 120 can be used to block the copper in the copper nitride layer 130 and the metal material subsequently formed in the opening 101 from entering the interlayer dielectric layer 110 or the underlying structure. By selecting a suitable barrier layer 120 material, the barrier layer 120 can be used to improve the adhesion of the copper nitride layer 130. The barrier layer 120 is, for example, a TiN / Ti layer (i.e., a stack of a titanium nitride layer and a titanium layer) or a TaN / Ta layer (i.e., a stack of a tantalum nitride layer and a tantalum layer).
[0041] The barrier layer 120, for example, conformally covers the top surface of the interlayer dielectric layer 110 and the inner surface of the opening 101. The copper nitride layer 130, for example, conformally covers the surface of the barrier layer 120. The copper nitride layer 130 can be formed by physical and chemical vapor deposition (PVD) or atomic layer deposition (ALD) process. The thickness of the copper nitride layer 130 is greater than 0, and the thickness of the copper nitride layer 130 is, for example, less than 20% of the maximum width of the opening 101 (the width direction of the opening is parallel to the top surface of the interlayer dielectric layer 110), or the thickness of the copper nitride layer 130 is, for example, less than 15% of the maximum width of the opening 101, or the thickness of the copper nitride layer 130 is, for example, less than 10% of the maximum width of the opening 101, or the thickness of the copper nitride layer 130 is, for example, greater than 0 and less than or equal to 15nm, or the thickness of the copper nitride layer 130 is, for example, 2nm to 20mm (i.e., greater than or equal to 2nm and less than or equal to 20mm). The deposition process and thickness of the copper nitride layer 130 can be set according to specific needs.
[0042] Reference Figure 1 and Figure 2C In the manufacturing method, step S4 includes: depositing a metal material 140 so that the metal material 140 fills the opening 101 and covers the interlayer dielectric layer 110 .
[0043] The metal material 140 is used to form an electrically connected metal layer located in the opening 101 and electrically connected to the lower conductive layer, and a suitable metal can be selected according to specific needs. Optionally, the metal material 140 may include at least one of a single metal (such as copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, cobalt, etc.) or an alloy (such as a copper alloy, a tungsten alloy or an aluminum alloy, etc.). In this embodiment, as an example, the metal material 140 is copper, and copper can be deposited in the opening 101 and on the interlayer dielectric layer 110 by electroplating or chemical plating. In this embodiment, the metal material 140 covers the surface of the copper nitride layer 130, and the top surface of the metal material 140 is higher than the top surface of the interlayer dielectric layer 110.
[0044] In order to improve the compactness of the metal material 140 and improve the quality of the subsequent planarization process, thermal annealing can be performed optionally before the subsequent process. The annealing temperature of the thermal annealing is lower than the temperature at which the copper nitride layer 130 decomposes. The annealing temperature of the thermal annealing is, for example, 150°C to 190°C (more specifically, for example, 180°C), and the annealing temperature is maintained for about 30s to 90s.
[0045] Reference Figure 1 and Figure 2D In the manufacturing method, step S5 includes: performing a planarization process to remove the metal material 140 outside the opening 101 , and the remaining metal material 140 forms an electrical connection metal layer 140 a located in the opening 101 .
[0046] By performing the planarization process, the top surface of the copper nitride layer 130 located on the side wall of the opening 101 can be exposed, so as to facilitate the release of nitrogen formed when the copper nitride layer 130 is subsequently decomposed. The planarization process is, for example, a CMP (chemical mechanical polishing) process. When the metal material 140 outside the opening 101 is removed by the CMP process, the copper nitride layer 130 or the barrier layer 120 can be used as a polishing stop layer. In this embodiment, the copper nitride layer 130 and the barrier layer 120 located above the top surface of the interlayer dielectric layer 110 can be removed by setting polishing parameters. After the planarization process, the remaining metal material 140 forms an electrical connection metal layer 140a located in the opening 101, and the electrical connection metal layer 140a is electrically connected to the lower conductive layer 100 exposed by the opening 101. Optionally, the opening 101 is a through hole penetrating the interlayer dielectric layer 110, and the electrical connection metal layer 140a is electrically connected to the lower conductive layer 100 through the through hole (in this embodiment, a TiN / Ti layer (as a barrier layer 120) is formed between the electrical connection metal layer 140a and the lower conductive layer 100, and the TiN / Ti layer is electrically connected to the electrical connection metal layer 140a and the lower conductive layer 100, respectively, so that the electrical connection metal layer 140a is electrically connected to the lower conductive layer 100), and the electrical connection metal layer 140a is, for example, a conductive plug formed in the through hole. The present invention is not limited to this. In another embodiment, the opening includes a groove formed on the upper part of the interlayer dielectric layer 110 and a through hole penetrating the interlayer dielectric layer 110 from the bottom surface of the groove, and the electrical connection metal layer 130a fills the groove and the through hole, and is electrically connected to the lower conductive layer 100 through the through hole.
[0047] Reference Figure 1 and Figure 2E In the manufacturing method, step S6 includes: heating the copper nitride layer 130 to decompose the copper nitride layer 130 into copper and nitrogen, so that an air gap 10 is formed between the side wall of the electrical connection metal layer 140a and the interlayer dielectric layer 110 in the opening 101.
[0048] The chemical reaction formula of the copper nitride layer 130 decomposing under heat is shown in formula (1):
[0049]
[0050] Formula (1) shows that copper nitride (Cu3N) will decompose at an appropriate heating temperature to form solid copper and gaseous nitrogen. The heating temperature is, for example, 200°C to 500°C, 200°C to 300°C, or 300°C to 450°C.
[0051] In the present embodiment, since a copper nitride layer 130 is formed between the electrical connection metal layer 140a and the interlayer dielectric layer 110 (more specifically, between the electrical connection metal layer 140a and the barrier layer 120) in the opening 101, the copper nitride layer 130 can be decomposed into copper and nitrogen by heating the copper nitride layer 130 at an appropriate temperature. The nitrogen is released from between the electrical connection metal layer 140a and the barrier layer 120 to the outside of the opening 101, and an air gap 10 is formed between the side wall of the electrical connection metal layer 140a and the barrier layer 120. The copper 130a generated by the decomposition is distributed in the gap between the electrical connection metal layer 140a and the barrier layer 120 to form a copper film and / or copper particles. The copper film and / or copper particles are, for example, attached to the surface of the barrier layer 120 or the surface of the electrical connection metal layer 140a, and can also be formed between the barrier layer 120 and the electrical connection metal layer 140a. Depending on the heating temperature and time, the copper 130a generated by decomposition can be concentrated in the gap between the electrical connection metal layer 140a and the interlayer dielectric layer 110, for example, concentratedly deposited at the bottom of the opening 101, but can also be dispersed in the gap, for example, the copper 130a generated by decomposition and the air gap 10 can form a honeycomb structure in the gap between the electrical connection metal layer 140a and the barrier layer 120. Therefore, the air gap 10 described in the present invention refers to the gap between the interlayer dielectric layer 110 or the barrier layer 120 and the electrical connection metal layer 140a, and the gap can be a continuous gap or a discontinuous gap formed by the presence of copper particles and / or copper films formed by decomposition in the gap. The width of the air gap 10 is, for example, close to or equal to the thickness of the copper nitride layer 130 (the width of the air gap 10 refers to the size of the air gap 10 along the thickness direction of the copper nitride layer 130). As an example, the width of the air gap 10 is less than 20% or 15% or 10% of the maximum width of the opening 101; or, the width of the air gap 10 is 2nm to 20mm, or, the width of the air gap 10 is greater than 0 and less than or equal to 15nm.
[0052] In order to heat the copper nitride layer 130 to decompose it, the semiconductor structure after the planarization process may be placed on a hot plate or a furnace tube for heating, but it is not limited thereto, and other heating methods may also be used. In this embodiment, in order to facilitate the timely release of nitrogen generated after the decomposition of the copper nitride layer 130 located below the opening 101, it is preferred that the copper nitride layer 130 located at the upper position in the opening 101 decomposes earlier than the copper nitride layer 130 located at the lower position. To this end, the heating source can be placed above the copper nitride layer 130, that is, the heating source is placed on the side of the copper nitride layer 130 away from the interlayer dielectric layer 110. In this way, when heated, the copper nitride layer 130 close to the heating source reaches the decomposition temperature and decomposes first, and forms an air gap in the upper part of the opening 101 after releasing nitrogen. Thereafter, the copper nitride layer 130 farther away from the heating source reaches the decomposition temperature and decomposes, and the generated nitrogen can be released to the outside of the opening 101 through the air gap that has been formed in the upper part of the opening 101, until the copper nitride layer 130 is completely decomposed, and an air gap 10 is formed between the side wall of the electrical connection metal layer 140a and the interlayer dielectric layer 110.
[0053] After the air gap 10 is formed in the opening 101, a dielectric material can be further covered on the interlayer dielectric layer 110 and other electrical connection metal layers can be further formed on the electrical connection metal layer 140a. When the dielectric material is formed, since the width of the air gap 10 formed in the opening 101 is small, it will not be filled by the dielectric material, so the air gap 10 will remain in the manufactured semiconductor device. In addition, the copper nitride layer 130 is prepared by a deposition process, which can well control the thickness of the film, that is, it can well control the width of the generated air gap 10, so that the width of the air gap 10 is small, which does not affect the overall structure of the device, and the area of the device will not be increased due to the provision of the air gap 10, so it will not affect the density of components and the integration of the chip.
[0054] In the method for manufacturing a semiconductor device described in the above embodiment, an opening 101 is formed in the interlayer dielectric layer 110, which has at least a partial overlap area with the lower conductive layer 100 in a top view, and then a copper nitride layer 130 is deposited in the opening 101 and filled with a metal material 140. After a planarization process, the remaining metal material 140 is located in the opening 101 to form an electrically connected metal layer 140a. Then, the copper nitride layer 130 is heated to decompose the copper nitride layer 130 into copper and nitrogen, so that the electrically connected metal layer 140a is formed in the opening 101. An air gap 10 is formed between the side wall of 140a and the interlayer dielectric layer 110, and the air gap 10 helps to reduce the parasitic capacitance between the electrically connected metal parts located on both sides of the air gap 10 (for example, the upper and lower sides or the left and right sides) and between the electrically connected metal parts and the conductive parts in the surface area of the substrate (such as the gate of the MOS tube), thereby reducing RC delay, increasing the electron migration rate, and improving the chip processing speed. In addition, the manufacturing method does not require the formation of additional grooves on the substrate, will not significantly increase the process complexity, and will not affect the component density and chip integration.
[0055] The embodiment of the present invention further relates to a semiconductor device, which can be formed by using the manufacturing method of the semiconductor device in the above embodiment. Figure 2E As shown, the semiconductor device includes a semiconductor structure and an electrically connected metal layer 140a, the semiconductor structure includes a lower conductive layer 100 formed on a substrate (not shown) and an interlayer dielectric layer 110 located on the upper layer of the lower conductive layer 100, the lower conductive layer 100 and the opening 101 have at least a partially overlapping area when viewed from a top view, the electrically connected metal layer 140a fills the opening 101, and, in the opening 101, an air gap 10 is provided between the side wall of the electrically connected metal layer 140a and the interlayer dielectric layer 110.
[0056] The opening 101 may be a through hole penetrating the interlayer dielectric layer 110, and the electrical connection metal layer 140a is electrically connected to the lower conductive layer 100 through the through hole. However, the present invention is not limited thereto. In another embodiment, the opening 101 includes a groove formed on the upper portion of the interlayer dielectric layer 110 and a through hole penetrating the interlayer dielectric layer 110 from the bottom surface of the groove, and the electrical connection metal layer 140a is electrically connected to the lower conductive layer 100 through the through hole.
[0057] like Figure 2EAs shown, the semiconductor device may further include a barrier layer 120, the barrier layer 120 covers the inner surface of the opening 101, and the air gap 10 is formed between the side wall of the electrical connection metal layer 140a and the barrier layer 120. In addition, a copper film and / or copper particles may also exist between the side wall of the electrical connection metal layer 140a and the barrier layer 120. The copper film and / or copper particles may be attached to the surface of the electrical connection metal layer 140a facing the barrier layer 120 and / or the surface of the barrier layer 120 facing the electrical connection metal layer 140a, or may be located in the gap between the electrical connection metal layer 140a and the barrier layer 120. The copper film and / or copper particles may be concentrated at the bottom of the opening 101, or may be dispersed between the electrical connection metal layer 140a and the barrier layer 120 in the opening 101. For example, the copper film and / or copper particles and the air gap 10 may form a honeycomb structure between the electrical connection metal layer 140a and the barrier layer 120.
[0058] In the semiconductor device, an air gap 10 is provided between the sidewall of the electrical connection metal layer 140a formed in the opening 101 of the interlayer dielectric layer 110 and the interlayer dielectric layer 110. The air gap 10 helps to reduce the parasitic capacitance between the electrical connection metal parts located on both sides of the air gap 10 and between the electrical connection metal parts and the conductive parts (such as the gate of the MOS tube) in the surface area of the substrate, thereby reducing RC delay, increasing the electron migration rate, and improving the chip processing speed without affecting the chip integration.
[0059] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor structure is provided, the semiconductor structure comprising a lower conductive layer formed on a substrate and an interlayer dielectric layer located above the lower conductive layer; An opening is formed in the interlayer dielectric layer, wherein the lower conductive layer and the opening have at least a partially overlapping area in a top view; Depositing a copper nitride layer on the inner surface of the opening; Depositing a metal material so that the metal material fills the opening and covers the interlayer dielectric layer; Performing a planarization process to remove the metal material outside the opening, and the remaining metal material forms an electrical connection metal layer located in the opening; as well as The copper nitride layer is heated to decompose the copper nitride layer into copper and nitrogen, so that an air gap is formed between the sidewall of the electrical connection metal layer and the interlayer dielectric layer in the opening.
2. The manufacturing method according to claim 1, characterized in that Before performing the planarization process, the method further includes: Thermal annealing is performed, wherein the annealing temperature of the thermal annealing is lower than a temperature at which the copper nitride layer decomposes.
3. The manufacturing method according to claim 2, characterized in that: The annealing temperature of the thermal annealing is 150°C to 190°C.
4. The manufacturing method according to claim 1, characterized in that: When heating the copper nitride layer, a heating source is located above the copper nitride layer.
5. The manufacturing method according to claim 1, characterized in that: When the copper nitride layer is heated to decompose the copper nitride layer into copper and nitrogen, the heating temperature is 200°C to 500°C, 200°C to 300°C, or 300°C to 450°C.
6. The manufacturing method according to claim 1, characterized in that: The thickness of the copper nitride layer is less than 20% or 15% or 10% of the maximum width of the opening; or, the thickness of the copper nitride layer is 2nm to 20mm; or, the thickness of the copper nitride layer is greater than 0 and less than or equal to 15nm.
7. The manufacturing method according to any one of claims 1 to 6, characterized in that: Before forming the copper nitride layer, a barrier layer is formed on the inner surface of the opening, wherein the copper nitride layer is formed on the surface of the barrier layer.
8. A semiconductor device, characterized in that: include: A semiconductor structure, the semiconductor structure comprising a lower conductive layer formed on a substrate and an interlayer dielectric layer located above the lower conductive layer, wherein the lower conductive layer and the opening have at least a partially overlapping area in a top view; as well as An electrical connection metal layer fills the opening, and an air gap exists between a side wall of the electrical connection metal layer and the interlayer dielectric layer in the opening.
9. The semiconductor device according to claim 8, characterized in that The opening is a through hole that penetrates the interlayer dielectric layer, and the electrically connected metal layer is electrically connected to the underlying conductive layer through the through hole; or, the opening includes a groove formed on the upper part of the interlayer dielectric layer and a through hole that penetrates the interlayer dielectric layer from the bottom surface of the groove, and the electrically connected metal layer is electrically connected to the underlying conductive layer through the through hole.
10. The semiconductor device according to claim 8, wherein The width of the air gap is less than 20% or 15% or 10% of the maximum width of the opening; or, the width of the air gap is 2nm to 20mm; or, the width of the air gap is greater than 0 and less than or equal to 15nm.
11. The semiconductor device according to claim 8, wherein Also includes: A barrier layer covers the inner surface of the opening, and the air gap is formed between the side wall of the electrical connection metal layer and the barrier layer.
12. The semiconductor device according to claim 11, wherein There is also a copper film and / or copper particles between the sidewall of the electrical connection metal layer and the barrier layer.
13. The manufacturing method according to claim 7 or the semiconductor device according to claim 11, characterized in that: The barrier layer is a TiN / Ti stack or a TaN / Ta stack.
14. The manufacturing method according to claim 1 or the semiconductor device according to claim 8, characterized in that: The electrical connection metal layer includes at least one of copper, nickel, zinc, tin, silver, gold, tungsten, magnesium, tantalum, titanium, molybdenum, platinum, aluminum, hafnium, ruthenium, cobalt, copper alloy, tungsten alloy, or aluminum alloy.