Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same. In one example, a semiconductor device may include: (a) an electronic device including a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side; (b) a first conductor comprising a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section; and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section may be higher than the device top side, and an upper surface of the first conductor bottom section may be lower than the device top side. Other examples and related methods are also disclosed herein.

Description

[0001] This application is a divisional application of an invention patent application with an application date of May 11, 2020, a priority date of May 22, 2019, an application number of 202010390048.3, and an invention name of “Semiconductor device and method for manufacturing a semiconductor device”. Technical Field

[0002] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0003] Previous semiconductor packages and methods of forming semiconductor packages have been inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of such methods will become apparent to those skilled in the art by comparing conventional and traditional methods with the present disclosure and referring to the accompanying drawings. Summary of the invention

[0004] In one aspect of the present invention, a semiconductor device comprises: an electronic device, the electronic device comprising: a device top side, the device top side comprising a device first terminal; a device bottom side, the device bottom side being opposite to the device top side; and a device first side wall, the device first side wall being between the device top side and the device bottom side; and a substrate, the substrate comprising: a dielectric material, the dielectric material comprising: a dielectric top section, the dielectric top section being above the device top side, wherein the dielectric top section comprises a dielectric first opening above the device first terminal; a dielectric side section, the dielectric side section being above the device first side wall and A semiconductor device is provided wherein the device bottom side defines a device bottom plane; the upper surface of the first conductive bottom segment is closer to the device bottom plane than the lower surface of the first conductive top segment. The semiconductor device is provided wherein the first conductive side segment is substantially orthogonal to the first conductive top segment and the first conductive bottom segment; and the first conductive side segment is provided wherein the first conductive top segment and the first conductive bottom segment are substantially non-overlapping. The semiconductor device further comprises: an encapsulation material over the substrate, forming a boundary of the device first sidewall, and comprising the encapsulation material first sidewall; wherein: the dielectric bottom segment comprises a dielectric first end exposed by the encapsulation material first sidewall and substantially coplanar with the encapsulation material first sidewall; and the first conductive bottom segment comprises a first conductive end point covered by the encapsulation material first sidewall, the first conductive end point being closer to the encapsulation material first sidewall than any other point of the first conductive bottom segment. The semiconductor device further comprises: an electronic component, the electronic component comprising: a component bottom side; a component first terminal, the component first terminal being on the component bottom side; and a component sidewall; and a first internal interconnect, the first internal interconnect being over the first conductive top segment and coupled to the component first terminal.In a semiconductor device, the electronic component includes: a component dielectric material, the component dielectric material is above the component bottom side and exposes the component first terminal; and a component conductive material, the component conductive material is above the component dielectric layer, extends laterally from the component first terminal, and couples the component first terminal to the first internal interconnect. The semiconductor device further includes: an encapsulation material, the encapsulation material extends between the component bottom side and the substrate, forms a boundary of the device first sidewall and the first internal interconnect, and includes an encapsulation material first sidewall; wherein the encapsulation material first sidewall is substantially coplanar with the component sidewall and the dielectric first layer of the substrate. In the semiconductor device, the component first terminal is coupled to the device first terminal through the dielectric first opening through the first internal interconnect and the first conductive top segment. In the semiconductor device, the first internal interconnect is laterally offset from the component first terminal and the device first terminal. The semiconductor device further comprises: a first external interconnection, the first external interconnection being on the bottom of the substrate; wherein the component first terminal is coupled to the first external interconnection through the first internal interconnection, the first conductive top section, the first conductive side section and the first conductive bottom section of the substrate. In the semiconductor device, the component first terminal is coupled to the device first terminal through the first internal interconnection and the first conductive top section through the dielectric first opening. In the semiconductor device, the electronic device comprises: a device second sidewall, the device second sidewall being between the device top side and the device bottom side; the dielectric side section extending over the device second sidewall; the substrate comprising a second conductive material, the second conductive material comprising: a second conductive top section, the second conductive top section being over the dielectric top section; a second conductive side section, the second conductive side section being over the dielectric side section, over the device second sidewall and connected to the second conductive top section; and a second conductive bottom section, the second conductive bottom section being over the dielectric bottom section and connected to the second conductive side section.The semiconductor device further includes: an electronic component, the electronic component including: a component bottom side; a component first terminal, the component first terminal is on the component bottom side; a component second terminal, the component second terminal is on the component bottom side; and a component sidewall; a first internal interconnect, the first internal interconnect is coupled to the component first terminal; a second internal interconnect, the second internal interconnect is coupled to the component second terminal; a first external interconnect, the first external interconnect is on the bottom of the substrate; and a second external interconnect, the second external interconnect is on the bottom of the substrate; wherein: the component first terminal is coupled to the device first terminal through the dielectric first opening through the first internal interconnect and the first conductive top segment; the component second terminal is coupled to the second external interconnect through the second internal interconnect, the second conductive top segment, the second conductive side segment, and the second conductive bottom segment.

[0005] In another aspect of the present invention, a semiconductor device comprises: an electronic device, the electronic device comprising: a device top side; a device bottom side, the device bottom side being opposite to the device top side; and a device side wall, the device side wall being between the device top side and the device bottom side; a first conductor, the first conductor comprising: a first conductor side segment, the first conductor side segment being on the device side wall; a first conductor top segment, the first conductor top segment being on the device top side and coupled to the first conductor side segment; and a first conductor bottom segment, the first conductor bottom segment being coupled to the first conductor side segment; and a protective material, the protective material covering the first conductor and the electronic device; wherein: a lower surface of the first conductor top segment is higher than the device top side; and an upper surface of the first conductor bottom segment is lower than the device top side. The semiconductor device further comprises: an external interconnect coupled to the first conductor bottom segment and exposed by the protective material; an electronic component comprising: a component bottom side; and a component first terminal, the component first terminal on the component bottom side; and a first internal interconnect coupled to the component first terminal and the first conductor top segment; wherein the component first terminal is coupled to the external interconnect through the first internal interconnect, the first conductor top segment, the first conductor side segment, and the first conductor bottom segment. In the semiconductor device, the electronic device comprises a device first terminal on the device top side; and the component first terminal is coupled to the device first terminal through the first internal interconnect and the first conductor top segment. The semiconductor device further comprises: a dielectric between the electronic device and the first conductor; wherein: the protective material comprises a protective sidewall; the electronic component comprises a component sidewall exposed by and coplanar with the protective sidewall; and the dielectric comprises a dielectric sidewall exposed by and coplanar with the protective sidewall. The semiconductor device further comprises: a dielectric between the electronic device and the first conductor; wherein the device bottom side is exposed by the dielectric.

[0006] In yet another aspect of the present invention, a method includes: providing an electronic device, the electronic device including: a device top side, the device top side including a device first terminal; a device bottom side, the device bottom side opposite to the device top side; and a device first side wall, the device first side wall between the device top side and the device bottom side; and providing a dielectric, the dielectric including: a dielectric top section, the dielectric top section above the device top side, wherein the dielectric top section includes a dielectric first opening above the device first terminal; a dielectric side section, the dielectric side section above the device first side wall and connected to the dielectric top section; and a dielectric bottom section, the dielectric bottom section connected to the dielectric side section; wherein: a lower surface of the dielectric bottom section is substantially coplanar with the device bottom side; and an upper surface of the dielectric bottom section is lower than an upper surface of the dielectric top section. The method further includes: providing a conductor, the conductor comprising: a conductor top segment, the conductor top segment being above the dielectric top segment; a conductor side segment, the conductor side segment being above the dielectric side segment and connected to the first conductive top segment; and a conductor bottom segment, the conductor bottom segment being above the dielectric bottom segment and connected to the first conductive side segment; providing an electronic component, the electronic component comprising: a component bottom side; and a component first terminal, the component first terminal being on the component bottom side; coupling a first internal interconnect to the component first terminal and the conductor top segment; and coupling an external interconnect with the conductor bottom segment through the dielectric bottom segment; wherein: providing the dielectric includes: providing the dielectric conforming to the outline of the electronic device; providing the conductor includes: providing the conductor conforming to the outline of the dielectric and the electronic device; and providing a portion of the conductor top segment passing through the dielectric first opening and coupled to the device first terminal; and coupling the external interconnect includes: coupling the component first terminal with the external interconnect through the first internal interconnect, the conductor top segment, the conductor side segment, and the conductor bottom segment.The method further includes: providing a conductor, the conductor comprising: a conductor top segment, the conductor top segment being above the dielectric top segment; a conductor side segment, the conductor side segment being above the dielectric side segment and connected to the first conductive top segment; and a conductor bottom segment, the conductor bottom segment being above the dielectric bottom segment and connected to the first conductive side segment; and providing an encapsulant over the conductor, the dielectric, and the electronic device; wherein: providing the dielectric includes: providing the dielectric conforming to the contour of the electronic device; providing the conductor includes: providing the conductor conforming to the contour of the dielectric and the electronic device; and providing a portion of the conductor top segment passing through the dielectric first opening and coupled to the device first terminal; and providing the encapsulant includes: providing a bottom of the encapsulant conforming to the conductor top segment, the conductor side segment, and the conductor bottom segment. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0008] Figures 2A to 2H A cross-sectional view illustrating an example method of manufacturing an example semiconductor device.

[0009] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0010] The drawings illustrate the general manner of construction, and may omit descriptions and details of well-known features and techniques so as not to unnecessarily obscure the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the size of some elements in the drawings may be enlarged relative to other elements in order to improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different drawings represent the same elements.

[0011] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0012] The terms “comprising” and / or “including” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0013] The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0014] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly connected to element B through an intervening element C. Similarly, the terms "on..." or "over..." may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. DETAILED DESCRIPTION

[0015] In one example, a semiconductor device may include: (a) an electronic device including a device top side including a device first terminal, a device bottom side opposite the device top side, and a device first sidewall between the device top side and the device bottom side; and (b) a substrate. The substrate may include a dielectric material including: (a) a dielectric top segment above the device top side, wherein the dielectric top segment includes a dielectric first opening above the device first terminal; (b) a dielectric side segment above the device first sidewall and connected to the dielectric top segment; and (c) a dielectric bottom segment including a lower surface that is substantially coplanar with the device bottom side and connected to the dielectric side segment. The substrate may also include a first conductive material, the first conductive material including: (a) a first conductive top segment, the first conductive top segment being above the dielectric top segment and coupled to the device first terminal through the dielectric first opening; (b) a first conductive side segment, the first conductive side segment being above the dielectric side segment and connected to the first conductive top segment; and (c) a first conductive bottom segment, the first conductive bottom segment being above the dielectric bottom segment and connected to the first conductive side segment.

[0016] In one example, a semiconductor device may include: (a) an electronic device including a device top side, a device bottom side opposite to the device top side, and a device sidewall between the device top side and the device bottom side; (b) a first conductor including a first conductor side segment on the device sidewall, a first conductor top segment on the device top side and coupled to the first conductor side segment, and a first conductor bottom segment coupled to the first conductor side segment; and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top segment may be higher than the device top side, and an upper surface of the first conductor bottom segment may be lower than the device top side.

[0017] In one example, a method may include: (a) providing an electronic device, the electronic device including a device top side including a device first terminal, a device bottom side opposite the device top side, and a device first sidewall between the device top side and the device bottom side; and (b) providing a dielectric including a dielectric top section above the device top side, wherein the dielectric top section includes a dielectric first opening above the device first terminal, a dielectric side section above the device first sidewall and connected to the dielectric top section, and a dielectric bottom section connected to the dielectric side section. The lower surface of the dielectric bottom section may be substantially coplanar with the device bottom side. The upper surface of the dielectric bottom section may be lower than the upper surface of the dielectric top section.

[0018] Other examples are included in the present disclosure. Such examples can be found in the drawings, claims, and / or description of the present disclosure.

[0019] Figure 1 A cross-sectional view of an example semiconductor device 100 is shown. Figure 1 In the example shown in , the semiconductor device 100 may include an electronic device 110 , an electronic component 130 , substrates 120 and 140 , interconnects 150 and 170 , and an encapsulation material 160 .

[0020] The electronic device 110 may include a terminal 111. The terminal 111 may be formed on a top surface of the electronic device 110. The substrate 120 may include a dielectric structure 121 and a conductive structure 122. The conductive structure 122 may be electrically connected to the terminal 111 of the electronic device 110.

[0021] The electronic component 130 may include a terminal 131. The terminal 131 may be formed on the bottom surface of the electronic component 130. The substrate 140 may include a dielectric structure 141 and a conductive structure 142. The conductive structure 142 may be electrically connected to the terminal 131 of the electronic component 130. The substrate 140 may be formed on the bottom surface of the electronic component 130.

[0022] The interconnect 150 may be formed of a conductive material and may electrically connect the conductive structure 142 and the conductive structure 122. The interconnect 170 may be formed of a conductive material and may be formed on the bottom surface of the substrate 140. The interconnect 170 may be electrically connected to the conductive structure 142. The encapsulant 160 may be interposed between the top surface of the substrate 120 and the bottom surface of the substrate 140.

[0023] Substrates 120 and 140, interconnects 150 and 170, and encapsulant 160 may include or be referred to as semiconductor package 101, which may provide protection for electronic device 110 and electronic component 130 from external elements and / or environmental exposure. In addition, semiconductor package 101 may provide electrical coupling between external electrical components and terminals 111 and 131.

[0024] Figures 2A to 2H A cross-sectional view illustrating an example method of manufacturing the semiconductor device 100 .

[0025] Figure 2A 1 shows a cross-sectional view of a semiconductor device 100 at an early stage of manufacture. Figure 2A In the example shown in FIG. 1 , the electronic device 110 may be mounted on the top surface 10a of the bracket 10. Here, a portion of the top surface 10a of the bracket 10 may be exposed. Examples of the bracket 10 may include silicon, low-grade silicon, glass, silicon carbide, sapphire, quartz, ceramics, metal oxides, metals, and the like.

[0026] The device bottom side 110b of the electronic device 110 may be secured to the top surface 10a of the bracket 10, for example, using an adhesive between the device bottom side 110b and the top surface 10a. In some examples, the adhesive may be a liquid epoxy adhesive, an adhesive film, or an adhesive tape.

[0027] In some examples, the electronic device 110 may include or be referred to as an electronic component, a semiconductor die, or a semiconductor package. The electronic device 110 may include, for example, a semiconductor material such as silicon (Si). The electronic device 110 may include a plurality of terminals 111 disposed on its device top side 110a. The electronic device 110 may include passive electronic circuits and / or active electronic circuits such as transistors. The electronic device 110 may have a thickness in the range of about 75 μm to about 775 μm. The bracket 10 may facilitate the handling of the electronic device 110 and may protect the electronic device 110 in the following manufacturing processes.

[0028] In some examples, the terminal 111 may include or be referred to as a die pad. The terminal 111 may include, for example, a conductive material such as a metal material, aluminum, copper, an aluminum alloy, or a copper alloy.

[0029] Figure 2B 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacturing. Figure 2B In the example shown in FIG. 1 , a dielectric structure 121 of substantially uniform thickness may be formed to cover the top surface 10a of the bracket 10 and the exposed surface of the electronic device 110. The dielectric structure 121 includes a substantially horizontal dielectric top section 121a above the device top side 110a, a substantially horizontal dielectric bottom section 121b extending above the bracket 10 or the device bottom plane 110p, and a substantially vertical dielectric side section 121c above the device sidewall 110c. The device bottom plane 110p may be defined by the device bottom side 110b. The upper surface of the dielectric bottom section 121b may be exposed by the dielectric top section 121a. The lower surface of the dielectric bottom section 121b may be substantially coplanar with the device bottom side 110b. The upper surface of the dielectric bottom section 121b can be lower than the upper surface of the dielectric top section 121a, or lower than the lower surface of the dielectric top section 121a. The dielectric top section 121a and the dielectric bottom section 121b can each be connected or connected to the dielectric side section 121c. The dielectric 121 can be applied or formed in a conformal manner with the bracket 10 and the electronic device 110 so as to obtain or conform to the contour or combined shape of the electronic device 110 and the bracket 10.

[0030] The dielectric structure 121 may have a thickness in the range of 5 μm to 10 μm. In some examples, the dielectric structure 121 may include or be referred to as a dielectric, a dielectric layer, a dielectric material, a non-conductive material, or an insulator. The dielectric structure 121 may include, for example, an insulating material such as a polymer, a polyimide (PI), a benzocyclobutene (BCB), a polybenzoxazole (PBO), a bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy resin, a silicone, or an acrylate polymer. Examples of forming the dielectric structure 121 may include using spin coating, spray coating, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), sheet lamination, or evaporation.

[0031] Figure 2C 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacturing. Figure 2CIn the example shown in FIG. 1 , the opening 121x exposing the terminal 111 can be formed by patterning the dielectric structure 121. The opening 121y exposing a portion of the top surface 10a of the bracket 10 can also be formed at this stage. For example, after forming a mask pattern that exposes the dielectric structure 121 corresponding to the area of ​​the opening 121x and the opening 121y, such exposed areas of the dielectric structure 121 can be removed, for example, by etching, thereby forming the opening 121x and the opening 121y. A photoresist can be used as a mask pattern.

[0032] In some examples, openings 121x and 121y may include or be referred to as openings or through-holes. Opening 121x may have a smaller perimeter than terminal 111. Accordingly, dielectric structure 121 may cover or remain on a portion of the outer periphery of terminal 111. Opening 121y may have a planar dimension in the range of about 10 μm to about 100 μm.

[0033] Figure 2D 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacturing. Figure 2D In the example shown in FIG. 1 , a conductive structure 122 covering the opening 121 x , the opening 121 y , and the exposed surface of the dielectric structure 121 may be formed.

[0034] Conductive structure 122 may include or be referred to as one or more conductive materials, conductors or conductive layers, patterns or traces, such as conductors 122x, 122y and 122z. In the present example, conductors 122x, 122y and 122z may be formed by a single conductive layer, which may be defined by one or more conductive sublayers, for example, by a main sublayer above a seed sublayer. Conductors 122x, 122y or 122z may be similar to each other and may include a corresponding conductor top segment, a conductor side segment 122c or a conductor bottom segment 122b adjacent to a corresponding side of electronic device 110. Conductors 122x and 122y extend over device top side 110a of electronic device 110 and may have first terminal portions connected to corresponding terminals 111 exposed through corresponding openings 121x, respectively. Conductor 122x also has a second terminal portion exposed and / or extended through a corresponding opening 121y of dielectric structure 121. The first and second terminal portions of the conductor 122x are connected to each other through the conductive path of the conductor 122x. The conductor 122x is on the dielectric structure 121 and includes a conductor top section 122a extending generally horizontally above the dielectric top section 121a and the device top side 110a, a conductor side section 122c extending generally vertically above the dielectric side section 121c and the device side wall 110c, and a conductor bottom section 122b extending generally horizontally above the dielectric bottom section 121b and above the bracket 10 beyond the perimeter of the electronic device 110. The conductor top section 122a and the conductor bottom section 122b may each be connected or connected to the conductor side section 122c. In some examples, the conductor side section 122c may be generally orthogonal to the conductor top section 122a and the conductor bottom section 122b. In some examples, the conductor top segment 122a and the conductor bottom segment 122b do not substantially overlap each other. In some examples, the upper surface of the conductor bottom segment 122b may be closer to the device bottom plane 110p than the lower surface of the conductor top segment 122a. In some examples, the lower surface of the conductor top segment 122a may be higher than the device top side 110a, and the upper surface of the conductor bottom segment 122b may be substantially parallel to the lower surface of the conductor top segment 122a but lower than the device top side 110a.

[0035] The conductor 122z also extends and has a first terminal portion over the device top side 110a of the electronic device 110, but as shown in the present example, the conductor 122z need not be connected to the electronic device 110 or any of the terminals 111. The conductor 122z also has a second terminal portion that is exposed and / or extends through a corresponding opening 121y of the dielectric structure 121. The first and second terminal portions of the conductor 122z are connected to each other by a conductive path of the conductor 122z, wherein such conductive path is on the dielectric structure 121 and extends generally horizontally over the device top side 110a of the electronic device 110, extends generally vertically over the device side wall 110c of the electronic device 110, and extends generally horizontally over the bracket 10 to exceed the perimeter of the electronic device 110.

[0036] Although the present example is described with a single conductive structure 122 and a single dielectric structure 121 for simplicity, such elements may represent one or more conductive structures or layers and / or one or more dielectric structures or layers, respectively, that may be alternately stacked with one another. In the same or other examples, one or more portions of the conductive structure 122 may have or may be formed with one or more layers of one or more conductive materials stacked with one another.

[0037] Conductive structure 122 may have a thickness in a range of about 3 μm to about 10 μm. In some examples, conductive structure 122 may include a conductive material such as titanium (Ti), titanium-tungsten (TiW), copper (Cu), or alloys of Ti, TiW, or Cu.

[0038] Examples of forming conductive structure 122 may include using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma vapor deposition, electroless plating, or electrolytic plating. In some examples, PVD may include or be referred to as sputtering.

[0039] The conductors 122x, 122y or 122z of the conductive structure 122, or their corresponding conductor top segments 122a, conductor side segments 122c or conductor bottom segments 122b may be applied or formed simultaneously or in a conformal manner to the bracket 10 and the electronic device 110 so as to obtain or conform to the contour or combined shape of the dielectric 121, the electronic device 110 or the bracket 10.

[0040] Figure 2E 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacturing. Figure 2EIn the example shown in , the electronic component 130 may be mounted on the conductive structure 122, with a substrate 140 and an internal interconnect 150 on the bottom side 130b of the electronic component 130. The electronic component 130 may include what is referred to as an electronic device, a semiconductor die, a semiconductor package and / or an interposer. The electronic component 130 may include, for example, a semiconductor material such as silicon (Si). The electronic component 130 may include a plurality of terminals 131 disposed on its bottom side 130b. The electronic component 130 may include passive electronic circuits and / or active electronic circuits, such as transistors. The electronic component 130 may have a thickness in the range of about 75 μm to about 775 μm.

[0041] In addition, a substrate 140 and an interconnect 150 may be disposed on the bottom side 130b of the electronic component 130. The substrate 140 may include a dielectric structure 141 covering the bottom side 130b of the electronic component 130 and exposing the terminal 131, and a conductive structure 142 electrically connected to the terminal 131 exposed by the dielectric structure 141. In some examples, the substrate 140, the dielectric structure 141, and / or the conductive structure 142 may be similar to the substrate 120, the dielectric structure 121, and / or the conductive structure 122. The conductive structure 142 may have a plurality of conductors, patterns, or traces extending over the bottom side 130b of the electronic component 130. For example, each of component conductors 142x, 142y, and 142z can have a corresponding first terminal portion coupled to a corresponding interconnect 150, a corresponding second terminal portion coupled to a corresponding terminal 131 of electronic component 130 exposed through dielectric structure 141, and a corresponding conductive path connecting the corresponding first and second terminal portions of each of conductors 142x, 142y, and 142z together. In the present example, the corresponding interconnect 150 simultaneously couples conductor 142x to conductor 122x, conductor 142y to conductor 122y, and conductor 142z to conductor 122z. For example, interconnect 1501 is coupled to conductor top segment 122a and is coupled to component terminal 1311 through component conductor 142x. In addition, component terminal 1311 is coupled to device terminal 1111 through interconnect 1501, conductor top segment 122a, and dielectric opening 121x. In the present example, assembly dielectric structure 141 is located on assembly bottom side 130b such that assembly terminal 1311 is exposed, and conductor 142x extends laterally from assembly terminal 1311 over assembly dielectric structure 141 such that assembly terminal 1311 is laterally offset relative to interconnect 1501. In addition, internal interconnect 1501 is coupled along conductor top segment 122a such that it is laterally offset relative to device terminal 1111. In some examples, internal interconnect 150 can be coupled to respective conductors of conductive structure 142 and / or respective conductors of conductive structure 122 via respective terminals, such as pads and / or under bump metallization (UBM) formed on such respective conductors.

[0042] The conductive structure 142 constituting the substrate 140 together with the dielectric structure 141 may be a wiring for redistributing electrical connections of the terminals 131 of the electronic component 130. The conductive structure 142 may have a thickness in the range of about 3 μm to about 10 μm, and the dielectric structure 141 may have a thickness in the range of about 5 μm to about 10 μm.

[0043] The dielectric structure 141 may include or be referred to as, for example, one or more dielectric layers, non-conductive materials, or insulators. The dielectric structure 141 may include, for example, insulating materials such as polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, silicones, or acrylate polymers. Examples of forming the dielectric structure 141 may include using spin coating, spray coating, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), thin film lamination, or evaporation. In addition, the dielectric structure 141 may be exposed by etching a portion of the terminal 131 in which the electronic component 130 is formed.

[0044] In some examples, the conductive structure 142 may include a conductive material, such as titanium (Ti), titanium-tungsten (TiW), copper (Cu), or an alloy of Ti, TiW or Cu. Examples of forming the conductive structure 142 may include using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma vapor deposition, electroless plating or electrolytic plating. In some examples, PVD may include or be referred to as sputtering. In addition, the conductive structure 142 may be patterned using a mask pattern to provide a plurality of patterns that are electrically connected to the terminals 131, respectively.

[0045] The interconnect 150 may be electrically connected to the bottom surface 142b of the conductive structure 142. The interconnect 150 may be set to the same size. The interconnect 150 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the interconnect 150 may include a solder ball, and / or a metal core ball having a solid metal core covered by solder. In some examples, the interconnect 150 may include a metal pillar, such as a copper pillar, which may be placed or formed on the conductive structure 142, and the metal pillar may have a solder tip or end. The interconnect 150 may have a size in the range of about 5 μm to about 100 μm.

[0046] Examples of forming the interconnect 150 include using a ball drop process, a screen printing process, or an electroplating process. In some examples, a conductive material including solder may be formed on the bottom surface of the conductive structure 142 using a solder ball drop process. Here, the bottom surface 142b of the conductive structure 142 may be disposed facing upward. The electronic component 130 and the substrate 140 may be heated to a predetermined temperature using a reflow process, and the shape of the interconnect 150 may change during the reflow process.

[0047] In some examples, the electronic component 130 having the substrate 140 and the interconnect 150 may be electrically connected to the conductive structure 122 of the substrate 120 using a large-scale reflow process, a hot pressing process, or a laser bonding process. The interconnect 150 may be inserted between the conductive structure 122 and the conductive structure 142 to electrically connect the substrate 120 and the substrate 140. The interconnect 150 may transmit current or signals between the electronic device 110 and the electronic component 130 through the substrate 120 and the substrate 140. In addition, one or more interconnects 150 may be connected to a conductor that is not electrically connected to the electronic device 110, such as the conductor 122z. In some examples, the interconnect 150 may electrically connect the electronic component 130 to the electronic device 110 through the substrate 140 and the substrate 120. In the same or other examples, one or more interconnects 150 may electrically connect the electronic component 130 to a conductor of the conductive structure 122 that extends beyond the perimeter of the electronic device 110 and is exposed through the opening 121y of the dielectric structure 121.

[0048] In some examples, one or more of the substrates that may be used as part of semiconductor device 100 (e.g., substrate 140 or 120) may be a redistribution layer (“RDL”) substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers that may be (a) formed layer by layer over an electronic device to be electrically coupled to the RDL substrate or (b) formed layer by layer over a carrier that may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be fabricated layer by layer as a wafer-level substrate on a circular wafer in a wafer-level process, and / or fabricated layer by layer as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed in an additive buildup process that may include alternating stacking of one or more dielectric layers with one or more conductive layers defining corresponding conductive redistribution patterns or traces that are configured to collectively (a) fan out the electrical traces outside the footprint of the electronic device, and / or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern may be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern may include a conductive material such as copper or other plateable metals. The location of the conductive pattern may be made using a photopatterning process such as a photolithography process and a photoresist material for forming a photolithography mask. The dielectric layer of the RDL substrate may be patterned using a photopatterning process that may include a photolithography mask, through which light is exposed to the desired features of the photopattern, such as through holes in the dielectric layer. The dielectric layer may be made of a photo-definable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO). Such dielectric materials may be spin-coated or otherwise applied in liquid form, rather than attached in the form of a preformed film. In order to allow the desired light-defined features to be properly formed, such photo-imageable dielectric materials may omit structural enhancers, or may be filler-free and free of strands, woven fabrics or other particles that may interfere with the light from the photopatterning process. In some examples, such filler-free characteristics of the filler-free dielectric material can result in a reduced thickness of the resulting dielectric layer. Although the photoimageable dielectric material described above can be an organic material, in other examples, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of the one or more inorganic dielectric layers can include silicon nitride (SiN). 3 N 4 ), silicon oxide (SiO 2) and / or SiON. The one or more inorganic dielectric layers may be formed not by using a photo-defined organic dielectric material but by growing an inorganic dielectric layer using an oxidation or nitridation process. Such inorganic dielectric layers may be filler-free and have no strands, woven fabrics, or other different inorganic particles. In some instances, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates. Other substrates in the present disclosure may also include an RDL substrate.

[0049] In some examples, one or more of the substrates that can be used as part of the semiconductor device 100, such as substrate 140, can be preformed substrates. The preformed substrate can be manufactured before being attached to the electronic device and can include a dielectric layer between the corresponding conductive layers. The conductive layer can include copper and can be formed using an electroplating process. The dielectric layer can be a relatively thick non-photoimageable layer that can be attached in the form of a preformed film rather than in the form of a liquid, and can include a resin with fillers such as strands, woven fabrics and / or other inorganic particles for rigidity and / or structural support. Since the dielectric layer is not photoimageable, features such as through holes or openings can be formed by using drilling or lasers. In some examples, the dielectric layer can include a prepreg material or an Ajinomoto built-up film (ABF). The preformed substrate can include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and the conductive layer can be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate omitting a permanent core structure, and the dielectric layer and the conductive layer may be formed on a sacrificial carrier that is removed after the dielectric layer and the conductive layer are formed and before being attached to the electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. Such a preformed substrate may be formed by a semi-additive process or a modified semi-additive process. Other substrates in the present disclosure may also include preformed substrates.

[0050] Figure 2F 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacturing. Figure 2F In the example shown, an encapsulation material 160 may be formed to cover the top of the substrate 120, the bottom of the semiconductor component 130 and the substrate 140, the electronic device 110, and the interconnect 150. The sidewalls of the electronic device 110, including the device sidewalls 110c, are at least partially bounded by the encapsulation material 160. The encapsulation material 160 may be provided to completely fill the area between the substrate 120 and the substrate 140.

[0051] In some examples, encapsulant 160 may include a non-conductive material, a resin, a polymer composite, a polymer with fillers, an epoxy resin, an epoxy resin, an epoxy acrylate with fillers such as silica or other inorganic materials, a silicone resin, or a resin-impregnated B-state prepreg.

[0052] Examples of forming encapsulant 160 may include compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, or film-assisted molding. In some examples, encapsulant 160 may include or be referred to as a protective material or molding compound. Encapsulant 160 may disconnect the electrical connection between substrate 120, substrate 140, and interconnect 150, thereby protecting substrate 120, substrate 140, and interconnect 150 from external peripheral influences.

[0053] Figure 2G A cross-sectional view of a semiconductor device 100 at a post-manufacturing stage is shown. In the example shown in 2G, the bracket 10 adhered to the device bottom side 110b of the electronic device 110 can be removed so that the device bottom side 110b of the electronic device 110 and the bottom surface of the substrate 120 are exposed. When the bracket 10 is removed, the bottom surface 121b of the dielectric structure 121 formed on the top surface 10a of the bracket 10 can be exposed. In addition, if the bracket 10 is removed, the conductive structure 122 formed on the top surface 10a of the bracket 10 can also be exposed through the opening 121y of the dielectric structure 121. Conductors that are not electrically connected to the conductive structure 122 of the electronic device 110, such as the conductor 122z, can also be exposed through the opening 121y.

[0054] The bracket 10 may be removed by general grinding or chemical etching. Alternatively, the bracket 10 may also be removed by a lift-off process using UV radiation or laser.

[0055] Figure 2H 1 shows a cross-sectional view of a semiconductor device 100 at a later stage of manufacturing. Figure 2H In the example shown in FIG. 1 , the interconnection 170 may be disposed on the conductive structure 122 exposed through the opening 121 y.

[0056] Interconnect 170 may be electrically connected to the bottom surface of conductive structure 122. In some examples, interconnect 170 may be electrically connected to electronic device 110 through conductive structure 122. In some examples, interconnect 170 may be electrically connected to electronic component 130 through conductive structure 122, interconnect 150, and conductive structure 142. Interconnect 170 may be referred to as an external interconnect that allows external connection from semiconductor device 100 to an external device or component, such as a printed circuit board or substrate.

[0057] The interconnect 170 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. Examples of forming the interconnect 170 include using a ball drop process, a screen printing process, or an electroplating process. In some examples, a conductive material including solder may be formed on the bottom surface 122b of the conductive structure 122 using a solder ball drop process. The bottom surface 122b of the conductive structure 122 may be arranged to face up at this stage. The semiconductor device 100 may be heated to a predetermined temperature using a reflow process, and the shape of the interconnect 170 may change during the reflow process. The electrical interconnect 170 may include or be referred to as a conductive ball (such as a solder ball), a conductive pillar (such as a copper pillar), or a conductive pillar having a solder cap formed on the copper pillar. The interconnect 170 may have a size in a range of about 60 μm to about 150 μm.

[0058] Interconnect 170 may allow external access to and / or from one or more components of semiconductor device 100 , such as electronic device 110 and / or electronic component 130 .

[0059] For example, in a first path adjacent to the sidewall 110c of the electronic device 110, the interconnect 1701 on the bottom of the substrate 120 is coupled to the component terminal 1311 of the electronic component 130 through a wiring including a conductor 122x (including a conductor bottom segment 122b, a conductor side segment 122c, and a conductor top segment 122a), through the interconnect 1501, and through the component conductor 142x. Likewise, in this example, the interconnect 1701 on the bottom of the substrate 120 is also coupled to the device terminal 1111 of the electronic device 130 along at least a portion of the first path through a wiring including a conductor 122x (including a conductor bottom segment 122b, a conductor side segment 122c adjacent to the sidewall 110c, and a conductor top segment 122a).

[0060] Similarly, in a second path adjacent to the sidewall 110d of the electronic device 110, an interconnect 1702 on the bottom of the substrate 120 is coupled to a component terminal 1312 of the electronic component 130 through a routing including a conductor 122z (and its corresponding conductor top segment 122a, conductor side segment 122c, and conductor bottom segment 122c), through an interconnect 1502, and through a component conductor 142z.

[0061] After being singulated into individual units, the semiconductor device 100 assumes its final form. Such singulation may be achieved, for example, by performing sawing to define sidewalls of the semiconductor device 100. In some examples, such singulation may define coplanar portions of different elements of the semiconductor device 100. For example, the component sidewall 130c of the electronic component 130 may be substantially coplanar with the sidewall of the encapsulation material 160. In some examples, the sidewall 130c of the electronic component 130 may be substantially coplanar with the sidewall of the encapsulation material 160. Figure 2H The sidewalls of the substrate 120 shown as the outer ends or sidewalls of the dielectric bottom section 121b are exposed by the sidewalls of the encapsulant 160 and are substantially coplanar with the sidewalls. Figure 2H , the outer conductor end point of the conductor bottom segment 122b is not exposed by the encapsulation material 160, but is covered by the encapsulation material. Such an end point of the conductor bottom segment 122b may be closest to the side wall of the encapsulation material 160 compared to any other point of the conductive bottom segment 122b. There may be other examples where the outer end of the conductor bottom segment 122b may extend further and thus be exposed in a coplanar form with the side wall of the encapsulation material 160.

[0062] By the arrangement described above for the different conductors of the interconnecting conductive structures 122 and 142, several signal paths of the semiconductor device 100 can be realized. For example, the path including the conductors 122x and 142x allows the electronic device 110 and the electronic component 130 to be electrically connected to each other and to the corresponding interconnect 170, thereby disconnecting the external connection of the semiconductor device 100. The path including the conductors 122y and 142y allows a direct internal connection between the electronic device 110 and the electronic component 130. The path including the conductors 122z and 142z allows the electronic device 130 to be electrically connected to the corresponding interconnect 170, so as to cross over the electronic device 100 but electrically bypass the electronic device 100, thereby disconnecting the connection of the semiconductor device 100. Accordingly, the electrical coupling between the top electronic device 130 and the external interconnect 170 can be realized without the need to additionally form a dedicated vertical via, which would otherwise have to extend completely from the top to the bottom of the encapsulation material 160 between the electronic device 130 and the external interconnect 170.

[0063] The present disclosure includes references to certain examples, however, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is not intended that the present disclosure be limited to the disclosed examples, but rather that the present disclosure will include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a first electronic device comprising a first electronic device bottom side, a first electronic device top side, and a first electronic device side wall, wherein the first electronic device top side comprises a first electronic device terminal, and the first electronic device side wall is between the first electronic device top side and the first electronic device bottom side; A first dielectric structure comprising: a dielectric structure top portion over the first electronic device top side and covering a first top side portion of the first electronic device terminal, wherein the dielectric structure top portion includes a first opening exposing a second top side portion of the first electronic device terminal; a dielectric structure sidewall portion over the first electronic device sidewall and coupled to the dielectric structure top portion; and a dielectric structure bottom portion coupled to the dielectric structure sidewall portion, wherein the dielectric structure bottom portion extends away from the first electronic device sidewall; and A first conductive structure comprising: a first conductive structure top portion, the first conductive structure top portion being above the dielectric structure top portion and coupled to the second top side portion of the first electronic device terminal through the first opening of the dielectric structure top portion; a first conductive structure sidewall portion overlying the dielectric structure sidewall portion and coupled to the first conductive structure top portion; and A first conductive structure bottom portion is above the dielectric structure bottom portion and coupled to the first conductive structure sidewall portion, wherein the first conductive structure bottom portion extends away from the first electronic device sidewall. 2 . The semiconductor device of claim 1 , comprising an external interconnect coupled to the first conductive structure bottom portion through a second opening in the dielectric structure bottom portion.

3. A semiconductor device comprising: a first electronic device, the first electronic device comprising a first electronic device top side, a first electronic device bottom side, and a first electronic device side wall, the first electronic device side wall being between the first electronic device top side and the first electronic device bottom side; A dielectric layer, the dielectric layer comprising: a top portion of a dielectric layer, the top portion of the dielectric layer conforming to the top side of the first electronic device; a dielectric layer sidewall portion, the dielectric layer sidewall portion being connected to the dielectric layer top portion and conformal to the first electronic device sidewall; as well as a dielectric layer bottom portion, the dielectric layer bottom portion being connected to the dielectric layer sidewall portion, the dielectric layer bottom portion extending outwardly from the dielectric layer sidewall portion; a first conductor coupled to the first electronic device through a first opening in the top portion of the dielectric layer, wherein the first conductor conforms to the top portion of the dielectric layer, the sidewall portion of the dielectric layer, and the bottom portion of the dielectric layer; an encapsulation material, the encapsulation material covering the first conductor and the first electronic device; as well as An external interconnect is at a bottom side of the substrate, wherein the external interconnect is coupled to the first conductor. 4 . The semiconductor device according to claim 3 , wherein the encapsulant and the end of the bottom portion of the dielectric layer provide at least a portion of an outer sidewall of the semiconductor device.

5. A method comprising: Providing a dielectric structure, the dielectric structure comprising a dielectric top portion, a dielectric sidewall portion, and a dielectric bottom portion, the dielectric top portion conforming to a top side of a first electronic device and a first electronic device terminal of the first electronic device, the dielectric sidewall portion conforming to a sidewall of the first electronic device, the dielectric bottom portion extending outwardly from the dielectric sidewall portion, the dielectric top portion comprising a first opening, the first opening portion exposing a top side of the first electronic device terminal; as well as A first conductive structure is provided, the first conductive structure being coupled to the first electronic device through the first opening in the dielectric top portion, the first conductive structure comprising a first conductive top portion conformal to the dielectric top portion, a first conductive sidewall portion conformal to the dielectric sidewall portion, and a first conductive bottom portion conformal to the dielectric bottom portion. 6 . The method of claim 5 , comprising providing a second electronic device over the first electronic device and coupled to the first conductive structure.

7. An electronic device, comprising: a first electronic device, the first electronic device comprising a first electronic device bottom side, a first electronic device top side, and a first electronic device side wall, the first electronic device top side comprising a first electronic device terminal, and the first electronic device side wall being between the first electronic device top side and the first electronic device bottom side; A first dielectric structure, the first dielectric structure comprising: a dielectric structure top portion overlying the top side of the first electronic device; a dielectric structure sidewall portion overlying the first electronic device sidewall and extending from the dielectric structure top portion; and a dielectric structure bottom portion extending from the dielectric structure sidewall portion, wherein the dielectric structure bottom portion extends away from the first electronic device sidewall; A first conductive structure, the first conductive structure comprising: a first conductive structure top portion over the dielectric structure top portion and coupled to at least one of the first electronic device terminals; a first conductive structure sidewall portion overlying the dielectric structure sidewall portion and extending from the first conductive structure top portion; and a first conductive structure bottom portion over the dielectric structure bottom portion and extending from the first conductive structure sidewall portion, wherein the first conductive structure bottom portion extends away from the first electronic device sidewall; a second conductive structure above the first electronic device; a second dielectric structure overlying the second conductive structure; and A first interconnect structure is coupled to a top portion of the first conductive structure and to the second conductive structure.

8. The electronic device of claim 7, comprising an encapsulant between the first conductive structure and the second conductive structure.

9. An electronic device, comprising: a first electronic device comprising a first electronic device top side, a first electronic device bottom side, and a first electronic device side wall, the first electronic device side wall being between the first electronic device top side and the first electronic device bottom side; a first dielectric layer over the first electronic device, wherein the first dielectric layer includes a first dielectric layer top side that conforms to the first electronic device top side, the first electronic device sidewall, and a bottom side of the electronic device; a first conductive layer overlying the first dielectric layer, wherein the first conductive layer comprises a first conductive trace conforming to a top side of the first dielectric layer; a second electronic device including a second electronic device bottom side, the second electronic device bottom side being above the first electronic device top side; as well as A first interconnect structure is between the first electronic device top side and the second electronic device bottom side, wherein the first interconnect structure couples the second electronic device to the first conductive trace.

10. A method for providing an electronic device, the method comprising: Providing a first electronic device, the first electronic device comprising a first electronic device top side, a first electronic device bottom side, and a first electronic device side wall, the first electronic device side wall being between the first electronic device top side and the first electronic device bottom side; providing a first dielectric layer, the first dielectric layer being above the first electronic device such that a top side of the first dielectric layer conforms to a top side of the first electronic device, a sidewall of the first electronic device, and a bottom side of the electronic device; providing a first conductive layer, the first conductive layer being above the first dielectric layer, such that the first conductive layer comprises a first conductive trace, the first conductive trace conforming to a top side of the first dielectric layer; providing a second electronic device such that a bottom side of the second electronic device is above a top side of the first electronic device; as well as A first interconnect structure is provided between the first electronic device top side and the second electronic device bottom side such that the first interconnect structure couples the second electronic device to the first conductive trace.

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