Semiconductor process monitoring structure and semiconductor process monitoring method
By designing a semiconductor process monitoring structure including test structure, input structure, output structure and detection structure, the problem of difficulty in monitoring the short-circuit bridging risk in the existing technology is solved, and the short-circuit bridging position is achieved, and the semiconductor device performance and manufacturing process improvement capabilities are improved.
Patent Information
- Application Number
- CN202510140459.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-08
- Publication Date
- 2025-05-13
AI Technical Summary
The prior art is difficult to accurately monitor the risk of short-circuit bridge between small-sized conductive layers, and cannot accurately determine the location of short-circuit bridges, resulting in limited performance improvement of semiconductor devices and manufacturing process improvements.
A semiconductor process monitoring structure is designed, including test structure, input structure, output structure and detection structure. The test structure includes a first test row and a second test row arranged spaced in the first direction. The input structure is electrically connected to the gate electrode of the transistor in the first test row. The output structure is electrically connected to the gate electrode of the transistor in the second test row. The detection structure is used to detect whether the output structure outputs current and thereby determine whether the transistors are short-connected.
Accurate monitoring of the risk of short-circuit bridging between small-sized conductive layers is achieved, and the positioning accuracy of short-circuit bridging positions is improved, thereby improving semiconductor device performance and manufacturing process improvement capabilities.
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Figure CN119993958A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor process monitoring structure and a semiconductor process monitoring method. Background Art
[0002] With the development of technology, especially the continuous improvement of lithography technology, the transistors in semiconductor devices are made smaller and smaller, which directly promotes the reduction of logic node size. With the continuous reduction of process size, the control of the cutting process of conductive layers such as poly becomes more difficult, which leads to an increased risk of short circuit between adjacent transistors, for example, an increased risk of short circuit between polysilicon gates in adjacent transistors. At present, in order to reduce the risk of short circuit between transistors, the commonly used monitoring structure is a forked finger non-series three-terminal device. The forked finger non-series three-terminal device monitors the risk of short circuit bridging between conductive layers according to the line width and line spacing of the conductive layer. However, the currently used forked finger non-series three-terminal device cannot accurately monitor the risk of short circuit bridging between small-sized conductive layers, and cannot accurately determine the position of the short circuit bridging, which is not conducive to the improvement of semiconductor device performance and the improvement of semiconductor manufacturing process.
[0003] Therefore, how to monitor the risk of short-circuit bridging between small-sized conductive layers and improve the accuracy of short-circuit bridging location, so as to provide a reference for improving the performance of semiconductor devices and the improvement of semiconductor manufacturing processes, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides a semiconductor process monitoring structure and a semiconductor process monitoring method, which are used to monitor the risk of short-circuit bridging between small-sized conductive layers and improve the accuracy of positioning the short-circuit bridging position, thereby providing a reference for improving the performance of semiconductor devices and improving semiconductor manufacturing processes.
[0005] According to some embodiments, the present invention provides a semiconductor process monitoring structure, comprising:
[0006] A test structure, comprising at least one test area, wherein the test area at least comprises a first test row and a second test row arranged at intervals along a first direction, wherein the first test row and the second test row each comprise a plurality of transistors arranged at intervals along a second direction, and the first direction intersects the second direction perpendicularly;
[0007] an input structure electrically connected to gate electrodes of a plurality of the transistors in the first test row;
[0008] an output structure electrically connected to gate electrodes of a plurality of the transistors in the second test row;
[0009] The detection structure is connected to the output structure and is used to detect whether the output structure outputs current.
[0010] In some embodiments, the test structure includes a plurality of the test areas arranged at intervals along the first direction, the input structure is electrically connected to the gate electrodes of all the transistors in the first test rows within all the test areas, and the output structure is electrically connected to the gate electrodes of all the transistors in the second test rows within all the test areas.
[0011] In some embodiments, within the same test area, a spacing between the gate electrodes of adjacent transistors in the first test row is greater than a spacing between the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row.
[0012] In some embodiments, the input structure includes a plurality of input conductive plugs and an input connection line, the plurality of input conductive plugs are electrically connected to the gate electrodes of the plurality of transistors in the first test row in a one-to-one correspondence, and the input connection line is electrically connected to all the input conductive plugs in a continuous manner;
[0013] The output structure includes a plurality of output conductive plugs and output connection lines. The plurality of output conductive plugs are electrically connected to the gate electrodes of the plurality of transistors in the second test row in a one-to-one correspondence. The output connection lines electrically connect all the output conductive plugs in a continuous manner.
[0014] In some embodiments, the input structure further includes an input pad electrically connected to the input connection line, and the output structure further includes an output pad electrically connected to the output connection line;
[0015] The input pad and the output pad are distributed on two opposite sides of the test structure along the second direction.
[0016] In some embodiments, the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row both extend along the first direction;
[0017] The input conductive plug is electrically connected to the end of the gate electrode of the transistor in the first test row away from the second test row along the first direction, and the output conductive plug is electrically connected to the end of the gate electrode of the transistor in the second test row away from the first test row along the first direction.
[0018] In some embodiments, the spacing width between two adjacent test regions along the first direction is greater than the spacing between the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row within the same test region.
[0019] In some embodiments, it also includes:
[0020] a substrate, a gate electrode of the transistor in the test structure being located above the substrate;
[0021] The grounding structure is electrically connected to the substrate.
[0022] According to some other embodiments, the present invention further provides a semiconductor process monitoring method, comprising the following steps:
[0023] forming a semiconductor process monitoring structure, the semiconductor process monitoring structure comprising a test structure, an input structure, an output structure and a detection structure, the test structure comprising at least one test area, the test area comprising at least a first test row and a second test row arranged at intervals along a first direction, the first test row and the second test row each comprising a plurality of transistors arranged at intervals along a second direction, the input structure being electrically connected to gate electrodes of the plurality of transistors in the first test row, the output structure being electrically connected to gate electrodes of the plurality of transistors in the second test row, the detection structure being connected to the output structure, and the first direction intersects the second direction perpendicularly;
[0024] transmitting a test signal to a plurality of said transistors in said first test row through said input structure;
[0025] The detection structure is used to detect whether the output structure outputs current. If so, it is confirmed that the transistors in the first test row are short-circuited with the transistors in the second test row.
[0026] In some embodiments, the specific steps of forming a semiconductor process monitoring structure include:
[0027] Providing a substrate and defining at least one test area in the substrate;
[0028] forming a plurality of active regions arranged along the first direction and the second direction in the substrate of the test area, and forming a gate electrode above the substrate of the active region to form the test structure;
[0029] The input structure and the output structure are formed above the test structure, and the detection structure electrically connected to the output structure is formed.
[0030] In some embodiments, a plurality of active regions arranged along the first direction and the second direction are formed in the substrate of the test area, and a gate electrode is formed above the substrate of the active area to form the test structure. Specific steps include:
[0031] forming a plurality of active regions arranged along the first direction and the second direction in the substrate of the test area;
[0032] A plurality of gate electrodes corresponding to the plurality of active regions are formed on the substrate, and a distance between two adjacent gate electrodes along the second direction is greater than a distance between two adjacent gate electrodes along the first direction.
[0033] In some embodiments, the multiple test areas are arranged along the first direction; the specific steps of forming multiple active areas arranged along the first direction and the second direction in the substrate of the test area, and forming a gate electrode above the substrate of the active area include:
[0034] forming a plurality of active regions arranged along the first direction and the second direction in the substrate of each of the test regions;
[0035] A plurality of gate electrodes corresponding to the plurality of active regions are formed above the substrate, and a spacing between the gate electrodes in two adjacent test regions along the first direction is greater than a spacing between two adjacent gate electrodes in the same test region along the first direction.
[0036] In some embodiments, the specific steps of forming the input structure and the output structure above the test structure, and forming the detection structure electrically connected to the output structure include:
[0037] forming a dielectric layer covering the test structure;
[0038] Forming a plurality of input conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the first test row and input connection lines electrically connecting all the input conductive plugs in succession on the dielectric layer, and forming a plurality of output conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the second test row and output connection lines electrically connecting all the output conductive plugs in succession on the dielectric layer, so as to form the input structure including the input conductive plugs and the input connection lines and the output structure including the output conductive plugs and the output connection lines;
[0039] The detection structure electrically connected to the output connection line is formed.
[0040] In some embodiments, the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row both extend along the first direction; forming a plurality of input conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the first test row and input connection lines electrically connecting all the input conductive plugs in succession above the dielectric layer, and forming a plurality of output conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the second test row and output connection lines electrically connecting all the output conductive plugs in succession above the dielectric layer include:
[0041] The input conductive plug is formed to be electrically connected to the end of the gate electrode of the transistor in the first test row away from the second test row along the first direction, and the output conductive plug is formed to be electrically connected to the end of the gate electrode of the transistor in the second test row away from the first test row along the first direction.
[0042] In some embodiments, the following steps are also included:
[0043] forming a plurality of the semiconductor process monitoring structures, wherein the sizes of the test structures in the plurality of the semiconductor process monitoring structures are different;
[0044] respectively monitoring whether the transistors in the first test row and the transistors in the second test row in each of the semiconductor process monitoring structures are short-circuited;
[0045] The test structure in which the transistors in the first test row and the transistors in the second test row are not short-circuited and has the smallest size is selected as a target test structure.
[0046] In some embodiments, the different dimensions of the test structure include any one of the length of the gate electrode along the first direction, the width of the gate electrode along the second direction, the spacing between adjacent gate electrodes along the second direction, and the spacing between adjacent gate electrodes along the first direction, or a combination of two or more thereof.
[0047] The semiconductor process monitoring structure and semiconductor process monitoring method provided by the present invention are configured to include a first test row and a second test row arranged at intervals along a first direction, wherein the first test row and the second test row both include a plurality of transistors arranged at intervals along a second direction, and the input structure is electrically connected to the gate electrodes of the plurality of transistors in the first test row, and the output structure is electrically connected to the gate electrodes of the plurality of transistors in the second test row, thereby determining whether the transistors in the first test row and the transistors in the second test row are short-circuited by detecting whether the output current of the output structure is detected by the detection structure, so as to monitor the manufacturing process of the gate electrodes in the transistors. The present invention is not limited by the size of the gate electrode and the spacing between adjacent gate electrodes, and can monitor the risk of short-circuit bridging between small-sized gate electrodes, thereby providing a reference for improving the performance of semiconductor devices and improving semiconductor manufacturing processes. At the same time, the present invention limits the spacing between the gate electrodes of adjacent transistors in the first test row to be greater than the spacing between the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row, thereby being able to accurately determine whether a short circuit bridge occurs between the transistors in the first test row and the transistors in the second test row, that is, being able to accurately determine the location of the short circuit, thereby providing further reference for improving the performance of semiconductor devices and improving semiconductor manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1 is a schematic top view of a semiconductor process monitoring structure in a specific embodiment of the present invention;
[0049] Figure 2 is a partial schematic diagram of a test structure in a specific embodiment of the present invention;
[0050] Figure 3 It is a flow chart of a semiconductor process monitoring method in a specific implementation manner of the present invention.
[0051] Description of Reference Numerals
[0052] 10. Test Area
[0053] 11 First test line
[0054] 12 Second test line
[0055] 13 Isolation Area
[0056] 15 Input conductive plug
[0057] 16 Input cable
[0058] 17 Input pad
[0059] 18 Output conductive plug
[0060] 19 Output cable
[0061] 20 Output pad
[0062] 21 Grounding structure
[0063] 22. Gate electrode DETAILED DESCRIPTION
[0064] The specific implementation modes of the semiconductor process monitoring structure and the semiconductor process monitoring method provided by the present invention are described in detail below with reference to the accompanying drawings.
[0065] This specific embodiment provides a semiconductor process monitoring structure. Figure 1 is a schematic top view of a semiconductor process monitoring structure in a specific embodiment of the present invention, Figure 2 FIG. 1 is a partial schematic diagram of a test structure in a specific embodiment of the present invention. Figure 1 and Figure 2 As shown, the semiconductor process monitoring structure comprises:
[0066] A test structure, comprising at least one test area 10, wherein the test area 10 at least comprises a first test row 11 and a second test row 12 arranged at intervals along a first direction D1, wherein the first test row 11 and the second test row 12 each comprise a plurality of transistors arranged at intervals along a second direction D2, wherein the first direction D1 intersects the second direction D2 perpendicularly;
[0067] An input structure electrically connected to the gate electrodes 22 of the plurality of transistors in the first test row 11;
[0068] an output structure electrically connected to the gate electrodes 22 of the plurality of transistors in the second test row 12;
[0069] The detection structure is connected to the output structure and is used to detect whether the output structure outputs current.
[0070] For example, the test structure includes a substrate and a semiconductor layer located above the top surface of the substrate, the substrate includes a functional area and an isolation area 13 distributed around the functional area, and the isolation area 13 is used to isolate adjacent functional areas. The functional area includes at least one test area 10, and the test area 10 includes a plurality of active areas arranged at intervals along the first direction D1 and the second direction D2, each of the active areas includes a channel area and a source area and a drain area distributed on opposite sides of the channel area. The semiconductor layer includes the gate electrode 22 located above the channel area. Each transistor includes one active area and the gate electrode 22 located above it. For two rows of transistors arranged along the first direction D1, one row of transistors is used as the first test row 11, and the other row of transistors is used as the second test row. Wherein, the first direction D1 and the second direction D2 are parallel to the top surface of the substrate. In one example, the material of the gate electrode 22 is polysilicon material. The input structure and the output structure are both located above the substrate, and the input structure is electrically connected to the gate electrodes 22 of all the transistors in the first test row 11, and the output structure is electrically connected to the gate electrodes 22 of all the transistors in the second test row 12. The detection structure is electrically connected to the output structure.
[0071] In this specific embodiment, the test structure is configured to include at least one test area 10, and the test area 10 includes at least a first test row 11 and a second test row 12 arranged at intervals along a first direction D1, and the first test row 11 and the second test row 12 both include a plurality of transistors arranged at intervals along a second direction D2, so that the size of the transistor can be reduced in a limited area, so as to facilitate monitoring of the manufacturing process of small-sized gate electrodes. In this specific embodiment, the input structure is electrically connected to the gate electrodes of the plurality of transistors in the first test row 11, and the output structure is electrically connected to the gate electrodes of the plurality of transistors in the second test row. When the gate electrode 22 in the first test row 11 is short-circuited with the gate electrode 22 in the second test row, a current loop is formed between the input structure and the output structure, so that the detection structure detects the output current of the output structure to determine whether the transistors in the first test row 11 are short-circuited with the transistors in the second test row, so as to realize monitoring of the manufacturing process of the gate electrode in the transistor. Moreover, this specific embodiment is not limited by the gate electrode size and the distance between adjacent gate electrodes, and can monitor the risk of short circuit bridging between small-sized gate electrodes, thereby providing a reference for improving the performance of semiconductor devices and improving semiconductor manufacturing processes.
[0072] In order to further improve the efficiency of process monitoring, in some embodiments, the test structure includes a plurality of the test areas 10 arranged at intervals along the first direction D1, the input structure is electrically connected to the gate electrodes 22 of all the transistors in the first test rows 11 within all the test areas 10, and the output structure is electrically connected to the gate electrodes 22 of all the transistors in the second test rows 12 within all the test areas.
[0073] In some embodiments, within the same test area 10 , a spacing S between the gate electrodes 22 of adjacent transistors within the first test row 11 is greater than a spacing E between the gate electrodes 22 of the transistors within the first test row 11 and the gate electrodes 22 of the transistors within the second test row 12 .
[0074] Specifically, for the same test area 10, by setting the spacing S between the gate electrodes 22 of the adjacent transistors in the first test row 11 to be larger than the spacing E between the gate electrodes 22 of the transistors in the first test row 11 and the gate electrodes 22 of the transistors in the second test row 12, and setting the spacing between the gate electrodes 22 of the adjacent transistors in the second test row 12 to be larger than the spacing E between the gate electrodes 22 of the transistors in the first test row 11 and the gate electrodes 22 of the transistors in the second test row 12, it is possible to avoid Short-circuit bridges occur between adjacent gate electrodes 22 in a test row 11, and short-circuit bridges occur between adjacent gate electrodes 22 in the second test row 12. Therefore, after the detection structure detects the output current of the output structure, it can be confirmed that the short-circuit bridge occurs between the gate electrode 22 of the transistor in the first test row 11 and the gate electrode 22 of the transistor in the second test row 12, that is, the location of the short-circuit bridge is located, and the location of the short circuit can be accurately determined, thereby providing further reference for improving the performance of semiconductor devices and improving semiconductor manufacturing processes. In an example, the spacing S between the gate electrodes 22 of adjacent transistors in the first test row 11 can be 70nm~90nm, and the spacing E between the gate electrodes 22 of the transistors in the first test row 11 and the gate electrodes 22 of the transistors in the second test row 12 can be 25nm~50nm.
[0075] In some embodiments, the input structure includes a plurality of input conductive plugs 15 and an input connection line 16, wherein the plurality of input conductive plugs 15 are electrically connected to the gate electrodes 22 of the plurality of transistors in the first test row 11 in a one-to-one correspondence, and the input connection line 16 is electrically connected to all the input conductive plugs 15 in a continuous manner;
[0076] The output structure includes a plurality of output conductive plugs 18 and output connection lines 19 . The plurality of output conductive plugs 18 are electrically connected one-to-one with the gate electrodes 22 of the plurality of transistors in the second test row 12 . The output connection lines 19 electrically connect all the output conductive plugs 18 in a continuous manner.
[0077] In some embodiments, the input structure further includes an input pad 17 electrically connected to the input connection line 16, and the output structure further includes an output pad 20 electrically connected to the output connection line 19;
[0078] The input pad 17 and the output pad 20 are distributed on two opposite sides of the test structure along the second direction D2.
[0079] For example, the input structure includes the input conductive plug 15 that penetrates the semiconductor layer in the test structure and is electrically connected to the gate electrode 22 of the transistor in the first test row 11, the input connection line 16 that is located above the semiconductor layer and continuously electrically connects all the input conductive plugs 15, and the input pad 17 that is electrically connected to the input connection line 16, so as to simultaneously transmit the test signal to the multiple transistors in the first test row 11. The output structure includes the output conductive plug 18 that penetrates the semiconductor layer in the test structure and is electrically connected to the gate electrode 22 of the transistor in the second test row 12, the output connection line 19 that is located above the semiconductor layer and continuously electrically connects all the output conductive plugs 18, and the output pad 20 that is electrically connected to the output connection line 19, so as to simultaneously detect the bridging conditions of the gate electrodes of multiple pairs of the transistors arranged at intervals along the first direction D1. The input pad 17 and the output pad 20 are distributed on two opposite sides of the test structure along the second direction D2, which can reduce signal crosstalk between the input structure and the output structure and reduce the manufacturing difficulty of the semiconductor process monitoring structure.
[0080] In some embodiments, the gate electrodes 22 of the transistors in the first test row 11 and the gate electrodes 22 of the transistors in the second test row 12 both extend along the first direction D1;
[0081] The input conductive plug 15 is electrically connected to the end of the gate electrode 22 of the transistor in the first test row 11 away from the second test row 12 along the first direction D1, and the output conductive plug 18 is electrically connected to the end of the gate electrode 22 of the transistor in the second test row 12 away from the first test row 11 along the first direction D1, thereby reducing the difficulty of the manufacturing process of the input conductive plug 15 and the output conductive plug 18 and further avoiding signal crosstalk between the input structure and the output structure.
[0082] In some embodiments, the spacing width W between the two adjacent test areas 10 along the first direction D1 is greater than the spacing E between the gate electrode 22 of the transistor in the first test row 11 and the gate electrode 22 of the transistor in the second test row 12 in the same test area 10, so as to meet the requirements of the manufacturing process of the input conductive plug 15 and the output conductive plug 18, and avoid the short circuit of the gate electrode 22 in the adjacent test area 10, so that after the detection structure detects the output current of the output structure, it can be confirmed that the short circuit bridge occurs between the gate electrode 22 of the transistor in the first test row 11 and the gate electrode 22 of the transistor in the second test row 12 in the same test area 10, that is, the short circuit bridge position is further quickly located. In one example, the spacing width W between the two adjacent test areas 10 along the first direction D1 is 80nm.
[0083] In some embodiments, the semiconductor process monitoring structure further includes:
[0084] a substrate, on which the gate electrode 22 of the transistor in the test structure is located;
[0085] The grounding structure 21 is electrically connected to the substrate to ground the substrate to prevent the substrate itself from interfering with the test results.
[0086] This specific embodiment also provides a semiconductor process monitoring method, Figure 3 1 is a flow chart of a semiconductor process monitoring method in a specific embodiment of the present invention. The semiconductor process monitoring method can be implemented as follows: Figure 1-Figure 2 The semiconductor process monitoring structure shown is implemented. Figure 1-Figure 3 As shown, the semiconductor process monitoring method comprises the following steps:
[0087] Step S31, forming a semiconductor process monitoring structure, the semiconductor process monitoring structure comprising a test structure, an input structure, an output structure and a detection structure, the test structure comprising at least one test area 10, the test area 10 at least comprising a first test row 11 and a second test row 12 arranged at intervals along a first direction D1, the first test row 11 and the second test row 12 both comprising a plurality of transistors arranged at intervals along a second direction D2, the input structure being electrically connected to gate electrodes 22 of the plurality of transistors in the first test row 11, the output structure being electrically connected to gate electrodes 22 of the plurality of transistors in the second test row 12, the detection structure being connected to the output structure, and the first direction D1 intersects the second direction D2 perpendicularly;
[0088] Step S32, transmitting a test signal to the plurality of transistors in the first test row 11 through the input structure;
[0089] Step S33 , detecting whether the output structure outputs current by the detection structure, and if so, confirming that the transistors in the first test row 11 and the transistors in the second test row 12 are short-circuited.
[0090] In some embodiments, the specific steps of forming a semiconductor process monitoring structure include:
[0091] Providing a substrate and defining at least one test area in the substrate;
[0092] Forming a plurality of active regions arranged along the first direction D1 and the second direction D2 in the substrate of the test area, and forming a gate electrode 22 above the substrate of the active region to form the test structure;
[0093] The input structure and the output structure are formed above the test structure, and the detection structure electrically connected to the output structure is formed.
[0094] In some embodiments, a plurality of active regions arranged along the first direction D1 and the second direction D2 are formed in the substrate of the test area 10, and a gate electrode 22 is formed above the substrate of the active region to form the test structure. Specific steps include:
[0095] forming a plurality of active regions arranged along the first direction D1 and the second direction D2 in the substrate of the test area 10;
[0096] A plurality of gate electrodes 22 corresponding to the plurality of active regions are formed on the substrate, and a distance between two adjacent gate electrodes 22 along the second direction D2 is greater than a distance between two adjacent gate electrodes 22 along the first direction D1.
[0097] In some embodiments, the plurality of test regions 10 are arranged along the first direction D1; the specific steps of forming a plurality of active regions arranged along the first direction D1 and the second direction D2 in the substrate of the test region 10, and forming a gate electrode 22 above the substrate of the active region include:
[0098] forming a plurality of active regions arranged along the first direction D2 and the second direction D3 in the substrate of each of the test regions 10;
[0099] A plurality of gate electrodes 22 corresponding to the plurality of active regions are formed above the substrate, and a spacing between the gate electrodes 22 in two adjacent test regions 10 along the first direction D1 is greater than a spacing between two adjacent gate electrodes 22 in the same test region 10 along the first direction D1.
[0100] For example, for each of the test areas 10, two rows of active areas are formed along the first direction D1, and each row of active areas includes a plurality of active areas arranged at intervals along the second direction D2. After the gate electrode 22 is formed above each of the active areas, two rows of transistors are formed along the first direction D1 in each of the test areas 10, with one row of transistors serving as the first test row 11 and the other row of transistors serving as the second test row. The spacing W between the gate electrodes 22 in two adjacent test areas 10 along the first direction D1 is greater than the spacing between two adjacent gate electrodes 22 in the same test area 10 along the first direction D1 (i.e., the spacing E between the gate electrodes 22 of the transistors in the first test row 11 and the gate electrodes 22 of the transistors in the second test row 12 in the same test area 10), thereby improving the accuracy of positioning the position where the short circuit bridge occurs between the gate electrodes.
[0101] In some embodiments, the specific steps of forming the input structure and the output structure above the test structure, and forming the detection structure electrically connected to the output structure include:
[0102] forming a dielectric layer covering the test structure;
[0103] Forming a plurality of input conductive plugs 15 electrically connected one by one to the gate electrodes 22 of the plurality of transistors in the first test row 11 and an input connection line 16 electrically connecting all the input conductive plugs 15 in succession on the dielectric layer, and forming a plurality of output conductive plugs 18 electrically connected one by one to the gate electrodes 22 of the plurality of transistors in the second test row 12 and an output connection line 19 electrically connecting all the output conductive plugs 18 in succession on the dielectric layer, so as to form the input structure including the input conductive plugs 15 and the input connection line 16 and the output structure including the output conductive plugs 18 and the output connection line 19;
[0104] The detection structure electrically connected to the output connection line 19 is formed.
[0105] In some embodiments, the gate electrodes 22 of the transistors in the first test row 11 and the gate electrodes 22 of the transistors in the second test row 12 both extend along the first direction D1; forming a plurality of input conductive plugs 15 electrically connected one by one to the gate electrodes 22 of the plurality of transistors in the first test row 11 and an input connection line 16 electrically connecting all the input conductive plugs 15 in a continuous manner above the dielectric layer, and forming a plurality of output conductive plugs 18 electrically connected one by one to the gate electrodes 22 of the plurality of transistors in the second test row 12 and an output connection line 19 electrically connecting all the output conductive plugs 18 in a continuous manner above the dielectric layer include:
[0106] The input conductive plug 15 is formed to be electrically connected to the end of the gate electrode 22 of the transistor in the first test row 11 away from the second test row 12 along the first direction D1, and the output conductive plug 18 is formed to be electrically connected to the end of the gate electrode 22 of the transistor in the second test row 12 away from the first test row 11 along the first direction D1, so as to reduce signal crosstalk between the input structure and the output structure.
[0107] In some embodiments, the semiconductor process monitoring method further includes the following steps:
[0108] forming a plurality of the semiconductor process monitoring structures, wherein the sizes of the test structures in the plurality of the semiconductor process monitoring structures are different;
[0109] respectively monitoring whether the transistors in the first test row 11 and the transistors in the second test row 12 in each of the semiconductor process monitoring structures are short-circuited;
[0110] The test structure in which the transistors in the first test row 11 and the transistors in the second test row 12 are not short-circuited and has the smallest size is selected as the target test structure.
[0111] In some embodiments, the different sizes of the test structure include any one or a combination of two or more of the length L of the gate electrode 22 along the first direction D1, the width R of the gate electrode 22 along the second direction D2, the spacing between adjacent gate electrodes 22 along the second direction D2 (e.g., the spacing S between the gate electrodes 22 of adjacent transistors in the first test row 11), and the spacing between adjacent gate electrodes 22 along the first direction D1 (e.g., the spacing E between the gate electrodes 22 of the transistors in the first test row 11 and the gate electrodes 22 of the transistors in the second test row 12 in the same test area 10). In one example, the length L of the gate electrode 22 along the first direction D1 may be 270nm to 5000nm, and the width R of the gate electrode 22 along the second direction D2 may be 24nm to 50nm.
[0112] For example, by setting up a plurality of test structures of different sizes and performing short-circuit bridging detection on the semiconductor process monitoring structure having the test structures of different sizes respectively, the minimum spacing between the gate electrodes can be obtained while ensuring that short-circuit bridging does not occur, thereby ensuring the performance of the semiconductor device while further reducing the size of the semiconductor device, providing further reference for the improvement of the semiconductor process.
[0113] The semiconductor process monitoring structure and semiconductor process monitoring method provided in this specific embodiment are configured to include a first test row and a second test row arranged at intervals along a first direction, wherein the first test row and the second test row both include a plurality of transistors arranged at intervals along a second direction, and the input structure is electrically connected to the gate electrodes of the plurality of transistors in the first test row, and the output structure is electrically connected to the gate electrodes of the plurality of transistors in the second test row, thereby determining whether the transistors in the first test row and the transistors in the second test row are short-circuited by detecting whether the output current of the output structure is detected by the detection structure, so as to monitor the manufacturing process of the gate electrode in the transistor. This specific embodiment is not limited by the size of the gate electrode and the spacing between adjacent gate electrodes, and can monitor the risk of short-circuit bridging between small-sized gate electrodes, thereby providing a reference for improving the performance of semiconductor devices and improving semiconductor manufacturing processes. At the same time, this specific embodiment limits the spacing between the gate electrodes of adjacent transistors in the first test row to be greater than the spacing between the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row, thereby being able to accurately determine whether a short circuit bridge occurs between the transistors in the first test row and the transistors in the second test row, that is, being able to accurately determine the location of the short circuit, thereby providing further reference for improving the performance of semiconductor devices and improving semiconductor manufacturing processes.
[0114] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A semiconductor process monitoring structure, characterized in that: include: A test structure, comprising at least one test area, wherein the test area at least comprises a first test row and a second test row arranged at intervals along a first direction, wherein the first test row and the second test row each comprise a plurality of transistors arranged at intervals along a second direction, and the first direction intersects the second direction perpendicularly; an input structure electrically connected to gate electrodes of a plurality of the transistors in the first test row; an output structure electrically connected to gate electrodes of a plurality of the transistors in the second test row; The detection structure is connected to the output structure and is used to detect whether the output structure outputs current.
2. The semiconductor process monitoring structure according to claim 1, characterized in that: The test structure includes a plurality of test areas arranged at intervals along the first direction, the input structure is electrically connected to the gate electrodes of all the transistors in the first test rows within all the test areas, and the output structure is electrically connected to the gate electrodes of all the transistors in the second test rows within all the test areas.
3. The semiconductor process monitoring structure according to claim 2, characterized in that: In the same test area, a distance between the gate electrodes of adjacent transistors in the first test row is greater than a distance between the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row.
4. The semiconductor process monitoring structure according to claim 3, characterized in that: The input structure comprises a plurality of input conductive plugs and an input connection line, wherein the plurality of input conductive plugs are electrically connected to the gate electrodes of the plurality of transistors in the first test row in a one-to-one correspondence, and the input connection line is electrically connected to all the input conductive plugs in a continuous manner; The output structure includes a plurality of output conductive plugs and output connection lines. The plurality of output conductive plugs are electrically connected to the gate electrodes of the plurality of transistors in the second test row in a one-to-one correspondence. The output connection lines electrically connect all the output conductive plugs in a continuous manner.
5. The semiconductor process monitoring structure according to claim 4, characterized in that: The input structure further includes an input pad electrically connected to the input connection line, and the output structure further includes an output pad electrically connected to the output connection line; The input pad and the output pad are distributed on two opposite sides of the test structure along the second direction.
6. The semiconductor process monitoring structure according to claim 4, characterized in that: The gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row both extend along the first direction; The input conductive plug is electrically connected to the end of the gate electrode of the transistor in the first test row away from the second test row along the first direction, and the output conductive plug is electrically connected to the end of the gate electrode of the transistor in the second test row away from the first test row along the first direction.
7. The semiconductor process monitoring structure according to claim 6, characterized in that: The spacing width between two adjacent test regions along the first direction is greater than the spacing between the gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row in the same test region.
8. The semiconductor process monitoring structure according to claim 1, characterized in that: Also includes: a substrate, a gate electrode of the transistor in the test structure being located above the substrate; The grounding structure is electrically connected to the substrate.
9. A semiconductor process monitoring method, characterized in that: The steps include: forming a semiconductor process monitoring structure, the semiconductor process monitoring structure comprising a test structure, an input structure, an output structure and a detection structure, the test structure comprising at least one test area, the test area comprising at least a first test row and a second test row arranged at intervals along a first direction, the first test row and the second test row each comprising a plurality of transistors arranged at intervals along a second direction, the input structure being electrically connected to gate electrodes of the plurality of transistors in the first test row, the output structure being electrically connected to gate electrodes of the plurality of transistors in the second test row, the detection structure being connected to the output structure, and the first direction intersects the second direction perpendicularly; transmitting a test signal to a plurality of said transistors in said first test row through said input structure; The detection structure is used to detect whether the output structure outputs current. If so, it is confirmed that the transistors in the first test row are short-circuited with the transistors in the second test row.
10. The semiconductor process monitoring method according to claim 9, characterized in that: The specific steps of forming a semiconductor process monitoring structure include: Providing a substrate and defining at least one test area in the substrate; forming a plurality of active regions arranged along the first direction and the second direction in the substrate of the test area, and forming a gate electrode above the substrate of the active region to form the test structure; The input structure and the output structure are formed above the test structure, and the detection structure electrically connected to the output structure is formed.
11. The semiconductor process monitoring method according to claim 10, characterized in that: The specific steps of forming a plurality of active regions arranged along the first direction and the second direction in the substrate of the test area, and forming a gate electrode above the substrate of the active area to form the test structure include: forming a plurality of active regions arranged along the first direction and the second direction in the substrate of the test area; A plurality of gate electrodes corresponding to the plurality of active regions are formed on the substrate, and a distance between two adjacent gate electrodes along the second direction is greater than a distance between two adjacent gate electrodes along the first direction.
12. The semiconductor process monitoring method according to claim 11, characterized in that: The specific steps of arranging a plurality of the test areas along the first direction; forming a plurality of active areas arranged along the first direction and the second direction in the substrate of the test area, and forming a gate electrode above the substrate of the active area include: forming a plurality of active regions arranged along the first direction and the second direction in the substrate of each of the test regions; A plurality of gate electrodes corresponding to the plurality of active regions are formed above the substrate, and a spacing between the gate electrodes in two adjacent test regions along the first direction is greater than a spacing between two adjacent gate electrodes in the same test region along the first direction.
13. The semiconductor process monitoring method according to claim 10, characterized in that: The specific steps of forming the input structure and the output structure above the test structure and forming the detection structure electrically connected to the output structure include: forming a dielectric layer covering the test structure; forming, on the dielectric layer, a plurality of input conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the first test row and an input connection line electrically connecting all the input conductive plugs in succession, and forming, on the dielectric layer, a plurality of output conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the second test row and an output connection line electrically connecting all the output conductive plugs in succession, so as to form the input structure including the input conductive plugs and the input connection line and the output structure including the output conductive plugs and the output connection line; The detection structure electrically connected to the output connection line is formed.
14. The semiconductor process monitoring method according to claim 13, characterized in that: The gate electrodes of the transistors in the first test row and the gate electrodes of the transistors in the second test row are both extended along the first direction; forming a plurality of input conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the first test row and input connection lines electrically connecting all the input conductive plugs in succession above the dielectric layer, and forming a plurality of output conductive plugs electrically connected one by one to the gate electrodes of the plurality of transistors in the second test row and output connection lines electrically connecting all the output conductive plugs in succession above the dielectric layer include: The input conductive plug is formed to be electrically connected to the end of the gate electrode of the transistor in the first test row away from the second test row along the first direction, and the output conductive plug is formed to be electrically connected to the end of the gate electrode of the transistor in the second test row away from the first test row along the first direction.
15. The semiconductor process monitoring method according to claim 11, characterized in that: The following steps are also included: forming a plurality of the semiconductor process monitoring structures, wherein the sizes of the test structures in the plurality of the semiconductor process monitoring structures are different; respectively monitoring whether the transistors in the first test row and the transistors in the second test row in each of the semiconductor process monitoring structures are short-circuited; The test structure in which the transistors in the first test row and the transistors in the second test row are not short-circuited and has the smallest size is selected as a target test structure.
16. The semiconductor process monitoring method according to claim 15, characterized in that: The different dimensions of the test structure include any one of the length of the gate electrode along the first direction, the width of the gate electrode along the second direction, the spacing between adjacent gate electrodes along the second direction, and the spacing between adjacent gate electrodes along the first direction, or a combination of two or more thereof.