VCSEL (Vertical Cavity Surface Emitting Laser) chip and preparation method thereof, light emitting component and optical module

Abstract

The invention relates to a VCSEL chip and a preparation method thereof, a light emitting assembly and an optical module. The VCSEL chip comprises a substrate, a heat conduction part and a VCSEL device function layer which are sequentially arranged on the substrate, and a heating layer arranged on the side, away from the heat conduction part, of the substrate. Wherein the substrate is provided with a through hole; and the heating layer is connected with the heat conduction part through the through hole, so that heat generated by the heating layer is transmitted to the VCSEL device functional layer through the heat conduction part. Under the condition that the VCSEL chip is in a low-temperature environment, the VCSEL chip can be heated through the heating layer, and heat generated by the heating layer is quickly transmitted to the VCSEL device functional layer through the heat conduction part, so that the transmission performance of the VCSEL device functional layer is not influenced by the low-temperature environment. And heat generated by the VCSEL chip can be efficiently conducted out through the heat conduction part, so that the heat dissipation efficiency of the VCSEL chip can be improved, and the situation that the output power of the VCSEL chip is reduced due to continuous temperature rise is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of VCSEL chips, and in particular to a VCSEL chip and a preparation method thereof, a light emitting component and an optical module. Background Art

[0002] With the continuous development of high-speed optical communication technology, VCSEL (Vertical Cavity Surface Emitting Laser) is widely used in multi-mode optical modules. The optical transmitter is a component used to convert electrical signals into optical signals in the optical network terminal (ONT), which mainly includes a laser and a driving circuit for driving the laser.

[0003] Since ONT is generally required to be able to operate in an environment of -40 degrees Celsius to +85 degrees Celsius, and the internal resistance of VCSEL increases as the temperature drops, the temperature range that the laser in the optical transmission component can adapt to is required to be high.

[0004] However, there is no corresponding solution for existing VCSEL chips to deal with the impact of low-temperature working environments. Summary of the invention

[0005] Based on this, it is necessary to provide a VCSEL chip and its preparation method, a light emitting component and an optical module that can improve the working performance of the VCSEL chip in a low temperature environment in order to solve the above technical problems.

[0006] In a first aspect, the present application provides a VCSEL chip, the VCSEL chip comprising a substrate, a heat conducting portion and a VCSEL device functional layer sequentially arranged on the substrate, and a heating layer arranged on a side of the substrate away from the heat conducting portion;

[0007] Wherein, the substrate is provided with a through hole; the heating layer is connected to the heat conducting part through the through hole, so that the heat generated by the heating layer is transmitted to the VCSEL device functional layer through the heat conducting part.

[0008] In one of the embodiments, the VCSEL device functional layer includes a buffer layer;

[0009] Wherein, the heat conducting portion is a heavily doped layer formed by ion implantation into the buffer layer through the through hole.

[0010] In one of the embodiments, the VCSEL device functional layer further includes an N-DBR layer disposed on the buffer layer;

[0011] Wherein, the heat conducting portion is a heavily doped layer formed by ion implantation into the buffer layer and a portion of the N-DBR layer through the through hole.

[0012] In one of the embodiments, the VCSEL device functional layer further includes an MQW layer and a P-DBR layer which are sequentially arranged on a side of the N-DBR layer away from the buffer layer;

[0013] A groove is formed in the VCSEL device functional layer and extends from a side of the P-DBR layer away from the MQW layer to at least a portion of the N-DBR layer along the thickness direction, so that the VCSEL chip is divided into a plurality of VCSEL units through the groove.

[0014] In one of the embodiments, an orthographic projection of the heat conducting portion on the substrate at least partially overlaps with an orthographic projection of the through hole on the substrate.

[0015] In one of the embodiments, the orthographic projection shape of the heat conducting portion on the substrate includes one of an ellipse, a ring, and a bar.

[0016] In one embodiment, the orthographic projection shape of the heat conducting portion on the substrate is a plurality of strips, and the strips are parallel to each other.

[0017] In one embodiment, the heating layer is configured with a first power connection terminal and a second power connection terminal; the heat conducting portion is configured with a third power connection terminal and a fourth power connection terminal;

[0018] The first electrical terminal of the heating layer is electrically connected to the third electrical terminal of the heat conducting part through the through hole, and the second electrical terminal of the heating layer is electrically connected to the fourth electrical terminal of the heat conducting part through the through hole, so that the heat conducting part and the heating layer are connected in parallel.

[0019] In one embodiment, the through hole is filled with the same metal thermal conductive material as the heating layer.

[0020] In one embodiment, the material of the heating layer includes at least one of TiN, W, and Cu.

[0021] In a second aspect, the present application further provides a method for preparing a VCSEL chip, which is used to prepare the VCSEL chip as described above; the method comprises:

[0022] Providing a substrate having a VCSEL device functional layer formed thereon;

[0023] A groove is formed on a side of the substrate facing away from the VCSEL device functional layer to form a through hole penetrating the substrate;

[0024] Performing ion implantation into the functional layer of the VCSEL device through the through hole to prepare a heat conducting portion;

[0025] A heating layer is formed on the through hole and on a side of the substrate away from the VCSEL device functional layer, so that the heating layer is connected to the heat conducting part through the through hole.

[0026] In a third aspect, the present application also provides a light emitting component, comprising a driver and at least one VCSEL chip as described above, which is electrically connected to the driver.

[0027] In a fourth aspect, the present application further provides an optical module, comprising an optical emitting component and an optical receiving component, wherein the optical emitting component adopts the optical emitting component as described above.

[0028] The above-mentioned VCSEL chip, method for preparing VCSEL chip, optical emission component and optical module, the VCSEL chip includes a substrate, a heat conducting part and a VCSEL device functional layer sequentially arranged on the substrate, and a heating layer arranged on the side of the substrate away from the heat conducting part; wherein, the substrate is provided with a through hole; the heating layer is connected to the heat conducting part through the through hole, so that the heat generated by the heating layer is transmitted to the VCSEL device functional layer through the heat conducting part. It can be seen that when the VCSEL chip is in a low temperature environment, the VCSEL chip of the present application can be heated by the heating layer, and the heat generated by the heating layer is quickly transmitted to the VCSEL device functional layer through the heat conducting part, so that the transmission performance of the VCSEL device functional layer is not affected by the low temperature environment. And the heat generated by the VCSEL chip can be efficiently conducted away through the heat conducting part, so the heat dissipation efficiency of the VCSEL chip in the present application can also be improved, avoiding the continuous increase in temperature and causing the output power of the VCSEL chip to decrease. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 This is one of the structural schematic diagrams of a VCSEL chip in one embodiment;

[0031] Figure 2 A schematic diagram of a parallel connection between a heating layer and a heat conducting part in an embodiment;

[0032] Figure 3 This is a second structural schematic diagram of a VCSEL chip in an embodiment;

[0033] Figure 4 This is a third structural diagram of a VCSEL chip in an embodiment;

[0034] FIG5( a ) is a schematic diagram showing that the orthographic projection shape of the heat conducting portion on the substrate is a circle in one embodiment;

[0035] FIG5( b ) is a schematic diagram showing that the orthographic projection shape of the heat conducting portion on the substrate is a ring in one embodiment;

[0036] FIG5( c ) is a schematic diagram showing that the orthographic projection shape of the heat conducting portion on the substrate is a bar in one embodiment;

[0037] Figure 6 This is a fourth structural schematic diagram of a VCSEL chip in an embodiment;

[0038] Figure 7 A schematic diagram of a process for preparing a VCSEL chip in an embodiment.

[0039] Description of Figure Numbers:

[0040] 100: VCSEL chip; 110: heating layer; 111: first power terminal; 112: second power terminal; 120: substrate; 121: through hole; 130: heat conduction part; 131: third power terminal; 132: fourth power terminal; 140: VCSEL device functional layer; 141: buffer layer; 142: N-DBR layer; 143: MQW layer; 144: P-DBR layer; 150: groove. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0042] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0044] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0045] See attached Figure 1 , attached Figure 1 One of the structural schematic diagrams of the VCSEL chip 100 in one embodiment of the present application is shown. The VCSEL chip 100 in this embodiment includes a substrate 120, a heat conducting portion 130 and a VCSEL device functional layer 140 sequentially arranged on the substrate 120, and a heating layer 110 arranged on the side of the substrate 120 away from the heat conducting portion 130; wherein the substrate 120 is provided with a through hole 121; the heating layer 110 is connected to the heat conducting portion 130 through the through hole 121, so that the heat generated by the heating layer 110 is transmitted to the VCSEL device functional layer 140 through the heat conducting portion 130.

[0046] The heating layer 110 has a resistance characteristic, and can generate heat when powered by the resistance characteristic, thereby transferring the heat to the VCSEL device functional layer 140 via the heat conducting portion 130 .

[0047] For example, the external temperature may be detected by a temperature detection module, and when the external temperature is lower than a preset temperature, the heating layer 110 is powered on so that the heating layer 110 starts to heat the VCSEL device functional layer 140 .

[0048] The substrate 120 provides mechanical support for the heat conducting part 130, the VCSEL device functional layer 140, etc., to ensure that the chip can withstand mechanical stress and external force. Exemplarily, the material of the substrate 120 may include gallium arsenide (GaAs), silicon (Si), gallium nitride (GaN), etc. When the VCSEL chip is working, a large amount of heat is generated. The substrate 120 serves as the main heat dissipation channel to conduct the heat from the inside of the chip to the external heat dissipation device. The substrate 120 helps to reduce the chip temperature and improve the performance and reliability of the chip. In this example, the thermal conductivity of the heating layer 110 and the heat conducting part 130 is better than that of the substrate 120, so that the heat dissipation efficiency of the VCSEL chip 100 can be improved, and the output power of the VCSEL chip 100 is prevented from decreasing due to the continuous increase in temperature.

[0049] The heat conducting part 130 can be implemented based on N-type or P-type ion implantation and / or silicon metallization. For example, the region to be doped of the etched substrate 120 can be treated with N-type or P-type ion implantation and / or silicon metallization, so that the material of the region to be doped of the substrate 120 has a resistance characteristic, thereby realizing the preparation of the heat conducting part 130, so that the heat conducting part 130 can further heat the VCSEL device functional layer 140 based on the heat generated by the heating layer 110.

[0050] The VCSEL device functional layer 140 refers to the core structural layer in the VCSEL chip that directly participates in laser generation, amplification and emission. The various functional layers in the VCSEL device functional layer 140 work together to ensure that the device can efficiently generate lasers and achieve vertical light emission.

[0051] Exemplarily, the VCSEL device functional layer 140 may include: an active layer (Active Region), a Bragg reflector layer (DBR, Distributed Bragg Reflector), an oxide layer (Oxidation Layer), a dielectric film layer, an electrode layer, etc. The active layer is the core area of ​​laser generation, responsible for the recombination and luminescence of carriers (electrons and holes). Exemplarily, the active layer may be composed of multiple quantum wells (MQW, Multiple Quantum Wells), such as InGaAs (Indium Gallium Arsenide) / GaAs (Gallium Arsenide) or AlGaInP (Aluminum Gallium Indium Phosphate) material system, which, under the injection of current, electrons and holes recombine in the active region, release photons, and amplify the light signal by stimulated radiation. The Bragg reflector layer is used to form a vertical resonant cavity, and realizes multiple reflections and resonant amplification of the light field through high reflectivity. The Bragg reflector layer is generally divided into an upper DBR and a lower DBR. The upper DBR and the lower DBR are located on the upper and lower sides of the active area, respectively. They are composed of periodically alternating high-refractive index and low-refractive index dielectric layers, such as AlGaAs (aluminum gallium arsenide) / AlAs (aluminum arsenide), which selectively reflect specific wavelengths by using the interference effect of light to form a vertical standing wave field. The oxide layer can be set in the DBR layer close to the active area. For example, in the P-type DBR (upper DBR), the high aluminum (such as AlAs or AlGaAs with high Al content) layer close to the active area is formed by a wet oxidation process. The oxide layer such as aluminum oxide (Al2O3) formed after oxidation has insulating properties and a greatly reduced refractive index. It can confine current and light to the active area in the vertical direction, reduce lateral current diffusion and light leakage, improve the performance and efficiency of the laser, and reduce the volume of the resonant cavity and the light output area, making the laser mode more stable. The dielectric film layer is used to cover the side walls and part of the surface of the chip. The material can be aluminum oxide (Al2O3) and the like. The dielectric film layer can protect the chip and prevent the chip from being affected by the external environment, such as preventing oxidation and corrosion. It also plays an insulating role to avoid short circuits between different electrodes or film layers. It can also improve the optical properties of the chip, such as reducing light scattering. The electrode layer includes an N-type electrode and a P-type electrode. The N-type electrode can be located on the surface of the substrate 120 or connected to the N-type DBR through a specific connection structure to provide an injection channel for electrons so that electrons can enter the active area inside the chip from the external circuit. It is usually composed of metal materials such as gold (Au), titanium (Ti), aluminum (Al), etc. The P-type electrode can be located at the top of the chip and contact the P-type DBR to inject holes and recombine with electrons in the active area to generate lasers. The material is similar to the N-type electrode, which is also a metal material and needs to have good conductivity and ohmic contact properties with semiconductor materials.

[0052] When the VCSEL chip 100 is in a low temperature environment, the VCSEL chip 100 in this embodiment can be heated by the heating layer 110, and the heat generated by the heating layer 110 is quickly transmitted to the VCSEL device functional layer 140 through the heat conducting portion 130, so that the transmission performance of the VCSEL device functional layer 140 is not affected by the low temperature environment. The thermal conductivity of the heat conducting portion 130 and the heating layer 110 is better than that of the substrate 120, so the heat generated by the VCSEL chip 100 can be efficiently conducted away through the heat conducting portion 130, and the heat dissipation efficiency of the VCSEL chip 100 in this application can also be improved, avoiding the temperature from continuously rising and causing the output power of the VCSEL chip 100 to decrease.

[0053] In one embodiment, see the attached Figure 2 , attached Figure 2 The schematic diagram of the parallel connection of the heating layer 110 and the heat conducting part 130 is shown. The heating layer 110 in this embodiment is configured with a first power connection terminal 111 and a second power connection terminal 112; the heat conducting part 130 is configured with a third power connection terminal 131 and a fourth power connection terminal 132; the first power connection terminal 111 of the heating layer 110 is electrically connected to the third power connection terminal 131 of the heat conducting part 130 via a through hole 121, and the second power connection terminal 112 of the heating layer 110 is electrically connected to the fourth power connection terminal 132 of the heat conducting part 130 via a through hole 121, so that the heat conducting part 130 and the heating layer 110 are connected in parallel.

[0054] The polarities of the first power connection terminal 111 and the second power connection terminal 112 in the heating layer 110 are different, and the polarities of the third power connection terminal 131 and the fourth power connection terminal 132 in the heat conducting portion 130 are different.

[0055] For example, Figure 2 The diagram shows a situation in which the first power connection terminal 111 of the heating layer 110 is connected to the third power connection terminal 131 of the heat conducting part 130 through the through hole 121, and the second power connection terminal 112 of the heating layer 110 is connected to the fourth power connection terminal 132 of the heat conducting part 130 through the through hole 121, wherein the first power connection terminal 111 of the heating layer 110 and the third power connection terminal 131 of the heat conducting part 130 have the same polarity (such as both are positive or both are negative), and the second power connection terminal 112 of the heating layer 110 and the fourth power connection terminal 132 of the heat conducting part 130 have the same polarity (such as both are negative or both are positive), so that the heating layer 110 and the heat conducting part 130 can be connected in parallel.

[0056] In this embodiment, the heating layer 110 is connected in parallel with the heat conducting part 130 through the first power connection terminal 111 and the second power connection terminal 112 of the heating layer 110 and the third power connection terminal 131 and the fourth power connection terminal 132 of the heat conducting part 130, so as to reduce the overall internal resistance of the VCSEL chip.

[0057] It is understandable that in other embodiments, further reference is made to the attached Figure 2 , if the polarities of the first power connection terminal 111 of the heating layer 110 and the third power connection terminal 131 of the heat conducting part 130 are opposite (e.g., one positive pole and one negative pole), and the polarities of the second power connection terminal 112 of the heating layer 110 and the fourth power connection terminal 132 of the heat conducting part 130 are also opposite (e.g., one negative pole and one positive pole), the heating layer 110 and the heat conducting part 130 can also be connected in series. In other embodiments, when there are multiple heat conducting parts 130 and heating layers 110, a mixed connection of series and parallel connection can also be set for the two, but it is not limited thereto.

[0058] In one embodiment, see the attached Figure 3 , attached Figure 3 FIG. 2 shows a second structural schematic diagram of the VCSEL chip 100 . The VCSEL device functional layer 140 in this embodiment includes a buffer layer 141 . The heat conducting portion 130 is a heavily doped layer formed by ion implantation into the buffer layer 141 through the through hole 121 .

[0059] Exemplarily, ion implantation may be performed on the buffer layer 141 through the through hole 121 to perform N++ doping (doping with high concentration of donor impurities such as phosphorus, arsenic, etc.) or P++ doping (doping with high concentration of acceptor impurities such as boron, aluminum, etc.).

[0060] In this embodiment, the heavily doped layer formed by ion implantation into the buffer layer 141 through the through hole 121 can ensure the heat conduction effect while not damaging the structures of other functional layers in the VCSEL device functional layer 140 .

[0061] In one embodiment, see the attached Figure 4 , attached Figure 4 The third structural diagram of the VCSEL chip 100 is shown. The VCSEL device functional layer 140 in this embodiment further includes an N-DBR layer 142 disposed on the buffer layer 141; wherein the heat conducting portion 130 is a heavily doped layer formed by ion implantation through the through hole 121 into the buffer layer 141 and a portion of the N-DBR layer 142.

[0062] In this embodiment, the buffer layer 141 and part of the N-DBR layer 142 may be simultaneously ion-implanted to form a heavily doped layer, so as to avoid the difficulty of the preparation process due to the thin buffer layer 141, and the thickness of the heat conducting part 130 decreases, thereby affecting the heat transfer effect. Therefore, the heavily doped layer formed by ion-implanting the buffer layer 141 and part of the N-DBR layer 142 at the same time can ensure the heat transfer effect of the heat conducting part 130 to the VCSEL device functional layer 140, thereby improving the heating efficiency.

[0063] In addition, in order to avoid a negative impact on the structure of the N-DBR layer 142 by forming a heavily doped layer through ion implantation into part of the N-DBR layer 142, the number of alternating stacks of high-refractive index and low-refractive index materials in the N-DBR layer 142 can be increased when preparing the N-DBR layer 142 to ensure its high reflectivity optical properties.

[0064] In one embodiment, the lattice constant of the buffer layer is between the lattice constant of the functional layer of the VCSEL device and the lattice constant of the substrate.

[0065] In this embodiment, the lattice constant of the buffer layer is also between the lattice constant of the VCSEL device functional layer and the lattice constant of the substrate, which can avoid the lattice adaptation problem between the VCSEL device functional layer and the substrate.

[0066] In one embodiment, the buffer layer may be an intrinsic semiconductor layer.

[0067] Intrinsic semiconductor is a pure semiconductor material that does not contain impurities and has a complete lattice structure. For example, when growing a germanium (Ge) epitaxial layer on a silicon (Si) substrate, due to the difference in the lattice constants of Si and Ge, a layer of silicon germanium (SiGe) alloy can be inserted between the two as a buffer layer. The lattice constant of SiGe can be adjusted by adjusting the Ge content to make it closer to the Si substrate and the Ge epitaxial layer, thereby alleviating the lattice mismatch.

[0068] In one embodiment, see the attached Figure 6 , attached Figure 6 The fourth structural diagram of the VCSEL chip is shown. The VCSEL device functional layer 140 in this embodiment further includes an MQW layer 143 and a P-DBR layer 144 which are sequentially arranged on the side of the N-DBR layer 142 away from the buffer layer 141; a groove 150 is formed in the VCSEL device functional layer 140, extending from the side of the P-DBR layer 144 away from the MQW layer 143 to at least part of the N-DBR layer 142 along the thickness direction, so that the VCSEL chip 100 is divided into a plurality of VCSEL units through the groove 150.

[0069] In this embodiment, the multiple VCSEL units are separated by the grooves 150, which can reduce the probability of mutual diffusion of materials in the VCSEL device functional layer 140 between the multiple VCSEL units, thereby reducing the risk of failure of the multiple VCSEL units, so that each VCSEL unit can work independently.

[0070] In one embodiment, an orthographic projection of the heat conducting portion on the substrate at least partially overlaps with an orthographic projection of the through hole on the substrate.

[0071] In this embodiment, the orthographic projection of the heat conducting part on the substrate at least partially overlaps with the orthographic projection of the through hole on the substrate, so that the heating layer can fully contact the heat conducting part through the through hole to achieve a tight connection, thereby improving heat transfer efficiency and heating effect.

[0072] In one embodiment, the orthographic projection shape of the heat conducting portion 130 on the substrate includes one of an ellipse, a ring, and a bar.

[0073] Among them, an ellipse can be understood as using a plane to cut a cone. When the angle between the plane and the axis of the cone is greater than the angle between the cone generatrix and the axis and less than 90 degrees, the intersection of the plane and the cone is an ellipse. When the plane is perpendicular to the axis of the cone, the resulting intersection is a circle. Therefore, a circle can also be regarded as a special case of an ellipse.

[0074] For example, referring to Figures 5(a) to 5(c), Figure 5(a) shows a case where the orthographic projection shape of the heat conducting portion 130 on the substrate is a circle; Figure 5(b) shows a case where the orthographic projection shape of the heat conducting portion 130 on the substrate is a ring; Figure 5(c) shows a case where the orthographic projection shape of the heat conducting portion 130 on the substrate is a strip.

[0075] In one embodiment, referring to FIG. 5( c ), the orthographic projection shape of the heat conducting portion 130 on the substrate is a plurality of strips, and the strips are parallel to each other.

[0076] In this embodiment, the orthographic projections of the plurality of strips of the heat conducting portion 130 on the substrate are parallel to each other, which can avoid interference between the plurality of heat conducting portions 130 and improve the heating stability of the heat conducting portion 130 .

[0077] In one embodiment, the through hole is filled with the same metal thermal conductive material as the heating layer, which can ensure the heat transfer effect between the heating layer and the heat conductive part and improve the heating efficiency.

[0078] In one embodiment, the material of the heating layer includes at least one of TiN (titanium nitride), W (tungsten), and Cu (copper).

[0079] In this embodiment, the heating layer is prepared by using at least one material of TiN (titanium nitride), W (tungsten), and Cu (copper), so that the heating layer has a resistance characteristic and achieves efficient heating.

[0080] In one example, the present application also provides a method for preparing a VCSEL chip, which is used to prepare the VCSEL chip in any of the above embodiments. The implementation solution for solving the problem provided by the method corresponds to the implementation solution recorded in the above VCSEL chip. Therefore, the specific limitations in one or more VCSEL chip preparation method embodiments provided below can refer to the above limitations on VCSEL chips and will not be repeated here.

[0081] See attached Figure 7 , attached Figure 7 A schematic flow chart of a method for preparing a VCSEL chip in this embodiment is shown. The method for preparing a VCSEL chip in this embodiment includes the following steps S701 to S704.

[0082] Step S701 , providing a substrate having a VCSEL device functional layer formed thereon.

[0083] Step S702 , grooves are formed on a side of the substrate facing away from the VCSEL device functional layer to form through holes penetrating the substrate.

[0084] Step S703 , ion implantation is performed on the VCSEL device functional layer through the through hole to prepare a heat conducting portion.

[0085] The orthographic projection of the heat conducting portion on the substrate may at least partially overlap with the orthographic projection of the through hole on the substrate.

[0086] Exemplarily, in some embodiments, the VCSEL device functional layer disposed on the side of the substrate away from the heating layer can be doped through a through hole to prepare a heat conducting portion. The VCSEL device functional layer may include a buffer layer and an N-DBR layer. When ion implantation is performed on the VCSEL device functional layer, ion implantation may be performed on the buffer layer, and doping is performed in the buffer layer to form a heavily doped layer, which can be used as a heat conducting portion. Ion implantation may also be performed on the buffer layer and a portion of the N-DBR layer, and doping is performed in the buffer layer and a portion of the N-DBR layer to form a heavily doped layer, which can be used as a heat conducting portion. The lattice constant of the buffer layer is between the lattice constant of the VCSEL device functional layer and the lattice constant of the substrate. For example, the material of the buffer layer may be an intrinsic semiconductor.

[0087] When preparing the heat conducting part, a third electrical terminal and a fourth electrical terminal of the heat conducting part may be prepared at positions corresponding to the through holes, so that the heat conducting part is electrically connected to the heating layer.

[0088] Exemplarily, before doping the VCSEL device functional layer disposed on the substrate through the through hole, etching can be performed on one side of the substrate close to the VCSEL device functional layer to form a doping track of a preset shape, so that when doping the VCSEL device functional layer through the through hole, it can be performed according to the doping track of the preset shape, so that the orthographic projection shape of the heat conducting portion on the substrate is a preset shape. Exemplarily, the preset shape can be one of an ellipse, a ring, and a bar. Wherein, when the orthographic projection shape of the heat conducting portion on the substrate is a plurality of bars, the bars can be parallel to each other.

[0089] Step S704 , forming a heating layer on the through hole and on a side of the substrate away from the VCSEL device functional layer, so that the heating layer is connected to the heat conducting part through the through hole.

[0090] For example, when preparing the heating layer, a first power terminal and a second power terminal can be prepared at both ends of the heating layer, respectively. The heating layer and the heat conducting part can be connected in parallel through the first power terminal and the second power terminal of the heating layer and the third power terminal and the fourth power terminal of the heat conducting part, thereby reducing the overall internal resistance of the VCSEL chip.

[0091] Exemplarily, the material of the heating layer may include at least one of TiN, W, and Cu.

[0092] In other embodiments, the buffer layer 141, the N-DBR layer 142, the MQW layer 143 and the P-DBR layer 144 are sequentially prepared, and etching is performed along the thickness direction from the side of the P-DBR layer 144 away from the MQW layer 143 to at least a portion of the N-DBR layer 142 to form the following Figure 6 The trenches 150 are shown so as to divide the VCSEL chip 100 into a plurality of VCSEL units through the trenches 150 .

[0093] The VCSEL chip prepared in this embodiment can be heated by the heating layer when the VCSEL chip is in a low-temperature environment, and the heat generated by the heating layer is quickly transmitted to the VCSEL device functional layer through the heat conducting part, so that the transmission performance of the VCSEL device functional layer is not affected by the low-temperature environment. And because the thermal conductivity of the heat conducting part and the heating layer is better than that of the substrate, the heat dissipation efficiency of the VCSEL chip in this application can also be improved, avoiding the continuous increase in temperature and causing the output power of the VCSEL chip to decrease.

[0094] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0095] In one embodiment, the present application further provides a light emitting component, which includes a driver and at least one VCSEL chip as described in any of the above embodiments electrically connected to the driver.

[0096] In the present embodiment, the light emitting assembly is heated by the heating layer of the VCSEL chip when it is in a low temperature environment, and the heat generated by the heating layer is quickly transmitted to the VCSEL device functional layer through the heat conducting part, so that the transmission performance of the VCSEL device functional layer is not affected by the low temperature environment, thereby ensuring the performance of the light emitting assembly. And because the thermal conductivity of the heat conducting part and the heating layer is better than that of the substrate, the heat dissipation efficiency of the VCSEL chip can also be improved, avoiding the continuous increase in temperature that causes the output power of the VCSEL chip to decrease, thereby affecting the performance of the light emitting assembly.

[0097] In one embodiment, the present application further provides an optical module, which includes a light emitting component and a light receiving component. The light emitting component is the light emitting component in the above embodiment.

[0098] In the optical module of this embodiment, when in a low-temperature environment, the heating layer of the VCSEL chip in the optical emission component is used for heating, and the heat generated by the heating layer is quickly transmitted to the VCSEL device functional layer through the heat-conducting part, so that the transmission performance of the VCSEL device functional layer is not affected by the low-temperature environment, thereby ensuring the performance of the optical module. And because the thermal conductivity of the heat-conducting part and the heating layer is better than that of the substrate, the heat dissipation efficiency of the VCSEL chip can also be improved, avoiding the continuous increase in temperature and causing the output power of the VCSEL chip to decrease, thereby affecting the performance of the optical module.

[0099] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0100] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A VCSEL chip, characterized in that: The VCSEL chip comprises a substrate, a heat conducting portion and a VCSEL device functional layer sequentially arranged on the substrate, and a heating layer arranged on a side of the substrate away from the heat conducting portion; Wherein, the substrate is provided with a through hole; the heating layer is connected to the heat conducting part through the through hole, so that the heat generated by the heating layer is transmitted to the VCSEL device functional layer through the heat conducting part.

2. The VCSEL chip according to claim 1, characterized in that: The VCSEL device functional layer includes a buffer layer; Wherein, the heat conducting portion is a heavily doped layer formed by ion implantation into the buffer layer through the through hole.

3. The VCSEL chip according to claim 2, characterized in that: The VCSEL device functional layer further includes an N-DBR layer disposed on the buffer layer; Wherein, the heat conducting portion is a heavily doped layer formed by ion implantation into the buffer layer and a portion of the N-DBR layer through the through hole.

4. The VCSEL chip according to claim 3, characterized in that: The VCSEL device functional layer further includes an MQW layer and a P-DBR layer which are sequentially arranged on a side of the N-DBR layer away from the buffer layer; A groove is formed in the VCSEL device functional layer and extends from a side of the P-DBR layer away from the MQW layer to at least a portion of the N-DBR layer along the thickness direction, so that the VCSEL chip is divided into a plurality of VCSEL units through the groove.

5. The VCSEL chip according to any one of claims 1 to 4, characterized in that: The orthographic projection of the heat conducting portion on the substrate at least partially overlaps with the orthographic projection of the through hole on the substrate.

6. The VCSEL chip according to any one of claims 1 to 4, characterized in that: The orthographic projection shape of the heat conducting portion on the substrate includes one of an ellipse, a ring, and a bar.

7. The VCSEL chip according to claim 6, characterized in that: The orthographic projection shape of the heat conducting portion on the substrate is a plurality of strips, and the strips are parallel to each other.

8. The VCSEL chip according to claim 1, characterized in that: The heating layer is provided with a first power connection terminal and a second power connection terminal; the heat conducting portion is provided with a third power connection terminal and a fourth power connection terminal; The first electrical terminal of the heating layer is electrically connected to the third electrical terminal of the heat conducting part via the through hole, and the second electrical terminal of the heating layer is electrically connected to the fourth electrical terminal of the heat conducting part via the through hole, so that the heat conducting part and the heating layer are connected in parallel.

9. The VCSEL chip according to claim 1, characterized in that: The through hole is filled with the same metal heat-conducting material as the heating layer.

10. The VCSEL chip according to claim 1 or 9, characterized in that: The material of the heating layer includes at least one of TiN, W and Cu.

11. A method for preparing a VCSEL chip, characterized in that: Used for preparing the VCSEL chip according to any one of claims 1 to 10; the method comprises: Providing a substrate having a VCSEL device functional layer formed thereon; A groove is formed on a side of the substrate facing away from the VCSEL device functional layer to form a through hole penetrating the substrate; Performing ion implantation into the functional layer of the VCSEL device through the through hole to prepare a heat conducting portion; A heating layer is formed on the through hole and on a side of the substrate away from the VCSEL device functional layer, so that the heating layer is connected to the heat conducting part through the through hole.

12. A light emitting component, characterized in that: The method comprises a driver and at least one VCSEL chip according to any one of claims 1 to 10 electrically connected to the driver.

13. An optical module, characterized in that: It comprises a light emitting component and a light receiving component, wherein the light emitting component adopts the light emitting component as claimed in claim 12.

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