VCSEL Chip, Its Preparation Method, Optical Emission Component and Optical Module

Abstract

The present application relates to a VCSEL chip and its preparation method, an optical emission component and an optical module. The VCSEL chip includes a substrate, a heat conducting portion and a VCSEL device functional layer sequentially arranged on the substrate, and a heating layer arranged on the side of the substrate away from the heat conducting portion; wherein the substrate is provided with a through hole; the heating layer is connected to the heat conducting portion through the through hole, so that the heat generated by the heating layer is transferred to the VCSEL device functional layer through the heat conducting portion. When the VCSEL chip is in a low-temperature environment, the VCSEL chip of the present application can be heated by the heating layer, and the heat generated by the heating layer is quickly transferred to the VCSEL device functional layer through the heat conducting portion, so that the transmission performance of the VCSEL device functional layer is not affected by the low-temperature environment. The heat generated by the VCSEL chip can be efficiently conducted away through the heat conducting portion, so that the heat dissipation efficiency of the VCSEL chip in the present application can also be improved, avoiding the continuous increase in temperature and the reduction in the output power of the VCSEL chip.

Description

Technical Field

[0001] The present application relates to the technical field of VCSEL chips, and in particular to a VCSEL chip and a preparation method thereof, a light emitting component, and an optical module. Background Art

[0002] With the continuous development of high-speed optical communication technology, VCSELs (Vertical Cavity Surface Emitting Lasers) are widely used in multimode optical modules. Optical transmitters (OTSs) are components in optical network terminals (ONTs) that convert electrical signals into optical signals. They primarily consist of lasers and the driver circuitry that drives them.

[0003] Since ONTs are generally required to operate in an environment of -40 degrees Celsius to 85 degrees Celsius, and the internal resistance of VCSELs increases as the temperature drops, the temperature range that the laser in the optical transmission component can adapt to is required to be high.

[0004] However, there is no corresponding solution for existing VCSEL chips to deal with the impact of low-temperature working environments. Summary of the invention

[0005] Based on this, it is necessary to address the above technical problems and provide a VCSEL chip and its preparation method, light emitting component and optical module that can improve the working performance of the VCSEL chip in a low-temperature environment.

[0006] In a first aspect, the present application provides a VCSEL chip, comprising a substrate, a heat conducting portion and a VCSEL device functional layer sequentially provided on the substrate, and a heating layer provided on a side of the substrate away from the heat conducting portion;

[0007] The substrate is provided with a through hole; the heating layer is connected to the heat conducting part through the through hole, so that the heat generated by the heating layer is transferred to the VCSEL device functional layer through the heat conducting part.

[0008] In one embodiment, the VCSEL device functional layer includes a buffer layer;

[0009] Wherein, the heat conducting portion is a heavily doped layer formed by ion implantation into the buffer layer through the through hole.

[0010] In one embodiment, the VCSEL device functional layer further includes an N-DBR layer provided on the buffer layer;

[0011] Wherein, the heat conducting part is a heavily doped layer formed by ion implanting the buffer layer and part of the N-DBR layer through the through hole.

[0012] In one embodiment, the functional layer of the VCSEL device further includes an MQW layer and a P-DBR layer sequentially disposed on a side of the N-DBR layer away from the buffer layer;

[0013] A groove is formed in the functional layer of the VCSEL device and extends from a side of the P-DBR layer away from the MQW layer to at least part of the N-DBR layer in the thickness direction, so as to divide the VCSEL chip into multiple VCSEL units through the groove.

[0014] In one embodiment, a positive projection of the heat conducting part on the substrate coincides with at least part of a positive projection of the through hole on the substrate.

[0015] In one embodiment, a shape of the positive projection of the heat conducting part on the substrate includes one of an ellipse, a ring, and a strip.

[0016] In one embodiment, the shape of the positive projection of the heat conducting part on the substrate is multiple strips, and the strips are parallel to each other.

[0017] In one embodiment, the heating layer is configured with a first power connection terminal and a second power connection terminal; the heat conducting part is configured with a third power connection terminal and a fourth power connection terminal;

[0018] The first power connection terminal of the heating layer is electrically connected to the third power connection terminal of the heat conducting part through the through hole, and the second power connection terminal of the heating layer is electrically connected to the fourth power connection terminal of the heat conducting part through the through hole, so that the heat conducting part and the heating layer are connected in parallel.

[0019] In one embodiment, the through hole is filled with the same metal heat conducting material as the heating layer.

[0020] In one embodiment, the material of the heating layer includes at least one of TiN, W, and Cu.

[0021] In a second aspect, the present application further provides a method for manufacturing a VCSEL chip for manufacturing the VCSEL chip as described above; the method includes:

[0022] Providing a substrate formed with a functional layer of a VCSEL device;

[0023] Grooving on a side of the substrate facing away from the functional layer of the VCSEL device to form a through hole penetrating the substrate;

[0024] Ion implant the functional layer of the VCSEL device through the through hole to prepare a heat conduction part;

[0025] Form a heating layer on the side of the through hole and the substrate facing away from the functional layer of the VCSEL device, so that the heating layer is connected to the heat conduction part through the through hole.

[0026] In a third aspect, the present application also provides an optical emission component, including a driver and at least one VCSEL chip electrically connected to the driver as described above.

[0027] In a fourth aspect, the present application also provides an optical module, including an optical emission component and an optical reception component, and the optical emission component adopts the optical emission component as described above.

[0028] For the above-mentioned VCSEL chip, the preparation method of the VCSEL chip, the optical emission component and the optical module, the VCSEL chip includes a substrate, a heat conduction part and a functional layer of the VCSEL device sequentially arranged on the substrate, and a heating layer arranged on the side of the substrate facing away from the heat conduction part; wherein, the substrate is provided with a through hole; the heating layer is connected to the heat conduction part through the through hole, so that the heat generated by the heating layer is transmitted to the functional layer of the VCSEL device through the heat conduction part. It can be seen that when the VCSEL chip is in a low-temperature environment, the VCSEL chip of the present application can be heated by the heating layer, and the heat generated by the heating layer is quickly transmitted to the functional layer of the VCSEL device through the heat conduction part, so that the transmission performance of the functional layer of the VCSEL device is not affected by the low-temperature environment. And the heat generated by the VCSEL chip can be efficiently conducted out through the heat conduction part, so the heat dissipation efficiency of the VCSEL chip in the present application can also be improved, avoiding the reduction of the output power of the VCSEL chip caused by continuous temperature rise. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0030] Figure 1 It is one of the schematic structural diagrams of the VCSEL chip in an embodiment;

[0031] Figure 2 It is a schematic diagram of the parallel connection of the heating layer and the heat conduction part in an embodiment;

[0032] Figure 3 It is another schematic structural diagram of the VCSEL chip in an embodiment;

[0033] Figure 4 It is the third schematic structural diagram of the VCSEL chip in an embodiment;

[0034] FIG. 5(a) is a schematic diagram showing that the orthographic projection shape of the heat conduction part on the substrate is circular in an embodiment;

[0035] FIG. 5(b) is a schematic diagram showing that the orthographic projection shape of the heat conduction part on the substrate is annular in an embodiment;

[0036] FIG. 5(c) is a schematic diagram showing that the orthographic projection shape of the heat conduction part on the substrate is strip-shaped in an embodiment;

[0037] Figure 6 It is the fourth schematic structural diagram of the VCSEL chip in an embodiment;

[0038] Figure 7 It is a schematic flow chart of the manufacturing method of the VCSEL chip in an embodiment.

[0039] Explanation of the reference numerals in the drawings:

[0040] 100: VCSEL chip; 110: heating layer; 111: first power connection terminal; 112: second power connection terminal; 120: substrate; 121: through hole; 130: heat conduction part; 131: third power connection terminal; 132: fourth power connection terminal; 140: VCSEL device functional layer; 141: buffer layer; 142: N-DBR layer; 143: MQW layer; 144: P-DBR layer; 150: trench. Detailed embodiments

[0041] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the detailed embodiments of the present application in conjunction with the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0042] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present application.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0044] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0045] See attached Figure 1 , attached Figure 1 FIG1 shows one structural schematic diagram of a VCSEL chip 100 in one embodiment of the present application. The VCSEL chip 100 in this embodiment includes a substrate 120, a heat conducting portion 130 and a VCSEL device functional layer 140 sequentially disposed on the substrate 120, and a heating layer 110 disposed on a side of the substrate 120 facing away from the heat conducting portion 130. The substrate 120 is provided with a through hole 121. The heating layer 110 is connected to the heat conducting portion 130 via the through hole 121, so that heat generated by the heating layer 110 is transferred to the VCSEL device functional layer 140 via the heat conducting portion 130.

[0046] The heating layer 110 has a resistance characteristic and can generate heat when powered by the resistance characteristic, thereby transferring the heat to the VCSEL device functional layer 140 through the heat conducting portion 130 .

[0047] For example, the external temperature may be detected by a temperature detection module. When the external temperature is lower than a preset temperature, the heating layer 110 is powered on so that the heating layer 110 starts to heat the VCSEL device functional layer 140 .

[0048] The substrate 120 provides mechanical support for the heat conduction part 130, the VCSEL device functional layer 140, etc., ensuring that the chip can withstand mechanical stress and external forces. Exemplarily, the material of the substrate 120 may include gallium arsenide (GaAs), silicon (Si), gallium nitride (GaN), etc. When the VCSEL chip operates, a large amount of heat is generated. The substrate 120, as the main heat dissipation channel, conducts the heat from the inside of the chip to the external heat dissipation device. The substrate 120 helps to reduce the chip temperature and improve the performance and reliability of the chip. In this example, the thermal conductivity coefficients of the heating layer 110 and the heat conduction part 130 are better than that of the substrate 120, so that the heat dissipation efficiency of the VCSEL chip 100 can be improved, and the output power of the VCSEL chip 100 is prevented from decreasing due to continuous temperature increase.

[0049] The heat conduction part 130 can be realized based on N-type or P-type ion implantation and / or silicon metallization. For example, the N-type or P-type ion doping treatment and / or silicon metallization treatment can be performed on the to-be-doped area of the etched substrate 120, so that the material of the to-be-doped area of the substrate 120 has resistance characteristics, thereby realizing the preparation of the heat conduction part 130, so that the heat conduction part 130 can further heat the VCSEL device functional layer 140 based on the heat generated by the heating layer 110.

[0050] The VCSEL device functional layer 140 refers to the core structural layer in the VCSEL chip that directly participates in laser generation, amplification, and emission. Each functional layer in the VCSEL device functional layer 140 works together to ensure that the device can efficiently generate laser and achieve light emission in the vertical direction.

[0051] Exemplarily, the VCSEL device functional layer 140 may include: an active region, a distributed Bragg reflector (DBR) layer, an oxidation layer, a dielectric film layer, an electrode layer, etc. The active region is the core area where laser generation occurs, responsible for the recombination luminescence of carriers (electrons and holes). Exemplarily, the active region may be composed of multiple quantum wells (MQWs), such as InGaAs (indium gallium arsenide) / GaAs (gallium arsenide) or AlGaInP (aluminum gallium indium phosphide) material systems. Under the injection of current, electrons and holes recombine in the active region, releasing photons and amplifying the optical signal through stimulated emission. The distributed Bragg reflector layer is used to form a vertical resonant cavity, and through high reflectivity, multiple reflections and resonance amplification of the optical field are achieved. The distributed Bragg reflector layer is generally divided into an upper DBR and a lower DBR, which are respectively located on the upper and lower sides of the active region and are composed of periodically alternating high-refractive-index and low-refractive-index dielectric layers, such as AlGaAs (aluminum gallium arsenide) / AlAs (aluminum arsenide). It uses the interference effect of light to selectively reflect specific wavelengths and form a standing wave field in the vertical direction. The oxidation layer can be disposed in the DBR layer near the active region. For example, in the P-type DBR (upper DBR), a high-aluminum (such as AlAs or AlGaAs with a high Al component) layer near the active region is formed through a wet oxidation process. The oxidation layer such as aluminum oxide (Al2O3) formed after oxidation has insulation properties and a greatly reduced refractive index, which can confine current and light in the active region in the vertical direction, reduce lateral current diffusion and light leakage, improve the performance and efficiency of the laser, and also reduce the volume of the resonant cavity and the light-emitting area, making the laser mode more stable. The dielectric film layer is used to cover the sidewalls and part of the surface of the chip, and the material can be aluminum oxide (Al2O3), etc. The dielectric film layer can protect the chip from the influence of the external environment, such as preventing oxidation, corrosion, etc., and at the same time also plays an insulating role to avoid short circuits between different electrodes or film layers, and can also improve the optical characteristics of the chip, such as reducing light scattering, etc. The electrode layer includes an N-type electrode and a P-type electrode. The N-type electrode can be located on the surface of the substrate 120 or connected to the N-type DBR through a specific connection structure, providing an injection channel for electrons, enabling electrons to enter the active region inside the chip from the external circuit. It is usually composed of metal materials such as gold (Au), titanium (Ti), aluminum (Al), etc. The P-type electrode can be located on the top of the chip, in contact with the P-type DBR, for injecting holes and recombining with electrons in the active region to generate laser. The material is similar to that of the N-type electrode and is also a metal material, which needs to have good electrical conductivity and ohmic contact characteristics with semiconductor materials.

[0052] When the VCSEL chip 100 is in a low-temperature environment, the VCSEL chip 100 in this embodiment can be heated by the heating layer 110, and the heat generated by the heating layer 110 is quickly transmitted to the VCSEL device functional layer 140 through the heat conduction part 130, so that the transmission performance of the VCSEL device functional layer 140 is not affected by the low-temperature environment. The heat conduction coefficients of the heat conduction part 130 and the heating layer 110 are better than those of the substrate 120. Therefore, the heat generated by the VCSEL chip 100 can be efficiently conducted out through the heat conduction part 130, and the heat dissipation efficiency of the VCSEL chip 100 in this application can also be improved, avoiding the reduction of the output power of the VCSEL chip 100 caused by continuous temperature rise.

[0053] In one embodiment, referring to the attached Figure 2 , the attached Figure 2 shows a schematic diagram of the parallel connection of the heating layer 110 and the heat conduction part 130. The heating layer 110 in this embodiment is configured with a first power connection end 111 and a second power connection end 112; the heat conduction part 130 is configured with a third power connection end 131 and a fourth power connection end 132; the first power connection end 111 of the heating layer 110 is electrically connected to the third power connection end 131 of the heat conduction part 130 through the through hole 121, and the second power connection end 112 of the heating layer 110 is electrically connected to the fourth power connection end 132 of the heat conduction part 130 through the through hole 121, so that the heat conduction part 130 and the heating layer 110 are connected in parallel.

[0054] Among them, the polarities of the first power connection end 111 and the second power connection end 112 in the heating layer 110 are different, and the polarities of the third power connection end 131 and the fourth power connection end 132 in the heat conduction part 130 are different.

[0055] Exemplarily, the attached Figure 2 shows the situation where the first power connection end 111 of the heating layer 110 is connected to the third power connection end 131 of the heat conduction part 130 through the through hole 121, and the second power connection end 112 of the heating layer 110 is connected to the fourth power connection end 132 of the heat conduction part 130 through the through hole 121. Among them, the polarities of the first power connection end 111 of the heating layer 110 and the third power connection end 131 of the heat conduction part 130 are the same (such as both being positive or both being negative), and the polarities of the second power connection end 112 of the heating layer 110 and the fourth power connection end 132 of the heat conduction part 130 are the same (such as both being negative or both being positive). Therefore, the parallel connection of the heating layer 110 and the heat conduction part 130 can be realized.

[0056] In this embodiment, the parallel connection of the heating layer 110 and the heat conduction part 130 is achieved through the first power connection end 111 and the second power connection end 112 of the heating layer 110, and the third power connection end 131 and the fourth power connection end 132 of the heat conduction part 130, which can reduce the overall internal resistance of the VCSEL chip.

[0057] It can be understood that in other embodiments, continue to refer to the attached Figure 2 , if the polarities of the first power connection terminal 111 of the heating layer 110 and the third power connection terminal 131 of the heat conducting part 130 are opposite (such as one being positive and the other being negative), and the polarities of the second power connection terminal 112 of the heating layer 110 and the fourth power connection terminal 132 of the heat conducting part 130 are also opposite (such as one being negative and the other being positive), it can also make the heating layer 110 and the heat conducting part 130 connected in series. In other embodiments, when the number of the heat conducting part 130 and the heating layer 110 is multiple, it can also be set to be connected in a hybrid manner of series and parallel, and is not limited thereto.

[0058] In one embodiment, refer to the attached Figure 3 , the attached Figure 3 shows a second schematic structural diagram of the VCSEL chip 100. The VCSEL device functional layer 140 in this embodiment includes a buffer layer 141. Among them, the heat conducting part 130 is a heavily doped layer formed by ion implanting the buffer layer 141 through the through hole 121.

[0059] Exemplarily, the buffer layer 141 can be ion implanted through the through hole 121 to perform N++ doping (doping with a high concentration of donor impurities such as phosphorus, arsenic, etc.) or P++ doping (doping with a high concentration of acceptor impurities such as boron, aluminum, etc.).

[0060] In this embodiment, the heavily doped layer formed by ion implanting the buffer layer 141 through the through hole 121 can ensure the heat conduction effect while not damaging the structures of other functional layers in the VCSEL device functional layer 140.

[0061] In one embodiment, refer to the attached Figure 4 , the attached Figure 4 shows a third schematic structural diagram of the VCSEL chip 100. The VCSEL device functional layer 140 in this embodiment further includes an N-DBR layer 142 disposed on the buffer layer 141; among them, the heat conducting part 130 is a heavily doped layer formed by ion implanting the buffer layer 141 and a part of the N-DBR layer 142 through the through hole 121.

[0062] In this embodiment, it is also possible to simultaneously form a heavily doped layer by ion implanting the buffer layer 141 and a part of the N-DBR layer 142, avoiding the increase in the preparation process difficulty due to the thinness of the buffer layer 141, and the reduction in the thickness of the heat conducting part 130, which affects the heat transfer effect. Therefore, simultaneously forming a heavily doped layer by ion implanting the buffer layer 141 and a part of the N-DBR layer 142 can ensure the heat transfer effect of the heat conducting part 130 on the VCSEL device functional layer 140 and improve the heating efficiency.

[0063] In addition, to avoid the negative impact on the structure of the N-DBR layer 142 caused by the heavily doped layer formed by ion implantation of part of the N-DBR layer 142, the number of alternating stacks of high-refractive-index and low-refractive-index materials in the N-DBR layer 142 can be increased during the preparation of the N-DBR layer 142 to ensure its optical property of high reflectivity.

[0064] In one embodiment, the lattice constant of the buffer layer is between the lattice constant of the VCSEL device functional layer and the lattice constant of the substrate.

[0065] In this embodiment, the lattice constant of the buffer layer is also between the lattice constant of the VCSEL device functional layer and the lattice constant of the substrate, which can avoid the lattice matching problem between the VCSEL device functional layer and the substrate.

[0066] In one embodiment, the buffer layer can be an intrinsic semiconductor layer.

[0067] An intrinsic semiconductor is a pure semiconductor material without impurities and with a complete lattice structure. Exemplarily, when growing a germanium (Ge) epitaxial layer on a silicon (Si) substrate, due to the certain difference in the lattice constants of Si and Ge, a layer of silicon germanium (SiGe) alloy can be selected to be inserted between them as the buffer layer. The lattice constant of SiGe can be adjusted by adjusting the content of Ge to make it closer to the Si substrate and the Ge epitaxial layer, thereby alleviating the lattice mismatch.

[0068] In one embodiment, referring to the appendix Figure 6 , appendix Figure 6 shows the fourth schematic diagram of the structure of the VCSEL chip. The VCSEL device functional layer 140 in this embodiment further includes a MQW layer 143 and a P-DBR layer 144 sequentially disposed on the side of the N-DBR layer 142 away from the buffer layer 141; a trench 150 is formed in the VCSEL device functional layer 140 and extends from the side of the P-DBR layer 144 away from the MQW layer 143 to at least part of the N-DBR layer 142 in the thickness direction, so as to divide the VCSEL chip 100 into multiple VCSEL units through the trench 150.

[0069] In this embodiment, the multiple VCSEL units are separated by the trench 150, which can reduce the probability of material mutual diffusion in the VCSEL device functional layer 140 between the multiple VCSEL units, and further reduce the risk of failure of the multiple VCSEL units, so that each VCSEL unit can work independently.

[0070] In one embodiment, the orthographic projection of the heat conduction part on the substrate coincides with at least part of the orthographic projection of the through hole on the substrate.

[0071] In this embodiment, the orthographic projection of the heat conduction part on the substrate coincides with at least part of the orthographic projection of the through hole on the substrate, so that the heating layer can be in full contact with the heat conduction part through the through hole, achieving a tight connection, improving the heat transfer efficiency and heating effect.

[0072] In one embodiment, the shape of the orthographic projection of the heat conduction part 130 on the substrate includes one of an ellipse, a ring, and a strip.

[0073] Among them, an ellipse can be understood as using a plane to intercept a conical surface. When the angle formed by the plane and the axis of the conical surface is greater than the angle between the generatrix of the conical surface and the axis and less than 90 degrees, the intersection line of the plane and the conical surface is an ellipse. And when the plane is perpendicular to the axis of the cone, the obtained intersection line is a circle. Therefore, a circle can also be regarded as a special case of an ellipse.

[0074] Exemplarily, referring to FIGS. 5(a) to 5(c), FIG. 5(a) shows the case where the shape of the orthographic projection of the heat conduction part 130 on the substrate is a circle; FIG. 5(b) shows the case where the shape of the orthographic projection of the heat conduction part 130 on the substrate is a ring; FIG. 5(c) shows the case where the shape of the orthographic projection of the heat conduction part 130 on the substrate is a strip.

[0075] In one embodiment, continuing to refer to FIG. 5(c), the shape of the orthographic projection of the heat conduction part 130 on the substrate is a plurality of strips, and the strips are parallel to each other.

[0076] In this embodiment, the orthographic projection shapes of the plurality of strips of the heat conduction part 130 on the substrate are parallel to each other, which can avoid interaction between multiple heat conduction parts 130, causing interference, and improving the heating stability of the heat conduction part 130.

[0077] In one embodiment, the through hole is filled with the same metal heat conduction material as the heating layer, which can ensure the heat transfer effect between the heating layer and the heat conduction part and improve the heating efficiency.

[0078] In one embodiment, the material of the heating layer includes at least one of TiN (titanium nitride), W (tungsten), and Cu (copper).

[0079] In this embodiment, by preparing the heating layer with at least one of TiN (titanium nitride), W (tungsten), and Cu (copper), the heating layer can have resistance characteristics and achieve efficient heating.

[0080] In one example, the present application further provides a method for manufacturing a VCSEL chip. This method is used to manufacture the VCSEL chip in any of the above embodiments. The implementation solutions provided to solve the problems correspond to the implementation solutions described in the above VCSEL chip. Therefore, the specific limitations in one or more of the following embodiments of the method for manufacturing a VCSEL chip can refer to the limitations on the VCSEL chip in the foregoing text, and will not be elaborated herein.

[0081] Refer to the attached Figure 7 , the attached Figure 7 shows a schematic flowchart of the method for manufacturing a VCSEL chip in this embodiment. The method for manufacturing a VCSEL chip in this embodiment includes the following steps S701 to step S704.

[0082] Step S701: Provide a substrate formed with a VCSEL device functional layer.

[0083] Step S702: Groove one side of the substrate facing away from the VCSEL device functional layer to form a through hole penetrating the substrate.

[0084] Step S703: Perform ion implantation on the VCSEL device functional layer through the through hole to prepare a heat conduction portion.

[0085] The orthographic projection of the heat conduction portion on the substrate and the orthographic projection of the through hole on the substrate may at least partially coincide.

[0086] Exemplarily, in some embodiments, the VCSEL device functional layer provided on one side of the substrate facing away from the heating layer may be doped through the through hole to prepare a heat conduction portion. Among them, the VCSEL device functional layer may include a buffer layer and an N-DBR layer. When performing ion implantation on the VCSEL device functional layer, ion implantation may be performed on the buffer layer, and doping may be performed in the buffer layer to form a heavily doped layer, and this heavily doped layer may be used as the heat conduction portion. Ion implantation may also be performed on the buffer layer and a part of the N-DBR layer, and doping may be performed in the buffer layer and a part of the N-DBR layer to form a heavily doped layer, and this heavily doped layer may be used as the heat conduction portion. Among them, the lattice constant of the buffer layer is between the lattice constant of the VCSEL device functional layer and the lattice constant of the substrate. For example, the material of the buffer layer may be an intrinsic semiconductor.

[0087] When preparing the heat conduction portion, a third electrical connection end and a fourth electrical connection end of the heat conduction portion may be prepared at a position corresponding to the through hole, so that the heat conduction portion is electrically connected to the heating layer.

[0088] Exemplarily, before doping the functional layer of the VCSEL device provided on the substrate through the through-hole, the surface of the substrate close to the functional layer of the VCSEL device can be etched to form a doping track with a preset shape, so that when doping the functional layer of the VCSEL device through the through-hole, it can be carried out according to the doping track with the preset shape, so that the orthographic projection shape of the heat conduction part on the substrate is the preset shape. Exemplarily, the preset shape can be one of an ellipse, a ring, and a strip. Wherein, when the orthographic projection shape of the heat conduction part on the substrate is multiple strips, the strips can be parallel to each other.

[0089] Step S704, form a heating layer on the side of the through-hole and the substrate facing away from the functional layer of the VCSEL device, so that the heating layer is connected to the heat conduction part through the through-hole.

[0090] Exemplarily, when preparing the heating layer, a first power connection terminal and a second power connection terminal can be respectively prepared at both ends of the heating layer. The first power connection terminal and the second power connection terminal of the heating layer, the third power connection terminal and the fourth power connection terminal of the heat conduction part can make the heating layer and the heat conduction part connected in parallel, thereby reducing the overall internal resistance of the VCSEL chip.

[0091] Exemplarily, the material of the heating layer can include at least one of TiN, W, and Cu.

[0092] In other embodiments, it also includes sequentially preparing a buffer layer 141, an N-DBR layer 142, an MQW layer 143, and a P-DBR layer 144, and etching at least part of the N-DBR layer 142 along the thickness direction from the side of the P-DBR layer 144 away from the MQW layer 143 to form a trench 150 as shown in the appendix Figure 6 to divide the VCSEL chip 100 into multiple VCSEL units through the trench 150.

[0093] The VCSEL chip prepared in this embodiment can be heated by the heating layer when the VCSEL chip is in a low-temperature environment, and the heat generated by the heating layer is quickly transmitted to the functional layer of the VCSEL device through the heat conduction part, so that the transmission performance of the functional layer of the VCSEL device is not affected by the low-temperature environment. And because the heat conduction coefficients of the heat conduction part and the heating layer are better than those of the substrate, the heat dissipation efficiency of the VCSEL chip in this application can also be improved, avoiding the reduction of the output power of the VCSEL chip due to continuous temperature rise.

[0094] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0095] In one embodiment, the present application further provides an optical emission component, which includes a driver and at least one VCSEL chip electrically connected to the driver as described in any of the above embodiments.

[0096] In the optical emission component of this embodiment, in a low-temperature environment, heating is performed through the heating layer of the VCSEL chip, and the heat generated by the heating layer is quickly transmitted to the VCSEL device functional layer through the heat conduction part, so that the transmission performance of the VCSEL device functional layer is not affected by the low-temperature environment, ensuring the performance of the optical emission component. And because the heat conduction coefficients of the heat conduction part and the heating layer are better than those of the substrate, the heat dissipation efficiency of the VCSEL chip can also be improved, avoiding the reduction of the output power of the VCSEL chip due to continuous temperature rise, thereby affecting the performance of the optical emission component.

[0097] In one embodiment, the present application further provides an optical module, which includes an optical emission component and an optical reception component, and the optical emission component adopts the optical emission component in the above embodiment.

[0098] In the optical module of this embodiment, in a low-temperature environment, heating is performed through the heating layer of the VCSEL chip in the optical emission component, and the heat generated by the heating layer is quickly transmitted to the VCSEL device functional layer through the heat conduction part, so that the transmission performance of the VCSEL device functional layer is not affected by the low-temperature environment, ensuring the performance of the optical module. And because the heat conduction coefficients of the heat conduction part and the heating layer are better than those of the substrate, the heat dissipation efficiency of the VCSEL chip can also be improved, avoiding the reduction of the output power of the VCSEL chip due to continuous temperature rise, thereby affecting the performance of the optical module.

[0099] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in the present application.

[0100] The embodiments described above merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A VCSEL chip, characterized in that, The VCSEL chip includes a substrate, a heat conducting portion and a VCSEL device functional layer sequentially arranged on the substrate, and a heating layer arranged on a side of the substrate away from the heat conducting portion; The substrate is provided with a through hole; the heating layer is connected to the heat conducting portion through the through hole, so that the heat generated by the heating layer is transferred to the VCSEL device functional layer through the heat conducting portion; The VCSEL device functional layer includes a buffer layer; Wherein, the heat conducting portion is a heavily doped layer formed by ion implantation into the buffer layer through the through hole.

2. The VCSEL chip according to claim 1, wherein The VCSEL device functional layer further includes an N-DBR layer provided on the buffer layer; The heat conducting portion is a heavily doped layer formed by ion implantation into the buffer layer and a portion of the N-DBR layer through the through hole.

3. The VCSEL chip according to claim 2, wherein The VCSEL device functional layer further includes an MQW layer and a P-DBR layer sequentially arranged on a side of the N-DBR layer away from the buffer layer; A groove is formed in the VCSEL device functional layer and extends from a side of the P-DBR layer away from the MQW layer to at least a portion of the N-DBR layer along the thickness direction, so that the VCSEL chip is divided into a plurality of VCSEL units through the groove.

4. The VCSEL chip according to any one of claims 1-3, characterized in that, An orthographic projection of the heat conducting portion on the substrate at least partially overlaps with an orthographic projection of the through hole on the substrate.

5. The VCSEL chip according to any one of claims 1-3, characterized in that, The orthographic projection shape of the heat conducting portion on the substrate includes one of an ellipse, a ring, and a bar.

6. The VCSEL chip according to claim 5, characterized in that, The heat conducting portion has an orthographic projection shape on the substrate of a plurality of strips, and the strips are parallel to each other.

7. The VCSEL chip according to claim 1, characterized in that, The heating layer is provided with a first power terminal and a second power terminal; the heat conducting portion is provided with a third power terminal and a fourth power terminal; The first electrical terminal of the heating layer is electrically connected to the third electrical terminal of the heat conducting part through the through hole, and the second electrical terminal of the heating layer is electrically connected to the fourth electrical terminal of the heat conducting part through the through hole, so that the heat conducting part and the heating layer are connected in parallel.

8. The VCSEL chip according to claim 1, wherein The through hole is filled with the same metal heat-conducting material as the heating layer.

9. The VCSEL chip according to claim 1 or 8, characterized in that, The material of the heating layer includes at least one of TiN, W, and Cu.

10. A method for preparing a VCSEL chip, characterized in that, Used for preparing the VCSEL chip according to any one of claims 1 to 9; the method comprises: Providing a substrate with a VCSEL device functional layer formed thereon; Grooving a side of the substrate away from the VCSEL device functional layer to form a through hole penetrating the substrate; Performing ion implantation on the VCSEL device functional layer through the through hole to prepare a heat conducting portion; A heating layer is formed on the through hole and on a side of the substrate facing away from the VCSEL device functional layer, so that the heating layer is connected to the heat conducting portion through the through hole.

11. An optical emission component, characterized in that, The VCSEL chip comprises a driver and at least one VCSEL chip according to any one of claims 1 to 9 electrically connected to the driver.

12. An optical module, characterized in that, It comprises a light emitting component and a light receiving component, wherein the light emitting component adopts the light emitting component as claimed in claim 11.

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