A multi-channel charging port isolation circuit and charging method

Abstract

The present invention discloses a multi-channel charging port isolation circuit and method, comprising at least two selection circuits, including a first selection circuit comprising a first overvoltage protection chip and a second overvoltage protection chip connected in series back-to-back. The first voltage input pin of the first overvoltage protection chip is connected to a first power input, and the first voltage output pin of the first overvoltage protection chip is electrically connected to the second voltage output pin of the second overvoltage protection chip. The second voltage input pin of the second overvoltage protection chip is used to output a first charging voltage to a device to be charged. The circuit also includes a control device that outputs a first control signal and / or a second control signal to control the on and off of the overvoltage protection chips. The present invention has a simple structure and utilizes a "back-to-back" connection method of OVP chips to achieve multi-channel isolation and selection.

Description

Technical Field

[0001] The invention belongs to the field of multi-channel charging technology, and specifically relates to a multi-channel charging port isolation circuit and a charging method. Background Art

[0002] Some electronic devices have multiple charging inputs. Because different chargers have different voltages on each input, plugging in multiple power sources simultaneously can easily cause short circuits and leakage between high-voltage and low-voltage power sources. Some exposed charging ports lack isolation switches, so as long as one input is active, the other inputs remain energized. For example, some POS machines use both USB and POGO pins for contact charging. If a USB input is live, the exposed POGO pin cannot be placed on a metal surface, as this would cause a short circuit between the positive and negative voltages. Some products prioritize multiple power inputs, so conventional multi-input designs typically include isolation circuits to isolate or switch the various power sources. For example, when wirelessly charging a mobile phone, the wired charging port must be closed to prevent damage to the electronic device from a short circuit caused by the voltage between the wired input and the wireless output.

[0003] Currently, a single NMOS is used as a switch, but because MOS tubes have parasitic diodes, they cannot achieve the purpose of bidirectional isolation. This will cause the following problems: when one line is powered, the other line will also be powered. When the other line is also plugged into the power supply, the voltage difference between the power supplies will cause a short circuit. Another method is to use two "back-to-back" NMOS, as shown below Figure 1 As shown, because there are two back-to-back MOSs, the parasitic diodes cannot conduct normally, and isolation can be achieved in both directions. However, the turning-on condition of the NMOS is to enable EN1' and EN2', which require a voltage higher than the output voltage VBUS' to drive. This high voltage is not available in some products, or high-voltage driving may increase costs. Therefore, it is very important to obtain a multi-channel charging port isolation circuit and charging method that overcome the above-mentioned defects. Summary of the Invention

[0004] To address at least one of the above technical issues, the present invention provides, in one aspect, a multi-channel charging port isolation circuit, comprising at least two selection circuits, the selection circuits including a first selection circuit, the first selection circuit including a first overvoltage protection chip and a second overvoltage protection chip connected in series back-to-back, a first voltage input pin of the first overvoltage protection chip being used to connect to a first power input, a first voltage output pin of the first overvoltage protection chip being electrically connected to a second voltage output pin of the second overvoltage protection chip, and the second voltage input pin of the second overvoltage protection chip being used to output a first charging voltage to a device to be charged;

[0005] The selection circuit includes a second selection circuit, the second selection circuit includes a third overvoltage protection chip and a fourth overvoltage protection chip connected in series back to back, the third voltage input pin of the third overvoltage protection chip is used to connect to the second power input, the third voltage output pin of the third overvoltage protection chip is electrically connected to the fourth voltage output pin of the fourth overvoltage protection chip, and the fourth voltage input pin of the fourth overvoltage protection chip is used to output the second charging voltage to the device to be charged;

[0006] The first enable terminal of the first overvoltage protection chip and the second enable terminal of the second overvoltage protection chip both input a first control signal;

[0007] The third enable terminal of the third overvoltage protection chip and the fourth enable terminal of the fourth overvoltage protection chip both input the second control signal;

[0008] The on and off of the overvoltage protection chip is controlled by the control signal of the enable terminal, thereby achieving bidirectional isolation of the two overvoltage protection chips of the selection circuit and providing voltage protection for the power input of each selection circuit.

[0009] It also includes a control device, which outputs a first control signal and / or a second control signal to control the on and off of the overvoltage protection chip.

[0010] It also includes a detection circuit, which is connected to the first power input of the first selection circuit and the second power input of the second selection circuit; the detection output signal of the detection circuit is electrically connected to the input end of the control device, and the control device outputs the first control signal and / or the second control signal according to the detection output signal.

[0011] The detection circuit includes a first detection circuit, the first detection circuit includes a fifth MOS transistor, the source of the fifth MOS transistor is electrically connected to the first voltage input pin of the first overvoltage protection chip through a second resistor and a first resistor, the source of the fifth MOS transistor is connected to the connection point of the first and second resistors, the drain of the fifth MOS transistor outputs a first detection signal, and a first bidirectional TVS diode is connected between the source and gate of the fifth MOS transistor. The detection circuit includes a second detection circuit, the second detection circuit includes a sixth MOS transistor, the source of the sixth MOS transistor is electrically connected to the second voltage input pin of the third overvoltage protection chip through a third resistor and a fourth resistor, the source of the sixth MOS transistor is connected to the connection point of the third and fourth resistors, the drain of the sixth MOS transistor outputs a second detection signal, and a second bidirectional TVS diode is connected between the source and gate of the sixth MOS transistor.

[0012] The use of the first bidirectional TVS diode and the second bidirectional TVS diode can limit the drain voltage of the MOS tube to not exceed the safety threshold, effectively avoiding device damage.

[0013] At least one of the first, second, third, and fourth overvoltage protection chips includes: a detection module, a first MOS transistor, an NMOS transistor, a boost module; a selection module, an operational amplifier, and a logic controller; a reference voltage source and an oscillator; the drain of the NMOS transistor is connected to an input port, the source is connected to an output port, the gate of the first MOS transistor is connected to the detection module, the detection module is connected to the input port, the detection module is grounded, the source of the first MOS transistor is grounded, and the gate of the NMOS transistor is connected to the boost module; the selection module is connected to the OVLO port, the drain of the NMOS transistor is connected to the selection module, the selection module is connected to the non-inverting input of the operational amplifier, the output of the operational amplifier is connected to the logic controller, and the output of the logic controller is connected to the boost module; the logic controller is connected to the ACOK port, the reference voltage source is connected to the inverting input of the operational amplifier, the reference voltage source is connected to the oscillator, and the oscillator is connected to the logic controller. The control device outputs a signal to control the on / off of the NMOS transistor via the enable port.

[0014] Through the above technical solution, the first overvoltage protection chip and the second overvoltage protection chip are integrated with a boost module to obtain a high voltage to drive the NMOS tube. The NMOS tube inside the overvoltage protection chip will be turned off when the OVP protection is triggered. The on and off of the NMOS tube can also be controlled by the enable terminal of the overvoltage protection chip, thereby achieving the purpose of autonomous selection through the controller.

[0015] In another aspect, the present invention provides a multi-port charging method, including the multi-port charging port isolation circuit described above. The multi-port charging port isolation circuit utilizes a controller to obtain, in real time, a signal from a detection circuit detecting whether a voltage is input to a first power input and a second power input, thereby controlling the first selection circuit or the second selection circuit to conduct, thereby selecting the first power input or the second power input for power supply. The power supply method includes:

[0016] When the controller receives a signal that both the first power input and the second power input have voltage inputs, the controller outputs a first control signal to control the first selection circuit to be turned on and the second selection circuit to be in an off state, so that the first power input supplies power, or the controller outputs a second control signal to control the second selection circuit to be turned on and the first selection circuit to be in an off state, so that the second power input supplies power;

[0017] When the controller only receives a signal that the first power input has a voltage input, the controller outputs a first control signal to control the first selection circuit to be turned on and the second selection circuit to be in an off state, so that the first power input is powered;

[0018] When the controller only receives a signal indicating that the second power input has a voltage input, the controller outputs a second control signal to control the second selection circuit to be turned on, and the first selection circuit is in an off state, so that the second power input provides power.

[0019] Compared with the prior art, the advantages of the present invention are: the present invention has a simple structure, adopts an OVP chip, has a high-voltage protection function, and adopts a "back-to-back" mode of the OVP chip to play a role of multi-path isolation and selection. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is the existing isolation circuit diagram;

[0021] Figure 2 This is a multi-channel charging port isolation circuit diagram of the present invention;

[0022] Figure 3 This is a schematic diagram of the internal structure of the OVP chip of the present invention;

[0023] Reference numerals:

[0024] 1 detection module, 2 first MOS transistor, 3 NMOS transistor, 4 boost module; 5 selection module, 6 operational amplifier, 7 logic controller; 8 reference voltage source, 9 oscillator; MA1 first overvoltage protection chip, MA2 second overvoltage protection chip; VBUS1 first power input; EN1A first control signal; MA3 third overvoltage protection chip, MA4 fourth overvoltage protection chip; VBUS2 second power input; EN2A second control signal; Q5 fifth MOS transistor; R2 second resistor; R1 first resistor; D1 first bidirectional TVS diode; Q6 sixth MOS transistor; R3 third resistor; R4 fourth resistor; D2 second bidirectional TVS diode; STATE1 first detection signal; STATE2 second detection signal. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the present invention and thus more clearly define the scope of protection claimed in the present invention, the present invention is described in detail below with respect to certain specific embodiments of the present invention. It should be noted that the following are only certain specific embodiments of the present invention, which are only part of the embodiments of the present invention. The specific and direct description of the relevant structures is only for the convenience of understanding the present invention, and the specific features do not necessarily and directly limit the scope of implementation of the present invention.

[0026] Referring to the accompanying drawings, the present invention adopts the following technical solutions. On the one hand, the present invention provides a multi-channel charging port isolation circuit, including at least two selection circuits, wherein the selection circuit includes a first selection circuit, the first selection circuit including a first overvoltage protection chip MA1 and a second overvoltage protection chip MA2 connected in series back-to-back, a first voltage input pin IN1 of the first overvoltage protection chip MA1 being used to connect to a first power input VBUS1, a first voltage output pin OUT1 of the first overvoltage protection chip MA1 being electrically connected to a second voltage output pin OUT2 of the second overvoltage protection chip MA2, and a second voltage input pin IN2 of the second overvoltage protection chip MA2 being used to output a first charging voltage to a device to be charged;

[0027] The selection circuit includes a second selection circuit, which includes a third overvoltage protection chip MA3 and a fourth overvoltage protection chip MA4 connected in series back to back. The third voltage input pin IN3 of the third overvoltage protection chip is used to connect to the second power input VBUS2, and the third voltage output pin OUT3 of the third overvoltage protection chip MA3 is electrically connected to the fourth voltage output pin OUT4 of the fourth overvoltage protection chip MA4. The fourth voltage input pin IN4 of the fourth overvoltage protection chip MA4 is used to output a second charging voltage to the device to be charged;

[0028] The first enable terminal EN1 of the first overvoltage protection chip MA1 and the second enable terminal EN2 of the second overvoltage protection chip MA2 both input the first control signal EN1A;

[0029] The third enable terminal EN3 of the third overvoltage protection chip MA3 and the fourth enable terminal EN4 of the fourth overvoltage protection chip MA4 both input the second control signal EN2A;

[0030] By controlling the enable terminals of the first, second, third, and fourth overvoltage protection chips MA1, MA2, MA3, and MA4, the controller outputs control signals to control the on / off switching of the first, second, and third overvoltage protection chips. This achieves bidirectional isolation between the two overvoltage protection chips in the first and second selection circuits. The two overvoltage protection chips, connected back-to-back, can effectively clamp overvoltages in both the positive and negative directions, respectively. In circuits where reverse power connection or bidirectional transient voltage surges may occur on signal lines, the back-to-back overvoltage protection chips can provide protection against both excessively high positive and negative voltages, preventing damage to sensitive components in the circuit due to overvoltage.

[0031] Overvoltage protection chips consume a certain amount of power during operation, generating significant heat, especially when responding to high overvoltages and currents. Back-to-back connection doubles the heat dissipation area of the two chips, facilitating better heat dissipation and reducing the chip's operating temperature, thereby increasing chip reliability and lifespan.

[0032] The first bidirectional TVS diode D1 and the second bidirectional TVS diode D2 are used to protect the MOS tube from transient overvoltage damage and prevent damage from reverse power connection. If the power supply is reversed, the bidirectional TVS diode can provide a low-resistance path between the source and ground, limiting the reverse voltage to a safe range and preventing reverse current from damaging the MOS tube and other circuit components. This can increase the circuit's fault tolerance in the event of a power connection error and protect the entire circuit system; it can also stabilize the source potential.

[0033] The system further includes a control device, which outputs a first control signal EN1A and / or a second control signal EN2A to control the on and off of the overvoltage protection chip.

[0034] It also includes a detection circuit, which is connected to the first power input VBUS1 of the first selection circuit and the second power input VBUS2 of the second selection circuit; the detection output signal of the detection circuit is electrically connected to the input end of the control device, and the control device outputs the first control signal EN1A and / or the second control signal EN2A according to the detection output signal.

[0035] The detection circuit includes a first detection circuit, which includes a fifth MOS transistor Q5. The source of the fifth MOS transistor Q5 is electrically connected to the first voltage input pin of the first overvoltage protection chip MA1 through a second resistor R2 and a first resistor R1. The source of the fifth MOS transistor Q5 is connected to the junction of the first resistor R1 and the second resistor R2. The drain of the fifth MOS transistor Q5 outputs a first detection signal STATE1. A first bidirectional TVS diode D1 is connected between the source and gate of the fifth MOS transistor Q5. The detection circuit includes a second detection circuit, which includes a sixth MOS transistor Q6. The source of the sixth MOS transistor Q6 is electrically connected to the second voltage input pin of the third overvoltage protection chip MA3 through a third resistor R3 and a fourth resistor R4. The source of the sixth MOS transistor Q6 is connected to the junction of the third resistor R3 and the fourth resistor R4. The drain of the sixth MOS transistor Q6 outputs a second detection signal STATE2. A second bidirectional TVS diode D2 is connected between the source and gate of the sixth MOS transistor Q6.

[0036] The first overvoltage protection chip MA1, the second overvoltage protection chip MA2, the third overvoltage protection chip MA3 and the fourth overvoltage protection chip MA4 include: a detection module 1, a first MOS transistor 2, an NMOS transistor 3, a boost module 4; a selection module 5, an operational amplifier 6, a logic controller 7; a reference voltage source 8 and an oscillator 9; the drain of the NMOS transistor 3 is connected to the input port IN and the source is connected to the output port OUT, the gate of the first MOS transistor 2 is connected to the detection module 1, the detection module 1 is connected to the input port IN, the detection module 1 is grounded, the source of the first MOS transistor 2 is grounded, and the gate of the NMOS transistor 3 is connected to the boost module 4; the selection module 5 is connected to the OVLO port, the drain of the NMOS transistor 3 is connected to the selection module 5, the selection module 5 is connected to the non-inverting input of the operational amplifier 6, the output of the operational amplifier 6 is connected to the logic controller 7, and the output of the logic controller 7 is connected to the boost module 4; the logic controller 7 is connected to the ACOK port, the reference voltage source 8 is connected to the inverting input of the operational amplifier 6, the reference voltage source 8 is connected to the oscillator 9, and the oscillator 9 is connected to the logic controller 7. The control device outputs a signal to control the on / off of the NMOS tube 3 through the enable terminal.

[0037] Through the above technical solution, the boost module 4 integrated inside the first overvoltage protection chip MA1 and the second overvoltage protection chip MA2 can obtain a high voltage to drive the NMOS tube 3. The NMOS tube 3 inside the overvoltage protection chip will be turned off when the OVP protection is triggered. The on and off of the NMOS tube 3 can also be controlled by the enable end of the overvoltage protection chip, thereby achieving the purpose of autonomous selection through the controller.

[0038] In another aspect, the present invention provides a multi-port charging method, including the multi-port charging port isolation circuit described above. The multi-port charging port isolation circuit utilizes a controller to obtain, in real time, a signal from a detection circuit to detect whether a first power input VBUS1 and a second power input VBUS2 have voltage inputs, thereby controlling the conduction of a first selection circuit or a second selection circuit, thereby selecting the first power input VBUS1 or the second power input VBUS2 for power supply. The power supply method includes:

[0039] When the controller receives a signal that both the first power input VBUS1 and the second power input VBUS2 have voltage inputs, the controller outputs a first control signal EN1A to control the first selection circuit to be turned on and the second selection circuit to be in an off state, so that the first power input VBUS1 is powered, or the controller outputs a second control signal EN2A to control the second selection circuit to be turned on and the first selection circuit to be in an off state, so that the second power input VBUS2 is powered;

[0040] When the controller only receives a signal that the first power input VBUS1 has a voltage input, the controller outputs a first control signal EN1A to control the first selection circuit to be turned on and the second selection circuit to be turned off, so that the first power input VBUS1 is powered.

[0041] When the controller only receives a signal indicating that the second power input VBUS2 has a voltage input, the controller outputs a second control signal EN2A to control the second selection circuit to be turned on, and the first selection circuit is in a disconnected state, so that the second power input VBUS2 provides power.

[0042] For example Figure 2 As shown, the first power input VBUS1 and the second power input VBUS2 are two power inputs. The first resistor R1 and the second resistor R2 are two voltage divider resistors. When the first power input VBUS1 is input, the fifth MOS transistor Q5 is turned on. The first detection signal STATE1 is used in conjunction with the controller, such as the internal pull-up of the CPU, to detect the insertion of the first power input VBUS1. The same applies to the second detection signal STATE2. Assuming that the first power input VBUS1 and the second power input VBUS2 of this product can be inserted at the same time, and when the first power input VBUS1 and the second power input VBUS2 are inserted at the same time, the power supply of the first power input VBUS1 needs to be used first. In this case, the circuit can use the first detection signal STATE1 and the second detection signal STATE2 to detect which power input is inserted. The first control signal EN1A and the second control signal EN2A can select and control the activation of any OVP chip.

[0043] Compared with the prior art, the advantages of the present invention are: the present invention has a simple structure, adopts an overvoltage protection chip, i.e., an OVP chip, has a high-voltage protection function, and the present invention adopts a "back-to-back" mode of the OVP chip to play a role of multi-path isolation and selection.

[0044] Thus far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present invention.

Claims

1. A multi-channel charging port isolation circuit, characterized in that: The device comprises at least two selection circuits, wherein the selection circuit comprises a first selection circuit, wherein the first selection circuit comprises a first overvoltage protection chip (MA1) and a second overvoltage protection chip (MA2) connected in series back to back, wherein a first voltage input pin of the first overvoltage protection chip (MA1) is used to connect to a first power input (VBUS1), a first voltage output pin of the first overvoltage protection chip (MA1) is electrically connected to a second voltage output pin of the second overvoltage protection chip (MA2), and the second voltage input pin of the second overvoltage protection chip (MA2) is used to output a first charging voltage to a device to be charged; The selection circuit includes a second selection circuit, the second selection circuit includes a third overvoltage protection chip (MA3) and a fourth overvoltage protection chip (MA4) connected in series back to back, the third voltage input pin of the third overvoltage protection chip (MA3) is used to connect to the second power input (VBUS2), the third voltage output pin of the third overvoltage protection chip (MA3) is electrically connected to the fourth voltage output pin of the fourth overvoltage protection chip (MA4), and the fourth voltage input pin of the fourth overvoltage protection chip (MA4) is used to output a second charging voltage to the device to be charged; A first control signal (EN1A) is input to the first enable terminal of the first overvoltage protection chip (MA1) and the second enable terminal of the second overvoltage protection chip (MA2); The third enable terminal of the third overvoltage protection chip (MA3) and the fourth enable terminal of the fourth overvoltage protection chip (MA4) are both input with the second control signal (EN2A); The on and off of the overvoltage protection chip is controlled by the control signal of the enable terminal, thereby achieving bidirectional isolation of the two overvoltage protection chips of the selection circuit and providing voltage protection for the power input of each selection circuit.

2. The multi-channel charging port isolation circuit according to claim 1, characterized in that: The system further comprises a control device, which outputs a first control signal (EN1A) and / or a second control signal (EN2A) to control the on and off of the overvoltage protection chip.

3. The multi-channel charging port isolation circuit according to claim 2, characterized in that: The device further includes a detection circuit connected to a first power input (VBUS1) of the first selection circuit and a second power input (VBUS2) of the second selection circuit; a detection output signal of the detection circuit is electrically connected to an input end of a control device, and the control device outputs a first control signal (EN1A) and / or a second control signal (EN2A) based on the detection output signal.

4. The multi-channel charging port isolation circuit according to claim 3, characterized in that: The detection circuit comprises a first detection circuit, which comprises a fifth MOS transistor (Q5). The source of the fifth MOS transistor (Q5) is electrically connected to a first voltage input pin (IN1) of a first overvoltage protection chip (MA1) through a second resistor (R2) and a first resistor (R1). The source of the fifth MOS transistor (Q5) is connected to a connection point between the first resistor (R1) and the second resistor (R2). The drain of the fifth MOS transistor (Q5) outputs a first detection signal (STATE1). A first bidirectional TVS diode (D1) is connected between the source and gate of the fifth MOS transistor (Q5).

5. The multi-channel charging port isolation circuit according to claim 3, characterized in that: The detection circuit comprises a second detection circuit, which comprises a sixth MOS tube (Q6); the source of the sixth MOS tube (Q6) is electrically connected to a second voltage input pin (IN3) of a third overvoltage protection chip (MA3) via a third resistor (R3) and a fourth resistor (R4); the source of the sixth MOS tube (Q6) is connected to the connection point of the third resistor (R3) and the fourth resistor (R4); the drain of the sixth MOS tube (Q6) outputs a second detection signal (STATE2); and a second bidirectional TVS diode (D2) is connected between the source and the gate of the sixth MOS tube (Q6).

6. The multi-channel charging port isolation circuit according to claim 1, characterized in that: At least one of the first overvoltage protection chip (MA1), the second overvoltage protection chip (MA2), the third overvoltage protection chip (MA3), and the fourth overvoltage protection chip (MA4) comprises: Detection module (1), first MOS tube (2), NMOS tube (3), boost module (4); Select module (5), operational amplifier (6), logic controller (7); Reference voltage source (8), oscillator (9); The drain of the NMOS tube (3) is connected to the input port, the source is connected to the output port, the gate of the first MOS tube (2) is connected to the detection module (1), the detection module (1) is connected to the input port, the detection module (1) is grounded, the source of the first MOS tube (2) is grounded, and the gate of the NMOS tube (3) is connected to the boost module (4); The selection module (5) is connected to the OVLO port, the drain of the NMOS tube (3) is connected to the selection module (5), the selection module (5) is connected to the non-inverting input terminal of the operational amplifier (6), the output of the operational amplifier (6) is connected to the logic controller (7), the output of the logic controller (7) is connected to the boost module (4); the logic controller (7) is connected to the ACOK port, the reference voltage source (8) is connected to the inverting input terminal of the operational amplifier (6), the reference voltage source (8) is connected to the oscillator (9), the oscillator (9) is connected to the logic controller (7), and the control device outputs a signal to control the on / off of the NMOS tube (3) through the enable terminal.

7. A multi-channel charging method, characterized in that: The multi-channel charging port isolation circuit comprises the multi-channel charging port isolation circuit according to any one of claims 1 to 6 above, wherein the multi-channel charging port isolation circuit utilizes a controller to obtain in real time a signal from a detection circuit to detect whether a first power input (VBUS1) and a second power input (VBUS2) have a voltage input, thereby controlling the first selection circuit or the second selection circuit to be turned on, thereby selecting the first power input (VBUS1) or the second power input (VBUS2) for power supply, wherein the power supply method comprises: When the controller receives a signal indicating that both the first power input (VBUS1) and the second power input (VBUS2) have voltage inputs, the controller outputs a first control signal (EN1A) to control the first selection circuit to be turned on and the second selection circuit to be in an off state, so that the first power input (VBUS1) is supplied with power, or the controller outputs a second control signal (EN2A) to control the second selection circuit to be turned on and the first selection circuit to be in an off state, so that the second power input (VBUS2) is supplied with power; When the controller receives only a signal indicating that the first power input (VBUS1) has a voltage input, the controller outputs a first control signal (EN1A) to control the first selection circuit to be turned on and the second selection circuit to be turned off, so that the first power input (VBUS1) is powered; When the controller only receives a signal indicating that the second power input (VBUS2) has a voltage input, the controller outputs a second control signal (EN2A) to control the second selection circuit to be turned on, and the first selection circuit is in an off state, so that the second power input (VBUS2) is powered.

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