High-efficiency low-ripple charge pump and charge pump loop

Abstract

The invention discloses a high-efficiency low-ripple charge pump and a charge pump loop, and relates to the technical field of charge pumps, the high-efficiency low-ripple charge pump comprises a charge pump core module, the charge pump core module at least comprises a first-stage charge pump circuit, the charge pump circuit comprises a first pump capacitor, a second pump capacitor, a charge recovery circuit and a time sequence switch circuit, in the working process of the charge pump circuit, the first pump capacitor and the second pump capacitor alternately work as boost capacitors under the control of the time sequence switching circuit; before the current boost capacitor is alternated, the charge pump circuit outputs voltage outwards by using the first end of the current boost capacitor, and after the voltage is output outwards, the charge recovery circuit connects the second end of the first pump capacitor with the second end of the second pump capacitor so as to recover charges at the second end of the current boost capacitor. The charge pump can improve efficiency and reduce output ripples.

Description

Technical Field

[0001] The present invention relates to the technical field of charge pumps, and in particular to a high-efficiency and low-ripple charge pump and a charge pump loop. Background Art

[0002] In recent years, portable consumer electronic devices have become an integral part of people's lives. These devices usually contain a large number of circuit subsystems, which require power management circuits to provide power for different voltage domains. At the same time, due to the increase in device integration and the widespread application of on-chip high-voltage technology, the demand for miniaturized, high-voltage gain power management circuits is also increasing.

[0003] At present, the topological structures of power management circuits mainly include low-dropout linear regulators (LDO), inductive switching power supplies (DC-DC) and capacitive switching regulator circuits, namely charge pumps. Among them, low-dropout linear regulators work in linear mode, have low output noise, and are suitable for noise-sensitive circuits. They also have fast transient response capabilities and can quickly adjust the output voltage when the load changes. Low-dropout linear regulators do not have switching properties inside, have very small output voltage ripple, and have high output accuracy. They are widely used in situations where voltage requirements are relatively precise. However, the principle of low-dropout linear regulators is to control the gate of the adjustment tube to adjust the output voltage, so they can only be used in step-down situations. When the input voltage and output voltage differ greatly or the load current is large, a large amount of energy will be dissipated in the adjustment tube in the form of heat energy, which greatly reduces the efficiency.

[0004] Inductive switching power supplies use inductors, capacitors, and charge transfer switches to achieve high-efficiency buck-boost operations. They have high conversion efficiency, especially under high voltage conversion ratios and high load current conditions. However, due to the large noise and ripple generated by the switching action, inductive switching power supplies usually require additional filtering circuits to reduce noise. Compared with low-dropout linear regulators, inductive switching power supplies have slower transient response speeds, and may experience problems such as output voltage overcharge under light load conditions. Because inductive coils generate electromagnetic interference and the winding coils occupy a large area, inductive switching power supplies are not suitable for on-chip integration.

[0005] The capacitive switching voltage regulator circuit, namely the charge pump, is an inductorless DC to DC power converter that can increase or decrease the voltage of the input power supply to generate a secondary constant voltage. The charge pump uses a charge transfer switch and a capacitor to transfer charge to the load circuit. It does not require complex frequency compensation, has a certain transient response capability, can achieve multiple voltage increases through a multi-stage cascade design, has a flexible structure, and is highly integrated. Therefore, in the topology of the above power management circuit, the charge pump is most suitable for systems with on-chip high voltage requirements.

[0006] However, since the charge pump circuit is limited by the capacitor charging and discharging process, its efficiency is lower than that of the inductive switching power supply, and since it uses the capacitor charging and discharging principle, the output voltage of the charge pump circuit has a large ripple. Therefore, in order to meet the chip's demand for power management circuits, the charge pump needs to be further optimized in terms of efficiency and output voltage ripple. Summary of the invention

[0007] In view of the above problems and technical requirements, the inventors have proposed a high-efficiency and low-ripple charge pump and a charge pump loop. The technical solution of the present invention is as follows:

[0008] A high-efficiency, low-ripple charge pump comprises a charge pump core module, wherein the charge pump core module comprises at least one charge pump circuit, wherein the charge pump circuit comprises a first pump capacitor, a second pump capacitor, a charge recovery circuit and a timing switch circuit, wherein:

[0009] During the operation of the charge pump circuit, the first pump capacitor and the second pump capacitor alternately work as boost capacitors under the control of the timing switching circuit; before the current boost capacitor alternates, the charge pump circuit uses the first end of the current boost capacitor to output voltage to the outside, and after outputting the voltage to the outside, uses the charge recovery circuit to connect the second end of the first pump capacitor with the second end of the second pump capacitor to recover the charge at the second end of the current boost capacitor.

[0010] A further technical solution is that the timing switch circuit includes a switch tube S 1 , switch tube S 2 , switch tube S 3 , switch tube S 4 , switch tube S 5 , switch tube S 6 , switch tube S 7 And the switch tube S 8 ,in,

[0011] The first end of the first pump capacitor is connected to the switch tube S 1 The third electrode of the switch tube S 1 The first electrode of the second pump capacitor is connected to the power supply voltage VDD, and the first end of the second pump capacitor is connected to the switch tube S 3 The third electrode of the switch tube S 3 The first electrode is connected to the power supply voltage VDD;

[0012] The first end of the first pump capacitor is connected to the switch tube S 2 The first electrode of the switch tube S 2 The first electrode and the switch tube S 4 The third electrode of the switch tube S is connected to form the output end of the charge pump circuit. 4The first electrode is connected to the first end of the second pump capacitor;

[0013] The second end of the first pump capacitor is connected to the switch tube S 5 The first electrode and the switch tube S 6 The third electrode of the switch tube S 5 The third electrode of the switch tube S is grounded. 6 The first electrode is connected to the power supply voltage VDD;

[0014] The second end of the second pump capacitor is connected to the switch tube S 7 The first electrode and the switch tube S 8 The third electrode of the switch tube S 7 The third electrode of the switch tube S is grounded. 8 The first electrode is connected to the power supply voltage VDD;

[0015] Switching tube S 1 , switch tube S 4 , switch tube S 5 And switch tube S 8 The conduction state of the switch tube S 2 , switch tube S 3 , switch tube S 6 And switch tube S 7 The conduction state is the same;

[0016] The switch tube S 1 , switch tube S 4 , switch tube S 5 And switch tube S 8 When both are turned on, the second pump capacitor works as a boost capacitor; the switch tube S 2 , switch tube S 3 , switch tube S 6 And switch tube S 7 When both are turned on, the first pump capacitor works as a boost capacitor.

[0017] A further technical solution is that the switch tube S 5 The second electrode is connected to the clock signal Φ 1 , the switch tube S 8 The second electrode is connected to the clock signal Φ 1 The inverting signal of the switch tube S 7 The second electrode is connected to the clock signal Φ 2 , the switch tube S 6 The second electrode is connected to the clock signal Φ 2 The inverted signal;

[0018] The switch tube S 1 And switch tube S 4The second electrode is connected to the clock signal Φ 3 , the switch tube S 2 And switch tube S 3 The second electrode is connected to the clock signal Φ 4 ;

[0019] The charge recovery circuit includes a switch tube S 9 , the switch tube S 9 The first electrode of the switch tube S is connected to the second end of the first pump capacitor. 9 The second electrode of the switch tube S is connected to the second end of the second pump capacitor. 9 The second electrode is connected to the clock signal Φ 5 The switch tube S 9 When turned on, the second end of the first pump capacitor is electrically connected to the second end of the second pump capacitor;

[0020] The switch tube S 1 , switch tube S 2 , switch tube S 3 , switch tube S 4 , switch tube S 5 , switch tube S 6 , switch tube S 7 , switch tube S 8 And the switch tube S 9 All are PMOS tubes;

[0021] The clock signal Φ 1 With the clock signal Φ 3 Synchronize, the clock signal Φ 2 With the clock signal Φ 4 Synchronization, clock signal Φ 1 With the clock signal Φ 2 is a two-phase non-overlapping clock, and the clock signal Φ 5 The effective level of the clock signal Φ 1 With the clock signal Φ 2 non-overlapping time.

[0022] A further technical solution thereof is that it also includes a clock generation module, wherein the clock generation module includes a non-overlapping clock generation circuit, and the non-overlapping clock generation circuit is used to generate the clock signal Φ 1 , clock signal Φ 2 and clock signal Φ 5 ;

[0023] The non-overlapping clock generation circuit includes a NOR gate NOR3, a first clock circuit and a second clock circuit, wherein the first clock circuit includes an inverter INV1, a NOR gate NOR1, a NOR gate NOR2, a first inverter chain and a second inverter chain, wherein:

[0024] The input end of the inverter INV1 is connected to the first input end of the NOR gate NOR1 and forms the input end of the first clock circuit, and the second input end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR3;

[0025] The output end of the inverter INV1 is connected to the second input end of the NOR gate NOR2, and the first input end of the NOR gate NOR2 is connected to the second input end of the NOR gate NOR3;

[0026] The output end of the NOR gate NOR1 is connected to the input end of the first inverter chain, and the output end of the first inverter chain is connected to the second input end of the NOR gate NOR3 to form a first output end of the non-overlapping clock generation circuit;

[0027] The output end of the NOR gate NOR2 is connected to the input end of the second inverter chain, the output end of the second inverter chain is connected to the first input end of the NOR gate NOR3, and form a second output end of the non-overlapping clock generation circuit, the second clock circuit has the same structure as the first clock circuit, the output end of the NOR gate NOR3 is connected to the input end of the second clock generation circuit, and a third output end of the non-overlapping clock generation circuit is formed based on the output end of the second clock circuit;

[0028] The first inverter chain and the second inverter chain have the same structure, and both the first inverter chain and the second inverter chain include an even number of inverters connected in series.

[0029] A further technical solution is that the clock generation module further includes a high-voltage clock generation circuit;

[0030] The high-voltage clock generation circuit includes at least one stage of cross-coupled boost circuit, and the cross-coupled boost circuit corresponds to the charge pump circuit one by one;

[0031] The cross-coupled boost circuit includes a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor. The first end of the first capacitor is connected to the clock signal φ 1 , the second end of the first capacitor is connected to the drain of the first PMOS tube and the drain of the first NMOS tube; the first end of the second capacitor is connected to the clock signal Φ 2 , a second end of the second capacitor is connected to the drain of the second PMOS tube and the drain of the second NMOS tube;

[0032] The source of the first PMOS tube is connected to the source of the second PMOS tube, and the source of the first NMOS tube and the source of the second NMOS tube are connected to the power supply voltage VDD;

[0033] The gate of the second PMOS tube, the gate of the second NMOS tube and the second end of the first capacitor are connected to form a first output end of the cross-coupled boost circuit, and the gate of the first PMOS tube, the gate of the first NMOS tube and the second end of the second capacitor are connected to form a second output end of the cross-coupled boost circuit.

[0034] A further technical solution is that the first output terminal of the non-overlapping clock generation circuit outputs a clock signal Φ 1 The first output terminal of the non-overlapping clock generating circuit is also connected to the input terminal of the inverter INV_1, and the output terminal of the inverter INV_1 outputs the clock signal Φ as the fourth output terminal of the non-overlapping clock generating circuit. 1 The inverted signal;

[0035] The second output terminal of the non-overlapping clock generation circuit outputs a clock signal Φ 2 The second output terminal of the non-overlapping clock generating circuit is also connected to the input terminal of the inverter INV_2, and the output terminal of the inverter INV_2 serves as the fifth output terminal of the non-overlapping clock generating circuit to output the clock signal Φ 2 The inverted signal;

[0036] The clock generation module further includes a clock drive enhancement circuit, which includes four clock drive chains, and the first output terminal, the second output terminal, the fourth output terminal and the fifth output terminal of the non-overlapping clock generation circuit are each connected to a corresponding switch tube in the timing switch circuit through a clock drive chain;

[0037] The clock drive chain includes an even number of inverters connected in series and whose width-to-length ratios increase in sequence according to a preset ratio.

[0038] A high-efficiency, low-ripple charge pump loop comprises the above-mentioned charge pump, wherein the charge pump loop further comprises a variable resistor voltage divider circuit, an error amplifier, a voltage-controlled oscillator and a clock shaping circuit, wherein:

[0039] The charge pump is connected to a variable resistor voltage divider circuit, the variable resistor voltage divider circuit is connected to an error amplifier, the error amplifier is connected to a voltage controlled oscillator, and the voltage controlled oscillator is connected to the charge pump via a clock shaping circuit;

[0040] The output voltage of the charge pump is divided by a variable resistor to generate a feedback voltage V F The error amplifier will input the feedback voltage V F With reference voltage V REF After comparison, the control voltage V EA , the control voltage V EAThe output clock signal of the voltage-controlled oscillator is input to the charge pump after being shaped by the clock circuit to adjust the output voltage of the charge pump.

[0041] A further technical solution is that the voltage-controlled oscillator includes a capacitor CO1, a resistor RO1, a resistor RO2, a PMOS tube MO2, a PMOS tube MO3, a PMOS tube MO4, an NMOS tube MO1, an NMOS tube MO5, an NMOS tube MO6, an inverter I1, an inverter I2, and an inverter I3, wherein:

[0042] The gate of the NMOS transistor MO1 is connected to the control voltage VEA, the source of the NMOS transistor MO1 is connected to one end of the resistor RO1, and the other end of the resistor RO1 is connected to one end of the resistor RO2 and connected to the temperature compensation current I PTAT , the other end of the resistor RO2 is grounded;

[0043] The drain of the NMOS tube MO1 is connected to the drain of the PMOS tube MO2, the gate of the PMOS tube MO2, the gate of the PMOS tube MO3 and the gate of the PMOS tube MO4, the source of the PMOS tube MO2, the source of the PMOS tube MO3 and the source of the PMOS tube MO4 are connected and connected to the power supply voltage VDD, the drain of the PMOS tube MO3 is connected to the drain of the NMOS tube MO5, the drain of the NMOS tube MO5 is connected to the gate, the source of the NMOS tube MO5 is connected to the source of the NMOS tube MO6 and is grounded, and the gate of the NMOS tube MO5 is connected to the gate of the NMOS tube MO6;

[0044] The input end of the inverter I1 is connected to the output end of the inverter I3, the output end of the inverter I1 is connected to the input end of the inverter I2 and is grounded through the capacitor CO1, the output end of the inverter I2 is connected to the input end of the inverter I3, and the output end of the inverter I3 is connected to the clock shaping circuit;

[0045] The source of the PMOS tube in the inverter I1 is connected to the drain of the PMOS tube MO4, and the source of the NMOS tube in the inverter I1 is connected to the drain of the NMOS tube MO6.

[0046] A further technical solution is that the variable resistor voltage divider circuit includes a resistor Rf1, a resistor Rf2 and a variable resistor unit, one end of the resistor Rf1 is connected to one end of the resistor Rf2 and the variable resistor unit to form an output end of the variable resistor voltage divider circuit, the other end of the resistor Rf1 is grounded, and the other end of the resistor Rf2 is connected to the output voltage V of the charge pump out ;

[0047] The variable resistor unit includes a resistor R0, a total transmission gate TG0 and a plurality of adjustment resistors, the resistor R0 is connected in series with the resistor Rf2, and the plurality of adjustment resistors are connected in series with the resistor R0;

[0048] Each regulating resistor is connected in parallel with a transmission gate, and all the transmission gates are connected in series to one end of a total transmission gate TG0, and the other end of the total transmission gate TG0 is grounded.

[0049] A further technical solution is that it also includes a hysteresis comparator, wherein the feedback voltage V F Connect to the positive input of the hysteresis comparator, and connect the reference voltage V to the negative input of the hysteresis comparator. REF , the hysteresis comparator compares the feedback voltage V F With reference voltage V REF And output the output feedback voltage V that represents the output state of the charge pump FOUT ;

[0050] The hysteresis comparator includes NMOS transistor MC1, NMOS transistor MC2, PMOS transistor MC3, PMOS transistor MC4, PMOS transistor MC5, PMOS transistor MC6, PMOS transistor MC7, PMOS transistor MC8, NMOS transistor MC9, NMOS transistor MC10 and NMOS transistor MC11, wherein:

[0051] The sources of the PMOS tubes MC3, MC4, MC5, MC6, MC7 and MC8 are connected to the power supply voltage VDD;

[0052] The gate of the PMOS tube MC3 is connected to the gate of the PMOS tube MC5, and the gate of the PMOS tube MC3 is also connected to the drain of the PMOS tube MC3, the gate of the PMOS tube MC7, the drain of the PMOS tube MC6, and the drain of the NMOS tube MC1;

[0053] The gate of the PMOS transistor MC4 is connected to the gate of the PMOS transistor MC6, and the gate of the PMOS transistor MC4 is also connected to the drain of the PMOS transistor MC4, the gate of the PMOS transistor MC8, the drain of the PMOS transistor MC5, and the drain of the NMOS transistor MC2;

[0054] The source of the NMOS transistor MC1 is connected to the source of the NMOS transistor MC2 and to the drain of the NMOS transistor MC11. The gate of the NMOS transistor MC1 is connected to the feedback voltage V F , the gate of NMOS tube MC2 is connected to the reference voltage V REF ;

[0055] The drain of the PMOS tube MC7 is connected to the drain of the NMOS tube MC9 and forms the output end of the hysteresis comparator, the gate of the NMOS tube MC9 is connected to the gate of the NMOS tube MC10, the gate of the NMOS tube MC10 is connected to the drain of the NMOS tube MC10 and the drain of the PMOS tube MC8, and the source of the NMOS tube MC9, the source of the NMOS tube MC10 and the source of the NMOS tube MC11 are all grounded.

[0056] The beneficial technical effects of the present invention are:

[0057] The charge pump circuit provided by the present invention enables the first pump capacitor and the second pump capacitor to work alternately as boost capacitors under the control of the timing switch circuit. The design of the two boost paths can effectively reduce the output voltage ripple, and the charge pump circuit has a charge recovery function, which can recover the charge lost when the boost capacitor is switched, effectively reducing the loss of the circuit and improving the efficiency of the charge pump circuit. A clock generation module is designed to provide non-overlapping clock signals for the charge recovery circuit and the timing switch circuit. A cross-coupled boost circuit is used in the clock generation module to generate a high-voltage clock signal, which simplifies the overall circuit structure of the clock generation module. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a simplified structural diagram of an embodiment of the charge pump circuit provided by the present invention.

[0059] Figure 2 The switch tube S in the timing switch circuit provided by the present invention 1 -S 9 Timing diagram of .

[0060] Figure 3 The circuit diagram of an embodiment of a high-efficiency and low-ripple charge pump circuit provided by the present invention.

[0061] Figure 4 is a clock signal Φ in an embodiment provided by the present invention 1 -Φ 5 Timing diagram of .

[0062] Figure 5 It is a circuit schematic diagram of an embodiment of a non-overlapping clock generation circuit provided by the present invention.

[0063] Figure 6 It is a circuit principle diagram of another embodiment of the charge pump circuit provided by the present invention.

[0064] Figure 7 It is a circuit principle diagram of another embodiment of the high-voltage clock generating circuit provided by the present invention.

[0065] Figure 8It is a structural block diagram of an embodiment of a high-efficiency, low-ripple charge pump provided by the present invention.

[0066] Fig. 9 It is a structural block diagram of an embodiment of a high-efficiency, low-ripple charge pump loop provided by the present invention.

[0067] Fig.10 The figure is a circuit diagram of an embodiment of the error amplifier provided by the present invention.

[0068] Fig.11 The diagram is a circuit diagram of an embodiment of a voltage-controlled oscillator provided by the present invention.

[0069] Fig.12 The circuit diagram of one embodiment of the clock shaping circuit provided by the present invention is shown in FIG.

[0070] Fig.13 The invention provides a circuit diagram of a variable resistor voltage divider circuit according to an embodiment of the invention.

[0071] Fig.14 The invention provides a circuit diagram of a hysteresis comparator according to an embodiment of the invention.

[0072] Fig.15 The invention provides a circuit schematic diagram of a bandgap reference circuit according to an embodiment of the invention.

[0073] Fig.16 The invention provides a circuit schematic diagram of an embodiment of a low-voltage common-source common-gate bias circuit. DETAILED DESCRIPTION

[0074] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0075] The present invention provides a high-efficiency and low-ripple charge pump, comprising a charge pump core module, wherein the charge pump core module comprises at least one charge pump circuit, wherein the charge pump circuit comprises a first pump capacitor, a second pump capacitor, a charge recovery circuit and a timing switch circuit, wherein:

[0076] During the operation of the charge pump circuit, the first pump capacitor and the second pump capacitor alternately work as boost capacitors under the control of the timing switch circuit; before the current boost capacitor alternates, the charge pump circuit uses the first end of the current boost capacitor to output voltage to the outside, that is, uses the first end of the first pump capacitor or the second pump capacitor to output voltage to the outside, and after outputting the voltage to the outside, uses the charge recovery circuit to connect the second end of the first pump capacitor with the second end of the second pump capacitor to recover the charge at the second end of the current boost capacitor.

[0077] The charge pump circuit performs voltage conversion by periodically charging and discharging the boost capacitor. In the traditional charge pump circuit, when the boost capacitor is discharged, all the charges acquired by charging will be released to the ground, which wastes a lot of charge and reduces the efficiency of the charge pump circuit. The present application provides a charge recovery circuit, which can recover part of the charge before the boost capacitor is discharged to improve the efficiency of the charge pump circuit. At the same time, the charge pump circuit provided by the present application is provided with two pump capacitors, and the two pump capacitors work alternately as boost capacitors during operation, that is, the charge pump circuit has two charge transfer paths, and the charge transfer path is an important factor affecting the output voltage ripple. Compared with the commonly used charge pump circuit with a single charge transfer path, the two charge transfer paths can double the frequency of the output voltage ripple while reducing the amplitude by half, that is, reducing the output ripple of the charge pump circuit.

[0078] The specific structure and working principle of the charge pump circuit, the charge recovery circuit and the timing switch circuit are described in detail below. The timing switch circuit includes a switch tube S 1 , switch tube S 2 , switch tube S3, switch tube S 4 , switch tube S 5 , switch tube S 6 , switch tube S 7 And the switch tube S 8 ,in,

[0079] The first end of the first pump capacitor is connected to the switch tube S 1 The third electrode of the switch tube S 1 The first electrode of the second pump capacitor is connected to the power supply voltage VDD, and the first end of the second pump capacitor is connected to the switch tube S 3 The third electrode of the switch tube S 3 The first electrode is connected to the power supply voltage VDD;

[0080] The first end of the first pump capacitor is connected to the switch tube S 2 The first electrode of the switch tube S 2 The first electrode and the switch tube S 4 The third electrode of the switch tube S is connected to form the output end of the charge pump circuit. 4 The first electrode is connected to the first end of the second pump capacitor;

[0081] The second end of the first pump capacitor is connected to the switch tube S 5 The first electrode and the switch tube S 6 The third electrode of the switch tube S 5 The third electrode of the switch tube S is grounded. 6 The first electrode is connected to the power supply voltage VDD;

[0082] The second end of the second pump capacitor is connected to the switch tube S 7 The first electrode and the switch tube S 8 The third electrode of the switch tube S 7 The third electrode of the switch tube S is grounded. 8 The first electrode is connected to the power supply voltage VDD;

[0083] Switching tube S 1 , switch tube S 4 , switch tube S 5 And switch tube S 8 The conduction state of the switch tube S 2 , switch tube S 3 , switch tube S 6 And switch tube S 7 The conduction state is the same;

[0084] The switch tube S 1 , switch tube S 4 , switch tube S 5 And switch tube S 8 When both are turned on, the second pump capacitor works as a boost capacitor; the switch tube S 2 , switch tube S 3 , switch tube S 6 When the switch tube S7 and the switch tube S7 are both turned on, the first pump capacitor works as a boost capacitor;

[0085] The charge recovery circuit includes a switch tube S 9 , the switch tube S 9 The first electrode of the switch tube S is connected to the second end of the first pump capacitor. 9 The second electrode is connected to the second end of the second pump capacitor.

[0086] Figure 1 A simplified schematic diagram showing one embodiment of a charge pump circuit is shown. Figure 1 Medium Capacitor C 1 Represents the first pump capacitor, capacitor C 2 In one working cycle of the charge pump circuit, the first pump capacitor and the second pump capacitor are alternately used as boost capacitors, and charge recovery is performed before each boost capacitor is discharged. Figure 2 The switch tube S 1 -S 9 The timing diagram is as follows: Figure 1 and Figure 2 The specific working principle of the charge pump circuit in one working cycle is explained. The charge pump circuit has four working stages in one working cycle. In the first stage, the switch tube S 1 , switch tube S 4 , switch tube S 5, switch tube S 8 The first end of capacitor C1 is charged to VDD, and the second end is discharged to GND. Capacitor C2 is used as a boost capacitor, and the second end of capacitor C2 is charged to VDD, and the first end is raised to 2VDD and output to the outside. 9 The other switch tubes are disconnected, and the second end of capacitor C1 and the second end of capacitor C2 are connected through switch tube S 9 The second end of capacitor C1 and the second end of capacitor C2 are connected, and the charge is redistributed. After stabilization, the voltage of the second end of capacitor C1 and the second end of capacitor C2 are both VDD / 2, the potential of the first end of capacitor C1 rises to 3VDD / 2, and the voltage of the first end of capacitor C2 drops to 3VDD / 2, which means that charge recovery is achieved. 2 , switch tube S 3 , switch tube S 6 , switch tube S 7 The second end of capacitor C1 only needs to be charged from VDD / 2 to VDD, and the potential of the first end is raised to 2VDD and output to the outside. The second end of capacitor C2 is discharged to GND, and the first end becomes VDD. The fourth stage repeats the operation of the second stage to recover the charge, and the switch tube S 9 The other switch tubes are disconnected, and the second end of capacitor C1 and the second end of capacitor C2 are connected through switch tube S 9 At this time, the second end of capacitor C1 and the second end of capacitor C2 redistribute the charge. After stabilization, the voltages of the second end of capacitor C1 and the second end of capacitor C2 are both VDD / 2, the potential of the first end of capacitor C2 rises to 3VDD / 2, and the voltage of the first end of capacitor C1 drops to 3VDD / 2.

[0087] In specific implementation, the switch tube S 1 -S 9 For power devices such as MOS tubes, generally, according to the principle of using PMOS for high-level transmission and NMOS for low-level transmission, the switch tube S 1 , switch tube S 3 , switch tube S 5 , switch tube S 7 NMOS tubes can be used, switch tubes S 2 , switch tube S 4 , switch tube S 6 , switch tube S 8 PMOS tubes can be used. However, in order to reduce the phase types of the clock required by the timing switch circuit, the switch tube S in this embodiment 1 -S 9 PMOS tubes are used. For the PMOS tubes, the first electrode is the source, the second electrode is the gate, and the third electrode is the drain. Figure 3The switch tube S 1 -S 9 The schematic diagram of the charge pump circuit when PMOS tubes are used is as follows: Figure 3 As shown, the switch tube S 5 The second electrode is connected to the clock signal Φ 1 , the switch tube S 8 The second electrode is connected to the clock signal Φ 1 The inverting signal of the switch tube S 7 The second electrode is connected to the clock signal Φ 2 , the switch tube S 6 The second electrode is connected to the clock signal Φ 2 The inverting signal of the switch tube S 1 And switch tube S 4 The second electrode is connected to the clock signal Φ 3 , the switch tube S 2 And switch tube S 3 The second electrode is connected to the clock signal Φ 4 The switch tube S 9 The second electrode is connected to the clock signal Φ 5 The switch tube S 9 When the first pump capacitor is turned on, the second end of the first pump capacitor is electrically connected to the second end of the second pump capacitor. 1 The inverted signal is Indicates that the clock signal Φ 2 The inverted signal is express.

[0088] Figure 4 shows the clock signal Φ 1 -Φ 4 The timing diagram of the clock signal Φ 1 With the clock signal Φ 3 Synchronize, the clock signal Φ 2 With the clock signal Φ 4 Synchronization, clock signal Φ 1 With the clock signal Φ 2 is a two-phase non-overlapping clock, and the clock signal Φ 5 The effective level of the clock signal Φ 1 With the clock signal Φ 2 Within the non-overlapping time, that is, the clock signal Φ 1 , clock signal Φ 2 , clock signal Φ 5 is a three-phase non-overlapping clock. In this embodiment, the clock signal Φ 1 With the clock signal Φ 3 These are clocks with the same phase and amplitude but different starting voltages.

[0089] In order to generate the clock signal required by the sequential switching circuit, the charge pump further comprises a clock generation module, the clock generation module comprises a non-overlapping clock generation circuit, and the non-overlapping clock generation circuit is used to generate the clock signal Φ 1 , clock signal Φ 2 and clock signal Φ 5 ;

[0090] like Figure 5 As shown, the non-overlapping clock generation circuit includes a NOR gate NOR3, a first clock circuit and a second clock circuit, wherein the first clock circuit includes an inverter INV1, a NOR gate NOR1, a NOR gate NOR2, a first inverter chain Delay1 and a second inverter chain Delay2, wherein:

[0091] The input end of the inverter INV1 is connected to the first input end of the NOR gate NOR1 and forms the input end of the first clock circuit, the input clock signal CLK_IN is input from the input end, and the second input end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR3;

[0092] The output end of the inverter INV1 is connected to the second input end of the NOR gate NOR2, and the first input end of the NOR gate NOR2 is connected to the second input end of the NOR gate NOR3;

[0093] The output end of the NOR gate NOR1 is connected to the input end of the first inverter chain Delay1, and the output end of the first inverter chain Delay1 is connected to the second input end of the NOR gate NOR3 to form a first output end of the non-overlapping clock generation circuit. The first output end outputs the first output clock signal CLK_NO1, that is, the clock signal Φ in the above embodiment. 1 .

[0094] The output end of the NOR gate NOR2 is connected to the input end of the second inverter chain Delay2, and the output end of the second inverter chain Delay2 is connected to the first input end of the NOR gate NOR3 to form a second output end of the non-overlapping clock generation circuit. The second output end outputs the second output clock signal CLK_NO2, that is, the clock signal Φ in the above embodiment. 2 The first inverter chain Delay1 and the second inverter chain Delay2 have the same structure, and both the first inverter chain Delay1 and the second inverter chain Delay2 include an even number of inverters connected in series.

[0095] The structure of the second clock circuit is the same as that of the first clock circuit, the output end of the NOR gate NOR3 is connected to the input end of the second clock generation circuit, and the third output end of the non-overlapping clock generation circuit is formed based on the output end of the second clock circuit. Specifically, the second clock circuit includes an inverter INV1', a NOR gate NOR1', a NOR gate NOR2', an inverter chain Delay1' and an inverter chain Delay2', the input end of the inverter INV1' is connected to the output end of the NOR gate NOR3 as the input end of the second clock generation circuit, and the output end of the inverter chain Delay1' is used as the third output end to output the third output clock signal CLK_NO3, that is, the above-mentioned clock signal Φ 5 The inverter INV1', NOR gate NOR1', NOR gate NOR2', inverter chain Delay1' and inverter chain Delay2' in the second clock circuit are connected in the same manner as the inverter INV1, NOR gate NOR1, NOR gate NOR2, first inverter chain Delay1 and second inverter chain Delay2 in the first clock circuit, and are not described in detail here. The structures of the inverter chain Delay1' and inverter chain Delay2' are the same as those of the first inverter chain Delay1.

[0096] When the input clock signal CLK_IN is at a low level, the output level of the NOR gate NOR1 cannot be determined. The clock signal CLK_IN is connected to the second input terminal of the NOR gate NOR2 after passing through the inverter. At this time, the output of the NOR gate NOR2 is at a low level. After the signal is delayed by the second inverter chain, CLK_NO2 and the second input terminal of the NOR gate NOR1 are at a low level. At this time, the output of the NOR gate NOR1 can be determined to be a high level. After being delayed by the first inverter chain, CLK_NO1 is determined to be a high level. In this process, CLK_NO1 is pulled high through one more NOR gate and one more inverter chain than CLK_NO2 is pulled low.

[0097] When the input clock signal CLK_IN flips to a high level, the output of the NOR gate NOR1 becomes a low level, and the clock input of the NOR gate NOR2 is at a low level. Then, before the output signal of the NOR gate NOR1 is delayed, the output of the NOR gate NOR2 is determined by the potential of the output of the NOR gate NOR1 after the delay before the clock flips, that is, CLK_NO1, and is still at a high level. After the output of the NOR gate NOR1 is delayed by the first inverter chain, CLK_NO1 flips to a low level, and the output of the NOR gate NOR2 changes to a high level. After the delay of the second inverter chain, CLK2 flips to a high level. From the above description, it can be seen that the high-level input clock signal CLK_IN needs to pass through two logic gates and two inverter chains during transmission, while the low-level input clock signal CLK_IN only needs to pass through one logic gate and one inverter chain during transmission. The non-overlapping time of the non-overlapping two-phase clock signals CLK_NO1 and CLK_NO2 is the delay time generated by one logic gate and one inverter chain. In specific implementation, the total delay time of the inverter chain can be adjusted by adjusting the aspect ratio, area and number of the inverters.

[0098] After obtaining the two-phase non-overlapping clock signal CLK_NO1 and the clock signal CLK_NO2, the clock signal CLK_NO1 and the clock signal CLK_NO2 are passed through the NOR gate NOR3 to obtain a clock signal with a high level in the two-phase clock non-overlapping region. The clock signal is input again into the second clock circuit with the same structure as the first clock circuit to obtain a clock signal CLK_NO3 that does not overlap with the clock signal CLK_NO1 and the clock signal CLK_NO2, that is, the clock signal Φ in the above embodiment. 5 .

[0099] Furthermore, the first output terminal of the non-overlapping clock generating circuit is also connected to the input terminal of the inverter INV_1, and the output terminal of the inverter INV_1 serves as the fourth output terminal of the non-overlapping clock generating circuit to output the clock signal Φ 1 The inverted signal;

[0100] The second output terminal of the non-overlapping clock generation circuit outputs a clock signal Φ 2 The second output terminal of the non-overlapping clock generating circuit is also connected to the input terminal of the inverter INV_2, and the output terminal of the inverter INV_2 serves as the fifth output terminal of the non-overlapping clock generating circuit to output the clock signal Φ 2 The inverted signal;

[0101] Considering that the boost capacitor has a large capacitance, the clock signal Φ 1 , clock signal Φ 2 , clock signal Φ 1 The inverted signal and clock signal Φ2 The inverted signal needs to have a strong driving capability, so the clock generation module also includes a clock drive enhancement circuit for enhancing the driving capability of the clock signal, and the clock drive enhancement circuit includes four clock drive chains. The first output end, the second output end, the third output end and the fourth output end of the non-overlapping clock generation circuit are each connected to the second electrode, i.e., the gate, of the corresponding switch tube in the timing switch circuit through a clock drive chain; the clock drive chain includes an even number of inverters connected in series and the width-to-length ratio increases sequentially according to a preset ratio.

[0102] The charge pump core module can increase the amplification factor of the output voltage by connecting multiple stages of charge pump circuits in series. Ideally, the output voltage Vout' of the charge pump core module is (N+1)VDD, where N is the number of stages of the charge pump circuit in the charge pump core module. In another embodiment of the present invention, the charge pump core module includes a four-stage series charge pump circuit. The circuit schematic diagram of the four-stage series charge pump circuit is as shown in FIG. Figure 6 As shown, it should be noted that in order to simplify the circuit structure, the first ends of the pump capacitors in two adjacent charge pump circuits are connected only by one switch tube, that is, when the charge pump core module includes multiple stages of charge pump circuits connected in series, one switch tube can be omitted between adjacent pump capacitors in two adjacent charge pump circuits.

[0103] When the charge pump core module includes multiple stages of charge pump circuits connected in series, the output values ​​of each charge pump circuit in the module will be multiplied in sequence, and the source and drain voltages of the switch tubes connected to the first end of the pump capacitor in each stage of the charge pump circuit will also increase in sequence. Therefore, in order to ensure the normal opening and closing of the switch tubes connected to the first end of the pump capacitor in each stage of the charge pump circuit, the switch tubes connected to the first end of the pump capacitor in each stage of the charge pump circuit need to use non-overlapping clock control in different voltage ranges, that is, Figure 6 Therefore, the present application provides a high-voltage clock generation circuit in the clock generation module.

[0104] The high-voltage clock generation circuit includes at least one cross-coupled boost circuit, and the cross-coupled boost circuit corresponds to the charge pump circuit one by one; the cross-coupled boost circuit includes a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, and the first end of the first capacitor is connected to the clock signal Φ 1 , the second end of the first capacitor is connected to the drain of the first PMOS tube and the drain of the first NMOS tube; the first end of the second capacitor is connected to the clock signal Φ 2, the second end of the second capacitor is connected to the drain of the second PMOS tube and the drain of the second NMOS tube; the source of the first PMOS tube is connected to the source of the second PMOS tube, and the source of the first NMOS tube and the source of the second NMOS tube are connected to the power supply voltage VDD; the gate of the second PMOS tube, the gate of the second NMOS tube and the second end of the first capacitor are connected to form a first output end of the cross-coupled boost circuit, and the gate of the first PMOS tube, the gate of the first NMOS tube and the second end of the second capacitor are connected to form a second output end of the cross-coupled boost circuit.

[0105] When the charge pump core module includes only one level of charge pump circuit, the high voltage clock module is used to generate a high voltage clock based on the clock signal Φ 1 and clock signal Φ 2 Generate clock signal Φ 3 and clock signal Φ 4 , that is, the clock signal Φ is output through the first output terminal of the cross-coupled boost circuit 3 , the clock signal Φ is output through the second output terminal of the cross-coupled boost circuit 4 When the charge pump core module includes a multi-stage charge pump circuit, the high-voltage clock generation circuit includes a multi-stage cross-coupled boost circuit that corresponds to the charge pump circuit one by one and is connected in series, and is used to provide non-overlapping clock signals in different voltage ranges. Using a cross-coupled voltage boost circuit to bootstrap and generate a high-voltage clock control signal can keep the high and low voltage clock phases consistent, and the circuit structure is simpler.

[0106] for Figure 6 The four-stage series charge pump circuit shown in the figure takes VDD as 5V as an example, and the valid level values ​​and invalid level values ​​of the non-overlapping clock signals in different voltage intervals required by the circuit are shown in Table 1.

[0107] Table 1 Valid / invalid level values ​​of non-overlapping clock signals required for four-stage series charge pump circuit

[0108]

[0109] Figure 7 Shown as Figure 6 The four-stage series charge pump circuit shown provides a clock signal Φ 3 ', clock signal Φ 4 ', clock signal Φ 5 ' and the clock signal Φ 6 -Φ 10 The high voltage clock module. The clock signal Φ 3 'Control switch tube K3, clock signal Φ 4 'Control switch tube K4, clock signal Φ 5 'Control switch tube K5, clock signal Φ 6Control switch tube K6, clock signal Φ 7 Control switch tube K7, clock signal Φ 8 Control switch tube K8, clock signal Φ 9 Control switch tube K9 and switch tube K12, clock signal Φ 10 Control switch tube K10 and switch tube K11. Figure 8 The connection relationship between the four-stage series charge pump circuit and each circuit in the clock generation module is shown. Figure 7 and Figure 8 The clock signals CLK3-CLK5 correspond to the clock signals Φ 3 '-Φ 5 ', the clock signals CLK6-CLK10 correspond to the clock signal Φ 6 -Φ 10 The clock signal CLK_NO1, the clock signal CLK_NO2, and the inverted signal of the clock signal CLK_NO1 generated by the non-overlapping clock generation circuit The inverted signal of the clock signal CLK_NO2 The clock signal CLK_NO3 corresponds to Figure 6 The clock signal Φ 1 ', clock signal Φ 2 ', clock signal Clock signal and the clock signal Φ 11 The clock signal Φ 1 'Control switch tube K1, switch tube K16, switch tube K19 and switch tube K24, clock signal Control switch tubes K14, K17, K22 and K25, clock signal Φ 2 'Control switch tube K2, switch tube K15, switch tube K20 and switch tube K23, clock signal Control switch tubes K13, K18, K21 and K26, clock signal Φ 11 Control switch tube K27, switch tube K28, switch tube K29 and switch tube K30.

[0110] Considering the influence of the on-resistance of the switch tube in the circuit, the capacitor C 1 -C 8 When the capacitance values ​​of are all C, the output voltage of the above four-stage series charge pump circuit can be expressed as:

[0111]

[0112] Among them, I out represents the load current, R onThe on-resistance of the switch in the four-stage series charge pump circuit is R, and f is the operating frequency of the four-stage series charge pump circuit. on’ It can be expressed as:

[0113]

[0114] Among them, μ n is the electron mobility, C ox is the gate oxide capacitance of the MOS tube, W is the channel width of the MOS tube, L is the channel length of the MOS tube, V GS is the gate-source voltage of the MOS tube, V TH is the threshold voltage of the MOS tube. Figure 6 The switch tubes in the four-stage series charge pump circuit shown are all PMOS tubes. PMOS tubes work in the linear region. on The specific value is the resistance value of the two conductive paths connected in parallel after the four-stage PMOS switch tubes are connected in series, that is, twice the on-resistance of a PMOS switch tube. The output voltage of the above four-stage series charge pump circuit can be expressed as:

[0115]

[0116] When applied, the charge pump is often set in a closed loop circuit, and a stable voltage output is achieved by closed-loop control of the charge pump. There are many forms of closed-loop control of the charge pump, including pulse width modulation (PWM), pulse skip modulation (PSM) and pulse frequency modulation (PFM). These three modulation methods all control the output voltage of the charge pump by adjusting the internal clock of the charge pump. Different modulation modes will have a huge impact on the structure, efficiency, power consumption, output voltage ripple, noise level and transient response capability of the circuit. Among them, the charge pump loop based on PFM regulation has a relatively balanced performance in output voltage ripple and power consumption. Therefore, the present invention provides a charge pump loop using a pulse frequency modulation mode.

[0117] Specifically, Fig. 9 It is a schematic diagram of the structure of the charge pump loop. Fig. 9 As shown, the charge pump loop includes the above-mentioned charge pump, a variable resistor voltage divider circuit, an error amplifier, a voltage-controlled oscillator (VCO) and a clock shaping circuit, wherein:

[0118] The charge pump is connected to a variable resistor voltage divider circuit, the variable resistor voltage divider circuit is connected to an error amplifier, the error amplifier is connected to a voltage controlled oscillator, and the voltage controlled oscillator is connected to the charge pump via a clock shaping circuit;

[0119] The output voltage of the charge pump is divided by a variable resistor to generate a feedback voltage V F The inverting input terminal of the error amplifier is inputted to the reference voltage V REF , the error amplifier will feedback voltage V F With reference voltage V REF After comparison, the control voltage V EA , the control voltage V EA The input is to the voltage-controlled oscillator to adjust the clock frequency of the output clock signal of the voltage-controlled oscillator. The output clock signal of the voltage-controlled oscillator is shaped by the clock circuit and input to the charge pump, specifically, as the input clock signal, which is input to the clock generation module of the charge pump to adjust the output voltage of the charge pump and make it stable.

[0120] The error amplifier is an important module in the charge pump loop. It is generally expected that the error amplifier can output a relatively stable value. However, since the output voltage of the charge pump has an inherent ripple related to the clock frequency, the voltage at the inverting input of the error amplifier fluctuates all the time, which has an impact on the control voltage V output by the error amplifier. EA The stability of the error amplifier is very unfavorable. Therefore, in order to ensure that the error amplifier can output a stable value, the design of the error amplifier does not need a large gain. In order to ensure that the voltage-controlled oscillator has the largest frequency adjustment range, the output of the error amplifier needs to have a large voltage swing. In order to ensure the rapid response of the circuit when the load fluctuates, the error amplifier needs to have a faster response speed. At the same time, in order to prevent the output voltage ripple from being transmitted to the voltage-controlled oscillator, the output signal of the error amplifier needs to be filtered.

[0121] like Fig.10 As shown, the error amplifier in this embodiment includes NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, PMOS tube PM1, PMOS tube PM2, resistor R E1 , capacitor C E1 And the capacitor C E2The sources of the NMOS tubes NM1 and NMOS tubes NM2 are connected to the drain of the NMOS tube NM3, the source of the NMOS tube NM3 is grounded, the gate of the NMOS tube NM3 is connected to the bias voltage, the drain of the NMOS tube NM1 is connected to the drain of the PMOS tube PM1, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube PM2, the sources of the PMOS tubes PM1 and PMOS tubes PM2 are connected to the power supply voltage VDD, the gates of the PMOS tubes PM1 and PMOS tubes PM2 are connected and connected to the drain of the PMOS tube PM1, and the gate of the NMOS tube NM1 is connected to the reference voltage V REF , the gate of NMOS tube NM2 is connected to the feedback voltage V F , the drain of NMOS tube NM2 and the drain of PMOS tube PM2 are connected through resistor R E1 With capacitor C E1 and capacitor C E2 The other end of the capacitor CE1 is connected to the drain of the NMOS tube NM4. E2 The other end of is grounded, the gate of the NMOS tube NM4 is connected to the control signal, and the source of the NMOS tube NM4 is grounded.

[0122] Use NMOS tube as input tube to ensure swing amplitude, control tail current through NMOS tube NM3 to ensure response speed, and resistor R E1 , capacitor C E1 And the capacitor C E2 An RC low-pass filter is formed. By controlling the NMOS tube NM4, the capacitance of the ground capacitor can be adjusted, thereby adjusting the cut-off frequency of the low-pass filter to achieve flexible filtering.

[0123] like Fig.11 As shown, the voltage-controlled oscillator includes a resistor RO1, a resistor RO2, a PMOS tube MO2, a PMOS tube MO3, a PMOS tube MO4, an NMOS tube MO1, an NMOS tube MO5, an NMOS tube MO6, an inverter I1, an inverter I2, and an inverter I3, wherein:

[0124] The gate of the NMOS transistor MO1 is connected to the control voltage VEA, the source of the NMOS transistor MO1 is connected to one end of the resistor RO1, and the other end of the resistor RO1 is connected to one end of the resistor RO2 and connected to the temperature compensation current I PTAT , the other end of the resistor RO2 is grounded;

[0125] The drain of the NMOS tube MO1 is connected to the drain of the PMOS tube MO2, the gate of the PMOS tube MO2, the gate of the PMOS tube MO3 and the gate of the PMOS tube MO4, the source of the PMOS tube MO2, the source of the PMOS tube MO3 and the source of the PMOS tube MO4 are connected and connected to the power supply voltage VDD, the drain of the PMOS tube MO3 is connected to the drain of the NMOS tube MO5, the drain of the NMOS tube MO5 is connected to the gate, the source of the NMOS tube MO5 is connected to the source of the NMOS tube MO6 and is grounded, and the gate of the NMOS tube MO5 is connected to the gate of the NMOS tube MO6;

[0126] The input end of the inverter I1 is connected to the output end of the inverter I3, the output end of the inverter I1 is connected to the input end of the inverter I2 and is grounded through the capacitor CO1, the output end of the inverter I2 is connected to the input end of the inverter I3, and the output end of the inverter I3 is connected to the clock shaping circuit;

[0127] The source of the PMOS tube in the inverter I1 is connected to the drain of the PMOS tube MO4, and the source of the NMOS tube in the inverter I1 is connected to the drain of the NMOS tube MO6.

[0128] Above I PTAT The current is proportional to the absolute temperature, and the capacitor CO1 is the deceleration capacitor between the first and second inverters. The ring oscillator is composed of three inverters connected end to end. The current of the first inverter I1 is controlled by VEA, and cooperates with the deceleration capacitor between the first and second stages to realize the function of voltage-controlled frequency. At the same time, I PTAT A certain degree of temperature compensation can be performed to make the output frequency of the oscillator relatively stable as the temperature changes.

[0129] When VEA increases, the input-stage branch current formed by the PMOS tube MO2 and the NMOS tube MO1 increases. Due to the existence of the resistors RO1 and RO2, the input-stage branch current has a source negative feedback mechanism, that is, when the current increases, the voltage drop on the resistors RO1 and RO2 increases, causing the source voltage of the NMOS tube MO1 to increase, slowing down the speed of the current increase in this path and improving the linearity of the voltage-controlled current. The input-stage branch current is copied to the first-stage inverter I1 through the current mirror formed by the PMOS tube MO3, PMOS tube MO4, NMOS tube MO5 and NMOS tube MO6, so that the charging speed of the capacitor CO1 is accelerated, the delay between the first and second inverters is reduced, and the output frequency of the oscillator is accelerated. When VEA decreases, the input-stage branch current decreases and is copied to the first-stage inverter I1 through the current mirror, so that the charging speed of the capacitor CO1 is reduced, the delay between the first and second inverters is increased, and the output frequency of the oscillator is reduced.

[0130] From the above description, it can be seen that the voltage-controlled oscillator uses a three-stage inverter to form a ring oscillator. The clock signal generated by it has a high frequency and poor quality. The establishment speed and duty cycle are not enough to meet the requirements of the subsequent circuit. Therefore, a clock shaping circuit is required to further shape the signal into a square wave with a duty cycle of 50%. The clock shaping circuit described in this embodiment is a single clocked D flip-flop (DFF), such as Fig.12 As shown, the D input terminal of the D flip-flop is connected to The output ends are connected to realize the two-frequency division function.

[0131] Furthermore, the variable resistor voltage divider circuit includes a resistor Rf1, a resistor Rf2 and a variable resistor unit, one end of the resistor Rf1 is connected to one end of the resistor Rf2 and the variable resistor unit to form an output end of the variable resistor voltage divider circuit, the other end of the resistor Rf1 is grounded, and the other end of the resistor Rf2 is connected to the output voltage V of the charge pump out ;

[0132] The variable resistor unit includes a resistor R0, a total transmission gate TG0 and a plurality of adjustment resistors, the resistor R0 is connected in series with the resistor Rf2, and the plurality of adjustment resistors are connected in series with the resistor R0;

[0133] Each regulating resistor is connected in parallel with a transmission gate, and all the transmission gates are connected in series to one end of a total transmission gate TG0, and the other end of the total transmission gate TG0 is grounded.

[0134] Fig.13 The circuit schematic diagram of an embodiment of a variable resistor unit is shown. In this embodiment, the variable resistor unit is provided with five adjusting resistors R1-R5, and the adjusting resistors are connected in parallel with the transmission gates TG1-TG5 one by one. The total resistance formed by the series connection of the resistors R0-R5 is Rx. By opening the transmission gates TG1-TG5, the corresponding resistors in the resistors R1-R5 can be short-circuited, thereby adjusting the resistance value of Rx in sections, so as to adjust the value of Rx by adjusting R x The resistance value of the charge pump output voltage can be adjusted in multiple stages. In this embodiment, the resistance values ​​of the resistors Rf1 and Rf2 are both Rf, then V out The relationship with VF is:

[0135]

[0136] In this embodiment, the resistance ratio of Rf to the resistors R0-R5 is 120:16:1:2:4:8:16, and R1 with the smallest resistance is set to R, and V REF =2.5V, in the stable state, the voltage of the error amplifier positive input terminal is equal to the voltage of the negative input terminal, that is, V F =V REF =2.5V, then in this embodiment, V out It can be expressed as:

[0137]

[0138] When TG0 is turned off, V out =5V, in this embodiment, the adjustment range of Rx is 16R-47R, so if the process limitation is not considered, V out The output range is 11.38-23.75V.

[0139] The charge pump loop also includes a hysteresis comparator, and the feedback voltage V F Connect to the positive input of the hysteresis comparator, and connect the reference voltage V to the negative input of the hysteresis comparator. REF , the hysteresis comparator compares the feedback voltage V F With reference voltage V REF And output the output feedback voltage V that represents the output state of the charge pump FOUT ;

[0140] like Fig.14 As shown, the hysteresis comparator includes NMOS transistor MC1, NMOS transistor MC2, PMOS transistor MC3, PMOS transistor MC4, PMOS transistor MC5, PMOS transistor MC6, PMOS transistor MC7, PMOS transistor MC8, NMOS transistor MC9, NMOS transistor MC10 and NMOS transistor MC11, wherein,

[0141] The sources of the PMOS tubes MC3, MC4, MC5, MC6, MC7 and MC8 are connected to the power supply voltage VDD;

[0142] The gate of the PMOS tube MC3 is connected to the gate of the PMOS tube MC5, and the gate of the PMOS tube MC3 is also connected to the drain of the PMOS tube MC3, the gate of the PMOS tube MC7, the drain of the PMOS tube MC6, and the drain of the NMOS tube MC1;

[0143] The gate of the PMOS transistor MC4 is connected to the gate of the PMOS transistor MC6, and the gate of the PMOS transistor MC4 is also connected to the drain of the PMOS transistor MC4, the gate of the PMOS transistor MC8, the drain of the PMOS transistor MC5, and the drain of the NMOS transistor MC2;

[0144] The source of the NMOS transistor MC1 is connected to the source of the NMOS transistor MC2 and to the drain of the NMOS transistor MC11. The gate of the NMOS transistor MC1 is connected to the feedback voltage V F , the gate of NMOS tube MC2 is connected to the reference voltage V REF ;

[0145] The drain of the PMOS tube MC7 is connected to the drain of the NMOS tube MC9 and forms the output end of the hysteresis comparator, the gate of the NMOS tube MC9 is connected to the gate of the NMOS tube MC10, the gate of the NMOS tube MC10 is connected to the drain of the NMOS tube MC10 and the drain of the PMOS tube MC8, and the source of the NMOS tube MC9, the source of the NMOS tube MC10 and the source of the NMOS tube MC11 are all grounded.

[0146] Specifically, the hysteresis comparator has two feedback paths, one positive and one negative. The currents of NMOS tube MC1 and NMOS tube MC2 flow through NMOS tube M11 to form a series current negative feedback path, and the gates and drains of PMOS tube MC5 and PMOS tube MC6 are connected to form a parallel voltage positive feedback path. When the positive feedback coefficient is greater than the negative feedback coefficient, the circuit exhibits a hysteresis characteristic. To this end, the circuit design must ensure that:

[0147]

[0148] (W / L) M5 is the size ratio of PMOS tube MC5, (W / L) M3 is the size ratio of PMOS tube MC3, (W / L) M6 is the size ratio of PMOS tube MC6, (W / L) M4 is the size ratio of the PMOS tube MC4.

[0149] When V F Much smaller than V REF When MC1 is turned off and MC2 is turned on, MC3 and MC5 are turned off, MC4 and MC6 are turned on, and the current of MC11 flows through MC2 and MC4. At this time, MC6 tube provides current for the branch where MC1 is located. F As V increases gradually, the current flowing through MC1 continues to increase, but even if the current flowing through MC1 exceeds the current flowing through MC2, the comparator will not flip. Because of the limitation of MC6, the comparator output can only flip when the current flowing through MC1 exceeds the current flowing through MC6. On the contrary, when V F When it decreases from high to low, MC5 amplifies the current flowing through MC1 and copies it to MC2. When the current flowing through MC2 increases to the same level as the current flowing through MC5, the comparator output flips.

[0150] The above reference voltage V REF Generally, it can be generated by a bandgap reference circuit. The specific structure of the bandgap reference circuit used in this embodiment is as follows: Fig.15 As shown, Fig.15The PMOS tube M1 is connected with the PMOS tube M2 in common source and gate, the drain of the NMOS tube M3 is connected with the gate of the NMOS tube M4 and the drain of the PMOS tube M1, and the source of the NMOS tube M3 is connected with the gate of the NMOS tube M4 and grounded. The drain of the NMOS tube M5 is connected with the drain of the PMOS tube M2 and the gate of the NMOS tube M6, and the source of the NMOS tube M5 and the source of the NMOS tube M6 are grounded. The drain of the NMOS tube M6 is connected with the gate of the PMOS tube M7, the drain of the PMOS tube M7 is connected with the source of the PMOS tube M8, the drain of the PMOS tube M8 is connected with the emitter of the transistor Q1, the collector and base of the transistor Q1 are grounded, and the gate of the transistor Q1 is connected with the gate of the PMOS tube M11 through the resistor R1. The drain of the PMOS tube M9 is connected to the source of the PMOS tube M10, the gate of the PMOS tube M9 is connected to the first bias voltage Vbias1, the gate of the PMOS tube M10 is connected to the second bias voltage Vbias2, the drain of the PMOS tube M10 is connected to the sources of the PMOS tubes M11 and M12, the drain of the PMOS tube M11 is connected to the drain of the NMOS tube M19, and the drain of the PMOS tube M12 is connected to the drain of the NMOS tube M20. The sources of the NMOS transistors M19 and M20 are grounded, and the gates are connected to the fourth bias voltage Vbias4. The drains of the NMOS transistors M19 and M20 are connected to the sources of the NMOS transistors M17 and M18 respectively, and the gates of the NMOS transistors M17 and M18 are connected to the third bias voltage Vbias3. The drains of the NMOS transistors M17 and M18 are connected to the drains of the PMOS transistors N15 and M16 respectively, and the gates of the PMOS transistors M15 and M16 are connected to the second bias voltage Vbias2. The sources of the PMOS transistors M15 and M16 are connected to the drains of the PMOS transistors M13 and M14 respectively, and the gates of the PMOS transistors M13 and M14 are connected and connected to the drain of the PMOS transistor M15.

[0151] The gate of the PMOS tube M7 is connected to the drain of the PMOS tube M16, and is also connected to the gates of the PMOS tube M21 and the PMOS tube M22. The gate of the PMOS tube M8 is connected to the gates of the PMOS tube M23 and the PMOS tube M24. The drain of the PMOS tube M21 is connected to the source of the PMOS tube M23, and the drain of the PMOS tube M23 is connected to the emitter of the n transistors Q2 through the resistor R3, the base and collector of the n transistors Q2 are grounded, and the base of the n transistors Q2 is connected to one end of the resistor R3 and the gate of the NMOS tube M12 through the resistor R2. The drain of the PMOS tube M22 is connected to the source of the PMOS tube M24, and the drain of the PMOS tube M24 is connected to one end of the resistor R4 to form a reference voltage output end, and the other end of the resistor R4 is grounded. Sources of the PMOS transistor M1 , the PMOS transistor M2 , the PMOS transistor M7 , the PMOS transistor M9 , the PMOS transistor M13 , the PMOS transistor M14 , the PMOS transistor M21 , and the PMOS transistor M22 are connected to the power supply voltage VDD.

[0152] When the circuit starts working, the MOS capacitor formed by the NMOS tube M4 and the gate capacitor of the NMOS tube M6 start to charge, and the gate capacitor of the NMOS tube M4 is set to be much larger than the gate capacitor of the NMOS tube M6, so that the NMOS tube M6 is turned on first. As a result, the PMOS tubes M7, M21 and M22 are turned on, and the bandgap reference circuit starts to work. When V REF When the voltage is greater than the threshold voltage of the NMOS tube M5, the NMOS tube M5 is turned on, and the gate of the NMOS tube M6 is grounded to turn it off, and the circuit outputs normally. When the circuit is powered off, the charge on the NMOS tube M4 can be discharged to zero potential through the PMOS tube M1.

[0153] A folded cascode amplifier is used to clamp the gate voltages of the PMOS tubes M11 and M12. The gate voltage of the PMOS tube M11 is the base-emitter voltage of the transistor Q1, which has a negative temperature coefficient. At the same time, the potential difference across the resistor R3 has a positive temperature coefficient. At this time, let R1 = R2, and adjust the resistance ratio of R1 and R3 to obtain a current flowing through the PMOS tubes M21 and M23 that is independent of temperature. The cascode current mirror formed by the PMOS tubes M21-24 copies this current to the output branch and flows through the resistor R4 to finally obtain a reference voltage V that is independent of temperature. REF .

[0154]

[0155] In the above formula, R1, R3, and R4 represent the resistance values ​​of resistors R1, R3, and R4 respectively, and V BEQ1 Represents the base-emitter voltage of transistor Q1, ΔV BE =VT lnn, thermal voltage V T =Kt / q, K is the Boltzmann constant, t is the absolute temperature, and q is the electron charge value.

[0156] The bias voltage Vbias1-4 can generally be provided by a low voltage common source common gate bias circuit. Fig.16 FIG. 1 is a circuit schematic diagram of an embodiment of a low voltage common source and common gate bias circuit, such as Fig.16 As shown, the drain of NMOS tube MB1 is connected to the bias current, the source is connected to the drain of NMOS tube MB2, and the sources of NMOS tubes MB2, MB4, MB6 and MB8 are grounded. The drains of NMOS tubes MB4, MB6 and MB8 are connected to the sources of NMOS tubes MB3, MB5 and MB7 respectively. The drains of NMOS tubes MB3, MB5 and MB7 are connected to the drains of PMOS tubes MB10, MB12 and MB14 respectively, the sources of PMOS tubes MB10, MB12 and MB14 are connected to the drains of PMOS tubes MB9, MB11 and MB13 respectively, and the sources of PMOS tubes MB9, MB11 and MB13 are connected to the power supply voltage VDD.

[0157] The gates of the PMOS tubes MB9, MB10, and MB12 are connected and connected to the drains of the PMOS tubes MB10 and MB12 to form the output end of Vbias2. The gates of the PMOS tubes MB11 and MB13 are connected and connected to the drain of MB14 to form the output end of Vbias1. The gates of the NMOS tubes MB2 and MB8 are connected and connected to the drains of MB1, MB4, and MB6 to form the output end of Vbias4. The gates of the NMOS tubes MB1, MB3, MB5, MB6, and MB7 are connected and connected to the drains of MB3 and MB5 to form the output end of Vbias3.

[0158] It should be noted that the terms "first" and "second" used in the above description are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. A high-efficiency, low-ripple charge pump, characterized in that: It includes a charge pump core module, the charge pump core module includes at least one charge pump circuit, the charge pump circuit includes a first pump capacitor, a second pump capacitor, a charge recovery circuit and a timing switch circuit, wherein: During the operation of the charge pump circuit, the first pump capacitor and the second pump capacitor alternately work as boost capacitors under the control of the timing switching circuit; before the current boost capacitor alternates, the charge pump circuit uses the first end of the current boost capacitor to output voltage to the outside, and after outputting the voltage to the outside, uses the charge recovery circuit to connect the second end of the first pump capacitor with the second end of the second pump capacitor to recover the charge at the second end of the current boost capacitor.

2. The high-efficiency, low-ripple charge pump according to claim 1, characterized in that: The timing switch circuit includes a switch tube S1, a switch tube S2, a switch tube S3, a switch tube S4, a switch tube S5, a switch tube S6, a switch tube S7 and a switch tube S8, wherein: The first end of the first pump capacitor is connected to the third electrode of the switch tube S1, and the first electrode of the switch tube S1 is connected to the power supply voltage VDD; the first end of the second pump capacitor is connected to the third electrode of the switch tube S3, and the first electrode of the switch tube S3 is connected to the power supply voltage VDD; The first end of the first pump capacitor is connected to the first electrode of the switch tube S2, the first electrode of the switch tube S2 is connected to the third electrode of the switch tube S4 and forms the output end of the charge pump circuit, and the first electrode of the switch tube S4 is connected to the first end of the second pump capacitor; The second end of the first pump capacitor is connected to the first electrode of the switch tube S5 and the third electrode of the switch tube S6, the third electrode of the switch tube S5 is grounded, and the first electrode of the switch tube S6 is connected to the power supply voltage VDD; The second end of the second pump capacitor is connected to the first electrode of the switch tube S7 and the third electrode of the switch tube S8, the third electrode of the switch tube S7 is grounded, and the first electrode of the switch tube S8 is connected to the power supply voltage VDD; The switch tubes S1, S4, S5 and S8 are in the same conduction state, and the switch tubes S2, S3, S6 and S7 are in the same conduction state; When the switch tubes S1, S4, S5 and S8 are all turned on, the second pump capacitor works as a boost capacitor; when the switch tubes S2, S3, S6 and S7 are all turned on, the first pump capacitor works as a boost capacitor.

3. The high-efficiency, low-ripple charge pump according to claim 2, characterized in that: The second electrode of the switch tube S5 is connected to the clock signal Φ1, the second electrode of the switch tube S8 is connected to the inverted signal of the clock signal Φ1, the second electrode of the switch tube S7 is connected to the clock signal Φ2, and the second electrode of the switch tube S6 is connected to the inverted signal of the clock signal Φ2; The second electrodes of the switch tubes S1 and S4 are connected to the clock signal Φ3, and the second electrodes of the switch tubes S2 and S3 are connected to the clock signal Φ4; The charge recovery circuit includes a switch tube S9, a first electrode of the switch tube S9 is connected to the second end of the first pump capacitor, a second electrode of the switch tube S9 is connected to the second end of the second pump capacitor, and the second electrode of the switch tube S9 is connected to the clock signal Φ5; when the switch tube S9 is turned on, the second end of the first pump capacitor is electrically connected to the second end of the second pump capacitor; The switch tube S1, switch tube S2, switch tube S3, switch tube S4, switch tube S5, switch tube S6, switch tube S7, switch tube S8 and switch tube S9 are all PMOS tubes; The clock signal Φ1 is synchronized with the clock signal Φ3, the clock signal Φ2 is synchronized with the clock signal Φ4, the clock signal Φ1 and the clock signal Φ2 are two-phase non-overlapping clocks, and the effective level of the clock signal Φ5 is within the non-overlapping time of the clock signal Φ1 and the clock signal Φ2.

4. The high-efficiency, low-ripple charge pump according to claim 2, characterized in that: It also includes a clock generation module, the clock generation module includes a non-overlapping clock generation circuit, the non-overlapping clock generation circuit is used to generate the clock signal Φ1, the clock signal Φ2 and the clock signal Φ5; The non-overlapping clock generation circuit includes a NOR gate NOR3, a first clock circuit and a second clock circuit, wherein the first clock circuit includes an inverter INV1, a NOR gate NOR1, a NOR gate NOR2, a first inverter chain and a second inverter chain, wherein: The input end of the inverter INV1 is connected to the first input end of the NOR gate NOR1 and forms the input end of the first clock circuit, and the second input end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR3; The output end of the inverter INV1 is connected to the second input end of the NOR gate NOR2, and the first input end of the NOR gate NOR2 is connected to the second input end of the NOR gate NOR3; The output end of the NOR gate NOR1 is connected to the input end of the first inverter chain, and the output end of the first inverter chain is connected to the second input end of the NOR gate NOR3 to form a first output end of the non-overlapping clock generation circuit; The output end of the NOR gate NOR2 is connected to the input end of the second inverter chain, the output end of the second inverter chain is connected to the first input end of the NOR gate NOR3, and form a second output end of the non-overlapping clock generation circuit, the second clock circuit has the same structure as the first clock circuit, the output end of the NOR gate NOR3 is connected to the input end of the second clock generation circuit, and a third output end of the non-overlapping clock generation circuit is formed based on the output end of the second clock circuit; The first inverter chain and the second inverter chain have the same structure, and both the first inverter chain and the second inverter chain include an even number of inverters connected in series.

5. The high-efficiency, low-ripple charge pump according to claim 4, characterized in that: The clock generation module also includes a high-voltage clock generation circuit; The high-voltage clock generation circuit includes at least one level of cross-coupled boost circuit, and the cross-coupled boost circuit corresponds to the charge pump circuit one by one; The cross-coupled boost circuit includes a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein a first end of the first capacitor is connected to a clock signal Φ1, and a second end of the first capacitor is connected to a drain of the first PMOS transistor and a drain of the first NMOS transistor; a first end of the second capacitor is connected to a clock signal Φ2, and a second end of the second capacitor is connected to a drain of the second PMOS transistor and a drain of the second NMOS transistor; The source of the first PMOS tube is connected to the source of the second PMOS tube, and the source of the first NMOS tube and the source of the second NMOS tube are connected to the power supply voltage VDD; The gate of the second PMOS tube, the gate of the second NMOS tube and the second end of the first capacitor are connected to form a first output end of the cross-coupled boost circuit, and the gate of the first PMOS tube, the gate of the first NMOS tube and the second end of the second capacitor are connected to form a second output end of the cross-coupled boost circuit.

6. The high-efficiency, low-ripple charge pump according to claim 4, characterized in that: The first output terminal of the non-overlapping clock generation circuit outputs the clock signal Φ1, and the first output terminal of the non-overlapping clock generation circuit is also connected to the input terminal of the inverter INV_1, and the output terminal of the inverter INV_1 serves as the fourth output terminal of the non-overlapping clock generation circuit to output the inverted signal of the clock signal Φ1; The second output terminal of the non-overlapping clock generating circuit outputs the clock signal Φ2. The second output terminal of the non-overlapping clock generating circuit is also connected to the input terminal of the inverter INV_2. The output terminal of the inverter INV_2 serves as the fifth output terminal of the non-overlapping clock generating circuit to output the inverted signal of the clock signal Φ2. The clock generation module further includes a clock drive enhancement circuit, which includes four clock drive chains, and the first output terminal, the second output terminal, the fourth output terminal and the fifth output terminal of the non-overlapping clock generation circuit are each connected to a corresponding switch tube in the timing switch circuit through a clock drive chain; The clock drive chain includes an even number of inverters connected in series and whose width-to-length ratios increase in sequence according to a preset ratio.

7. A high efficiency and low ripple charge pump loop, characterized in that: The charge pump comprises the charge pump as claimed in any one of claims 1 to 6, wherein the charge pump loop further comprises a variable resistor voltage divider circuit, an error amplifier, a voltage-controlled oscillator and a clock shaping circuit, wherein: The charge pump is connected to a variable resistor voltage divider circuit, the variable resistor voltage divider circuit is connected to an error amplifier, the error amplifier is connected to a voltage controlled oscillator, and the voltage controlled oscillator is connected to the charge pump via a clock shaping circuit; The output voltage of the charge pump is divided by a variable resistor to generate a feedback voltage V F The error amplifier will input the feedback voltage V F With reference voltage V REF After comparison, the control voltage V EA , the control voltage V EA The output clock signal of the voltage-controlled oscillator is input to the charge pump after being shaped by the clock circuit to adjust the output voltage of the charge pump.

8. The high-efficiency, low-ripple charge pump loop according to claim 7, characterized in that: The voltage-controlled oscillator includes a capacitor CO1, a resistor RO1, a resistor RO2, a PMOS tube MO2, a PMOS tube MO3, a PMOS tube MO4, an NMOS tube MO1, an NMOS tube MO5, an NMOS tube MO6, an inverter I1, an inverter I2, and an inverter I3, wherein: The gate of the NMOS transistor MO1 is connected to the control voltage VEA, the source of the NMOS transistor MO1 is connected to one end of the resistor RO1, and the other end of the resistor RO1 is connected to one end of the resistor RO2 and connected to the temperature compensation current I PTAT , the other end of the resistor RO2 is grounded; The drain of the NMOS tube MO1 is connected to the drain of the PMOS tube MO2, the gate of the PMOS tube MO2, the gate of the PMOS tube MO3 and the gate of the PMOS tube MO4, the source of the PMOS tube MO2, the source of the PMOS tube MO3 and the source of the PMOS tube MO4 are connected and connected to the power supply voltage VDD, the drain of the PMOS tube MO3 is connected to the drain of the NMOS tube MO5, the drain of the NMOS tube MO5 is connected to the gate, the source of the NMOS tube MO5 is connected to the source of the NMOS tube MO6 and is grounded, and the gate of the NMOS tube MO5 is connected to the gate of the NMOS tube MO6; The input end of the inverter I1 is connected to the output end of the inverter I3, the output end of the inverter I1 is connected to the input end of the inverter I2 and is grounded through the capacitor CO1, the output end of the inverter I2 is connected to the input end of the inverter I3, and the output end of the inverter I3 is connected to the clock shaping circuit; The source of the PMOS tube in the inverter I1 is connected to the drain of the PMOS tube MO4, and the source of the NMOS tube in the inverter I1 is connected to the drain of the NMOS tube MO6.

9. The high-efficiency, low-ripple charge pump loop according to claim 7, characterized in that: The variable resistor voltage divider circuit includes a resistor Rf1, a resistor Rf2 and a variable resistor unit. One end of the resistor Rf1 is connected to one end of the resistor Rf2 and the variable resistor unit to form an output end of the variable resistor voltage divider circuit. The other end of the resistor Rf1 is grounded, and the other end of the resistor Rf2 is connected to the output voltage V of the charge pump. out ; The variable resistor unit includes a resistor R0, a total transmission gate TG0 and a plurality of adjustment resistors, the resistor R0 is connected in series with the resistor Rf2, and the plurality of adjustment resistors are connected in series with the resistor R0; Each regulating resistor is connected in parallel with a transmission gate, and all the transmission gates are connected in series to one end of a total transmission gate TG0, and the other end of the total transmission gate TG0 is grounded.

10. The high efficiency and low ripple charge pump loop according to claim 7, characterized in that: A hysteresis comparator is also included, and the feedback voltage V F Connect to the positive input of the hysteresis comparator, and connect the reference voltage V to the negative input of the hysteresis comparator. REF , the hysteresis comparator compares the feedback voltage V F With reference voltage V REF And output the output feedback voltage V that represents the output state of the charge pump FOUT ; The hysteresis comparator includes NMOS transistor MC1, NMOS transistor MC2, PMOS transistor MC3, PMOS transistor MC4, PMOS transistor MC5, PMOS transistor MC6, PMOS transistor MC7, PMOS transistor MC8, NMOS transistor MC9, NMOS transistor MC10 and NMOS transistor MC11, wherein: The sources of the PMOS tubes MC3, MC4, MC5, MC6, MC7 and MC8 are connected to the power supply voltage VDD; The gate of the PMOS tube MC3 is connected to the gate of the PMOS tube MC5, and the gate of the PMOS tube MC3 is also connected to the drain of the PMOS tube MC3, the gate of the PMOS tube MC7, the drain of the PMOS tube MC6, and the drain of the NMOS tube MC1; The gate of the PMOS transistor MC4 is connected to the gate of the PMOS transistor MC6, and the gate of the PMOS transistor MC4 is also connected to the drain of the PMOS transistor MC4, the gate of the PMOS transistor MC8, the drain of the PMOS transistor MC5, and the drain of the NMOS transistor MC2; The source of the NMOS transistor MC1 is connected to the source of the NMOS transistor MC2 and to the drain of the NMOS transistor MC11. The gate of the NMOS transistor MC1 is connected to the feedback voltage V F , the gate of NMOS tube MC2 is connected to the reference voltage V REF ; The drain of the PMOS tube MC7 is connected to the drain of the NMOS tube MC9 and forms the output end of the hysteresis comparator, the gate of the NMOS tube MC9 is connected to the gate of the NMOS tube MC10, the gate of the NMOS tube MC10 is connected to the drain of the NMOS tube MC10 and the drain of the PMOS tube MC8, and the source of the NMOS tube MC9, the source of the NMOS tube MC10 and the source of the NMOS tube MC11 are all grounded.

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