Harmonic attenuation system and uninterruptible power supply comprising same

Abstract

The invention provides a harmonic attenuation control system for controlling an inverter, which comprises a phase-locked loop controller, a voltage and loop controller, a repetitive controller, a current loop controller and a harmonic acquisition module, and is characterized in that the harmonic acquisition module detects a harmonic value of load current from a load side; when the power grid and the load are directly connected at the bypass, the load current is equal to the sum of the output of the inverter and the power grid current; the control system generates an inversion current reference value according to a voltage and a first current value and a harmonic value output by a loop controller, and a phase-locked loop controller calculates a real-time frequency value according to the voltage of a power grid. The repetitive controller calculates and obtains an output value of the repetitive controller according to the inverter current reference value, the inverter output current serving as the auxiliary feedback and a real-time frequency value output by the phase-locked loop controller, and the current loop controller outputs a first duty ratio according to the output value of the repetitive controller; the control system defines the inverter output current according to the first duty cycle such that grid harmonic pollution is reduced, thus having higher power quality.

Description

Technical Field

[0001] The invention belongs to the field of power quality management, and in particular relates to a harmonic attenuation system and an uninterruptible power supply comprising the same. Background Art

[0002] A power conversion device or an uninterruptible power supply (UPS) including the power conversion device is a power supply device widely used in the industrial field, which is mainly composed of a rectifier, an inverter, an AC solid-state switch, etc. For an uninterruptible power supply, when the mains voltage is normal, the uninterruptible power supply is in online mode, and the mains supplies power to the load; when the mains voltage is abnormal or there is a power outage, the uninterruptible power supply is in battery mode, and the inverter is controlled to work to convert the DC power provided by the rechargeable battery pack into AC power and supply power to the load.

[0003] In existing uninterruptible power supplies or power conversion devices, the output waveform quality of the inverter may deteriorate or even cause system instability due to the influence of possible nonlinear factors on the load side, such as distortion of voltage and current waveforms on the grid side.

[0004] Figure 1 A simplified schematic block diagram of an uninterruptible power supply is shown. The uninterruptible power supply 10 includes a rectifier 101, an inverter 103 and a bypass module 102. In the normal mode of the uninterruptible power supply 10, the AC voltage input from the mains 100 is preferentially output to the load 105 through the rectifier 101 and the inverter 103. Figure 1 The bypass module 102 (shown as an SCR solid-state switch) in the figure is disconnected and does not work. However, in another "high-efficiency mode" with higher requirements for economy and efficiency, the rectifier 101 is disconnected ( Figure 1 The dotted line on the right side of the rectifier 101 indicates disconnection), and the AC voltage input from the mains 100 is bypassed and output to the load 105 through the SCR solid-state switch 102. In the high-efficiency mode, the inverter can still perform high-frequency switching through the pulse width modulation instruction, thereby generating a corresponding modulation waveform according to the waveform distortion on the load side and superimposing it on the bypass input to the load side, ultimately making the grid-side voltage waveform approach a perfect or ideal waveform to reduce or avoid harmonic pollution to the grid.

[0005] However, the existing control methods for this waveform distortion have slow response speed, poor stability and narrow adaptability. Summary of the invention

[0006] In order to solve the above technical problems, a first aspect of the present invention provides a harmonic attenuation control system for controlling an inverter connected between a DC bus and a load, wherein the inverter has an inverter topology composed of transistors, and the harmonic attenuation control system comprises:

[0007] A phase-locked loop controller, a voltage and loop controller, a repetitive controller, a current loop controller and a harmonic acquisition module, wherein the harmonic acquisition module detects the harmonic value of the load current from the load side;

[0008] Wherein, when the grid and the load are directly connected in bypass mode, the load current is equal to the sum of the inverter output current and the grid current; and

[0009] The harmonic attenuation control system is configured to generate an inverter current reference value according to the voltage and the first current value output by the loop controller and the harmonic value, the phase-locked loop controller calculates a real-time frequency value according to the voltage of the power grid, the repetitive controller calculates a repetitive controller output value according to the inverter current reference value, the inverter output current as a secondary feedback and the real-time frequency value output by the phase-locked loop controller, and the current loop controller outputs a first duty cycle according to the repetitive controller output value; and

[0010] The harmonic attenuation control system controls the transistors of the inverter according to the first duty cycle to limit the inverter output current so that harmonics of the grid current in the bypass mode are reduced.

[0011] Preferably, the harmonic attenuation control system further includes a voltage difference loop controller,

[0012] The voltage and loop controller outputs a second current value according to the bus voltage reference value and the bus voltage as negative feedback;

[0013] The harmonic attenuation control system is configured as follows:

[0014] The α / β axis current reference value is obtained according to the second current value and the weighted value of the AC voltage and the standard sinusoidal voltage.

[0015] The voltage difference loop controller obtains a γ-axis current reference value according to the voltage difference loop reference value of the positive and negative sides of the bus and the voltage amplitude difference of the positive and negative sides of the bus as negative feedback, and

[0016] An inverter current reference value is generated according to the α / β axis current reference value, the γ axis current reference value and the harmonic value.

[0017] Preferably, the phase-locked loop controller of the harmonic attenuation control system is a double decoupled synchronous reference frame phase-locked loop (DDSRF) controller.

[0018] Preferably, the dual decoupled synchronous reference frame phase-locked loop controller of the harmonic attenuation control system is configured to obtain voltage values ​​in the dqo positive sequence rotating frame and the dqo negative sequence rotating frame. and The inverter voltage sinusoidal amplitude and the forward gain coefficient of the phase-locked loop controller are calculated based on the obtained values, and the forward gain coefficient of the phase-locked loop controller is used to calculate the real-time frequency value.

[0019] Preferably, the repetitive controller of the harmonic attenuation control system is described by the following mathematical model:

[0020]

[0021]

[0022] N is the carrier ratio, Q(z) is the gain of the output of the discrete domain positive feedback transfer function, S(z) is the discrete domain filter transfer function, Z -N is the delay link of N beats, T s is the control period of the inverter, f inv is the real-time frequency value.

[0023] Preferably, the discrete domain filter transfer function S(z) of the harmonic attenuation control system is a simulated Bessel function, which is described by the following mathematical model:

[0024]

[0025] where b 0 、b 1 、b 2 is the polynomial coefficient of the zero part of the filter, a 1 、a 2 are the polynomial coefficients of the pole part of the filter.

[0026] Preferably, the harmonic attenuation control system further comprises a feedforward transfer function module, the feedforward transfer function module being used to output a feedforward duty cycle of the grid voltage according to the grid voltage, and

[0027] The harmonic attenuation control system generates a second duty cycle according to the sum of the first duty cycle and the feedforward duty cycle, and the second duty cycle is used to control the transistor of the inverter to limit the inverter output current instead of the first duty cycle, so that the harmonics of the grid current in the bypass mode are reduced.

[0028] Preferably, the current loop controller of the harmonic attenuation control system adopts a double-zero double-pole type current loop controller, and the transfer function of the double-zero double-pole type current loop controller can be described by the following mathematical model in the continuous domain:

[0029]

[0030] Where K fw_i is the current loop feedforward gain, τ a, τ b a, b, τ are the zero time constants of the current controller c is the current controller pole time constant c.

[0031] A second aspect of the present invention provides an inverter connected between a DC bus and a load, wherein the inverter is a three-phase inverter having the harmonic attenuation control system according to the first aspect of the present invention.

[0032] A third aspect of the present invention provides an uninterruptible power supply having the three-phase inverter as described in the second aspect of the present invention, wherein the uninterruptible power supply directly supplies power from the grid to the load in the bypass mode.

[0033] The harmonic attenuation control system of the present invention can reduce the harmonic pollution of the power grid, and at the same time has faster response speed, higher stability and wider adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0035] Figure 1 A simplified schematic block diagram of an uninterruptible power supply in the prior art is shown;

[0036] Figure 2 A brief schematic diagram of an uninterruptible power supply according to a preferred embodiment of the present invention is shown;

[0037] Figure 3 The preferred embodiment is shown for controlling Figure 2 The four transistors of each phase I-type inverter structure of the uninterruptible power supply 2 shown perform a high-frequency pulse width modulation harmonic attenuation control system 3;

[0038] Figure 4 A partial schematic diagram of a harmonic attenuation control system according to another preferred embodiment of the present invention is shown;

[0039] Figure 5 A partial schematic diagram of a harmonic attenuation control system according to another preferred embodiment of the present invention is shown;

[0040] Figure 6 A partial schematic diagram of a harmonic attenuation control system according to another preferred embodiment of the present invention is shown;

[0041] Figure 7 and Figure 8 The open-loop Bode diagram corresponding to the simulation result of the harmonic control system according to the present embodiment is given;

[0042] Fig. 9 and Fig.10The simulation results of the phase-locked loop controller are given;

[0043] Fig.11 It is the simulation result in the current loop controller;

[0044] Fig.12 and Fig.13 The Fourier analysis comparison of the harmonic components in the bypass current before and after attenuation is given;

[0045] Fig.14 The display data of the actual circuit waveform in the oscilloscope when the harmonic attenuation control system is not working under the full load state of nonlinear load (pf=0.9) is shown;

[0046] Fig.15 The display data of the actual circuit waveform of the harmonic attenuation control system in the oscilloscope from the time when the nonlinear load is reduced from 100% to 50% is shown;

[0047] Fig.16 The actual circuit waveform display data in the oscilloscope when the harmonic attenuation control system is working under the full load state of nonlinear load (pf=0.9) is given;

[0048] Fig.17 and Fig.18 The measurement results of total harmonics and harmonics of each order before and after the operation of the harmonic attenuation control system in the actual experiment are given. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings.

[0050] According to a preferred embodiment of the present invention, an uninterruptible power supply and a harmonic attenuation control system for controlling the same are described.

[0051] Figure 2 FIG. 2 shows a simplified schematic diagram of an uninterruptible power supply according to the preferred embodiment. Figure 1 The inverter 103 shown, Figure 2 The inverter 203 of the uninterruptible power supply 2 and its more detailed arrangement with the positive and negative busbars, the mains input and the load are shown. For the convenience of highlighting the description, other parts of the uninterruptible power supply 2 are shown in FIG. Figure 2 is omitted.

[0052] Figure 2 The inverter 203 in the power supply is configured as a three-phase three-level I-type inverter topology, and the uninterruptible power supply is configured to be in the high-efficiency mode, so that the mains voltage is directly connected to the load through the bypass. Figure 2A three-phase inverter topology is shown, but in other embodiments, a single-phase or multi-phase inverter circuit can still apply the harmonic control method described in the present invention.

[0053] Figure 2 The load current in is equal to the sum of the bypass current and the inverter current.

[0054] Figure 3 The preferred embodiment is shown for controlling Figure 2 The four transistors of the I-type inverter structure of each phase of the uninterruptible power supply 2 shown in the figure implement a high-frequency pulse width modulated harmonic attenuation control system 3. The harmonic attenuation control system is used to reduce or avoid harmonic pollution input to the power grid.

[0055] like Figure 3 As shown, the harmonic attenuation control system 3 includes a subtractor 301, a phase-locked loop controller 302, a DC bus voltage and loop controller 303, a multiplier 304, an adder 305, a subtractor 306, a repetitive control module 307, and a harmonic generation module 309; Figure 3 The inverter hardware model 308 preset for simulating the real inverter 203 is also shown. In the real circuit arrangement, the inverter hardware model 308 is Figure 2 The inverter 203 of the uninterruptible power supply 20 is shown. The harmonic generation module 309 is used to obtain harmonics of various orders in the load current.

[0056] Figure 3 The phase-locked loop controller 302 is shown separately from the circuit below. The external output parameter of the harmonic attenuation control system 3 is the abc three-phase inverter output voltage V abc and the DC bus voltage reference value V bus_rf (or V bus_ref ), voltage V abc is output to the phase-locked loop controller 302, and the phase-locked loop controller 302 outputs the inverter voltage phase θ according to the phase inv and inverter voltage frequency f inv , where the inverter voltage phase θ inv Used to calculate the sine reference table sin(ωt), inverter voltage frequency f inv Output to the repetition control module 307.

[0057] exist Figure 3 In the control scheme shown below, the subtractor 301 is used to convert the DC bus voltage reference value V bus_rf With the DC bus voltage V bus (V busThe calculation result of the subtractor 301 is processed by the DC bus voltage and loop controller (referred to as the voltage and loop controller) 303 as a first current value and output to the multiplier 304. The multiplier 304 receives the first current value and the sine reference table sin(ωt) and multiplies them to obtain the baseband current reference value. The adder 305 accumulates the baseband current reference value and the k-order current harmonic output by the harmonic generation module 309 to obtain the inverter current reference value i ref ; Among them, the sine reference table sin(ωt)=f(V abc ,θ inv ), f is based on V abc Inverter voltage and θ inv Function of inverter voltage phase.

[0058] The subtractor 306 converts the inverter current reference value i ref With the inductor current i L Subtract (i L As negative feedback), and the result is input to the repetitive control module 307; wherein the repetitive control module 307 includes a current repetitive controller D RP (s) and current loop controller D i (s), the repetitive control module 307 calculates and outputs the duty cycle d, which is input into the inverter hardware model 308 (shown in the dotted box in the figure), and the inverter hardware model 308 obtains the modulated bus voltage V through pulse width modulation. bus and the inductor current i L (i L Right now Figure 2 The inverter current I inv ). The inverter hardware model 308 is a hardware modeling of the inverter 203, including the state equation and output equation of the inverter. The harmonic attenuation control system 3 of this embodiment takes into account that after the uninterruptible power supply 20 is configured in the high-efficiency mode, it is likely that the base frequency position will shift relative to the normal state due to the fluctuation of the power frequency signal of the power grid, thereby causing the fixed modulation mode predetermined by the controller to be inaccurate. Therefore, the system is configured to obtain the inverter voltage frequency f in real time through the phase-locked loop controller 302. inv And output to the repetitive control module 307, thereby improving the accuracy of the dynamic response of the repetitive control module 307, so that it has a wide grid frequency matching range, can better adapt to grid systems under various fluctuation levels, and ensure the reliability of the uninterruptible power supply under various complex working conditions.

[0059] Figure 4 A partial schematic diagram of a harmonic attenuation control system according to another preferred embodiment of the present invention is shown. Figure 4Only the arrangement details of the phase-locked loop controller 40 of the harmonic attenuation control system 4 are shown, and the remaining modules of the harmonic attenuation control system 4 described in this embodiment are the same as those of the harmonic attenuation control system 4. Figure 3 The harmonic attenuation control system 3 shown is similar and therefore not shown again.

[0060] like Figure 4 As shown, the phase-locked loop control system 40 is configured to have a dual decoupled synchronous reference frame phase-locked loop (DDSRF) topology. The phase-locked loop controller 40 includes a subtractor 401, an inverter voltage positive sequence frame conversion module 402, an inverter voltage positive sequence frame inverse conversion module 403, a subtractor 404, an inverter voltage negative sequence frame conversion module 405, an inverter voltage negative sequence frame inverse conversion module 406, an inverter voltage sinusoidal amplitude calculation module 407, a phase-locked loop controller forward gain coefficient module 408, a phase-locked loop 409, an adder 410, an integrator transfer function module 411, a frequency acquisition function module 412, and an inverse calculation unit 413. The above modules 411-413 are collectively referred to as the physical part 414 of the algorithm.

[0061] Subtractor 401 receives the inverter abc phase voltage V abc And the voltage value in the abc negative sequence coordinate system as negative feedback Subtract the two and output them.

[0062] The inverter voltage positive sequence coordinate system conversion module 402 receives the output of the subtractor 401 and the inverter voltage negative sequence phase Therefore, the inverter voltage positive sequence coordinate system conversion module 402 converts V abc The voltage value converted from the abc positive sequence coordinate system to the dqo positive sequence rotating coordinate system in The inverter voltage positive sequence coordinate system inverse conversion module 403 receives the inverter voltage positive sequence phase and Will The voltage value converted from the dqo positive sequence rotating coordinate system to the abc positive sequence coordinate system

[0063] Subtractor 404 receives the inverted abc phase voltage V abc And the voltage value in the abc negative sequence coordinate system as negative feedback The inverter voltage negative sequence coordinate system conversion module 405 receives the output of the subtractor 404 and the inverter voltage positive sequence phase Therefore, the inverter voltage negative sequence coordinate system conversion module 405 converts V abc Voltage value from the abc negative sequence coordinate system to the dqo negative sequence rotating coordinate system in The inverter voltage negative sequence coordinate system inverse conversion module 406 receives the inverter voltage negative sequence phase and Will The voltage value converted from the dqo negative sequence rotating coordinate system to the abc negative sequence coordinate system Figure 4 The thick lines marked in the figure indicate that the variables in the three phases are transformed together.

[0064] The inverter voltage sinusoidal amplitude calculation module 407 receives the voltage value in the dqo positive and negative sequence rotating coordinate system and Calculate the inverter voltage sinusoidal amplitude V amp The obtained forward gain coefficient K of the phase-locked loop controller pll Input to the phase-locked loop controller forward gain coefficient module 408; the calculation formula is as follows:

[0065]

[0066] K pll =V amp

[0067] The inverter voltage positive sequence coordinate system conversion module 402 outputs The voltage positive sequence q-axis value of the inverter positive sequence rotating coordinate system After being processed by the forward gain coefficient module 408 of the phase-locked loop controller, it is output to the phase-locked loop 409, where it is processed and outputs the angular frequency value ω mo Angular frequency value ω mo The feedforward angular frequency value ω set by the phase-locked loop used to indicate the distance between the actual inverter angular frequency and the ideal grid frequency * The deviation, ω * With ω mo After addition by adder 410, the updated angular frequency value ω of the inverter voltage is obtained. inv Output to the physical part 414 of the algorithm.

[0068] The dotted box portion represents the physical part 414 of the algorithm, and the angular frequency value ω of the inverter voltage output from the adder 410 is inv is input to the integrator transfer function module 411 to obtain the inverter voltage positive sequence phase in is the differential operator; and the angular frequency value ω inv It is also input to the frequency acquisition function module 412 to calculate the angular frequency value ω inv Divide by 2π to obtain the inverter voltage frequency f inv The inverter voltage positive sequence phase obtained by the integrator transfer function module 411 The reverse phase of the inverter voltage is obtained by the reverse phase calculation unit 413.

[0069] The physical part 414 of the algorithm can be described by the following mathematical model:

[0070]

[0071] θ inv (s) = θ grid (s)+Δθ rf (s)G pll_cl (s)

[0072]

[0073]

[0074] Among them, D pll (s) have:

[0075]

[0076] is the phase-locked loop controller model;

[0077] G pll (s) is the phase-locked loop controlled object transfer function, G pll_ol (s) is the transfer function of the phase-locked loop open-loop system, G pll_cl (s) is the phase-locked loop closed-loop system transfer function, θ inv (s) is the inverter voltage phase transfer function, θ grid (s) is the grid voltage phase transfer function, Δθ rf (s) is the reference value transfer function of the phase difference between the inverter and the grid, Δθ(s) is the transfer function of the phase difference between the inverter and the grid, ω inv is the inverter voltage angular frequency, is the derivative of the inverter voltage phase, T i s is the control period of the inverter, f s is the control frequency of the inverter.

[0078] According to the dual-decoupled synchronous reference coordinate system phase-locked loop controller in the harmonic attenuation control system described in this embodiment, the positive and negative amplitudes are normalized to a unit gain, and the phase-locked loop control loop gain is compatible with a wide range of voltage power grids and phase-unbalanced power grids. The dynamic response to power grid frequency fluctuations is faster, and the consistency of the crossover frequency and gain margin with the rated voltage is effectively maintained, thereby ensuring the high accuracy of the power factor compensation of the harmonic attenuation control system.

[0079] Figure 5 FIG. 2 is a partial schematic diagram of a harmonic attenuation control system according to another preferred embodiment of the present invention. Figure 5The inverter voltage frequency f that provides real-time updates to the repetitive control module is omitted. inv (exist Figure 5 The output voltage frequency f is shown in o , both correspond to the same physical quantity) of a phase-locked loop controller.

[0080] like Figure 5 The harmonic attenuation control system 5 shown includes: a subtractor 501, a DC bus voltage and loop controller 502, a multiplier 503, a subtractor 504, a DC bus voltage difference loop controller 505, an adder 506, a subtractor 507, a repetitive controller 508, a current loop controller 509, a feedforward transfer function module 510 of the grid voltage, and an adder 511.

[0081] Subtractor 501 converts the input DC bus voltage reference value V bus_rf and the positive and negative bus voltages V across the inverter bus Subtract and output the result to the DC bus voltage and loop controller 502, and output the second current value to the multiplier 503 after processing. The multiplier 503 also receives the weighted value v of the AC voltage input by the phase-locked loop controller and the standard sinusoidal voltage ac (t):v sin , and multiply it with the second current value and output it as the voltage and loop output α / β axis current reference value i mo_αβ ; Subtractor 504 takes the voltage difference between the positive and negative sides of the input DC bus as the reference value V diff_ref The voltage amplitude difference v between the positive and negative sides of the DC bus connected to the inverter bus_diff The result is subtracted and output to the DC bus voltage difference loop controller 505, which is processed and output as the γ-axis current reference value i of the voltage difference loop output. mo_γ .i mo_αβ and i mo_γ Combined as the fundamental frequency current reference value i mo The adder 506 also receives the accumulated value of all n-order harmonics output by the harmonic generation module, adds it to the fundamental frequency current and outputs the inverter current reference value i ref , the calculation formula is as follows:

[0082] i ref =i mo +i o

[0083]

[0084] where i k_th Represents the kth harmonic of the current.

[0085] Subtractor 507 converts the inverter current reference value i ref With the inductor current i LSubtract the subtraction, and input the result to the repetitive control module 508, which also receives the real-time updated inverter voltage frequency f provided by the phase-locked loop controller. o The calculation result is input to the current loop controller 509, and the current loop controller 509 outputs the current loop duty cycle d accordingly. mo The grid voltage feedforward transfer function module 510 outputs a grid voltage feedforward duty ratio d according to the input grid AC voltage. ff To adder 511, adder 511 converts the current loop duty cycle d mo and the feedforward duty cycle d ff The total duty cycle is added and output to the inverter hardware model 512. The inverter hardware model 512 can be understood as the controlled object of the harmonic attenuation system. It is a mathematical model preset in the simulation to simplify the calculation and is used to simulate the inductor current i corresponding to the output of the corresponding controlled real inverter. L , bus voltage V bus (the voltage difference between the positive and negative sides of the bus) and the difference in voltage amplitude between the positive and negative sides of the bus v bus_diff , when the device of this embodiment is applied to control Figure 2 In the case of the uninterruptible power supply shown, the output value of the above-mentioned inverter hardware model 512 is usually obtained by a voltage or current sensor arranged in the uninterruptible power supply, which is well known to ordinary technicians in this field and will not be repeated here.

[0086] Figure 6 FIG. 2 is a partial schematic diagram of a harmonic attenuation control system according to another preferred embodiment of the present invention. Figure 6 FIG. 6 shows the arrangement details of the repetitive control module 60 of the harmonic attenuation control system 6 and its control of the current part of the inverter hardware model 61, and the remaining modules of the harmonic attenuation control system 6 described in this embodiment are similar to Figure 3 The harmonic attenuation control system 3 shown is similar and therefore not shown again.

[0087] As an example, Figure 6 The mathematical symbols shown in the figure are all marked as the representation method in the discrete domain (the independent variable in the bracket is replaced from the continuous variable s to the discrete variable z), but it can also be applied in the continuous domain. The repetitive control module 60 includes a repetitive controller 601, an adder 602, a current loop controller 603 and an adder 604. The repetitive controller 601 includes an adder 6010, an N-beat delay link 6011, a discrete domain filter transfer function 6012, and a discrete domain positive feedback transfer function 6013.

[0088] Among them, Figure 3 Similar to the example shown, the subtractor 600 converts the inverter current reference value i ref With the inductor current i LSubtract and obtain the difference i between the current reference value and the feedback value err The result is input to the adder 6010 of the repetition controller 601.

[0089] The adder 6010 receives the i output by the subtractor 600. err The value outputted by the discrete domain positive feedback transfer function 6013 as positive feedback is added and outputted to the N-beat delay link 6011, and after processing, it is outputted to the discrete domain filter transfer function 6012 and the discrete domain positive feedback transfer function 6013 respectively. The current value outputted by the discrete domain filter transfer function 6012 is used as the output current value i of the repetitive controller 601. RP .

[0090] Adder 602 repeats the current value i output by controller 601. RP The output of the subtractor 600 is err The current loop controller 603 outputs a current loop duty cycle value d mo .and Figure 5 Similar to the embodiment shown in FIG. 1 , there is also a feedforward duty cycle d of the grid voltage output by the feedforward transfer function module 510 according to the input grid AC voltage. ff , adder 604 adds the current loop duty cycle d mo and the feedforward duty cycle d ff The total duty cycle d is added and output as the control quantity to the controlled hardware, that is, the inverter hardware model 61 (this embodiment only describes the current harmonic attenuation process for the sake of simplicity. Figure 6 Only the current control part of the inverter hardware model is shown, and the voltage control part is omitted). The current control part of the inverter hardware model 61 controls the output inductor current i L .

[0091] The repetitive controller 601 can be described by the following mathematical model:

[0092]

[0093]

[0094] N is the carrier ratio, Q(z) is the gain of the discrete domain positive feedback transfer function output (as positive feedback), S(z) is the discrete domain filter transfer function, z -N is the delay link of N beats, T s is the control period of the inverter.

[0095] The filter is an analog Bessel filter, and the filter transfer function S(z) is described by the following function in the continuous domain (the same is true in the discrete domain described in this embodiment):

[0096]

[0097] where b 0 、b 1 、b 2 is the polynomial coefficient of the zero part of the filter, a 1 、a 2 are the polynomial coefficients of the pole part of the filter.

[0098] The characteristic of the analog Bessel filter is that the group delay is almost constant throughout the passband, so the waveform of the filtered signal in the passband can be preserved. The optimal bandwidth can be obtained by adjusting the above function S(s).

[0099] The current loop controller transfer function of the current loop controller 603 adopts a double-zero double-pole type transfer function, which can be described by the following mathematical model in the continuous domain (the same is true in the discrete domain described in this embodiment):

[0100]

[0101] K fw_i is the current loop feedforward gain, τ a , τ b a, b, τ are the zero time constants of the current controller c is the current controller pole time constant c.

[0102] The transfer function of the current control part of the inverter hardware model 61 can be described by the following mathematical model in the continuous domain (the same is true in the discrete domain described in this embodiment):

[0103]

[0104] Among them G i_ol (s) is the open-loop transfer function of the current loop, G i_cl (s) is the closed-loop transfer function of the current loop.

[0105] The current loop controller transfer function of this embodiment adopts a double-zero double-pole type transfer function to effectively reduce the phase lag caused by the repetitive controller. By cooperating with the analog Bessel filter, more efficient dynamic response, sufficient phase and amplitude margin and better cross-over frequency can be guaranteed.

[0106] The parameter values ​​in the formula given in this embodiment can be set specifically according to the actual uninterruptible power supply, and changes made thereto do not depart from the protection scope of this application.

[0107] The inventors have demonstrated the technical effects of the present invention through simulation and experimental test results.

[0108] Figure 7 and Figure 8 The open-loop Bode diagram corresponding to the simulation results of the harmonic control system according to this embodiment is given. Figure 7 The calculation results of the current loop are as follows: the loop crossing frequency is 1.3e+03Hz, the phase margin PM (Phase Margin) = 91.4deg, and the amplitude margin Gm (Gain Margin) = 14.3dB, in the UPS field. Figure 8 The calculation result of the voltage loop is 233Hz, the phase margin PM (Phase Margin) = 106deg, and the amplitude margin Gm (Gain Margin) = inf (infinity). In the UPS field, this current and voltage index shows that the harmonic attenuation performance is significantly improved, meeting the usual design requirements for stability and reliability in this field.

[0109] Fig. 9 and Fig.10 The simulation results of the phase-locked loop controller are given.

[0110] Fig. 9 From top to bottom, they are the input voltage signal of the phase-locked loop controller under the positive sequence three-phase inverter voltage, the inverter frequency setting value and the phase-locked value, the inverter voltage phase angle (from -π to π), and the voltage value V converted to the dqo rotating coordinate system. dqo .like Fig. 9 As shown, high-precision phase locking can be achieved in the phase-locked loop controller described in this application under positive-sequence three-phase inverter voltage.

[0111] Fig.10 From top to bottom, they are the input voltage signal of the phase-locked loop controller under the negative sequence three-phase inverter voltage, the inverter frequency setting value and the phase-locked value, the inverter voltage phase angle (from -π to π), and the voltage value V converted to the dqo rotating coordinate system. dqo .like Fig.10 As shown, the phase-locked loop controller described in this application can also achieve high-precision phase locking under negative-sequence three-phase inverter voltage.

[0112] Fig.11 It is the simulation result in the current loop controller. Fig.11 From top to bottom, they are the ideal input abc phase voltage signal of the three phases, the abc phase current signal output by the inverter, the abc phase current signal of the load, and the abc phase current signal of the bypass (i.e., the abc phase current signal of the input grid, which is equal to the load current signal minus the current signal output by the inverter). Fig.11 It can be seen that the harmonic attenuation effect is very significant, and the harmonic component in the waveform of the input power grid is greatly reduced.

[0113] Fig.12 and Fig.13The Fourier analysis comparison of the harmonic components in the bypass current before and after attenuation is given. Fig.12 and Fig.13 It can be seen that for the nonlinear RCD load, when the harmonic attenuation control system is not working, the load current harmonic value THD_Iload=220.9%; when the harmonic attenuation control system is working, the load current harmonic value THD_Iload=111.9%.

[0114] The inventor also verified the technical effect of the harmonic attenuation control system through computer experiments.

[0115] Figures 14 to 18 The oscilloscope display data in the actual test is given.

[0116] Fig.14 The figure shows the display data of the actual circuit waveform in the oscilloscope when the harmonic attenuation control system is not working under the full load state of nonlinear load (pf=0.9). Fig.14 Channels 1 to 4 of different colors in the oscilloscope are shown. Channel 1 corresponds to the yellow curve, indicating the bypass a-phase voltage; Channel 2 corresponds to the green curve, indicating the load a-phase current; Channel 3 corresponds to the purple curve, indicating the inverter a-phase current; and Channel 4 corresponds to the blue curve, indicating the bypass a-phase current. The clearer curve at the bottom is an enlargement of the portion of the upper curve intercepted in the white time window. Fig.14 Serious harmonic distortion occurs.

[0117] Fig.15 The figure shows the actual circuit waveform displayed in the oscilloscope when the nonlinear load is reduced from 100% to 50%. Fig.14 The clearer curve below is the enlarged portion of the upper curve intercepted in the purple time window. The mutation of each signal waveform in the purple time window corresponds to the time when the harmonic attenuation control system starts to work. The current waveform in the blue part can be seen, that is, the grid current tends to a perfect waveform after the harmonic attenuation control system starts to work.

[0118] Fig.16 The actual circuit waveform display data of the harmonic attenuation control system working under the full load state of nonlinear load (pf = 0.9) in the oscilloscope is given. In order to clearly show the harmonic suppression effect of the bypass current (grid current) when the harmonic attenuation control system is working, the upper time window is selected to be narrower, so that the shape of the blue curve (bypass current) after compensation below is clearer. Fig.16 It shows that the grid current after compensation by the harmonic attenuation control system approaches a perfect waveform and harmonic pollution is significantly suppressed.

[0119] Fig.17 and Fig.18 The measurement results of total harmonics and harmonics of each order before and after the operation of the harmonic attenuation control system in the actual experiment are given.

[0120] like Fig.17 As shown in the figure, before the harmonic attenuation control system works, as shown in the first line of the interface, the total load harmonic THD_Iload is approximately equal to 44.3%. The following data gives the proportion of the 3rd to 15th order harmonics.

[0121] like Fig.18 As shown in the first line of the interface, after the harmonic attenuation control system is working, the total bypass harmonic THD_Iload is about 12.3%. The following data shows the proportion of the 3rd to 15th order harmonics, compared with Fig.17 All of them have decreased to varying degrees.

[0122] Although the present invention has been described through preferred embodiments, the present invention is not limited to the embodiments described herein but includes various changes and modifications that may be made without departing from the scope of the present invention.

Claims

1. A harmonic attenuation control system for controlling an inverter connected between a DC bus and a load, wherein the inverter has an inverter topology composed of transistors, characterized in that: The harmonic attenuation control system comprises: A phase-locked loop controller, a voltage and loop controller, a repetitive controller, a current loop controller and a harmonic acquisition module, wherein the harmonic acquisition module detects the harmonic value of the load current from the load side; Wherein, when the grid and the load are directly connected in bypass mode, the load current is equal to the sum of the inverter output current and the grid current; and The harmonic attenuation control system is configured to generate an inverter current reference value according to the voltage and the first current value output by the loop controller and the harmonic value, the phase-locked loop controller calculates a real-time frequency value according to the voltage of the power grid, the repetitive controller calculates a repetitive controller output value according to the inverter current reference value, the inverter output current as a secondary feedback and the real-time frequency value output by the phase-locked loop controller, and the current loop controller outputs a first duty cycle according to the repetitive controller output value; and The harmonic attenuation control system controls the transistors of the inverter according to the first duty cycle to limit the inverter output current so that harmonics of the grid current in the bypass mode are reduced.

2. The harmonic attenuation control system according to claim 1, characterized in that: It also includes a voltage difference loop controller, The voltage and loop controller outputs a second current value according to the bus voltage reference value and the bus voltage as negative feedback; The harmonic attenuation control system is configured as follows: The α / β axis current reference value is obtained according to the second current value and the weighted value of the AC voltage and the standard sinusoidal voltage. The voltage difference loop controller obtains a γ-axis current reference value according to the voltage difference loop reference value of the positive and negative sides of the bus and the voltage amplitude difference of the positive and negative sides of the bus as negative feedback, and An inverter current reference value is generated according to the α / β axis current reference value, the γ axis current reference value and the harmonic value.

3. The harmonic attenuation control system according to claim 1, characterized in that: The phase-locked loop controller is a dual decoupled synchronous reference frame phase-locked loop (DDSRF) controller.

4. The harmonic attenuation control system according to claim 3, characterized in that: The dual decoupled synchronous reference frame phase-locked loop controller is configured to obtain voltage values ​​in the dqo positive sequence rotating frame and the dqo negative sequence rotating frame and The inverter voltage sinusoidal amplitude and the forward gain coefficient of the phase-locked loop controller are calculated based on the obtained values. The forward gain coefficient of the phase-locked loop controller is used to calculate the real-time frequency value.

5. The harmonic attenuation control system according to claim 1, characterized in that: The repetitive controller is described by the following mathematical model: N is the carrier ratio, Q(z) is the gain of the output of the discrete domain positive feedback transfer function, S(z) is the discrete domain filter transfer function, z -N is the delay link of N beats, T s is the control period of the inverter, f inv is the real-time frequency value.

6. The harmonic attenuation control system according to claim 5, characterized in that: The discrete domain filter transfer function S(z) is a simulated Bessel function, which is described by the following mathematical model: Among them, b0, b1, b2 are the polynomial coefficients of the zero part of the filter, and a1, a2 are the polynomial coefficients of the pole part of the filter.

7. The harmonic attenuation control system according to claim 1, characterized in that: It also includes a feedforward transfer function module, wherein the feedforward transfer function module is used to output a feedforward duty cycle of the grid voltage according to the grid voltage, and The harmonic attenuation control system generates a second duty cycle according to the sum of the first duty cycle and the feedforward duty cycle, and the second duty cycle is used to control the transistor of the inverter to limit the inverter output current instead of the first duty cycle, so that the harmonics of the grid current in the bypass mode are reduced.

8. The harmonic attenuation control system according to claim 1, characterized in that: The current loop controller adopts a double-zero double-pole type current loop controller, and the transfer function of the double-zero double-pole type current loop controller can be described by the following mathematical model in the continuous domain: Where K fw_i is the current loop feedforward gain, τ a , τ b a, b, τ are the zero time constants of the current controller c is the current controller pole time constant c.

9. An inverter connected between a DC bus and a load, characterized in that: The inverter is a three-phase inverter having the harmonic attenuation control system according to any one of claims 1 to 8.

10. An uninterruptible power supply, characterized in that: The uninterruptible power supply has the three-phase inverter as claimed in claim 9, wherein the uninterruptible power supply directly supplies power from the grid to the load in the bypass mode.

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