Controller for switching converter

Abstract

A controller for a switching converter. The switching converter is configured to receive an input voltage and generate an output voltage. The switching converter includes one or more power switches and one or more energy storage elements. The one or more energy storage elements include a first energy storage element. The controller is configured to control the switching converter when operating in a first control mode during a first state, and to control the switching converter when operating in a hysteretic control mode during a second state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 597,874, filed on November 10, 2023. The entire contents of U.S. Provisional Application No. 63 / 597,874 are incorporated herein by reference. field

[0004] The present disclosure relates to a controller for a switching converter. background

[0006] Figure 1 is a schematic diagram of a digital buck converter 100 having analog-to-digital converters (ADCs) 102, 104, 106 and a controller 108. Buck converter 100 includes switches 110, 112, an inductor 114, and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT. A buck converter is a type of DC / DC converter.

[0007] While the power stage and passive components (inductor 114 and capacitor 116) remain the same as for the analog buck converter, the ADC 102 converts the output voltage VOUT into a digital value. Note that the power switches 110, 112 are also the same for the analog / digital converter.

[0008] Optionally, the inductor current IL of the inductor 114 and the input voltage VIN may also be converted from analog to digital according to a digital control method.

[0009] The switching frequency (FSW) of the buck converter 100 is, for example, 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage.

[0010] The processing frequency (FS) of the digital controller 108 is, for example, about 100 MHz. FS is equal to 1 / TS, where TS is the processing period of the controller 108. Alternatively, FS may also be the sampling frequency of the ADC 102. Overview

[0012] It is desirable to provide an improved controller for a switching converter, such as a digital buck converter.

[0013] According to a first aspect of the present disclosure, a controller for a switching converter is provided, the switching converter being configured to receive an input voltage and generate an output voltage, and comprising one or more power switches and one or more energy storage elements, the one or more energy storage elements comprising a first energy storage element, the controller being configured to control the switching converter when operating in a first control mode during a first state, and to control the switching converter when operating in a hysteresis control mode during a second state.

[0014] Optionally, the controller is a digital controller.

[0015] Optionally, the switching converter is a buck converter, a boost converter, a buck-boost converter or a hybrid converter.

[0016] Optionally, the first energy storage element is an inductor.

[0017] Optionally, the one or more power switches include a first power switch and a second power switch.

[0018] Optionally, the first control mode is a linear control mode.

[0019] Optionally, the linear control mode is a current control mode.

[0020] Optionally, the controller is configured to receive a digitized output voltage signal, the digitized output voltage signal being a digital representation of the output voltage of the switching converter.

[0021] Optionally, the digitized output voltage signal is received from a first analog-to-digital converter configured to receive the output voltage and digitize the output voltage to generate a digitized output voltage signal.

[0022] Optionally, the controller comprises a first control circuit which is activated during the first state to provide the first control mode.

[0023] Optionally, the first control circuit is configured to generate a digital target current signal using the digitized output voltage signal.

[0024] Optionally, the first control circuit includes: a first voltage error generating circuit, which is configured to generate a digital error signal using a digitized output voltage signal and a digital voltage reference signal; and a digital target current signal generating circuit, which is configured to convert the digital error signal into a digital target current signal.

[0025] Optionally, the digital target current signal generating circuit includes a proportional-integral circuit or a proportional-integral-differential circuit.

[0026] Optionally, the first voltage error generating circuit is configured to generate a digital error signal by subtracting the digitized output voltage signal from a digital voltage reference signal.

[0027] Optionally, the first control circuit includes a first current error generating circuit configured to: receive a digital target current signal and receive a digitized current signal, the digitized current signal being a digital representation of a current flowing through the first energy storage element, and generate a digital current error signal.

[0028] Optionally, the digitized current signal is received from a digitized current generating circuit.

[0029] Optionally, the digitized current generating circuit includes a second analog-to-digital converter configured to sense the current flowing through the first energy storage element and digitize the sensed current to generate a digitized current signal.

[0030] Optionally, the digitized current generating circuit comprises a current synthesizer.

[0031] Optionally, the first control circuit includes a modulator configured to generate a first mode control signal using the digital current error signal, and the controller includes a logic and gate driver circuit configured to receive the first mode control signal during the first state and generate a gate drive signal for each of the one or more power switches using the first mode control signal.

[0032] Optionally, the controller comprises a hysteresis control circuit which is activated during the second state to provide a hysteresis control mode.

[0033] Optionally, the hysteresis control circuit is configured to generate an up signal for charging the first energy storage element during the second state when the digitized output voltage signal drops below a first threshold voltage, and to generate a down signal for discharging the first energy storage element during the second state when the digitized output voltage signal rises above a second threshold voltage.

[0034] Optionally, the controller includes logic and gate driver circuitry configured to receive the up signal and the down signal during the second state and use the up signal and the down signal to generate a gate drive signal for each of the one or more power switches.

[0035] Optionally, the controller is configured to switch from the first control mode to the hysteretic control mode in response to a load transient.

[0036] Optionally, the controller is configured to detect load transients.

[0037] Optionally, the controller is configured to receive a digitized output voltage signal, the digitized output voltage signal being a digital representation of the output voltage of the switching converter.

[0038] Optionally, the controller comprises a first control circuit which is activated during the first state to provide the first control mode.

[0039] Optionally, the first control circuit is configured to generate a digital target current signal using the digitized output voltage signal.

[0040] Optionally, the first control circuit includes a first current error generating circuit configured to: receive a digital target current signal and receive a digitized current signal, the digitized current signal being a digital representation of a current flowing through the first energy storage element, and generate a digital current error signal.

[0041] Optionally, the first control circuit includes a modulator configured to generate a first mode control signal using the digital current error signal, and the controller includes logic and gate driver circuitry configured to receive the first mode control signal during the first state and generate a gate drive signal for each of the one or more power switches using the first mode control signal.

[0042] Optionally, the controller comprises a hysteresis control circuit which is activated during the second state to provide a hysteresis control mode.

[0043] Optionally, the hysteresis control circuit is configured to generate an up signal for charging the first energy storage element during the second state when the digitized output voltage signal drops below a first threshold voltage, and to generate a down signal for discharging the first energy storage element during the second state when the digitized output voltage signal rises above a second threshold voltage.

[0044] Optionally, the logic and gate driver circuit is configured to receive the up signal and the down signal during the second state and to generate a gate drive signal for each of the one or more power switches using the up signal and the down signal.

[0045] Optionally, the controller includes one or more digital gates configured to receive a first mode control signal, an up signal, and a down signal, provide the first mode control signal to the logic and gate driver during a first state, and provide the up signal and the down signal to the logic and gate driver during a second state.

[0046] Optionally, the one or more digital gates include an AND gate and an OR gate, the AND gate including a first inverting input terminal for receiving a down signal and a first non-inverting input terminal for receiving a first mode control signal, the OR gate including a first input terminal for receiving an up signal, a second input terminal for receiving an output of the AND gate, and an output terminal for providing the first mode control signal to the logic and gate driver during the first state and for providing the up signal and the down signal to the logic and gate driver during the second state.

[0047] Optionally, the controller is configured to: sample the output voltage to obtain a first sampled voltage at a first time step and a second sampled voltage at a second time step, determine a sampled voltage difference by subtracting the second sampled voltage from the first sampled voltage, generate an up signal for charging the first energy storage element during the second state when the sampled voltage difference is less than a first voltage difference threshold, and generate a down signal for discharging the first energy storage element during the second state when the sampled voltage difference is greater than a second voltage difference threshold.

[0048] Optionally, a first sampled voltage is acquired during a first switching cycle of the switching converter, and a second sampled voltage is acquired during a second switching cycle of the switching converter.

[0049] Optionally, the second time step is a switching cycle of the switching converter after the first time step.

[0050] Optionally, the controller is configured to: periodically sample the output voltage to obtain n sampled voltages at n time steps, where n is an integer, repeatedly determine the nth sampled voltage difference by subtracting the (nm)th sampled voltage from the nth sampled voltage, where m is an integer, generate an up signal for charging the first energy storage element during the second state when the nth sampled voltage difference is less than a first voltage difference threshold, and generate a down signal for discharging the first energy storage element during the second state when the nth sampled voltage difference is greater than a second voltage difference threshold.

[0051] Optionally, the (nm)th sampling voltage is acquired during a first switching cycle of the switching converter, and the nth sampling voltage is acquired during a second cycle of the switching converter.

[0052] Optionally, the nth time step is a switching cycle of the switching converter after the (nm)th time step.

[0053] Optionally, m is equal to 8.

[0054] Optionally, the controller is configured to control the switching converter when operating in the intermediate control mode during the third state.

[0055] Optionally, the controller is configured to switch from the first control mode to the hysteretic control mode in response to a load transient.

[0056] Optionally, the controller is configured to switch to the intermediate control mode after the hysteresis control mode and before switching to the first control mode.

[0057] Optionally, the controller is configured to receive a digitized output voltage signal, the digitized output voltage signal being a digital representation of the output voltage of the switching converter.

[0058] Optionally, the controller comprises a first control circuit which is activated during the first state to provide the first control mode.

[0059] Optionally, the first control circuit is configured to generate a digital target current signal using the digitized output voltage signal.

[0060] Optionally, the first control circuit includes: a first voltage error generating circuit, which is configured to generate a digital error signal using a digitized output voltage signal and a digital voltage reference signal; and a digital target current signal generating circuit, which is configured to convert the digital error signal into a digital target current signal.

[0061] Optionally, the controller is configured to correct the digital target current signal during the intermediate control mode.

[0062] Optionally, the digital target current signal generating circuit includes a proportional-integral circuit or a proportional-integral-differential circuit.

[0063] Optionally, the first control circuit includes a first current error generating circuit configured to: receive a digital target current signal and receive a digitized current signal, the digitized current signal being a digital representation of a current flowing through the first energy storage element, and generate a digital current error signal.

[0064] Optionally, the proportional-integral circuit includes a first amplifier, a second amplifier, a first summing circuit, a second summing circuit and a register.

[0065] Optionally, the first amplifier and the second amplifier are configured to receive a digital error signal, the first amplifier includes an output terminal coupled to a first input terminal of a first summing circuit, the second amplifier includes an output terminal coupled to a first input terminal of a second summing circuit, the output terminal of the second summing circuit is coupled to a second input terminal of the first summing circuit and an input terminal of a register, and the register includes an output terminal coupled to a second input terminal of the second summing circuit.

[0066] Optionally, the controller is configured to update the register based on the digitized current signal, the gain of the first amplifier, the digitized output voltage signal and the digital voltage reference signal to correct the digital target current signal during the intermediate control mode.

[0067] Optionally, the digital target current signal generating circuit includes one or more registers.

[0068] Optionally, the controller is configured to update at least one of the one or more registers based on the digitized current signal to correct the digital target current signal during the intermediate control mode.

[0069] Optionally, the controller is configured to resynchronize a clock cycle of the switching converter to the carrier clock after switching from the intermediate control mode.

[0070] According to a second aspect of the present disclosure, a method for controlling a switching converter using a controller is provided, the switching converter being configured to receive an input voltage and generate an output voltage, and comprising one or more power switches and one or more energy storage elements, the one or more energy storage elements comprising a first energy storage element, the method comprising controlling the switching converter when operating in a first control mode during a first state, and controlling the switching converter when operating in a hysteresis control mode during a second state.

[0071] It is to be understood that the method of the second aspect may include the features set out in the first aspect, and may be combined with other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0074] Figure 1 is a schematic diagram of a digital buck converter;

[0075] Figure 2A is a schematic diagram of a buck converter in which the controller is implemented as a current mode linear controller;

[0076] Figure 2B is a schematic diagram of a buck converter in which the controller is implemented as an analog hysteretic "Bang-Bang" type controller;

[0077] Figure 3A is a schematic diagram of a controller of a switching converter according to a first embodiment of the present disclosure;

[0078] Figure 3B is a timing diagram illustrating the operation of a controller and a switching converter for a practical implementation of the present disclosure;

[0079] Figure 4A is a schematic diagram of a controller according to a second embodiment of the present disclosure;

[0080] Figure 4B is a schematic diagram of a controller according to a third embodiment of the present disclosure;

[0081] Figure 4C is a schematic diagram of a controller according to a fourth embodiment of the present disclosure;

[0082] Figure 5A is shown with Figure 4C timing diagrams of waveforms related to practical implementations of controllers and switching converters;

[0083] Figure 5B is shown with Figure 4C Another timing diagram of waveforms related to a practical implementation of a controller and a switching converter;

[0084] Figure 5C It is shown as Figure 5B Another timing diagram of the waveform presented in over a specific time period;

[0085] Figure 6 is a timing diagram related to the actual implementation of the controller in this embodiment;

[0086] Fig. 7A is a timing diagram related to the actual implementation of the controller in this embodiment;

[0087] Figure 7B is shown by Fig. 7A a flow chart of a process performed by a particular embodiment of the described controller;

[0088] Fig. 8A shows simulation results for a practical implementation of the controller;

[0089] Figure 8B Simulation results for a practical implementation of the controller are shown, illustrating random hysteresis events with clock slip recovery;

[0090] Figure 8C shows simulation results for a practical implementation of the controller;

[0091] Fig.8Dshows simulation results of a practical implementation of the controller compared to a system providing only linear control; and Fig. 9 is a schematic diagram of a controller according to a fifth embodiment of the present disclosure. Detailed Description

[0093] Figure 2A is a schematic diagram of a buck converter 100 in which the controller 108 is implemented as a current mode linear controller. The controller 108 is a digital controller.

[0094] Figure 2A The operation of the circuit is as follows:

[0095] The output voltage VOUT is digitized by ADC 102 to give a digitized output voltage signal DOUT. The digitized output voltage signal DOUT is compared with a digital reference voltage DREF corresponding to a target voltage of the output voltage VOUT. The two digital DOUT, DREF can be, for example, 8-bit buses, where the digital code [0;

[0096] 255] corresponds to the analog range [0.50V; 1.50V].

[0097] The digital error voltage signal DVERR is equal to DREF-DOUT, which is provided to the linear digital loop control circuit 200 to convert the digitized error voltage DVERR into a digital target current DITARGET=DP+DI, which is a digital value as a target to be set for the analog inductor current IL to restore the output voltage VOUT. The digital error voltage signal DVERR is provided by the error circuit 201.

[0098] The linear digital loop control circuit 200 can be implemented using proportional integral derivative. In this example, the control circuit 200 includes a P path and an I path, the P path includes an amplifier 202 with a gain P and providing an output DP, and the I path has an amplifier 204 with a gain I and providing an output DI. Optionally, a D path can be provided. The circuit 200 also includes summing circuits 206, 208 and a register 210.

[0099] The digital target current DITARGET may be encoded on more bits (eg 16 bits) and the following signal.

[0100] The digital target current DITARGET is compared to the digitized inductor current DIL by a difference circuit 212, and the difference DIERR enters a modulator 214, which adjusts the duty cycle MAG / DEMAG so that the analog inductor current IL on average matches its digital counterpart DITARGET. A logic and driver circuit 218 provides gate driver signals GP, GN to the transistor gates.

[0101] The digital current generating circuit 216 may be as follows: Figure 1 The ADC 104 shown in FIG. 1 may be a “synthesizer” so that it can digitally reproduce the inductor current IL behavior based on the input voltage VIN, the output voltage VOUT, the duty cycle, and possibly other parameters.

[0102] The digital modulator 214 can be a peak, valley or average modulator. The modulator 214 ensures that the analog current IL follows the digital target current DITARGET. This is why Figure 2A The control method provided by the controller 108 in is called "current mode" (the regulated control current DITARGET), and the modulator ensures that the average digital target current is equal to the average digital inductor current, which can be expressed as follows:

[0103] <ditarget> ＝ <dil>(1)

[0104] Variables enclosed in "<>" are used to represent the mean value of the variable. For example, <x>Represents the mean value of the variable x.

[0105] It will be appreciated that equation (1) relates to a modulator configured to match DITARGET to the average DIL. However, in other embodiments, the modulator may be a peak or valley modulator, as will be appreciated by those skilled in the art.

[0106] Constant frequency linear modulation such as current mode offers advantages and disadvantages, examples of which are provided below:

[0107] advantage:

[0108] Constant frequency of EMI (electromagnetic interference)

[0109] Easy to design and calculate stability parameters

[0110] shortcoming:

[0111] The constant frequency makes it inherently slow: if VOUT drops, action can only be taken at the next clock edge inside the modulator.

[0112] In PID, the P path gain must be limited to 100A / V (the I path is slower and is only used for fine tuning). Here is why: For a COUT of about 9uF, the 0dB gain crossover frequency is Fu = Gm / (2PI.COUT), with these values, Fu is about 2MHz. For a DCDC converter switching at 4MHz, it corresponds to Nyquist

[0113] Frequency Fnyquist. If Fu>Fnyquist, or are close to being equal, unpredictable instability may occur. Therefore, if P=100, a 6A load means that VOUT will spontaneously drop by 60mV. For practical applications, a voltage drop of about 40mV is expected.

[0114] Figure 2B is a schematic diagram of a buck converter 100 in which the controller 108 is implemented as an analog hysteretic "Bang-Bang" type controller. Digital hysteretic controllers are also known. Hysteretic regulators (also called "ripple" regulators) are used in conjunction with linear control modes such as Figure 2A Provides superior performance when compared to the previous mode.

[0115] The controller 108 includes comparators CS, CR, a logic circuit RSLATCH, and voltage sources 220 , 222 .

[0116] When VOUT drops below VREF-5mV, comparator CS sets RSLATCH to turn on HS and turn off LS: we recharge VOUT. When VOUT exceeds VREF+5mV, comparator CR resets RSLATCH, turns off HS and turns on LS: we stop recharging VOUT, and VOUT drops due to the load. Thus, the hysteretic controller sets the ripple to + / -5mV (hence the name "ripple regulator").

[0117] Hysteretic controllers have the following advantages / disadvantages:

[0118] advantage:

[0119] It reacts spontaneously and therefore performs better than linear control mode regulators.

[0120] shortcoming:

[0121] The frequency is variable: not only in steady state (constant load, VIN and VOUT), but also when the load changes. The method of adjusting the frequency is very common, using FLL / PLL to adjust the above + / -5mV to different values,

[0122] But they settle slowly, so frequency jumps always occur when there are transient load / line conditions.

[0123] Figure 3A is a schematic diagram of a controller 300 for a switching converter 302 according to a first embodiment of the present disclosure.

[0124] During operation, switching converter 302 receives an input voltage VIN and generates an output voltage VOUT. Switching converter 302 includes one or more power switches 304 and one or more energy storage elements including a first energy storage element 306.

[0125] Controller 300 is configured to control switching converter 302 when operating in a first control mode during a first state, and to control the switching converter when operating in a hysteretic control mode during a second state.

[0126] The controller 300 may be configured to switch from the first control mode to the hysteretic control mode in response to a load transient.The controller 300 may be configured to detect a load transient.

[0127] The controller 300 may be a digital controller. The switching converter 302 may be, for example, a buck converter, a boost converter, a buck-boost converter, or a hybrid converter. It should be understood that the switching converter 302 may be a single-phase converter, such as a buck converter, a boost converter, or a buck-boost converter; or may be a multi-phase converter, such as a hybrid converter.

[0128] It will be appreciated that the hybrid converter may have two or more energy storage elements.The two or more energy storage elements of the hybrid converter may include inductors and / or capacitors.

[0129] The first energy storage element 306 may be an inductor 308. The first control mode is a linear control mode, such as a current control mode. "Linear" describes that the controller is mathematically describable and its behavior is predictable.

[0130] Controller 300 enables switching of control schemes during operation of switching converter 302 , thereby providing the benefits of a hysteretic control mode when desired.

[0131] Specifically, it is desirable to combine the benefits of a hysteretic control mode, such as fast reaction speed, with the benefits of a linear control mode, such as good EMI performance and constant frequency. For example, it is desirable that there be an immediate reaction of the controller 300 in response to a transient load, and this is provided by the controller 300, where the immediate reaction is provided by switching to a hysteretic control mode, where the switching converter 302 returns to the linear mode in a seamless manner. It is also desirable that occasional hysteresis events have little effect on the overall operation of the switching converter 302.

[0132] Figure 3B is a timing diagram showing the operation of controller 300 and switching converter 302 for a practical implementation of the present disclosure. Load current ILOAD (trace 310), inductor current IL (trace 312), control mode (labeled 314) and charging pulses (trace 316) are shown.

[0133] The load current ILOAD is the current drawn by the external circuit: it is the current source that pulls the output voltage VOUT down. The switching converter 302 will adjust the current IL to match the load current ILOAD on average, thereby regulating the output voltage VOUT. Load transients describe sudden changes in load current, which occur at times t1, t2.

[0134] Inductor current IL is the current flowing through inductor 308 of switching converter 302 during operation.

[0135] Control Mode shows the current control mode at different stages of operation. "LINEAR" indicates that the switching converter 302 operates in the linear control mode. "HYSTUP" and "HYSTDW" indicate hysteresis control modes for rising load transients and falling load transients, respectively. Time period P1 shows an example of a "first state" as described above, and time period P2 shows an example of a "second state" as described above. It should be understood that when a load transient occurs, the cycle of the first state and the second state can be repeated during operation.

[0136] The charging pulses illustrate control of switch 304, where the upward arrow indicates when switch 304 is configured to allow charging of inductor 308. It can be observed that during linear mode, charging and discharging of inductor 308 occurs at a constant frequency FSW, while during hysteretic mode, the frequency undergoes variations.

[0137] In summary, the mode switches from linear (PID regulation in control) to an occasional state called HYSTUP / HYSTDW to allow the load current IL to ramp up continuously (which means the system no longer operates at a constant frequency). When it is no longer necessary to ramp up the inductor current IL continuously, regulation returns to linear mode.

[0138] Figure 4A is a schematic diagram of a controller 300 according to a second embodiment of the present disclosure. In this embodiment, the controller 300 is configured to receive a digitized output voltage signal DOUT, which is a digital representation of the output voltage VOUT of the switching converter 302. The digitized output voltage signal DOUT may be received from an analog-to-digital converter (ADC) 400, which is configured to receive the output voltage VOUT and then digitize the output voltage VOUT to generate a digitized output voltage signal DOUT.

[0139] Figure 4B is a schematic diagram of a controller 300 according to a third embodiment of the present disclosure, illustrating a specific implementation of the controller 300 .

[0140] In this embodiment, the controller 300 includes a first control circuit 402, which is activated during a first state during operation to provide a first control mode. As previously described, the first control mode can be a linear control mode, such as a current control mode. The controller 300 also includes a hysteresis control circuit 404, which is activated during a second state during operation to provide hysteresis control.

[0141] A control circuit being "activated" simply means that a particular activated control circuit is managing the control of switching converter 302. For example, "activated" may refer to an activated control circuit transitioning from an off-state in which it does not receive power to an on-state in which it is powered. Alternatively, "activated" may refer to an activated control circuit transitioning from a standby mode (in which it does not manage the control of switching converter 302) to an operating mode (in which it manages the control of switching converter 302), wherein the control circuit receives power regardless of whether it is operating in the standby mode or the operating mode.

[0142] Figure 4C is a schematic diagram of a controller 300 according to a fourth embodiment of the present disclosure, showing a specific implementation of control circuits 402, 404. It should be understood that the first control circuit 402 is shown as providing current mode control. However, in other embodiments, according to the understanding of those skilled in the art, an alternative control scheme may be provided by the first control circuit 402. In this example, the switching converter 302 is a buck converter. However, in other embodiments, according to the understanding of those skilled in the art, the switching converter 302 may be a different type of switching converter, such as a boost converter, a buck-boost converter, or a hybrid converter.

[0143] Buck converter 302 includes power switches 406 , 408 , an inductor 410 (as a first energy storage element), and a capacitor 412 .

[0144] The first control circuit 402 is configured to generate a digital target current signal DITARGET using the digitized output voltage signal DOUT. The first control circuit 402 includes a voltage error generating circuit 414 configured to generate a digital error signal DVERR using the digitized output voltage signal DOUT and a digital voltage reference signal DREF. The first control circuit 402 also includes a digital target current signal generating circuit 416 configured to convert the digital error signal DVERR into a digital target current signal DITARGET.

[0145] The digital target current signal generating circuit 416 may include a proportional-integral (PI) circuit or a proportional-integral-differential (PID) circuit. In the present embodiment, the circuit 416 includes a PI circuit. In the present embodiment, the PI circuit 416 includes: amplifiers 418, 420; summing circuits 422, 424 and a register 426. The register 426 may alternatively be referred to as a memory element. It should be understood that, according to the understanding of those skilled in the art, a PI circuit without a differential component may still be referred to as a "PID".

[0146] The voltage error generation circuit 414 may be configured to generate a digital error signal DVERR by subtracting the digitized output voltage signal DOUT from the digital voltage reference signal DREF.

[0147] The first control circuit 402 may include a current error generating circuit 428 configured to receive a digital target current signal DITARGET and a digitized current signal DIL and then generate a digital current error signal DIERR. The digitized current signal DIL is a digital representation of the current flowing through the first energy storage element, which is the inductor 410 in this embodiment.

[0148] The digitized current signal DIL may be received from the digitized current generating circuit 430. The digitized current generating circuit 430 may include an analog-to-digital converter configured to sense the current flowing through the first energy storage element 410 and digitize the sensed current to generate the digitized current signal DIL. The digitized current generating circuit 430 may additionally or alternatively include a current synthesizer for generating the digitized current signal DIL.

[0149] The first control circuit 402 may include a modulator 432 configured to generate a first mode control signal MOD_MAG using the digital current error signal DIERR. The controller 300 may also include a logic and gate driver circuit 434 configured to receive the first mode control signal MOD_MAG during the first state and generate a gate drive signal GP, GN for each of the power switches 406, 408 using the first mode control signal MOD_MAG.

[0150] It should be understood that the present embodiment includes a buck converter having two power switches. Additional embodiments may be provided that have different switching converter configurations and include fewer power switches or more power switches than the present embodiment.

[0151] The hysteresis control circuit 404 is configured to generate an up signal 436 for controlling the power switches 406, 408 to charge the first energy storage element 410 and a down signal 438 for controlling the power switches 406, 408 to discharge the first energy storage element 410. During operation, the up signal 436 is generated when the digitized output voltage DOUT drops below a first threshold voltage, and the down signal 438 is generated when the digitized output voltage DOUT rises above a second threshold voltage.

[0152] The controller 300 may also include a logic and gate driver circuit 434 configured to receive the first mode control signal MOD_MAG during the first state and generate a gate drive signal GP, GN for each of the power switches 406 , 408 using the first mode control signal MOD_MAG.

[0153] The logic and gate driver circuit 434 is configured to receive the up signal 436 and the down signal 438 during the second state and generate a gate drive signal GP, GN for each of the power switches 406 , 408 using the up signal 436 and the down signal 438 .

[0154] It should be understood that the present embodiment includes a buck converter having two power switches. Additional embodiments may be provided that have different switching converter configurations and include fewer power switches or more power switches than the present embodiment.

[0155] The controller 300 may include one or more digital gates configured to receive the first mode control signal MOD_MAG, the up signal 436, and the down signal 438. During the first state, the one or more digital gates provide the first mode control signal MOD_MAG to the logic and gate driver 434, and during the second state, the one or more digital gates provide the up signal 436 and the down signal 438 to the logic and gate driver 434.

[0156] In this embodiment, the one or more digital gates include an AND gate 440 and an OR gate 442. The AND gate 440 includes an inverting input terminal 444 for receiving the down signal 438 and a non-inverting input terminal 446 for receiving the first mode control signal MOD_MAG. The OR gate 442 includes an input terminal 448 for receiving the up signal 436 and an input terminal 450 for receiving the output of the AND gate 440.

[0157] The OR gate 442 further includes an output terminal 452 for providing the first mode control signal MOD_MAG during the first state, and for providing the up signal 436 and the down signal 438 during the second state.

[0158] In this embodiment, the first control circuit 402 is as follows Figure 2A works as described in Figure 2A In the embodiment of the present invention, the first control circuit 402 is used as a PI linear loop, which generates a digital target current DITARGET and causes the modulator 432 to generate a first mode control signal MOD_MAG to ensure that the inductor current IL is approximately equal to the digital target current DITARGET.

[0159] A hysteresis assist loop is provided by a hysteresis control circuit 404. In response to a load transient, the hysteresis control circuit 404 sets one of its outputs (labeled HYSTUP and HYSTDW) to 1, providing an up signal 436 and a down signal 438, depending on whether the transient is rising or falling. This is used to override the first mode control signal MOD_MAG through gates 440, 442. If there is no sudden load transient, the outputs HYSTUP, HYSTDW are zero and the modulator 432 drives the switching operation.

[0160] Figure 5A is shown with Figure 4C 300 and a timing diagram of waveforms related to an actual implementation of the switching converter 302. The output voltage (trace 500), the threshold voltage Vth1, and the threshold voltage Vth2 of the switching converter 302 are shown. When the output voltage VOUT drops below the threshold voltage Vth1, an up signal 436 is generated; and when the output voltage VOUT rises above the threshold voltage Vth2, a down signal 438 is generated.

[0161] Also shown are the inductor current IL (trace 502 ) and the load current ILOAD (trace 504 ).

[0162] In this embodiment, when the linear PI control 402 provides control of the switching converter 302, the hysteresis loop no longer sets the ripple. The ripple in the linear control mode can be as high as + / -30mV. Therefore, in order to prevent the hysteresis control circuit 404 from over-triggering, we will need to extend the threshold for the hysteresis triggering to exceed Figure 2B The + / -5mV of the hysteretic system presented in Figure 1 can be extended to more than + / -30mV. This can be called "oversizing the hysteretic limits".

[0163] Figure 5B is shown with Figure 4C 300 and a practical implementation of the switching converter 302. The inductor current IL (trace 506), the load current ILOAD (trace 508), the digital target current DITARGET (trace 510), the control mode (labeled as 512) and the charging pulse (trace 514) are shown.

[0164] Figure 5C It is shown as Figure 5B 5. Another timing diagram of the waveform presented in FIG. 5 over a specific time period. Also shown is the clock signal (trace 516) used to enable the modulator 432.

[0165] refer to Figure 5A , if the load current ILOAD steps upward while the control circuit 402 provides control, the inductor current IL will not react spontaneously and it keeps ramping up and then down (linear PI is slow).

[0166] However, as shown in the graph, when the inductor current IL is very low, the output VOUT collapses and the hysteretic control circuit 404 can (at "TRIGUP") charge the inductor 410. As a result, the output voltage VOUT will drop further until the inductor current IL has accumulated up to the load current ILOAD.

[0167] Intuitively, we see that the output voltage VOUT can drop by half of the 30mV ripple, or a total of 60mV, which is undesirable for a practical implementation of a hysteretic converter.

[0168] When the hysteresis control circuit 404 controls the switching converter 302, it controls the gate drive signals GP, GN independently of the inductor current IL. Therefore, the inductor current IL will vary without feedback of the inductor current IL to assist in the control. Additionally, the control of the switch no longer follows a constant switching frequency FSW.

[0169] This leads to two potential problems that may occur when leaving hysteresis mode and returning to linear mode, such as Figure 5B shown.

[0170] 1. Inductor current IL control continuity. When the load current ILOAD steps upwards, the hysteresis takes over (HYSTUP), but at the same time, the PI regulation slowly increases DITARGET (which is no longer used because the hysteresis has taken over). At point STOPUP1, DITARGET has only reached, for example, 3A, while the hysteresis control has generated 6A. When we now switch back to linear regulation, IL will suddenly drop from 6A to 3A because the linear regulation sets it back to 3A. This will reduce the output voltage VOUT and trigger the hysteresis again (TRIGUP2). The same switching (which may even lead to continuous oscillations) also applies to HYSTDW1,2.

[0171] 2. Frequency continuity. Figure 5C , at point STOPUP1, the DC / DC clock that causes magnetization to start, for example, can be anywhere (as shown by trace 516). Figure 5C An undesirable sequence is shown where magnetization starts right at STOPUP1 and the inductor 410 continues to charge. While some modulators (such as the peak current modulator) will stop magnetization immediately, Figure 5C As shown, other modulator types (e.g., average current mode) can have an additional 50ns magnetization time beyond STOPUP1. The dashed line shows the expected performance at this point. Continued magnetization may cause a "bounce" on the output voltage VOUT, which may over-trigger, for example, HYSTDW (hysteresis to reduce VOUT) and cause continued oscillation.

[0172] In a particular embodiment, controller 300 is configured to sample the output voltage VOUT of switching converter 302 at two time steps and then determine the sampled voltage difference by subtracting the initial sample from the subsequent sample, as follows:

[0173] ΔVOUT=VOUT2-VOUT1 (2)

[0174] Wherein, ΔVOUT is the sampled voltage difference, VOUT2 is the second voltage sample, and VOUT1 is the first voltage sample, wherein the second voltage sample VOUT2 is obtained after the first VOUT1.

[0175] The controller 300 is also configured to generate an up signal 436 for charging the first energy storage element 410 when the sampled voltage difference is less than the voltage difference threshold VDIFFTH1, which can be represented as follows:

[0176] ΔVOUT <VDIFFTH1 (3)

[0177] The controller 300 may also be configured to generate a down signal 438 for discharging the first energy storage element 410 when the sampled voltage difference is greater than the voltage difference threshold VDIFFTH2, which may be represented as follows:

[0178] ΔVOUT>VDIFFTH2 (4)

[0179] The sampled voltages VOUT1, VOUT2 may be acquired during different switching cycles of the switching converter 302. In certain embodiments, the time step when the second voltage sample VOUT2 is acquired may be a single switching cycle after the first voltage sample VOUT1 is acquired.

[0180] The voltage sampling process may be repeated multiple times and may be repeated periodically.

[0181] In a general embodiment, the controller 300 is configured to periodically sample the output voltage VOUT to obtain n sampled voltages at n time steps, where n is an integer. The controller 300 repeatedly determines the nth sampled voltage difference ΔVOUT[n] (where m is an integer) by subtracting the (nm)th sampled voltage VOUT[nm] from the nth sampled voltage VOUT[n], which can be expressed as follows:

[0182] ΔVOUT[n]=VOUT[n]-VOUT[nm] (5)

[0183] When the nth sampled voltage difference is less than the voltage difference threshold VDIFFTH1, an up signal 436 is generated for charging the first energy storage element 410, which can be expressed as follows:

[0184] ΔVOUT[n] <VDIFFTH1 (6)

[0185] When the nth sampled voltage difference is greater than the voltage difference threshold VDIFFTH2, a down signal 438 is generated to discharge the first energy storage element 410, which can be represented as follows:

[0186] ΔVOUT[n] > VDIFFTH2 (7)

[0187] The first voltage difference threshold VDIFFTH1 can be a negative value of the second voltage difference threshold VDIFFTH2.

[0188] Figure 6 is a timing diagram related to the actual implementation of the controller 300 in this embodiment. In this example, referring to Equation (4), m is equal to 8. The output voltage VOUT (trace 600), the voltage sample VOUT[n] (point 602), and the voltage sample VOUT[n - 8] (point 604) are shown. The voltage difference threshold VDIFFTH1 is labeled with reference numeral 606. The load current ILOAD (trace 608) is also shown.

[0189] Eight samples are acquired within a single switching cycle of the switching converter 302, where for each sample acquisition, ΔVOUT[n] is calculated and evaluated with respect to the threshold.

[0190] As an example, we assume that VOUT[n] is 0.97V, VOUT[n - 8] is 1V, and VDIFFTH1 is -15mV. From Equation (5), ΔVOUT[n] = -30mV. According to Equation (6), if ΔVOUT[n] < VDIFFTH1, an up signal 436 is generated and the first energy storage element 410 is charged.

[0191] The output voltage VOUT can have any large amplitude and random-shaped ripple because the controller 300 can be applied to multi-phase. In this example, each switching cycle TSW can have 8 digital sampling points processed.

[0192] Reference Figure 6 , the first two DCDC cycles of the output voltage VOUT exhibit periodic behavior. Then the load current ILOAD steps up, and the subsequent data points show that the output voltage VOUT collapses.

[0193] In this example, there are 8 points per DCDC cycle, and the controller 300 continuously compares VOUT[n] with VOUT[n - 8], rather than simply comparing the output voltage VOUT with a fixed threshold.

[0194] This condition allows the controller 300 to ignore the ripple, and when VOUT[n] has dropped by 15mV compared to its previous corresponding value of VOUT[n - 8], it allows triggering of hysteresis. Compared with having a constant -30mV threshold (as shown in Figure 5A ), it makes the hysteresis triggering more responsive even for large random ripples on the voltage VOUT.

[0195] Using the above technique, where the output voltage VOUT is sampled to identify the sampled voltage difference, the problem of having to make the hysteresis limit too large (e.g., Figure 5A ) because the hysteresis entry is not based on a fixed limit.

[0196] In further embodiments, other conditions may be added based on both the output voltage VOUT history and the output voltage VOUT level and slope.

[0197] In certain embodiments, controller 300 is configured to control switching converter 302 when operating in the intermediate control mode during the third state. Fig. 7A 7 is a timing diagram of the actual implementation of the controller 300 in this embodiment. It shows: carrier clock signal (trace 700); clock signal (trace 702); output voltage VOUT (trace 704); first control mode signal MOD_MAG (trace 706); control mode (labeled as 708); magnetization signal MAG provided to logic and driver 434 (trace 710); load current ILOAD (trace 712); inductor current IL (trace 714); and digital target current DITARGET (trace 716).

[0198] exist Fig. 7A In FIG. 7 , the control mode 708 is labeled “ITGLOAD” during the time period during which the controller 300 provides the intermediate control mode control.

[0199] The controller 300 is configured to switch from a first control mode (in this example, a linear mode and labeled LINEAR) to a hysteretic control mode (e.g., labeled HYSTUP) in response to a load transient (labeled LOAD step). The controller 300 is configured to switch to an intermediate control mode after the hysteretic control mode and before switching to the first control mode.

[0200] In the present embodiment, the controller 300 is configured to correct the digital target current signal DITARGET during the intermediate control mode.

[0201] Amplifiers 418, 420 are configured to receive a digital error signal DVERR. Amplifier 418 includes an output coupled to an input of a summing circuit 422. Amplifier 420 includes an output coupled to an input of a summing circuit 424. An output of summing circuit 424 is coupled to an input of summing circuit 422 and to an input of register 426. Register 426 includes an output coupled to an input of summing circuit 424. Note that the combination of summing circuit 424 and register 426 is a digital integrator, and thus its output is named DI.

[0202] The controller 300 is configured to update the register 426 based on the digitized current signal DIL, the gain P of the amplifier 418 , the digitized output voltage signal DOUT, and the digital voltage reference signal DREF to correct the digital target current signal DITARGET during the intermediate control mode.

[0203] The controller 300 may also be configured to resynchronize the clock cycle of the switching converter 302 to the carrier clock after switching from the intermediate control mode. Fig. 7A , where, after switching from the intermediate control mode, the clock phase shown in trace 702 shifts after becoming out of sync, closer to the carrier clock signal. We "slide" the clock back into phase with the fixed carrier. This creates an advantage in achieving EMI spectrum.

[0204] The carrier may be a constant reference frequency to which the switching converter is preferably aligned in phase. Thus, when there is a hysteresis event, the switching converter clock is no longer used. At the end of the hysteresis, it will restart arbitrarily, but then we expect it to slide so that it will eventually be in phase with the carrier (carrier unchanged). For large circuits with several switching converters (such as a buck converter), we want to control the phase of each switching converter. Each switching converter gets a carrier and will lock its switching frequency with the carrier except for these occasional hysteresis events.

[0205] like Fig. 7A The operation of the particular embodiment of the illustrated controller 300 can be summarized as follows:

[0206] The controller 300 initially operates in a linear control mode, where the control circuit 402 provides PID control to generate a digital target current that controls the average inductor current IL. The DCDC "clock" follows the carrier clock, which remains constant, as shown by the pulses of traces 700, 702 that are in sync. MAG signal (trace 710)

[0207] Same as the MOD_MAG signal (trace 706).

[0208] The load step then triggers a drop in the output voltage (trace 704), and the controller 300 switches to the hysteretic control mode based on the previously described sampling method for triggering entry into the hysteretic control mode. MAG signal (trace 710)

[0209] Now forced by hysteretic modulation, and no longer equal to the MOD_MAG signal (trace 706). The MAG signal is maintained until the output voltage VOUT stops falling, which means that enough inductor current IL has accumulated to match the load current ILOAD. At this point, the hysteretic mode can be exited.

[0210] In this embodiment, an intermediate control mode ITGLOAD is provided, in which the following two operations are performed:

[0211] The digital target current DITARGET is adjusted so that the digital target current DITARGET controls the inductor current IL, thereby solving the problem of the slow ramp-up of DITARGET, as previously described. Figure 5B discussed.

[0212] The digital target current DITARGET is corrected as if the PID circuit controlled the effective inductor current, which can be written as follows:

[0213] DITARGET=DP+DI=P(DREF-DOUT)+DI (8)

[0214] Wherein DP is the output of amplifier 418, DI is the output of summing circuit 424, P is the gain of amplifier 418, and the other symbols have the meanings as described above.

[0215] The digitized inductor current DIL must be equal to DITARGET, which can be written as follows:

[0216] DIL=P(DREF-DOUT)+DI (9)

[0217] It can be rewritten as follows:

[0218] DI=DIL-P(DREF-DOUT) (10)

[0219] In operation, register 426 is loaded with the new value of output DI and the digitized inductor current DIL using equation (10).

[0220] The DCDC clock may be changed during the intermediate mode ITGLOAD to avoid further extension of the magnetization, e.g. due to Figure 5C In this embodiment, the modulator 432 can be implemented as described in US 18 / 361,274. In this embodiment, a rising clock edge is used, and in other embodiments, any suitable clock phase can be used according to the understanding of those skilled in the art.

[0221] Then, after these two ITG / CLOCK updates during state ITGLOAD, the PID linear regulation takes over (indicated by the linearity in trace 708). It is now correctly preset to avoid any excessively long magnetizing periods or incorrect DITARGET.

[0222] Additionally, the controller 300 is configured to "slowly slide" during subsequent cycles (cycle 2, cycle 3, ...)

[0223] The edges of the clock (trace 702) are modulated so that it eventually gets back in phase with the carrier (trace 700). The advantage is that it becomes as if the clock signal has a constant frequency but with phase jumps. Therefore, this is phase modulation rather than frequency modulation, and has an effect on the spectrum.

[0224] It should be appreciated that the above process utilizes the following features of a particular embodiment of the digital controller 300:

[0225] The inductor current IL is digitized, for example, according to US 18 / 361,240. Figure 5B In Figure 1, we see that at point STOPUP1, IL can be much higher than the current commanded by the PID, and the modulator clock can be anywhere.

[0226] The clock is a digital signal; we can control when it starts / stops in time steps from the system clock: for example, the DCDC clock can be 5MHz and the system clock can be 40MHz. In this case, the DCDC clock can be started / stopped at any time with a resolution of 25ns.

[0227] Figure 7B is shown by Fig. 7A A flow chart of a process performed by a particular embodiment of the controller 300 is described.

[0228] Fig. 8A The simulation results of the actual implementation of the controller 300 are shown. The following are shown: carrier clock signal (trace 800), clock signal (trace 802), hysteresis up mode status signal (trace 804), output voltage (trace 806), sensed current voltage representing inductor current (trace 808), output DI (trace 810), output DP (trace 812).

[0229] Figure 8B Simulation results of an actual implementation of controller 300 are shown, showing random hysteresis events with clock slip recovery. Shown are: trace 818, trace 820, trace 822, trace 824, trace 826.

[0230] Trace 818 is the 40 MHz 1 / Ts clock used for processing.

[0231] Trace 820 is a hysteresis event, HYSTUP or HYSTDW, which allows VOUT to recover faster.

[0232] Trace 822 is a constant carrier frequency: for example, 4 MHz: this is the signal we will always try to synchronize the FSW to.

[0233] Trace 824 is the effective DCDC clock. This overall picture shows that this clock has a discontinuity every time a hystout event ends because this is our clock recovery scheme as described in the figure above. Later, after each hystout event, 824 will slide back in phase with 822 through the sliding scheme.

[0234] Trace 826: The actual signal generated by the modulator and driving the power switch. Therefore, we also see that it has discontinuities: for example, a constant "1" whenever there is a hystout event.

[0235] The advantage of this clocking scheme is that since the DCDC clock is always shifted back to a fixed carrier, the hysteresis event can be considered as a phase disturbance rather than a frequency disturbance. Since phase is the integral of frequency, it compresses the spectrum: if the FSW is 4MHz, the standard hysteresis loop will produce random jumps even with PLL / FLL assistance and spread the spectrum uncontrollably around 4MHz. This hysteresis scheme will tighten this spread around 4MHz.

[0236] Figure 8C The simulation results of the actual implementation of the controller 300 are shown. There are shown traces 830, 832. A spurious attenuation of 6dB to 20dB can be observed around the harmonics 4MHz, 8MHz.

[0237] Figure 1 , Figure 2A and Figure 2B The switch node SW in the circuit behaves like an antenna. Traces 830, 832 are Figure 8B The Fourier transform of this SW node captured on the simulation shown.

[0238] For example, since the power level is switching at 4 MHz, then if the SW spectrum is tight on that 4 MHz, it means the antenna is transmitting but under control at a known frequency location.

[0239] The DCDC 4MHz (usually this is negligible) may be offset slightly in close channel situations. For example, if close to the radio 3.9MHz channel, then we offset the BUCK frequency to 4.2MHz. Therefore, it is preferred to have a tight spectrum.

[0240] Fig.8D Simulation results of an actual implementation of controller 300 are shown compared to a system that provides only linear control. The output voltage of switching converter 302 using a specific embodiment of controller 300 of the present disclosure (trace 834) and the output voltage of a system using only linear mode control (trace 836) are shown. The load current for an embodiment of the present disclosure (trace 838) and the load current for only linear control (trace 840) are also shown.

[0241] It can be observed that the controller 300 of the present disclosure provides substantial improvements over systems using only linear control.

[0242] In general, embodiments of the present disclosure may provide one or more of the following:

[0243] Combined digital linear control and digital hysteresis assistance, swappable on the fly. This is applicable to any current mode digitally controlled converter.

[0244] Transition to hysteresis based on VOUT history. An algorithm based on VOUT history that does not require a fixed threshold. This is applicable to hysteresis controllers as auxiliary loops. In embodiments of the present disclosure, the hysteresis controller does not set the voltage ripple, but rather suppresses the ripple.

[0245] Swapping back from hysteresis to linear using the DIL internal state value to update the integrator path or any other internal variables ensures that the linear regulation target is the actual DIL (and therefore the actual inductor current) when the linear loop takes back control.

[0246] Swapping from hysteresis back to linear: offset the clock edges to ensure continuity of modulation.

[0247] Slide clock recovery to ensure phase modulation rather than frequency modulation: preferably reconnect to a fixed carrier.

[0248] Fig. 9 is a schematic diagram of a controller 300 according to a fifth embodiment of the present disclosure. In this embodiment, an alternative implementation of the digital target current signal generating circuit 416 is provided.

[0249] The digital target current signal generation circuit 416 may include one or more registers, wherein in the present embodiment, four registers 900 are provided. The register 900 may be referred to as a memory element.

[0250] The controller 300 is configured to update at least one of the one or more registers in the register 900 based on the digitized current signal DIL, thereby correcting the digital target current signal DITARGET during the intermediate control mode.

[0251] The digital target current signal generation circuit 416 may further include circuit components 902 , 904 , 906 , 908 , 910 , 912 , 914 , 916 , 918 .

[0252] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.< / x> < / dil> < / ditarget>

Claims

1. A controller for a switching converter, the switching converter being configured to receive an input voltage and generate an output voltage, and comprising one or more power switches and one or more energy storage elements, the one or more energy storage elements comprising a first energy storage element, the controller being configured to: controlling the switching converter when operating in a first control mode during a first state; and The switching converter is controlled while operating in a hysteretic control mode during a second state.

2. The controller according to claim 1, wherein: The controller is further configured to receive a digitized output voltage signal, the digitized output voltage signal being a digital representation of an output voltage of the switching converter; The controller further includes a first control circuit that is activated during the first state to provide the first control mode; in The first control circuit is configured to generate a digital target current signal using the digitized output voltage signal; and The first control circuit comprises: a first voltage error generating circuit configured to generate a digital error signal using the digitized output voltage signal and a digital voltage reference signal; as well as A digital target current signal generating circuit is configured to convert the digital error signal into the digital target current signal. 3 . The controller of claim 2 , further comprising a hysteresis control circuit that is activated during the second state to provide the hysteresis control mode.

4. The controller according to claim 1, wherein: The controller is further configured to switch from the first control mode to the hysteretic control mode in response to a load transient; and The controller is also configured to receive a digitized output voltage signal that is a digital representation of an output voltage of the switching converter.

5. The controller according to claim 4, further comprising: a first control circuit, the first control circuit being activated during the first state to provide the first control mode; in The first control circuit is configured to generate a digital target current signal using the digitized output voltage signal; and The first control circuit includes a first current error generating circuit, and the first current error generating circuit is configured to: receiving the digital target current signal; receiving a digitized current signal, the digitized current signal being a digital representation of current flowing through the first energy storage element; as well as A digital current error signal is generated.

6. The controller according to claim 3, wherein: The controller is also configured to: Sampling the output voltage to obtain a first sampled voltage at a first time step and a second sampled voltage at a second time step; determining a sampled voltage difference by subtracting the second sampled voltage from the first sampled voltage; generating an up signal for charging the first energy storage element during the second state when the sampled voltage difference is less than a first voltage difference threshold; generating a down signal for discharging the first energy storage element during the second state when the sampled voltage difference is greater than a second voltage difference threshold; as well as The first sampled voltage is acquired during a first switching cycle of the switching converter, and the second sampled voltage is acquired during a second switching cycle of the switching converter.

7. The controller according to claim 1, wherein: The controller is also configured to control the switching converter when operating in an intermediate control mode during a third state.

8. The controller according to claim 7, wherein: The controller is further configured to switch from the first control mode to the hysteretic control mode in response to a load transient; and The controller is further configured to switch to the intermediate control mode after the hysteresis control mode and before switching to the first control mode.

9. The controller according to claim 8, wherein: The controller is further configured to receive a digitized output voltage signal, the digitized output voltage signal being a digital representation of an output voltage of the switching converter; and The controller further includes a first control circuit that is activated during the first state to provide the first control mode; in The first control circuit is configured to generate a digital target current signal using the digitized output voltage signal; and The first control circuit comprises: a first voltage error generating circuit configured to generate a digital error signal using the digitized output voltage signal and a digital voltage reference signal; and a digital target current signal generating circuit, wherein the digital target current signal generating circuit is configured to convert the digital error signal into the digital target current signal; The controller is also configured to correct the digital target current signal during the intermediate control mode.

10. A method of controlling a switching converter using a controller, the switching converter being configured to receive an input voltage and generate an output voltage and comprising one or more power switches and one or more energy storage elements, the one or more energy storage elements comprising a first energy storage element, the method comprising: controlling the switching converter when operating in a first control mode during a first state; as well as The switching converter is controlled while operating in a hysteretic control mode during a second state.

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