Switching power supply loop compensation circuit

Abstract

The invention discloses a switching power supply loop compensation circuit, which comprises a current mirror unit, and is characterized in that the current mirror unit comprises a first current mirror branch and a second current mirror branch; the first current mirror branch comprises a first MOS switch tube, a compensation resistor and a compensation capacitor; the second current mirror branch comprises a second MOS switch tube and a third MOS switch tube; the current mirror unit further comprises an operational amplifier, the non-inverting input end of the operational amplifier is connected with the drain electrode of the first MOS switch tube, the inverting input end of the operational amplifier is connected with the drain electrode of the second MOS switch tube, and the output end of the operational amplifier is connected with the grid electrode of the third MOS tube. The first MOS switch tube and the third MOS switch tube have the same gate-source voltage value; the current copy multiple of the first current mirror branch and the second current mirror branch is M.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a switching power supply loop compensation circuit. Background Art

[0002] Switching Mode Power Supply, also known as switching power supply or switching converter, is a high-frequency power conversion device. Its function is to convert a voltage level into the voltage or current required by the user through different forms of architecture. A switching power supply is a power supply that maintains a stable output voltage by controlling the time ratio of the switch tube to be turned on and off. A switching power supply is generally composed of a pulse width modulation (PWM) control IC and a MOSFET. The transfer function of the main circuit of the switching power supply contains a zero point. And as the switching frequency increases, the transfer function gain increases accordingly, but the phase angle decreases. If it is not filtered out (compensated), positive feedback will be formed, making the control system of the entire switching power supply ineffective and causing damage to the entire circuit.

[0003] like Figure 1 As shown in the figure, in the prior art, loop compensation for switching power supplies uses a relatively large loop compensation capacitor. Therefore, for cost considerations, the compensation capacitor and the compensation resistor are generally disposed outside the switching power supply chip. Figure 1 Taking the switching power supply circuit shown in the figure as an example, the main pole of the system is located at the output section of the error amplifier EA, PAD is the pin of the switching power supply chip, and the external compensation capacitor C and the external compensation resistor R are set outside the chip. Therefore, the entire switching power supply has the following relationship after stabilization:

[0004]

[0005] When the peak current comparator of comparator CMP flips,

[0006] Vsns=Isns*Rsns=Vc;

[0007] Where Vsns is the sampling voltage, Isns is the sampling current, and Rsns is the sampling resistor. Therefore, the sampling current Isns can be expressed as:

[0008]

[0009] The loop compensation circuit of the current technical solution requires the switching power supply chip to have an additional pin for connecting external compensation capacitors and resistors, thereby increasing the production cost of the chip.

[0010] It can be seen that a new switching power supply loop compensation circuit is needed in the art, which can achieve the purpose of setting the switching power supply loop compensation circuit inside the switching power supply chip by setting an equivalent capacitor and resistor compensation circuit inside the chip. Summary of the invention

[0011] The present invention provides a switching power supply loop compensation circuit. The switching power supply loop compensation circuit sets an external compensation circuit equivalently inside a chip by setting a circuit including an equivalent compensation capacitor and an equivalent compensation resistor, thereby reducing the pin settings of the chip.

[0012] Based on the above technical purpose, the present invention provides a switching power supply loop compensation circuit, the switching power supply loop compensation circuit includes a current mirror unit, the current mirror unit includes a first current mirror branch and a second current mirror branch;

[0013] The first current mirror branch comprises a first MOS switch tube, a compensation resistor and a compensation capacitor; the drain of the first MOS switch tube is sequentially connected in series with an equivalent capacitor and an equivalent resistor; the gate and drain of the first MOS switch tube are short-circuited;

[0014] The second current mirror branch includes a second MOS switch tube and a third MOS switch tube, the gate of the second MOS switch tube is connected to the gate of the first MOS switch tube, and the drain of the second MOS switch tube is connected to the source of the third MOS switch tube;

[0015] A first voltage is inputted from a high potential end of the current mirror unit to the drain of the compensation resistor and the third MOS switch tube;

[0016] The current mirror unit further includes an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is connected to the drain of the first MOS switch tube, an inverting input terminal of the operational amplifier is connected to the drain of the second MOS switch tube, and an output terminal of the operational amplifier is connected to the gate of the third MOS tube;

[0017] The first MOS switch tube and the third MOS switch tube have the same gate-source voltage value;

[0018] The current replication multiples of the first current mirror branch and the second current mirror branch are M, and the compensation coefficient of the switching power supply loop compensation circuit is adjusted by adjusting the current replication multiple M, the resistance value of the compensation resistor and the capacitance value of the compensation capacitor.

[0019] In one embodiment, sources of the first MOS switch tube and the second MOS switch tube are grounded.

[0020] In one embodiment, the switching power supply loop compensation circuit also includes an error amplifier and a voltage divider unit, wherein the voltage divider unit divides the output voltage of the switching power supply and inputs the voltage to the inverting input terminal of the error amplifier, a reference voltage is input to the non-inverting input terminal of the error amplifier, and the error amplifier outputs the first voltage.

[0021] In one embodiment, the switching power supply loop compensation circuit further includes a comparator, the first voltage is input to the inverting input terminal of the comparator, the sampling voltage of the switching power supply is input to the non-inverting input terminal of the comparator, and the peak current of the switching power supply is output by the comparator.

[0022] In one embodiment, the switching power supply loop compensation circuit further includes a sampling current source, a sampling resistor and a fourth MOS switch tube, the source of the fourth MOS switch tube is grounded, and the gate and drain of the fourth MOS switch tube are short-circuited, the drain of the fourth MOS switch tube is connected to the first end of the sampling resistor, the second end of the sampling resistor is connected to the sampling current source, and the second end of the sampling resistor generates the sampling voltage.

[0023] Compared with the prior art, one or more embodiments of the present invention may have the following advantages:

[0024] The present invention arranges equivalent compensation capacitor and compensation resistor circuits inside the chip, thereby eliminating the need for additional chip pins to connect external compensation capacitors and compensation resistors in the prior art loop compensation method.

[0025] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0027] Figure 1 It is a schematic diagram of the structure of a switching power supply loop compensation circuit in the prior art;

[0028] Figure 2 It is a schematic diagram of the structure of the switching power supply loop compensation circuit of the present invention. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0030] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present invention necessarily has the first element, component, region, layer or part.

[0031] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] Example

[0034] like Figure 1As shown, the switching power supply loop compensation circuit of the present invention includes: an error amplifier EA, a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2, and the non-inverting input terminal of the error amplifier EA outputs a reference voltage V ref , whose inverting input end is connected to the first end of the first voltage-dividing resistor R1 and the first end of the second voltage-dividing resistor R2, and the second end of the first voltage-dividing resistor R1 is connected to the input voltage V out , the second end of the second voltage-dividing resistor R2 is grounded. Thus, the voltage-dividing voltage V generated by the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 is out_div The output terminal of the error amplifier EA outputs the error amplifier EA output current I c And the error amplifier EA output voltage V c .

[0035] The switching power supply loop compensation circuit also includes: a first NMOS switch tube N1, a second NMOS switch tube N2 and a third NMOS switch tube N3. It also includes a compensation resistor R0, a compensation capacitor C0 and an operational amplifier OP. Among them, the first end of the compensation resistor R0 is connected to the output end of the error amplifier EA, the second end of the compensation resistor R0 is connected to the first end of the compensation capacitor C0, and the second end of the compensation capacitor C0 is simultaneously connected to the drain of the first NMOS switch tube N1 and the non-inverting input end of the operational amplifier OP. The source of the first NMOS switch tube N1 is grounded, the gate of the first NMOS switch tube N1 is connected to the gate of the second NMOS switch tube N2 and is simultaneously connected to the drain of the first NMOS switch tube N1, the source of the second NMOS switch tube N2 is grounded, the drain of the second NMOS switch tube N2 is simultaneously connected to the inverting input end of the operational amplifier OP and the source of the third NMOS switch tube N3, the output end of the operational amplifier OP is connected to the gate of the third NMOS switch tube N3, and the drain of the third NMOS switch tube N3 is connected to the output end of the error amplifier EA.

[0036] The switching power supply loop compensation circuit also includes: a comparator CMP, a sampling current source I sns , sampling resistor R sns The inverting input terminal of the comparator CMP is connected to the output terminal of the error amplifier EA, and the non-inverting input terminal of the comparator CMP is connected to the sampling resistor R sns The first end of the sampling resistor R sns The second end of is connected to the drain of the fourth NMOS switch tube N4, the drain and gate of the fourth NMOS switch tube N4 are short-circuited, and the source of the fourth NMOS switch tube N4 is grounded. snsConnect the sampling resistor R sns The fourth NMOS switch tube N4 is used to offset the influence of the first NMOS switch tube N1 and the second NMOS switch tube N2 in the current mirror on the output voltage of the error amplifier EA.

[0037] The first NMOS switch tube N1 and the second NMOS switch tube N2 form a mutually matched NMOS current mirror, and the mirror ratio multiple is M, that is, the current I C1 is the current I of the current mirror branch where the second NMOS switch tube N2 is located C2 1 / M, expressed as I C2 =M*I C1 Under the action of the operational amplifier OP and the third NMOS switch tube N3, the voltages at points A and B are equal in a stable state, thereby improving the accuracy of the current mirrors of N1 and N2.

[0038] According to the above circuit structure, the following relationship exists:

[0039] IC=IC1+IC2=(1+M)*IC1---(1)

[0040]

[0041] Substituting (1) into (2) yields:

[0042]

[0043] When the I2 peak current comparator flips,

[0044] VSNS=ISNS*RSNS+VGS N3 =VC---(4)

[0045] Substituting (3) into (4), we can get the power tube sampling current ISNS as:

[0046]

[0047] By designing appropriate parameters, we can achieve:

[0048]

[0049] Where R and C are the compensation resistor and compensation capacitor used in the prior art when external compensation is used. SNS can be simplified to:

[0050]

[0051] That is, by setting the adjustment coefficient 1 / (1+M) for the compensation resistor R0 and the adjustment coefficient (1+M) for the compensation capacitor C0, and setting the gate-source voltages of the first NMOS switch tube N1 and the third NMOS switch tube N3 to be approximately the same, it is possible to satisfy the above-mentioned in-chip compensation circuit to be equivalent to the external compensation circuit used in the prior art.

[0052] When M is large, such as M = 200, if the external compensation capacitor C = 10nF and the external compensation resistor R = 10Kohm, the equivalent circuit will correspond to C0 of about 50pF and R0 of about 2Mohm, which can be realized by high resistance, thus being easily integrated inside the chip, reducing the extra cost caused by R and C outside the chip. In addition, by adjusting the ratio M of the current mirror, different compensation capacitors and resistors can be realized.

[0053] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A switching power supply loop compensation circuit, characterized in that: The switching power supply loop compensation circuit comprises a current mirror unit, and the current mirror unit comprises a first current mirror branch and a second current mirror branch; The first current mirror branch comprises a first MOS switch tube, a compensation resistor and a compensation capacitor; the drain of the first MOS switch tube is sequentially connected in series with an equivalent capacitor and an equivalent resistor; the gate and drain of the first MOS switch tube are short-circuited; The second current mirror branch includes a second MOS switch tube and a third MOS switch tube, the gate of the second MOS switch tube is connected to the gate of the first MOS switch tube, and the drain of the second MOS switch tube is connected to the source of the third MOS switch tube; A first voltage is inputted from a high potential end of the current mirror unit to the drain of the compensation resistor and the third MOS switch tube; The current mirror unit further includes an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is connected to the drain of the first MOS switch tube, an inverting input terminal of the operational amplifier is connected to the drain of the second MOS switch tube, and an output terminal of the operational amplifier is connected to the gate of the third MOS tube; The first MOS switch tube and the third MOS switch tube have the same gate-source voltage value; The current replication multiples of the first current mirror branch and the second current mirror branch are M, and the compensation coefficient of the switching power supply loop compensation circuit is adjusted by adjusting the current replication multiple M, the resistance value of the compensation resistor and the capacitance value of the compensation capacitor.

2. The switching power supply loop compensation circuit according to claim 1, characterized in that: Sources of the first MOS switch tube and the second MOS switch tube are grounded.

3. The switching power supply loop compensation circuit according to claim 1, characterized in that: The switching power supply loop compensation circuit also includes an error amplifier and a voltage divider unit. The voltage divider unit divides the output voltage of the switching power supply and inputs it to the inverting input terminal of the error amplifier. The reference voltage is input to the non-inverting input terminal of the error amplifier, and the error amplifier outputs the first voltage.

4. The switching power supply loop compensation circuit according to claim 1, characterized in that: The switching power supply loop compensation circuit also includes a comparator, the first voltage is input to the inverting input terminal of the comparator, the sampling voltage of the switching power supply is input to the non-inverting input terminal of the comparator, and the peak current of the switching power supply is output by the comparator.

5. The switching power supply loop compensation circuit according to claim 4, characterized in that: The switching power supply loop compensation circuit also includes a sampling current source, a sampling resistor and a fourth MOS switch tube, the source of the fourth MOS switch tube is grounded, and the gate and drain of the fourth MOS switch tube are short-circuited, the drain of the fourth MOS switch tube is connected to the first end of the sampling resistor, the second end of the sampling resistor is connected to the sampling current source, and the second end of the sampling resistor generates the sampling voltage.

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