Motor inter-wire voltage reversal mitigation

Abstract

The present disclosure provides mitigation of motor line-to-line voltage inversion. Based on the first gate duty cycle command for the current cycle, the first gate duty cycle command for the next cycle of the carrier, a changed polarity complement for the first gate duty cycle command for the next cycle is generated for the second gate duty cycle command for the current cycle and for the second gate duty cycle command for the next cycle. A switch of the inverter is operated according to the changed polarity complement of the first gate duty cycle command.

Description

Technical Field

[0001] The present disclosure relates to automotive power systems. Background Art

[0002] Cars can use electrical energy to power electric motors. The electric motors can convert this electrical energy into mechanical energy to propel the vehicle. Cars can include various power electronics to regulate and store the electrical energy. Summary of the invention

[0003] An automotive control system includes one or more controllers programmed to, in response to a carrier countdown during a current cycle, a first gate duty cycle command associated with a first phase for the current cycle being 1 and the first gate duty cycle command for a next cycle being less than 1, a second gate duty cycle command associated with a second phase for the current cycle being less than 1 and the second gate duty cycle command for the next cycle being 1, set the first gate duty cycle command for the next cycle to be equal to the complement of the first gate duty cycle command for the next cycle and change the polarity of the complement of the first gate duty cycle command to generate a changed polarity complement of the first gate duty cycle command and operate switches of an inverter according to the changed polarity complement of the first gate duty cycle command during the next cycle.

[0004] A method includes generating a changed polarity complement of the first gate duty cycle command for a next cycle based on a first gate duty cycle command for a current cycle, the first gate duty cycle command for a next cycle, a second gate duty cycle command for the current cycle, and the second gate duty cycle command for the next cycle. The method also includes operating switches of an inverter according to the changed polarity complement of the first gate duty cycle command.

[0005] A vehicle includes: a traction battery; a motor; an inverter electrically connected between the traction battery and the motor; and one or more controllers. The one or more controllers set the first gate duty cycle command for a next cycle of an asymmetric carrier to a predefined value based on a first gate duty cycle command for a current cycle of the asymmetric carrier and a second gate duty cycle command for the current cycle and the next cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of the vehicle.

[0007] Figure 2 , Figure 4 and Figure 6 It is a flow chart of the inverter gate control algorithm.

[0008] Figure 3A , Figure 5A and Fig. 7A are the carrier signal, gate signal and line voltage waveforms (unmodified).

[0009] Figure 3B , Figure 5B and Figure 7B They are respectively Figure 2 , Figure 4 and Figure 6 The carrier signal, gate signal and line-to-line voltage waveforms (modified) obtained by the algorithm. DETAILED DESCRIPTION

[0010] Embodiments are described herein. However, it should be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The drawings are not necessarily drawn to scale. Some features may be enlarged or minimized to show details of particular components. Therefore, the specific structural details and functional details disclosed herein should not be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art.

[0011] The various features shown and described with reference to any one of the accompanying drawings may be combined with features shown in one or more other drawings to produce embodiments not explicitly shown or described. The combinations of features shown provide representative embodiments for typical applications. However, for specific applications or implementations, various combinations and modifications of features consistent with the teachings of the present disclosure may be desired.

[0012] In automotive inverter control systems, pulse width modulation (PWM) is the basic technique used to regulate the voltage or current supplied to electric motors and various devices. The core of this method lies in a high-frequency waveform or carrier signal. This carrier signal acts as a reference signal and usually takes the form of a square or triangular wave with a fixed frequency known as the carrier frequency or switching frequency. This determines the update frequency of the control signal and affects the overall performance of the system.

[0013] The modulation signal operates in conjunction with a carrier signal. This signal represents a desired output voltage or current that varies based on the specific control requirements of the system. For example, in an electric vehicle, it might depict the desired motor speed or torque. The function of a PWM controller is to continuously compare the modulation signal to the carrier signal. This comparison determines how long the inverter's switching devices (usually transistors) should remain in the on (high) state or the off (low) state during each cycle of the carrier signal.

[0014] As a result of this comparison, the duty cycle is proposed. The duty cycle indicates the proportion of time that the PWM signal is in a high state (effectively on) during a carrier signal cycle. It reflects the current state of the modulation signal; for example, a high value in the modulation signal corresponds to a high duty cycle. This longer on-time duration during the carrier cycle results in a higher average output voltage or current, thereby maintaining consistency with the control requirements.

[0015] PWM control in the context of automotive applications provides precision. By continuously adjusting the duty cycle based on the modulation signal, the inverter can fine-tune the output voltage or current. This level of control is helpful in the context of things like electric vehicles, where accurate control of the speed and torque of the motor during operation is useful.

[0016] The choice of carrier frequency can affect system performance. Higher carrier frequencies result in smoother output waveforms and control resolution, but can increase switching losses. Conversely, lower frequencies improve efficiency but can introduce more harmonics in the output, affecting electromagnetic compatibility and potentially requiring additional filtering.

[0017] refer to Figure 1 The vehicle 10 includes a traction battery 12, a DC link capacitor 14, an inverter 16, an electric motor 18, and one or more controllers 20. The DC link capacitor 14 is electrically connected between the traction battery 12 and the inverter 16. The inverter 16 is electrically connected between the DC link capacitor 14 and the motor 18.

[0018] One or more controllers 20 generate gate signals that determine the turning on and off of the switches of the inverter 16, thereby generating power flow between the traction battery 12 and the motor 18. The terminal voltage of the motor 18 is controlled to a PWM voltage. The gate signals can be generated by comparing the duty cycle with a triangular carrier during each control cycle.

[0019] The PWM voltage has fast transients. During the transitions, a ringing effect can be observed. This ringing can stress the insulation of the motor 18. The most prominent case involves the voltage transitions between -Vdc and +Vdc.

[0020] From a physical point of view, the root cause of voltage reversal is the use of an effective voltage vector during state vector PWM and the use of a non-adjacent effective voltage vector immediately following it. As a result, both phases switch simultaneously and the line voltage reverses. In one example, the desired voltage vector travels along the edge of the voltage hexagon from one sector to a non-adjacent sector. Voltage reversal occurs whether counting up or down.

[0021] For practical implementations, the duty cycle command can be used to count up or down to detect voltage reversal. Voltage reversal occurs when the duty cycle and the up or down count meet either of two conditions. The carrier changes from counting up to counting down, the duty cycle of one phase changes from non-zero to 0, and the duty cycle of the other phase changes from 0 to non-zero (condition 1). The carrier changes from counting down to counting up, the duty cycle of one phase changes from 1 to less than 1, and the duty cycle of the other phase changes from less than 1 to 1 (condition 2).

[0022] When conditions 1 or 2 are met, the polarity of the PWM can be changed as a voltage reversal is about to occur. This allows a falling edge to be generated during the down count and a rising edge to be generated during the up count. The duty cycle command can be flipped so that the average voltage during the control cycle does not change. Therefore, voltage reversal is avoided, the average voltage during one control cycle remains unchanged, and voltage distortion is minimized.

[0023] For each of the following algorithms, which may be implemented by one or more controllers 20 , the duty cycle commands for each phase are first calculated using known motor control techniques.

[0024] refer to Figure 2 , at operation 22, it is determined whether the carrier signal is counting down during cycle k. If yes, at operation 24, it is determined whether the duty cycle Da(k) of phase A during cycle k is 1, and whether the duty cycle Da(k+1) of phase A during cycle k+1 will be less than 1. If no, at operation 26, the duty cycle and polarity of phase A are output to the inverter 16. If yes, at operation 28, it is determined whether the duty cycle Db(k) of phase B during cycle k is less than 1, and whether the duty cycle Db(k+1) of phase B during cycle k+1 will be 1. If no, at operation 30, it is determined whether the duty cycle Dc(k) of phase C during cycle k is less than 1, and whether the duty cycle Dc(k+1) of phase C during cycle k+1 will be 1. If no, the algorithm proceeds to operation 26. If yes, then at operation 32, Da(k+1) is set equal to (1-Da(k+1)), which is its complement. At operation 34, the polarity of (1-Da(k+1)) is changed. Then, the algorithm proceeds to operation 26. Returning to operation 28, if yes, the algorithm proceeds to operation 32.

[0025] Referring to operation 22, if no, at operation 36, it is determined whether Da(k) is 0 and whether Da(k+1) will be greater than 0. If no, the algorithm proceeds to operation 26. If yes, at operation 38, it is determined whether Db(k) is greater than 0 and whether Db(k+1) will be 0. If no, at operation 40, it is determined whether Dc(k) is greater than 0 and whether Dc(k+1) will be 0. If no, the algorithm proceeds to operation 26. If yes, at operation 42, Da(k+1) is set equal to (1-Da(k+1)). At operation 44, the polarity of (1-Da(k+1)) is changed. Then, the algorithm proceeds to operation 26. Returning to operation 38, if yes, the algorithm proceeds to operation 42.

[0026] The above algorithm is then performed for phases B and C. For phase B, references to Da are replaced with Db (e.g., Da(k+1) is replaced with Db(k+1)), references to Db are replaced with Dc (e.g., Db(k) is replaced with Dc(k)), and references to Dc are replaced with Da (e.g., Dc(k+1) is replaced with Da(k+1)). For phase C, references to Da are replaced with Dc, references to Db are replaced with Da, and references to Dc are replaced with Db.

[0027] refer to Figure 3A , assuming that the gate signal of phase C is 0 during cycle k and cycle k+1, it is shown that when not using Figure 2 The carrier signal, the gate signal for phase A, the gate signal for phase B, and the resulting line voltage Vab when reversed are shown in the algorithm of FIG. These are the duty cycle commands for each phase that are first calculated using known motor control techniques.

[0028] refer to Figure 3B , assuming that the gate signal of phase C is 0 during cycle k and cycle k+1, the carrier signal, the gate signal of phase A, and the gate signal of phase B are shown (due to Figure 2 The modified gate signal for phase B is generated by performing operations 22, 36, 40, 42, 44 when checking phase B) and the resulting line voltage Vab when there is no inversion. In this example, the modified gate signal for phase B is generated by performing operations 22, 36, 40, 42, 44 when checking phase B.

[0029] For symmetrical PWM applications, when a potential voltage reversal is detected, the polarity of the PWM is changed to allow a falling edge to be generated during the down count and a rising edge to be generated during the up count. The duty cycle command is also flipped so that the average voltage during the control cycle does not change. Therefore, voltage reversals are avoided, the average voltage during one control cycle remains constant, and voltage distortion is minimized.

[0030] refer to Figure 4(and assuming symmetrical PWM is used), at operation 46, it is determined whether Da(k) is 1 and whether Da(k+1) will be less than 1. If not, at operation 48, the duty cycle command for phase A, which is first calculated using known motor control techniques, is output to the inverter 16. If yes, at operation 50, it is determined whether Db(k) is less than 1 and whether Db(k+1) will be 1. If no, at operation 52, it is determined whether Dc(k) is less than 1 and whether Dc(k+1) will be 1. If no, the algorithm proceeds to operation 48. If yes, at operation 54, Da(k+1) is set equal to (1-Da(k+1)). At operation 56, the polarity of (1-Da(k+1)) is changed. Then, the algorithm proceeds to operation 48. Returning to operation 50, if yes, the algorithm proceeds to operation 54.

[0031] The above algorithm is then performed for Phase B and Phase C. For Phase B, references to Da are replaced with Db, references to Db are replaced with Dc, and references to Dc are replaced with Da. For Phase C, references to Da are replaced with Dc, references to Db are replaced with Da, and references to Dc are replaced with Db.

[0032] refer to Figure 5A , assuming that the gate signal of phase C is 0 during cycle k and cycle k+1, it is shown that when not using Figure 4 The carrier signal, the gate signal for phase A, the gate signal for phase B, and the resulting line voltage Vab when reversed are shown in the algorithm of FIG. These are the duty cycle commands for each phase that are first calculated using known motor control techniques.

[0033] refer to Figure 5B , assuming that the gate signal of phase C is 0 during cycle k and cycle k+1, the carrier signal, the gate signal of phase A (due to Figure 4 ), the gate signal of phase B and the resulting line voltage Vab without inversion. In this example, the modified gate signal of phase A is the result of performing operations 46, 50, 54, 56 when checking phase A.

[0034] When condition 1 is met and thus a voltage reversal is imminent, the minimum duty cycle command may be limited to be above 0. When condition 2 is met and thus a voltage reversal is imminent, the maximum duty cycle command may be limited to be below 1.

[0035] refer to Figure 6, at operation 58, it is determined whether the carrier signal is counting down during cycle k. If so, at operation 60, it is determined whether Da(k) is 1 and whether Da(k+1) will be less than 1. If not, at operation 62, phase B is checked. If yes, at operation 64, it is determined whether Db(k) is less than 1 and whether Db(k+1) will be 1. If not, at operation 66, it is determined whether Dc(k) is less than 1 and whether Dc(k+1) will be 1. If not, the algorithm proceeds to operation 62. If yes, at operation 68, Dc(k+1) is set to a predetermined maximum value. Then, the algorithm proceeds to operation 62. Returning to operation 64, if yes, at operation 70, Db(k+1) is set to a predetermined maximum value. Then, the algorithm proceeds to operation 62. The predetermined value may be determined via testing, simulation, etc., and may depend on system design and characteristics.

[0036] After operation 62, it is determined whether all phases have been checked. If not, the algorithm returns to operation 58. If yes, at operation 84, the duty cycle and polarity of the three phases are output to the inverter 16.

[0037] Returning to operation 58, if no, then at operation 72, determine if Da(k) is 0 and if Da(k+1) will be greater than 0. If no, then at operation 62, check phase B. If yes, then at operation 74, determine if Db(k) is greater than 0 and if Db(k+1) will be 0. If no, then at operation 76, determine if Dc(k) is greater than 0 and if Dc(k+1) will be 0. If no, then the algorithm proceeds to operation 62. If yes, then at operation 78, Dc(k+1) is set to a predetermined minimum value. Then, the algorithm proceeds to operation 62. Returning to operation 74, if yes, then at operation 80, Db(k+1) is set to a predetermined minimum value. Then, the algorithm proceeds to operation 62.

[0038] To check phase B, references to Da are replaced with Db, references to Db are replaced with Dc, and references to Dc are replaced with Da. To check phase C, references to Da are replaced with Dc, references to Db are replaced with Da, and references to Dc are replaced with Db.

[0039] refer to Fig. 7A , assuming that the gate signal of phase C is 1 during cycle k and cycle k+1, it is shown that when not using Figure 6 The carrier signal, the gate signal for phase A, the gate signal for phase B, and the resulting line voltage Vab when reversed are shown in the algorithm of FIG. These are the duty cycle commands for each phase that are first calculated using known motor control techniques.

[0040] refer to Figure 7B, assuming that the gate signal of phase C is 1 during cycle k and cycle k+1, the carrier signal, the gate signal of phase A (due to Figure 6 ), the gate signal of phase B, and the resulting line voltage Vab without inversion. In this example, the modified gate signal of phase A is the result of performing operations 72, 74, 76, 78 when checking phase B.

[0041] The algorithm, method or process disclosed herein can be delivered to or implemented by a computer, controller or processing device, which can include any dedicated electronic control unit or programmable electronic control unit. Similarly, the algorithm, method or process can be stored in various forms as data and instructions that can be executed by a computer or controller, including but not limited to information permanently stored on a non-writable storage medium such as a read-only memory device and information that can be modified and stored on a writable storage medium such as an optical disk, a random access memory device or other magnetic and optical media. The algorithm, method or process can also be implemented by a software executable object. Alternatively, a suitable hardware component (such as an application-specific integrated circuit, a field programmable gate array, a state machine or other hardware component or device) or a combination of firmware, hardware and software components can be used to embody the algorithm, method or process in whole or in part.

[0042] While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms encompassed by the claims.

[0043] The words used in the specification are descriptive rather than limiting, and it should be understood that various changes may be made without departing from the spirit and scope of these disclosed materials. For example, the terms "controller" and "controllers" may be used interchangeably herein because the functionality of a controller may be distributed across several controllers / modules that may all communicate via standard techniques.

[0044] As previously mentioned, the features of the various embodiments may be combined to form additional embodiments of the invention that may not be explicitly described or shown. Although various embodiments may have been described as providing advantages or being preferred over other embodiments or prior art implementations with respect to one or more desired characteristics, it will be appreciated by those of ordinary skill in the art that one or more features or characteristics may be compromised to achieve desired overall system properties, depending on the specific application and implementation. These properties may include, but are not limited to, strength, durability, marketability, appearance, packaging, size, serviceability, weight, manufacturability, ease of assembly, and the like. For this reason, embodiments described as being less desirable than other embodiments or prior art implementations with respect to one or more characteristics are not outside the scope of this disclosure and may be desirable for specific applications.

[0045] According to the present invention, an automobile control system is provided, which has: one or more controllers, the one or more controllers being programmed to, in response to a carrier counting down during a current cycle, a first gate duty cycle command associated with a first phase for the current cycle being 1 and the first gate duty cycle command for a next cycle being less than 1, and a second gate duty cycle command associated with a second phase for the current cycle being less than 1 and the second gate duty cycle command for the next cycle being 1, set the first gate duty cycle command for the next cycle to be equal to the complement of the first gate duty cycle command for the next cycle and change the polarity of the complement of the first gate duty cycle command to generate a changed polarity complement of the first gate duty cycle command and operate switches of an inverter according to the changed polarity complement of the first gate duty cycle command during the next cycle.

[0046] According to an embodiment, the one or more controllers are further programmed to generate the changed polarity complement of the first gate duty cycle command and operate the switch according to the changed polarity complement of the first gate duty cycle command during the next cycle in response to the carrier counting down during the current cycle, the first gate duty cycle command for the current cycle being 1 and the first gate duty cycle command for the next cycle being less than 1, the second gate duty cycle command for the current cycle being less than 1 and the second gate duty cycle command for the next cycle being less than 1, and the third gate duty cycle command associated with the third phase for the current cycle being less than 1 and the third gate duty cycle command for the next cycle being 1.

[0047] According to an embodiment, the one or more controllers are also programmed to generate the changed polarity complement of the first gate duty cycle command and operate the switches of the inverter according to the changed polarity complement of the first gate duty cycle command during the next cycle in response to the carrier counting up during the current cycle, the first gate duty cycle command for the current cycle being 0 and the first gate duty cycle command for the next cycle being greater than 0, and the second gate duty cycle command for the current cycle being greater than 0 and the second gate duty cycle command for the next cycle being 0.

[0048] According to an embodiment, the one or more controllers are further programmed to generate the changed polarity complement of the first gate duty cycle command and operate the switch according to the changed polarity complement of the first gate duty cycle command during the next cycle in response to the carrier counting up during the current cycle, the first gate duty cycle command for the current cycle being 0 and the first gate duty cycle command for the next cycle being greater than 0, the second gate duty cycle command for the current cycle being greater than 0 and the second gate duty cycle command for the next cycle being greater than 0, and the third gate duty cycle command associated with the third phase for the current cycle being greater than 0 and the third gate duty cycle command for the next cycle being 0.

[0049] According to an embodiment, the carrier is asymmetric.

[0050] According to an embodiment, the carrier is symmetrical.

[0051] According to the present invention, a method includes: generating a changed polarity complement of the first gate duty cycle command for the next cycle based on a first gate duty cycle command for a current cycle, the first gate duty cycle command for the next cycle, a second gate duty cycle command for the current cycle, and the second gate duty cycle command for the next cycle; and operating a switch of an inverter according to the changed polarity complement of the first gate duty cycle command.

[0052] In one aspect of the invention, the generating is further based on a third gate duty cycle command for the current cycle and the next cycle.

[0053] In one aspect of the present invention, the generating is further based on whether the third gate duty cycle command for the current cycle is less than 1 and whether the third gate duty cycle command for the next cycle is 1.

[0054] In one aspect of the present invention, the generating is further based on whether the first gate duty cycle command for the current cycle is 1 and whether the first gate duty cycle command for the next cycle is less than 1.

[0055] In one aspect of the present invention, the generating is further based on whether the second gate duty cycle command for the current cycle is less than 1 and whether the second gate duty cycle command for the next cycle is 1.

[0056] In one aspect of the present invention, the carriers defining the current cycle and the next cycle are symmetrical.

[0057] According to the present invention, a vehicle is provided, which has: a traction battery; a motor; an inverter, the inverter being electrically connected between the traction battery and the motor; and one or more controllers, the one or more controllers being programmed to set the first gate duty cycle command for a next cycle of an asymmetric carrier to a predefined value based on a first gate duty cycle command for a current cycle of the asymmetric carrier and a second gate duty cycle command for the current cycle and the next cycle.

[0058] According to an embodiment, the one or more controllers are further programmed to set the first gate duty cycle command for the next cycle to the predefined value based on the third gate duty cycle commands for the current cycle and the next cycle.

[0059] According to an embodiment, said predefined value is a maximum value.

[0060] According to an embodiment, said predefined value is a minimum value.

Claims

1. An automobile control system, comprising: One or more controllers programmed to, in response to a carrier counting down during a current cycle, a first gate duty cycle command associated with a first phase for the current cycle being 1 and the first gate duty cycle command for a next cycle being less than 1, and a second gate duty cycle command associated with a second phase for the current cycle being less than 1 and the second gate duty cycle command for the next cycle being 1, set the first gate duty cycle command for the next cycle to be equal to the complement of the first gate duty cycle command for the next cycle, change the polarity of the complement of the first gate duty cycle command to generate a changed polarity complement of the first gate duty cycle command and operate switches of an inverter according to the changed polarity complement of the first gate duty cycle command during the next cycle.

2. The automotive control system of claim 1 , wherein the one or more controllers are further programmed to generate the changed polarity complement of the first gate duty cycle command and operate the switch according to the changed polarity complement of the first gate duty cycle command during the next cycle in response to the carrier counting down during the current cycle, the first gate duty cycle command for the current cycle being 1 and the first gate duty cycle command for the next cycle being less than 1, the second gate duty cycle command for the current cycle being less than 1 and the second gate duty cycle command for the next cycle being less than 1, and a third gate duty cycle command associated with a third phase for the current cycle being less than 1 and the third gate duty cycle command for the next cycle being 1.

3. The automotive control system of claim 1 , wherein the one or more controllers are further programmed to generate the changed polarity complement of the first gate duty cycle command and operate the switches of the inverter according to the changed polarity complement of the first gate duty cycle command during the next cycle in response to the carrier counting up during the current cycle, the first gate duty cycle command for the current cycle being 0 and the first gate duty cycle command for the next cycle being greater than 0, and the second gate duty cycle command for the current cycle being greater than 0 and the second gate duty cycle command for the next cycle being 0.

4. The automotive control system of claim 3, wherein the one or more controllers are further programmed to generate the changed polarity complement of the first gate duty cycle command and operate the switch according to the changed polarity complement of the first gate duty cycle command during the next cycle in response to the carrier counting up during the current cycle, the first gate duty cycle command for the current cycle being 0 and the first gate duty cycle command for the next cycle being greater than 0, the second gate duty cycle command for the current cycle being greater than 0 and the second gate duty cycle command for the next cycle being greater than 0, and a third gate duty cycle command associated with a third phase for the current cycle being greater than 0 and the third gate duty cycle command for the next cycle being 0.

5. The automotive control system of claim 1, wherein the carrier wave is asymmetric.

6. The automotive control system of claim 1, wherein the carrier wave is symmetrical.

7. A method comprising: generating a changed polarity complement of the first gate duty cycle command for the next cycle based on the first gate duty cycle command for the current cycle, the first gate duty cycle command for the next cycle, the second gate duty cycle command for the current cycle, and the second gate duty cycle command for the next cycle; as well as Switches of an inverter are operated according to the changed polarity complement of the first gate duty cycle command.

8. The method of claim 7, wherein the generating is further based on a third gate duty cycle command for the current cycle and the next cycle. 9 . The method of claim 8 , wherein the generating is further based on whether the third gate duty cycle command for the current cycle is less than 1 and whether the third gate duty cycle command for the next cycle is 1. 10 . 10 . The method of claim 7 , wherein the generating is further based on whether the first gate duty cycle command for the current cycle is 1 and whether the first gate duty cycle command for the next cycle is less than 1. 11 . The method of claim 7 , wherein the generating is further based on whether the second gate duty cycle command for the current cycle is less than 1 and whether the second gate duty cycle command for the next cycle is 1.

12. The method of claim 7, wherein carriers defining the current cycle and the next cycle are symmetrical.

13. A vehicle comprising: Traction batteries; Motor; an inverter electrically connected between the traction battery and the motor; as well as One or more controllers programmed to set the first gate duty cycle command for a next cycle of an asymmetric carrier to a predefined value based on a first gate duty cycle command for a current cycle of the asymmetric carrier and a second gate duty cycle command for the current cycle and the next cycle.

14. The vehicle of claim 13, wherein the one or more controllers are further programmed to set the first gate duty cycle command for the next cycle to the predefined value based on the third gate duty cycle commands for the current cycle and the next cycle.

15. The vehicle of claim 13, wherein the predefined value is a maximum value or a minimum value.

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