Joint design method for predistorter and post-distorter

Abstract

The invention provides a joint design method for a predistorter and a post-distorter. The joint design method comprises the steps of setting system parameters, obtaining expected output of the predistorter and real output of a power amplifier, designing the predistorter, designing the post-distorter and the like. According to the method, on the basis of system parameter configuration, an iterative learning control theory is adopted to obtain expected output of a predistorter and real output of a power amplifier, then based on the expected output of the predistorter, a sparse memory polynomial model is adopted to design the predistorter, and finally, the real output of the power amplifier is combined to design the predistorter. The sparse memory polynomial model is adopted to design the post-distorter, so that the design complexity of the pre-distorter is reduced, the error rate of signal detection is reduced, and the system performance is improved.

Description

Technical Field

[0001] The invention relates to a method for eliminating nonlinear distortion of a power amplifier, and in particular to a method for jointly designing a predistorter and a postdistorter. Background Art

[0002] As an indispensable component in modern wireless communication systems, power amplifiers (PAs) will cause nonlinear distortion of signals when converting low-power signals into high-power signals, especially in orthogonal frequency division multiplexing (OFDM) systems. The high peak-to-average power ratio of OFDM signals inevitably causes PA to introduce nonlinear distortion, resulting in a decrease in signal quality. Therefore, it is necessary to eliminate the nonlinear distortion of signals caused by PA. Among them, signal predistortion is an important method to eliminate nonlinear distortion. To this end, a variety of predistorter design methods have been proposed (see Hu Jie's "A Direct MP Model Predistortion Scheme Based on Memory Polynomial RF Power Amplifier" 2016 "Electronic Devices" No. 6; Zeng Dejun's "Design of Digital Predistorter Based on New Parallel LMS Algorithm" 2022 "Communication Technology" No. 6; Ericsson's "Iterative Learning Control for RF Power Amplifier Linearization" 2016 "IEEE Transactions on Microwave Theory Techniques"), these methods can effectively eliminate the nonlinear deformation caused by PA.

[0003] However, these predistorters designed based on polynomial models have the problem of too many parameters and complex design methods. In addition, these predistorters cannot completely eliminate the nonlinear deformation generated by the PA, and there is still a certain amount of residual nonlinear deformation in their output signals. The above problems will lead to two deficiencies: first, the design of the predistorter is complex, which affects the efficiency of real-time signal processing; second, the residual nonlinear deformation will also increase the bit error rate of the detection signal at the receiving end, reducing the performance of the communication system. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies in the above-mentioned prior art and to provide a joint design method of a pre-distorter and a post-distorter.

[0005] The present invention provides a method for jointly designing a pre-distorter and a post-distorter, comprising the following steps:

[0006] Step 1: Set the signal length to N, the nonlinear series to D, the delay series to Q, and the maximum delay τ Q, the initial input signal x, where x = [x(0), x(1), …, x(N - 1)] T , the desired input signal z0 of the predistorter, z0 = x, the initial output signal u0 of the power amplifier, the adjustment factor β of the desired output signal of the power amplifier, the desired output signal of the power amplifier is u = βx, the adjustment factor γ of the desired output signal of the postdistorter, the desired output signal rate amplifier of the postdistorter is y = γx, the number of iterations T, the initial learning matrix A0 = 0, where, a T represents the transpose of the vector a;

[0007] Step Two: Design the desired output signal of the predistorter using iterative learning control theory;

[0008] Step Three: Model the predistorter based on the sparse memory polynomial model to obtain the non - linear coefficient vector α of the predistorter;

[0009] Step Four: Model the postdistorter based on the sparse memory polynomial model to obtain the non - linear coefficient vector θ of the modulus of the predistorter.

[0010] Further, the specific steps of Step Two are as follows:

[0011] Step 1) Initialization: The desired output signal z0 of the predistorter, the initial desired output signal u0 of the power amplifier = 0, the desired output signal u of the power amplifier, the initial learning matrix A0 = 0, the iteration counter t = 0, the maximum number of iterations T;

[0012] Step 2) t = t + 1;

[0013] Step 3) Calculate the desired error e t-1 = u - u t-1 ;

[0014] Step 4) Update the desired output signal z of the predistorter t = z t-1 + A t-1 -1 e t-1 ;

[0015] Step 5) Obtain the actual output u of the power amplifier according to z t ; t ;

[0016] Step 6) Update the learning matrix

[0017] Step 7) If t < T, go to Step 2);

[0018] Step 8) Output the final estimation result zT and the actual output u of the power amplifier T .

[0019] Further, the step three specifically includes the following steps:

[0020] The predistorter is constructed using a sparse memory polynomial model. The expected output signal z of the predistorter is T The nth element z in T (n) is expressed as:

[0021]

[0022] Where n = 0, 1, ..., N-1, α 2d-1,q It means that the predistorter has a nonlinear order of 2d-1 and a delay of τ q The coefficients on τ1<τ2<…<τ Q ,function The expression is:

[0023] G d,q (n) = x(n-τ q )|x(n-τ q )| 2(d-1)

[0024] Among them, x(n-τ q ) is the n-τth q elements;

[0025] The measurement matrix G is composed of the following formula:

[0026]

[0027] At this time, based on the constructed measurement matrix G, the nonlinear coefficient vector α of the predistorter, α =

[0028] [α 1,0 ,α 3,0 ,…,α 2D-1,0 ,…,α 1,1 ,α 3,1 ,…,α 2D-1,Q ] T The orthogonal matching pursuit method can be used to obtain the following equation:

[0029] α=argmin‖α‖1s.tz T =Gα

[0030] Among them, ‖α‖1 represents the 1-norm of vector α.

[0031] Further, the step 4 specifically includes the following steps:

[0032] The predistorter is constructed using a sparse memory polynomial model, and the nth element y(n) in the output signal y of the postdistorter is expressed as:

[0033]

[0034] Among them, θ 2d-1,q It means that the post-distorter has a nonlinear order of 2d-1 and a delay of τ q The coefficients on the function F d,q The expression of (n) is:

[0035] F d,q (n) = u t (n-τ q )|u t (n-τ q )| 2(d-1)

[0036] Among them, u t (n-τ q ) is the input signal u t The n-τ q elements;

[0037] The matrix F is composed of the following formula:

[0038]

[0039] At this time, based on the constructed matrix F, the nonlinear coefficient vector θ of the post-distorter is θ=

[0040] [θ 1,0 ,θ 3,0 ,…,θ 2D-1,0 ,…,θ 1,1 ,θ 3,1 ,…,θ 2D-1,Q ] T The orthogonal matching pursuit method can be used to obtain the following equation:

[0041] θ=argmin‖θ‖1s.ty=Gθ.

[0042] The beneficial effects of the present invention are as follows: in order to solve the problems that the existing pre-distorter adopts too many model parameters, resulting in a complicated design method, and the residual nonlinear deformation increases the bit error rate of the detection signal at the receiving end, a joint design method of a pre-distorter and a post-distorter is proposed. The proposed method first adopts iterative learning control theory to design the expected output of the pre-distorter, then adopts a sparse memory polynomial model to design the pre-distorter through the orthogonal matching pursuit method, and finally, according to the output of the power amplifier, the sparse memory polynomial model is also used to design the post-distorter. Examples show that this method has lower computational complexity than the existing methods, and can effectively eliminate the nonlinear deformation caused by the power amplifier and improve the performance of the communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the connection relationship between the pre-distorter, the post-distorter and the power amplifier;

[0044] Figure 2 is a flow chart of the method of the present invention;

[0045] Figure 3 The figure is a comparison chart of the data bit error rate obtained by the proposed method and the comparative method. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with the accompanying drawings and examples of the present invention.

[0047] The present invention is achieved by the following steps: Figure 1 As shown in FIG, the predistorter is placed before the power amplifier to predistort the signal; the postdistorter is placed after the power amplifier to process the residual nonlinear deformation of the power amplifier output signal. Figure 2 As shown in Figure 1, first set the system parameters according to actual needs, and then use iterative learning control theory to design the desired output signal z of the predistorter. t , then based on the signal z t , a pre-distorter is constructed using a sparse memory polynomial model to obtain the nonlinear coefficient vector α of the pre-distorter, and finally a post-distorter is constructed using a sparse memory polynomial model to obtain the nonlinear coefficient vector θ of the post-distorter. The specific description is as follows:

[0048] Step 1: System parameter settings are as follows:

[0049] The initial input signal is x = [x(0), x(1), ..., x(N-1)] T, the expected input signal of the predistorter is z0=x, the initial output signal of the power amplifier is u0, the adjustment factor of the expected output signal of the power amplifier is β, the expected output signal of the power amplifier is u=βx, the adjustment factor of the expected output signal of the postdistorter is γ, the expected output signal of the postdistorter is y=γx, and the number of iterations is T, the initial learning matrix A0=0, the signal length is N, the nonlinear series is D, the delay series is Q, and the maximum delay is τ Q , where a T represents the transpose of vector a;

[0050] Step 2: Use iterative learning control theory to design the desired output signal of the predistorter;

[0051] Iterative learning control theory can design the expected output signal of the predistorter according to the expected output signal of the power amplifier without knowing the characteristics of the power amplifier. Using this theory, the expected output signal of the predistorter can be designed through the following steps. Assuming that the t-1th iteration has been completed, the actual output signal of the power amplifier of the t-1th iteration is u t-1 , at this time, the error between it and the expected output signal u of the power amplifier is

[0052] e t-1 =uu t-1

[0053] Then based on the z obtained in the t-1th iteration t-1 and A t-1 , update the expected output z of the predistorter according to the following formula t

[0054] z t =z t-1 +A t-1 -1 e t-1

[0055] Based on the expected output of the predistorter, the actual output signal u of the power amplifier is obtained t , and update each element in the learning matrix using the following formula

[0056]

[0057] After T iterations, the final predistorter expected output signal z can be obtained. T This can be achieved through the following steps:

[0058] Step 1) Initialization: expected output signal z0 of the predistorter, expected output signal u0=0 of the initial power amplifier, expected output signal u of the power amplifier, initial learning matrix A0=0, iteration counter t=0, maximum number of iterations T;

[0059] Step 2) t = t + 1;

[0060] Step 3) Calculate the expected error e t-1 = u - u t-1 ;

[0061] Step 4) Update the expected output signal z of the predistorter t = z t-1 + A t-1 -1 e t-1 ;

[0062] Step 5) Obtain the actual output u of the power amplifier according to z t ; t ;

[0063] Step 6) Update the learning matrix

[0064] Step 7) If t < T, go to Step 2);

[0065] Step 8) Output the final estimation result z T and the actual output u of the power amplifier T .

[0066] Step 3: Construct the predistorter using the sparse memory polynomial model;

[0067] Construct the predistorter using the sparse memory polynomial model. At this time, the nth element z T in the expected output signal z of the predistorter is expressed as: T

[0068]

[0069] where n = 0, 1,..., N - 1, x(n - τ q ) is the (n - τ q )th element in the input signal x, α 2d-1,q represents the coefficient of the predistorter at the non - linear order 2d - 1 and delay τ q , τ1 < τ2 <... < τ Q , define the function The expression is:

[0070] G d,q (n) = x(n - τ q )|x(n - τ q )| 2(d-1)

[0071] Construct the measurement matrix G through the following formula:

[0072]

[0073] At this time, based on the constructed measurement matrix G, the output signal of the predistorter can be expressed in matrix form, as shown in the following formula:

[0074] z T =Gα

[0075] Where α=[α 1,0 ,α 3,0 ,…,α 2D-1,0 ,…,α 1,1 ,α 3,1 ,…,α 2D-1,Q ] T is a vector of nonlinear coefficients of the predistorter. According to the sparse memory polynomial model, α is only valid at a specific delay τ q There are non-zero values ​​on , and the rest of the element values ​​are zero, so α is sparse, and the orthogonal matching pursuit method can be used to solve α, which is obtained by solving the following formula:

[0076] α=argmin‖α‖1 stz T =Gα

[0077] Among them, ‖α‖1 represents the 1-norm of vector α.

[0078] Step 4: construct the post-distorter using the sparse memory polynomial model;

[0079] After the pre-distorter is processed, the nonlinear deformation generated by the power amplifier has been eliminated to a certain extent, but there is still some nonlinear deformation in its output signal that cannot be completely eliminated by the pre-distorter. In order to further eliminate the residual nonlinear deformation, a sparse memory polynomial model is used to construct a post-distorter. At this time, the nth element y(n) in the output signal y of the post-distorter is expressed as:

[0080]

[0081] Among them, u T (n-τ q ) is the input signal u T The n-τ q elements, θ 2d-1,q It means that the post-distorter has a nonlinear order of 2d-1 and a delay of τ q The coefficients on the function F d,q (n) is:

[0082] F d,q (n) = u T (n-τ q )|u T (n-τq )| 2(d-1)

[0083] The matrix F is constructed by the following formula:

[0084]

[0085] At this time, based on the constructed measurement matrix F, the output signal of the post-distorter can be expressed in matrix form as shown below:

[0086] y=Fθ

[0087] Where θ=[θ 1,0 ,θ 3,0 ,…,θ 2D-1,0 ,…,θ 1,1 ,θ 3,1 ,…,θ 2D-1,Q ] T is a vector of nonlinear coefficients of the post-distorter. According to the sparse memory polynomial model, θ is also sparse, and the orthogonal matching pursuit method can also be used to solve θ, which is obtained by solving the following formula:

[0088] θ=argmin‖θ‖1 sty=Gθ

[0089] The proposed method makes full use of the sparse characteristics of the sparse memory polynomial model, significantly reduces the number of model parameters, reduces the design complexity of the pre-distorter, and improves the efficiency of the system in real-time signal processing. In addition, the post-distorter is designed to further eliminate the residual nonlinear deformation in the signal, thereby reducing the bit error rate of the detection signal at the receiving end and improving the system performance.

[0090] Example: Simulation experiment of joint design of pre-distorter and post-distorter

[0091] Experiment: In the simulation experiment, an orthogonal frequency division multiplexing system with orthogonal phase shift coding is used. In order to avoid the randomness of the test results, the present invention conducts a total of 500 random experiments. In each experiment, the present invention randomly generates an input signal x. The parameters of the power amplifier used in the simulation are shown in Table 1, where the nonlinear order D = 2, the delay order Q = 100, and the delay τ q The values ​​of are 1, 10, 50 and 100 respectively. In order to verify the effectiveness of the method, the present invention conducts the following simulation experiments.

[0092] Table 1: Nonlinear parameters of power amplifiers

[0093]

[0094] Simulation 1: In order to verify that the proposed method can effectively reduce the design complexity of the predistorter, the present invention conducts the following simulation experiments.

[0095] The present invention compares the proposed method with Ericsson's method (for specific methods, see Ericsson's "Iterative learning control for RF power amplifier linearization"), and illustrates that the proposed method has lower computational complexity by comparing the number of complex multiplications required for predistorter design by the two methods. The present invention uses signals of different lengths to calculate the number of complex multiplications required for designing a predistorter, and the specific comparison results are shown in Table 2. As can be seen from Table 2, when the value of N is 128, 256, 512 and 1024, the computational complexity required by the proposed method is lower than that of the comparison method, which illustrates that the proposed method can effectively reduce the difficulty required for predistorter design.

[0096] Table 2: Comparison of computational complexity results

[0097] method N＝128 N＝256 N＝512 N＝1024 Proposed method <![CDATA[2.081×10 7 ]]> <![CDATA[4.596×10 7 ]]> <![CDATA[1.843×10 8 ]]> <![CDATA[1.166×10 9 ]]> Comparison Method <![CDATA[2.914×10 6 ]]> <![CDATA[2.040×10 7 ]]> <![CDATA[1.502×10 8 ]]> <![CDATA[1.144×10 9 ]]>

[0098] Simulation 2: In order to verify that the proposed method can reduce the bit error rate of signal detection, the following experiment is carried out.

[0099] In 500 random experiments, 5000 signals of length N=256 were transmitted to the receiving end for bit error rate detection. The present invention also compares the proposed method with Ericsson's method (for specific methods, see Ericsson's "Iterative learning control for RF power amplifier linearization"). The specific bit error rate comparison results are as follows: Figure 3 As shown. Figure 3 It can be seen that with the increase of signal-to-noise ratio, the bit error rate of the proposed method becomes lower and lower, which shows that the proposed method can effectively eliminate the nonlinear deformation caused by the power amplifier, thereby improving the system performance. Compared with the comparison method, the results in the figure show that the bit error rate of the proposed method is lower, which shows that the proposed method can eliminate the nonlinear deformation caused by the power amplifier better than the comparison method, thereby making the bit error rate detected by the receiving end lower.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or some technical features can be replaced by equivalents without departing from the spirit of the technical solution of the present invention, which should be included in the scope of the technical solution for protection of the present invention.

Claims

1. A method for joint design of a pre-distorter and a post-distorter, characterized in that: It includes the following steps: Step 1: Set the signal length to N, the nonlinear series to D, the delay series to Q, and the maximum delay τ Q , initial input signal x, x=[x(0),x(1),…,x(N-1)] T , the expected input signal of the predistorter is z0, z0 = x, the initial output signal of the power amplifier is u0, the adjustment factor of the expected output signal of the power amplifier is β, the expected output signal of the power amplifier is u = βx, the adjustment factor of the expected output signal of the postdistorter is γ, the expected output signal of the postdistorter is y = γx, the number of iterations is T, the initial learning matrix A0 = 0, where a T represents the transpose of vector a; Step 2: Design the desired output signal of the predistorter using the iterative learning control theory; Step 3: Model the predistorter based on the sparse memory polynomial model to obtain the nonlinear coefficient vector α of the predistorter; Step 4: Model the postdistorter based on the sparse memory polynomial model to obtain the nonlinear coefficient vector θ of the modulus of the predistorter.

2. The method for joint design of a pre-distorter and a post-distorter according to claim 1, characterized in that: The specific content of Step 2 is as follows: The specific steps of designing the desired output signal of the predistorter using the iterative learning control theory in Step 2 are as follows: Step 1) Initialization: The desired output signal z0 of the predistorter, the initial desired output signal u0 of the power amplifier = 0, the desired output signal u of the power amplifier, the initial learning matrix A0 = 0, the iteration counter t = 0, and the maximum number of iterations T; Step 2) t = t + 1; Step 3) Calculate the expected error e t-1 =uu t-1 ; Step 4) Update the expected output signal z of the predistorter t =z t-1 +A t-1 -1 e t-1 ; Step 5) According to z t Get the real output u of the power amplifier t ; Step 6) Update the learning matrix Step 7) If t < T, go to Step 2); Step 8) Output the final estimated result z T and the actual output u of the power amplifier T .

3. The method for joint design of a pre-distorter and a post-distorter according to claim 1, characterized in that: The specific content of Step 3 is as follows: The predistorter is constructed using a sparse memory polynomial model. The expected output signal z of the predistorter is T The nth element z in T (n) is expressed as: Where n = 0, 1, ..., N-1, α 2d-1,q It means that the predistorter has a nonlinear order of 2d-1 and a delay of τ q The coefficients on τ1<τ2<…<τ Q ,function The expression is: G d,q (n)=x(n-τ q )|x(n-τ q )| 2(d-1) Among them, x(n-τ q ) is the n-τth q elements; The measurement matrix G is composed of the following formula: At this time, based on the constructed measurement matrix G, the nonlinear coefficient vector α of the predistorter, α = [α 1,0 ,α 3,0 ,…,α 2D-1,0 ,…,α 1,1 ,α 3,1 ,…,α 2D-1,Q ] T The orthogonal matching pursuit method can be used to obtain the following equation: α=argmin‖α‖1s.tz T =Gα where, ‖α‖1 represents the 1-norm of the vector α.

4. The method for joint design of a pre-distorter and a post-distorter according to claim 1, characterized in that: The specific content of Step 4 is as follows: Construct a predistorter using the sparse memory polynomial model. The nth element y(n) in the output signal y of the postdistorter is expressed as: Among them, θ 2d-1,q It means that the post-distorter has a nonlinear order of 2d-1 and a delay of τ q The coefficients on the function F d,q The expression of (n) is: F d,q (n)=u t (n-t q )|u t (n-t q )| 2(d-1) Among them, u t (n-τ q ) is the input signal u t The n-τ q elements; The matrix F is composed of the following formula: At this time, based on the constructed matrix F, the nonlinear coefficient vector θ of the post-distorter is θ=[θ 1,0 ,θ 3,0 ,…,θ 2D-1,0 ,…,θ 1,1 ,θ 3,1 ,…,θ 2D-1,Q ] T The orthogonal matching pursuit method can be used to obtain the following equation: θ = argmin ‖θ‖1 s.t. y = Gθ.

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