A high-frequency digital phase-locked amplifier based on parallel digital algorithm and a control method thereof

Abstract

The application discloses a high-frequency digital phase-locked amplifier based on a parallel digital algorithm and a control method. The amplifier comprises an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module. The method comprises the following steps: obtaining an analog input signal and a reference signal and performing sampling processing; performing serial-to-parallel conversion processing on the sampled digital input signal and the digital reference signal; performing frequency measurement on the N-parallel digital reference signal to obtain reference signal frequency measurement information; performing phase-locked regulation on the N-parallel digital reference signal to obtain frequency information and phase information; and performing demodulation processing on the N-parallel digital input signal to obtain amplitude information, phase information and XY component information of the digital input signal. The embodiment of the application can reduce the rate of data flow and improve the throughput of data information, thereby improving the bandwidth of the phase-locked amplification system. The application can be widely applied to the technical field of phase-locked amplification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phase-locked amplification, and particularly relates to a high-frequency digital phase-locked amplifier based on a parallel digital algorithm and a control method. BACKGROUND

[0002] Phase-locked amplification technology is an important technology in the field of weak signal detection, which can extract signals in a specific frequency band under strong background noise based on the principle of cross-correlation operation, and is widely used in the fields of biology, medicine, optics and electricity. The bandwidth of the phase-locked amplifier directly determines the frequency range that the phase-locked amplifier can process, which is a very critical parameter. For a digital phase-locked amplifier, this parameter is mainly limited by the rate of the digital-to-analog converter, the analog-to-digital converter and the digital processing module.

[0003] In the related art digital phase-locked amplifier, the input signal is collected into the FPGA through the analog-to-digital converter, the reference signal is converted into a square wave through a sine-to-square wave module, or the reference signal is triggered and phase-shifted in the analog domain, and then collected into a digital signal for processing. The data stream is consistent with the sampling rate of the analog-to-digital converter, and the digital part is processed through a serial algorithm. Since the processing frequency of the FPGA is generally up to 300-400MHz, the data stream is also up to 300-400MHz, thereby causing the bandwidth of the phase-locked amplifier in the related art to be limited by the frequency, which reduces the frequency range of the signals that the phase-locked amplifier can measure.

[0004] In summary, the technical problems in the related art need to be improved. SUMMARY

[0005] The main purpose of the embodiments of the present application is to provide a high-frequency digital phase-locked amplifier based on a parallel digital algorithm and a control method, which can reduce the rate of the data stream and improve the throughput of the data information, thereby improving the bandwidth of the phase-locked amplification system.

[0006] To achieve the above object, one aspect of the embodiment of the present application proposes a high-frequency digital phase-locked amplifier based on parallel digital algorithm, which comprises an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module. The output end of the analog-to-digital converter module is connected with the input end of the serial-to-parallel module. The first output end of the serial-to-parallel module is connected with the input end of the N-parallel frequency measurement module. The second output end of the serial-to-parallel module is connected with the first input end of the N-parallel phase-locked loop module. The output end of the N-parallel frequency measurement module is connected with the second input end of the N-parallel phase-locked loop module. The third output end of the serial-to-parallel module is connected with the first input end of the N-parallel input coherent demodulation module. The output end of the N-parallel phase-locked loop module is connected with the second input end of the N-parallel input coherent demodulation module. Wherein:

[0007] The analog-to-digital converter module is used for acquiring an analog input signal and a reference signal and performing sampling processing to obtain a sampled digital input signal and a sampled digital reference signal.

[0008] The serial-to-parallel module is used for performing serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain an N-parallel digital input signal and an N-parallel digital reference signal.

[0009] The N-parallel frequency measurement module is used for performing frequency measurement on the N-parallel digital reference signal to obtain reference signal frequency measurement information.

[0010] The N-parallel phase-locked loop module is used for performing phase-locked adjustment on the N-parallel digital reference signal according to the reference signal frequency measurement information to obtain reference signal frequency information and reference signal phase information.

[0011] The N-parallel input coherent demodulation module is used for performing demodulation processing on the N-parallel digital input signal according to the reference signal frequency information and the reference signal phase information to obtain digital input signal amplitude information, digital input signal phase information and digital input signal XY component information.

[0012] In some embodiments, the N-parallel frequency measurement module comprises an N-parallel pipeline type zero-crossing detector, a delay compensation module, an N-parallel rising edge detection module, an N-parallel pipeline type frequency divider, and an N-parallel pipeline type counter, a first output terminal of the N-parallel pipeline type zero-crossing detector is connected with an input terminal of the delay compensation module, a second output terminal of the N-parallel pipeline type zero-crossing detector is connected with a first input terminal of the N-parallel rising edge detection module, an output terminal of the delay compensation module is connected with a second input terminal of the N-parallel rising edge detection module, an output terminal of the N-parallel rising edge detection module is connected with an input terminal of the N-parallel pipeline type frequency divider, and an output terminal of the N-parallel pipeline type frequency divider is connected with an input terminal of the N-parallel pipeline type counter, wherein:

[0013] The N-parallel pipeline type zero-crossing detector is configured to perform zero-crossing detection on the N-parallel digital reference signal to obtain an N-parallel square wave reference signal.

[0014] The delay compensation module and the N-parallel rising edge detection module are configured to perform conversion processing on the N-parallel square wave reference signal to obtain an N-parallel pulse reference signal.

[0015] The N-parallel pipeline type frequency divider is configured to perform frequency division on the N-parallel pulse reference signal according to a frequency division coefficient to obtain a frequency-divided N-parallel pulse reference signal.

[0016] The N-parallel pipeline type counter is configured to count the frequency-divided N-parallel pulse reference signal to obtain the reference signal frequency measurement information.

[0017] In some embodiments, the N-parallel pipeline type zero-crossing detector comprises a first-stage delay compensation module, a hysteresis comparator, a second-stage delay compensation module, and a hysteresis decision device, the first-stage delay compensation module, the hysteresis comparator, the second-stage delay compensation module, and the hysteresis decision device are connected in sequence, wherein:

[0018] The first-stage delay compensation module is configured to perform first compensation processing on the N-parallel digital reference signal to obtain a preliminary compensation N-parallel digital reference signal.

[0019] The hysteresis comparator is configured to compare the preliminary compensation N-parallel digital reference signal to obtain a compared N-parallel digital reference signal.

[0020] The second-stage delay compensation module is configured to perform second compensation processing on the compared N-parallel digital reference signal to obtain a compensation N-parallel digital reference signal.

[0021] The hysteresis decision device is configured to make a decision on the compensation N-parallel digital reference signal to obtain the N-parallel square wave reference signal.

[0022] In some embodiments, the N parallel phase-locked loop module comprises an N parallel reference coherent demodulation module, a frequency locker and a phase locker, which are connected in sequence, and the output end of the frequency locker and the output end of the phase locker are connected with the input end of the N parallel reference coherent demodulation module, wherein:

[0023] The frequency locker is used to obtain the frequency information of the reference signal frequency measurement information;

[0024] The phase locker is used to obtain the phase information of the reference signal frequency measurement information;

[0025] The N parallel reference coherent demodulation module is used to coherently demodulate the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal;

[0026] The frequency locker and the phase locker are also used to adjust according to the phase information of the reference signal and the reference signal frequency measurement information to obtain the frequency information of the reference signal.

[0027] In some embodiments, the N parallel reference coherent demodulation module comprises a first N parallel digital frequency synthesizer, a first N parallel pipeline multiplier, a first N parallel pipeline low-pass filter and an N parallel arctangent angle operation module, which are connected in sequence, wherein:

[0028] The first N parallel digital frequency synthesizer is used to synthesize the frequency information and the phase information to obtain N parallel quadrature triangular signals;

[0029] The first N parallel pipeline multiplier is used to multiply the N parallel quadrature triangular signals and the N parallel digital reference signal to obtain N parallel reference signal product operation results;

[0030] The first N parallel pipeline low-pass filter is used to filter out the double frequency term of the N parallel reference signal product operation results to obtain the XY component information of the reference signal;

[0031] The N parallel arctangent angle operation module is used to perform arctangent angle operation on the XY component information of the reference signal to obtain the phase information of the reference signal.

[0032] In some embodiments, the N-parallel input coherent demodulation module comprises a second N-parallel digital frequency synthesizer, a second N-parallel pipeline multiplier, a second N-parallel pipeline low-pass filter, and an N-parallel arctangent modulo operation module, which are connected in sequence, wherein:

[0033] The second N-parallel digital frequency synthesizer is configured to perform a synthesis process on the phase information of the reference signal and the frequency information of the reference signal to obtain N-parallel same-frequency and same-phase quadrature triangular signals.

[0034] The second N-parallel pipeline multiplier is configured to perform a multiplication operation on the N-parallel same-frequency and same-phase quadrature triangular signals and the N-parallel digital input signals to obtain N-parallel digital input signal multiplication results.

[0035] The second N-parallel pipeline low-pass filter is configured to filter out a double-frequency term from the N-parallel digital input signal multiplication results to obtain XY component information of the digital input signals.

[0036] The N-parallel arctangent modulo operation module is configured to perform an arctangent modulo operation on the XY component information of the digital input signals to obtain amplitude information of the digital input signals, phase information of the digital input signals, and XY component information of the digital input signals.

[0037] To achieve the above object, another aspect of the embodiment of the present application proposes a control method of a high-frequency digital phase-locked amplifier based on a parallel digital algorithm, which comprises the following steps:

[0038] An analog input signal and a reference signal are acquired and sampled to obtain a sampled digital input signal and a sampled digital reference signal.

[0039] The sampled digital input signal and the sampled digital reference signal are subjected to serial-to-parallel processing to obtain an N-parallel digital input signal and an N-parallel digital reference signal.

[0040] The N-parallel digital reference signal is subjected to frequency measurement to obtain reference signal frequency measurement information.

[0041] The N-parallel digital reference signal is subjected to phase-locked adjustment according to the reference signal frequency measurement information to obtain frequency information of the reference signal and phase information of the reference signal.

[0042] According to the frequency information of the reference signal and the phase information of the reference signal, the N parallel digital input signals are demodulated to obtain the amplitude information of the digital input signal, the phase information of the digital input signal, and the XY component information of the digital input signal.

[0043] In some embodiments, the frequency measurement on the N parallel digital reference signals to obtain the reference signal frequency measurement information comprises:

[0044] Zero-crossing detection is performed on the N parallel digital reference signals to obtain N parallel square wave reference signals;

[0045] Conversion processing is performed on the N parallel square wave reference signals to obtain N parallel pulse reference signals;

[0046] The N parallel pulse reference signals are divided by a frequency division coefficient to obtain divided N parallel pulse reference signals;

[0047] The divided N parallel pulse reference signals are counted to obtain the reference signal frequency measurement information.

[0048] In some embodiments, the phase-locked regulation on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain the frequency information of the reference signal and the phase information of the reference signal comprises:

[0049] The frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information are obtained;

[0050] The frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information are coherently demodulated to obtain the phase information of the reference signal;

[0051] The reference signal frequency information is obtained according to the phase information of the reference signal and the reference signal frequency measurement information.

[0052] In some embodiments, the demodulation processing on the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal, and the XY component information of the digital input signal comprises:

[0053] Synthesis processing is performed on the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel same-frequency and same-phase quadrature triangular signals;

[0054] The N parallel same-frequency and same-phase quadrature triangular signals are multiplied by the N parallel digital input signals to obtain N parallel digital input signal multiplication results;

[0055] The N parallel digital input signal product operation results are filtered to obtain XY component information of the digital input signal;

[0056] The XY component information of the digital input signal is subjected to an inverse tangent modulo operation to obtain amplitude information of the digital input signal, phase information of the digital input signal, and XY component information of the digital input signal.

[0057] The present application provides a high-frequency digital phase-locked amplifier based on a parallel digital algorithm and a control method. The input signal and the reference signal are sampled and serial-to-parallel processed by an analog-to-digital converter module and a serial-to-parallel module, realizing conversion of a serial analog signal into N parallel digital signals, reducing the rate of data flow, further frequency measurement of the N parallel digital reference signal by an N parallel frequency measurement module, and phase-locked regulation of the N parallel digital reference signal according to the reference signal frequency measurement information by an N parallel phase-locked loop module. Finally, the N parallel digital input signal is demodulated by an N parallel input coherent demodulation module, so that the equivalent running frequency of the digital module can be N times the highest rate of FPGA running, and for modules with data dependency and modules requiring multi-cycle operation, a pipeline structure is adopted, so that the throughput is also improved, and the bandwidth of the phase-locked amplification system is improved. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1 is a module structure schematic diagram of a high-frequency digital phase-locked amplifier based on a parallel digital algorithm provided by the present application;

[0059] Figure 2 is a step flowchart schematic diagram of a control method of a high-frequency digital phase-locked amplifier based on a parallel digital algorithm provided by the present application;

[0060] Figure 3 is a framework principle schematic diagram of a high-frequency digital phase-locked amplifier provided by the present application;

[0061] Figure 4 is a structure principle schematic diagram of an N parallel frequency measurement module provided by the present application;

[0062] Figure 5 is a structure principle schematic diagram of an N parallel phase-locked loop module provided by the present application;

[0063] Figure 6 is a structure principle schematic diagram of an N parallel input coherent demodulation module provided by the present application.

[0064] Reference numerals: 101, first analog-to-digital converter; 102, first serial-to-parallel module; 103, N parallel input coherent demodulation module; 104, second analog-to-digital converter; 105, second serial-to-parallel module; 106, N parallel phase-locked loop module; 107, N parallel reference coherent demodulation module; 108, frequency locker; 109, phase locker; 110, N parallel frequency measurement module; 111, N parallel pipeline zero-crossing detector module; 112, N parallel pipeline counter; 113, N parallel rising edge detection module; 114, N parallel pipeline frequency divider; 201, first pipeline zero-crossing detection module; 202, second pipeline zero-crossing detection module; 20N, Nth pipeline zero-crossing detection module; 211, first parallel rising edge detection module; 212, second parallel rising edge detection module; 21N, Nth parallel rising edge detection module; 210, first delay compensation module; 220, N parallel pipeline frequency divider; 221, N parallel pipeline counter; 301, first reference digital frequency synthesizer; 302, second reference digital frequency synthesizer; 30N, Nth reference digital frequency synthesizer; 311, first reference pipeline multiplier; 312, second reference pipeline multiplier; 31N, Nth reference pipeline multiplier; 321, second reference pipeline multiplier; 322, second reference pipeline multiplier; 32N, Nth reference pipeline multiplier; 331, first parallel low-pass filter; 332, second parallel low-pass filter; 33N, Nth parallel low-pass filter; 341, second parallel low-pass filter; 342, second parallel low-pass filter; 34N, Nth parallel low-pass filter; 330, second delay compensation module; 340, third delay compensation module; 350, N parallel arctangent angle operation module; 351, frequency locker; 352, phase locker; 401, first input digital frequency synthesizer; 402, second input digital frequency synthesizer; 40N, Nth input digital frequency synthesizer; 411, first input pipeline multiplier; 412, second input pipeline multiplier; 41N, Nth input pipeline multiplier; 421, second input pipeline multiplier; 422, second input pipeline multiplier; 42N, Nth input pipeline multiplier; 431, first pipeline low-pass filter; 432, second pipeline low-pass filter; 43N, Nth pipeline low-pass filter; 441, second pipeline low-pass filter; 442, second pipeline low-pass filter; 44N, Nth pipeline low-pass filter; 430, fourth delay compensation module; 440, fifth delay compensation module; 450, N parallel arctangent modulo operation module. DETAILED DESCRIPTION

[0065] For the purpose of making the purpose, technical solutions and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementation described in the following exemplary examples does not represent all the implementations consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0066] It can be understood that the terms "first", "second" and the like used in the present application can be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determining".

[0067] The terms "at least one", "multiple", "each", "any" and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by those skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0069] Reference Figure 1 , Figure 1 A flowchart of a high-frequency digital phase-locked amplifier based on a parallel digital algorithm is provided for the embodiments of the present application, with reference to Figure 1The high-frequency digital phase-locked amplifier comprises an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module, the output end of the analog-to-digital converter module is connected with the input end of the serial-to-parallel module, the first output end of the serial-to-parallel module is connected with the input end of the N-parallel frequency measurement module, the second output end of the serial-to-parallel module is connected with the first input end of the N-parallel phase-locked loop module, the output end of the N-parallel frequency measurement module is connected with the second input end of the N-parallel phase-locked loop module, the third output end of the serial-to-parallel module is connected with the first input end of the N-parallel input coherent demodulation module, and the output end of the N-parallel phase-locked loop module is connected with the second input end of the N-parallel input coherent demodulation module, wherein:

[0070] The analog-to-digital converter module is used for acquiring an analog input signal and a reference signal and performing sampling processing to obtain a sampled digital input signal and a sampled digital reference signal.

[0071] The serial-to-parallel module is used for performing serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain an N-parallel digital input signal and an N-parallel digital reference signal.

[0072] In the embodiment, the analog-to-digital converter samples the input signal and the reference signal respectively, the sampled digital signal is converted into an N-parallel signal through the serial-to-parallel module, the data stream rate of the digital signal is 1 / N of the sampling rate, so that a lower data stream rate can be obtained at a higher sampling rate, and the slower running rate of the FPGA is adapted.

[0073] The N-parallel frequency measurement module is used for performing frequency measurement on the N-parallel digital reference signal to obtain reference signal frequency measurement information.

[0074] Further, it needs to be explained that the N-parallel frequency measurement module comprises an N-parallel pipeline type zero-crossing detector, a delay compensation module, an N-parallel rising edge detection module, an N-parallel pipeline type frequency divider and an N-parallel pipeline type counter, the first output end of the N-parallel pipeline type zero-crossing detector is connected with the input end of the delay compensation module, the second output end of the N-parallel pipeline type zero-crossing detector is connected with the first input end of the N-parallel rising edge detection module, the output end of the delay compensation module is connected with the second input end of the N-parallel rising edge detection module, the output end of the N-parallel rising edge detection module is connected with the input end of the N-parallel pipeline type frequency divider, and the output end of the N-parallel pipeline type frequency divider is connected with the input end of the N-parallel pipeline type counter, wherein the N-parallel pipeline type zero-crossing detector is used for performing zero-crossing detection on the N-parallel digital reference signal to obtain an N-parallel square wave reference signal; the delay compensation module and the N-parallel rising edge detection module are used for performing conversion processing on the N-parallel square wave reference signal to obtain an N-parallel pulse reference signal; the N-parallel pipeline type frequency divider is used for performing frequency division on the N-parallel pulse reference signal according to a frequency division coefficient to obtain a frequency-divided N-parallel pulse reference signal; and the N-parallel pipeline type counter is used for counting the frequency-divided N-parallel pulse reference signal to obtain reference signal frequency measurement information.

[0075] Further, the N-parallel pipeline type zero-crossing detector comprises a first-stage delay compensation module, a hysteresis comparator, a second-stage delay compensation module and a hysteresis decision device, which are connected in sequence, wherein the first-stage delay compensation module is used for performing first compensation processing on the N-parallel digital reference signal to obtain a preliminarily compensated N-parallel digital reference signal; the hysteresis comparator is used for comparing the preliminarily compensated N-parallel digital reference signal to obtain a compared N-parallel digital reference signal; the second-stage delay compensation module is used for performing second compensation processing on the compared N-parallel digital reference signal to obtain a compensated N-parallel digital reference signal; and the hysteresis decision device is used for judging the compensated N-parallel digital reference signal to obtain the N-parallel square wave reference signal.

[0076] In the embodiment, the N-parallel frequency measurement part comprises an N-parallel pipeline type zero-crossing detector, a delay compensation module, an N-parallel rising edge detection module, an N-parallel pipeline type frequency divider and an N-parallel pipeline type counter. The N-parallel reference signal is converted into an N-parallel square wave through the zero-crossing detection module, the N-parallel square wave output by the zero-crossing detection module is converted into an N-parallel pulse signal through the rising edge detection and delay compensation module, and the frequency measurement information of the reference signal is obtained by performing frequency division and counting on the N-parallel pulse signal. The N-parallel pipeline type frequency divider internally comprises a hysteresis comparator, the frequency division coefficient adopts hysteresis control, the frequency division coefficient is prevented from jumping, and the measurement precision and time are ensured.

[0077] The N-parallel phase-locked loop module is used for phase-locked regulation of the N-parallel digital reference signal according to the frequency information of the reference signal, so as to obtain the frequency information of the reference signal and the phase information of the reference signal.

[0078] Further, it needs to be explained that the N-parallel phase-locked loop module comprises an N-parallel reference coherent demodulation module, a frequency locker and a phase locker, the N-parallel reference coherent demodulation module, the frequency locker and the phase locker are connected in sequence, the output end of the frequency locker and the output end of the phase locker are connected with the input end of the N-parallel reference coherent demodulation module, wherein the frequency locker is used for obtaining the frequency information of the reference signal frequency information; the phase locker is used for obtaining the phase information of the reference signal frequency information; the N-parallel reference coherent demodulation module is used for coherent demodulation of the frequency information of the reference signal frequency information and the phase information of the reference signal frequency information, so as to obtain the phase information of the reference signal; the frequency locker and the phase locker are also used for adjusting according to the phase information of the reference signal and the reference signal frequency information, so as to obtain the frequency information of the reference signal.

[0079] Further, the N-parallel reference coherent demodulation module comprises a first N-parallel digital frequency synthesizer, a first N-parallel pipeline multiplier, a first N-parallel pipeline low-pass filter and an N-parallel arctangent angle operation module, the first N-parallel digital frequency synthesizer, the first N-parallel pipeline multiplier, the first N-parallel pipeline low-pass filter and the N-parallel arctangent angle operation module are connected in sequence, wherein the first N-parallel digital frequency synthesizer is used for synthesizing the frequency information and the phase information, so as to obtain N-parallel orthogonal triangular signals; the first N-parallel pipeline multiplier is used for multiplying the N-parallel orthogonal triangular signals and the N-parallel digital reference signal, so as to obtain the N-parallel reference signal multiplication operation result; the first N-parallel pipeline low-pass filter is used for filtering the N-parallel reference signal multiplication operation result to obtain the XY component information of the reference signal; the N-parallel arctangent angle operation module is used for arctangent angle operation on the XY component information of the reference signal, so as to obtain the phase information of the reference signal.

[0080] In the embodiment, the N parallel phase-locked loop module comprises an N parallel reference coherent demodulation module, a frequency locker and a phase locker, and the N parallel reference coherent demodulation module comprises an N parallel digital frequency synthesizer, an N parallel pipeline multiplier, an N parallel pipeline low-pass filter and an N parallel arctangent angle operation. The module mainly adopts the method of combining coherent demodulation with a phase-frequency controller, obtains the phase difference between the reference signal and the digital frequency direct synthesizer through coherent demodulation, and adjusts the phase difference to 0 through the frequency locker and the phase locker. Specifically, the N parallel digital frequency synthesizer generates N parallel quadrature triangular signals according to the phase information and the frequency information provided by the frequency locker and the phase locker, and provides the N parallel quadrature triangular signals to the N parallel pipeline multiplier for multiplication operation with the N parallel reference signals, then filters out the double frequency term through the N parallel pipeline low-pass filter to obtain the x, y components, and obtains the phase information of the reference signal through the N parallel arctangent angle operation. The frequency locker and the phase locker adjust according to the phase information and the frequency information of the N parallel frequency measurement module, so that the sinusoidal signal generated by the N parallel digital frequency synthesizer is the same frequency and phase as the reference signal, and the phase information and the frequency information are provided to the N parallel input coherent demodulation module.

[0081] The N parallel input coherent demodulation module is used for demodulating the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

[0082] Further, it should be noted that the N parallel input coherent demodulation module comprises a second N parallel digital frequency synthesizer, a second N parallel pipeline multiplier, a second N parallel pipeline low-pass filter and an N parallel arctangent modulo operation module, which are connected in sequence. The second N parallel digital frequency synthesizer is used for synthesizing according to the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel same-frequency and same-phase quadrature triangular signals; the second N parallel pipeline multiplier is used for multiplying the N parallel same-frequency and same-phase quadrature triangular signals with the N parallel digital input signals to obtain the N parallel digital input signal multiplication operation results; the second N parallel pipeline low-pass filter is used for filtering the N parallel digital input signal multiplication operation results to obtain the XY component information of the digital input signal; and the N parallel arctangent modulo operation module is used for performing arctangent modulo operation on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

[0083] In the embodiment, the N-parallel input coherent demodulation part also comprises an N-parallel digital frequency synthesizer, an N-parallel pipeline multiplier, an N-parallel pipeline low-pass filter and an N-parallel arctangent modulo operation. The N-parallel digital frequency synthesizer generates N-parallel same-frequency and same-phase quadrature triangular signals according to the phase information and frequency information provided by the N-parallel phase-locked loop module, and provides the N-parallel same-frequency and same-phase quadrature triangular signals to the N-parallel pipeline multiplier to perform multiplication operation with the N-parallel input signals, and then the x and y components are obtained by filtering out the double frequency terms through the N-parallel pipeline low-pass filter, and finally the amplitude R and the phase Φ are obtained by the N-parallel arctangent modulo operation.

[0084] In summary, the phase-locked amplification system of the embodiment of the application comprises an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module. The analog-to-digital converter directly samples the analog input signal and the reference signal. The serial high-speed digital signals after sampling are converted into parallel data through the serial-to-parallel module. The N-parallel frequency measurement module obtains the frequency information of the reference signal according to the N-parallel reference signal, and provides the frequency information to the N-parallel phase-locked loop module. The N-parallel phase-locked loop obtains the stable frequency information and phase information according to the reference signal and the frequency information. The N-parallel input coherent demodulation module demodulates the parallel digital input signal according to the frequency information and the phase information to obtain the amplitude and the phase of the input signal.

[0085] Please refer to Figure 2 The embodiment of the application further provides a control method of the high-frequency digital phase-locked amplifier based on the parallel digital algorithm, which can realize the high-frequency digital phase-locked amplifier based on the parallel digital algorithm. The control method comprises the following steps:

[0086] S100, obtaining an analog input signal and a reference signal and performing sampling processing to obtain a digital input signal after sampling and a digital reference signal after sampling;

[0087] S200, performing serial-to-parallel processing on the digital input signal after sampling and the digital reference signal after sampling to obtain an N-parallel digital input signal and an N-parallel digital reference signal;

[0088] S300, performing frequency measurement on the N-parallel digital reference signal to obtain reference signal frequency measurement information;

[0089] It should be noted that, in some embodiments, step S300 may include: S310, performing zero-crossing detection on N parallel digital reference signals to obtain N parallel square wave reference signals; S320, performing conversion processing on the N parallel square wave reference signals to obtain N parallel pulse reference signals; S330, dividing the N parallel pulse reference signals according to the frequency division coefficient to obtain N parallel pulse reference signals after division; S340, counting the N parallel pulse reference signals after division to obtain reference signal frequency measurement information.

[0090] S400, performing phase-locked adjustment on N parallel digital reference signals according to the reference signal frequency measurement information to obtain frequency information and phase information of the reference signal;

[0091] It should be noted that, in some embodiments, step S400 may include: S410, obtaining the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information; S420, coherently demodulating the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal; S430, adjusting according to the phase information of the reference signal and the reference signal frequency measurement information to obtain the frequency information of the reference signal.

[0092] S500, demodulating the N parallel digital input signals according to the frequency information and the phase information of the reference signal to obtain the amplitude information, the phase information and the XY component information of the digital input signal;

[0093] It should be noted that, in some embodiments, step S500 may include: S510, performing synthesis processing based on the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel same-frequency and same-phase orthogonal triangular signals; S520, multiplying the N parallel same-frequency and same-phase orthogonal triangular signals with N parallel digital input signals to obtain the product operation results of the N parallel digital input signals; S530, filtering out the double frequency terms of the product operation results of the N parallel digital input signals to obtain XY component information of the digital input signal; S540, performing an inverse tangent modulo operation on the XY component information of the digital input signal to obtain amplitude information of the digital input signal, phase information of the digital input signal, and XY component information of the digital input signal.

[0094] Further, the following description will be given in conjunction with the accompanying drawings of the embodiments of the present invention:

[0095] like Figure 3As shown, the phase-locked amplification system of the embodiment of the present application comprises a first analog-to-digital converter 101 and a second analog-to-digital converter 104, a first serial-to-parallel module 101 and a second serial-to-parallel module 104, an N-parallel frequency measurement module 110, an N-parallel input coherent demodulation module 103 and an N-parallel phase-locked loop module 106. The input signal and the reference signal are converted into serial digital signals by the first digital-to-analog converter 101 and the second digital-to-analog converter 102 respectively, and then converted into parallel digital signals by the first serial-to-parallel module 102 and the second serial-to-parallel module 105, the parallel input signal is provided to the N-parallel input coherent demodulation module 103, and the parallel reference signal is provided to the N-parallel frequency measurement module 110 and the N-parallel phase-locked loop module 106. The N-parallel frequency measurement module 110 obtains frequency measurement information according to the reference signal, and provides the information to the N-parallel phase-locked loop module 106, the N-parallel phase-locked loop module 106 obtains phase information and frequency information according to the reference signal and the frequency measurement information, and provides the information to the N-parallel input coherent demodulation module 103, and then the N-parallel input coherent demodulation module 103 demodulates the input signal according to the phase information, the frequency information and the input signal to obtain the amplitude R, the phase φ and the XY component of the input signal.

[0096] The specific block diagram of the N-parallel frequency measurement module 110 of the embodiment of the present application is shown in FIG. 2. Figure 4The reference signal is shown. Parallel reference signal is transmitted to the first, second and Nth pipeline zero-crossing detection module respectively. Each zero-crossing detection module is composed of first stage delay compensation, hysteresis comparator, second stage delay compensation and hysteresis decision maker. The output of each hysteresis comparator is affected by the previous stage hysteresis comparator, so the output of the first hysteresis comparator of the first pipeline zero-crossing detection module 201 needs to be connected to the input of the second hysteresis comparator of the second pipeline zero-crossing detection module 202, and so on. The output of the hysteresis comparator of the 2(N-1)th pipeline zero-crossing detection module needs to be connected to the hysteresis comparator of the Nth pipeline zero-crossing detection module 20N. Because of the data dependence between multiple hysteresis comparators, two-stage delay compensation modules are used to align the flow of different zero-crossing detection modules. For the first pipeline zero-crossing detection module 201, the delay time of the first stage delay compensation is 0 cycle, and the delay time of the second stage delay compensation is N cycle. For the second pipeline zero-crossing detection module 202, the delay time of the first stage delay compensation is 1 cycle, and the delay time of the second stage delay compensation is N-1 cycle. For the Nth pipeline zero-crossing detection module 20N, the delay time of the first stage delay compensation is N cycle, and the delay time of the second stage delay compensation is 0 cycle. The output of the hysteresis decision maker of the Nth pipeline zero-crossing detection module 20N needs to be connected to the input of the hysteresis decision maker of the first, second and Nth pipeline zero-crossing detection module. After hysteresis decision, the parallel reference signal is converted into parallel square wave. Because multiple data are needed for rising edge detection, the output of the first pipeline zero-crossing detection module 201 needs to be connected to the first and second parallel rising edge detection module 211 and 212, the output of the second pipeline zero-crossing detection module 202 needs to be connected to the second and third parallel rising edge detection module, and so on. The output of the 2(N-1)th pipeline zero-crossing detection module needs to be connected to the 21(N-1)th and Nth parallel rising edge detection module 21N. For the Nth pipeline zero-crossing detection module 20N, its output needs to be connected to the Nth parallel rising edge detection module 21N and the first delay compensation module 210 for one cycle of delay compensation, and then connected to the first parallel rising edge detection module 211. Each of the N parallel rising edge detection modules judges according to its two inputs and outputs parallel pulse signal. The converted pulse signal is provided to the N parallel pipeline frequency divider 220 and the N parallel pipeline counter 221.The N parallel pipeline type frequency divider 220 has a hysteresis comparison structure inside, and selects a suitable frequency division coefficient according to the input pulse result. If the frequency of the pulse signal is detected to be low, the frequency division coefficient is reduced to reduce the frequency division measurement time. If the frequency of the pulse signal is detected to be high, the frequency division coefficient is increased to improve the frequency division measurement precision. The N parallel pipeline type frequency divider 220 performs frequency division according to the frequency division coefficient pulse input, and the N parallel pipeline type counter 221 performs counting according to the frequency-divided pulse to obtain a counting result, which is transmitted to the N parallel phase-locked loop module 106 as frequency measurement information. Since the counter and the frequency divider both need to operate for multiple cycles, a pipeline type design is adopted.

[0097] The structure of the N parallel phase-locked loop module 106 is as shown in FIG. 6. Figure 5The shown. Divided into 2N pipeline type multiplier, including the first reference pipeline type multiplier 311, the second reference pipeline type multiplier 312, the first N reference pipeline type multiplier 31N, the second reference pipeline type multiplier 321, the second reference pipeline type multiplier 322, the second N reference pipeline type multiplier 32N, N digital frequency synthesizer, including the first reference digital frequency synthesizer 301, the second reference digital frequency synthesizer 302, the N reference digital frequency synthesizer 30N, 2N pipeline low pass filter, including the first parallel low pass filter 331, the second parallel low pass filter 332, the first N parallel low pass filter 33N, the second parallel low pass filter 341, the second parallel low pass filter 342, the second N parallel low pass filter 34N, N parallel arctangent angle operation module 350, the second delay compensation module 330 and the third delay compensation module 340, frequency lock 351 and phase lock 352. The first reference digital frequency synthesizer 301, the second reference digital frequency synthesizer 302, the N reference digital frequency synthesizer 30N respectively according to the phase information and frequency information of the frequency lock 351 and the phase lock 352, generate the same frequency and phase parallel mutually orthogonal triangle signal, a group of sine triangle signal is provided to the first reference pipeline type multiplier 311, the second reference pipeline type multiplier 312, the first N reference pipeline type multiplier 31N, the other group of cosine triangle signal is provided to the second reference pipeline type multiplier 321, the second reference pipeline type multiplier 322, the second N reference pipeline type multiplier 32N. Because the multiplier needs multiple operation period, therefore adopts the pipeline type design. Because the pipeline low pass filter needs multiple data before and after, therefore the first reference pipeline type multiplier 311 multiplies the reference signal 1 and the sine signal of the first reference digital frequency synthesizer 301, and outputs the result to the first parallel low pass filter 331 and the second delay compensation module 330, the second delay compensation module 330 again outputs the result to the first N parallel low pass filter 33N. Similarly, the second reference pipeline type multiplier 312 multiplies the reference signal 2 and the sine signal of the second reference digital frequency synthesizer 302, and outputs the result to the second parallel low pass filter 332 and the first parallel low pass filter 331.Similarly, the 1st N reference pipeline multiplier 31N multiplies the reference signal N and the sine signal of the Nth reference digital frequency synthesizer 30N, and outputs the result to the 1st N parallel low-pass filter 33N and the 1st N-1 parallel low-pass filter; the 2nd reference pipeline multiplier 321 multiplies the reference signal 1 and the cosine signal of the 1st reference digital frequency synthesizer 301, and outputs the result to the 2nd parallel low-pass filter 341 and the third delay compensation module 340, which further outputs the result to the 2Nth parallel low-pass filter 34N. The 2nd reference pipeline multiplier 322 multiplies the reference signal 2 and the cosine signal of the 2nd reference digital frequency synthesizer 302, and outputs the result to the 2nd parallel low-pass filter 342 and the 1st parallel low-pass filter 341. Similarly, the 2Nth reference pipeline multiplier 32N multiplies the reference signal N and the cosine signal of the Nth reference digital frequency synthesizer 30N, and outputs the result to the 2Nth parallel low-pass filter 34N and the 2N-1 parallel low-pass filter. The low-pass filter also needs to be pipelined because it needs to operate for multiple cycles. The 1st parallel low-pass filter 331, the 2nd parallel low-pass filter 332, and the 1st N parallel low-pass filter 33N combine two inputs to perform low-pass filtering and obtain parallel X components. Similarly, the 1st parallel low-pass filter 341, the 2nd parallel low-pass filter 342, and the 2Nth parallel low-pass filter 34N combine two inputs to perform low-pass filtering and obtain parallel Y components. The X components and the Y components are respectively input to the N parallel arctangent angle operation module 350. The N parallel arctangent angle operation module 350 performs arctangent operation to obtain phase information, i.e., the phase difference between the reference signal and the triangular signal output by the parallel digital frequency synthesizer. The phase difference and the frequency measurement information are both input to the frequency locker 351 and the phase locker 352, which adjust the frequency and phase of the 1st reference digital frequency synthesizer 301, the 2nd reference digital frequency synthesizer 302, and the Nth reference digital frequency synthesizer 30N, so that the phase difference is ultimately 0, i.e., the triangular signal output by the digital frequency synthesizer is the same frequency and in phase with the reference signal, and the phase information and the frequency information at this time are transmitted to the N parallel input coherent demodulation module 103.

[0098] The N parallel input coherent demodulation module 103 is similar to the N parallel phase-locked loop module 106, and the specific block diagram is as follows: Figure 6As shown, divided into 2N pipeline multipliers, including the first input pipeline multiplier 411, the first second input pipeline multiplier 412, the first N input pipeline multiplier 41N, the second input pipeline multiplier 421, the second second input pipeline multiplier 422, the second N input pipeline multiplier 42N, N digital frequency synthesizer, including the first input digital frequency synthesizer 401, the second input digital frequency synthesizer 402, the N input digital frequency synthesizer 40N, 2N pipeline low pass filter, including the first pipeline low pass filter 431, the first second pipeline low pass filter 432, the first N pipeline low pass filter 43N, the second pipeline low pass filter 441, the second second pipeline low pass filter 442, the second N pipeline low pass filter 44N, N parallel arctangent modulo operation module 450, fourth delay compensation module 430 and fifth delay compensation module 440. The first input digital frequency synthesizer 401, the second input digital frequency synthesizer 402, the N input digital frequency synthesizer 40N respectively according to the phase information and frequency information of N parallel phase-locked loop module 106, generate the same frequency and phase parallel mutually orthogonal triangular signal, a group of sine triangular signal is provided to the first input pipeline multiplier 411, the first second input pipeline multiplier 412, the first N input pipeline multiplier 41N, the other group of cosine triangular signal is provided to the second input pipeline multiplier 421, the second second input pipeline multiplier 422, the second N input pipeline multiplier 42N. Because the multiplier needs multiple operation period, therefore adopts the pipeline type design. Because the pipeline low pass filter needs multiple data before and after, therefore the first input pipeline multiplier 411 multiplies the input signal 1 and the sine signal of the first input digital frequency synthesizer 401, and outputs the result to the first pipeline low pass filter 431 and the fourth delay compensation module 430, the fourth delay compensation module 430 outputs the result to the first N pipeline low pass filter 43N. Similarly, the first second input pipeline multiplier 412 multiplies the input signal 2 and the sine signal of the second input digital frequency synthesizer 402, and outputs the result to the first second pipeline low pass filter 432 and the first pipeline low pass filter 431.Similarly, the 1Nth input pipeline multiplier 41N multiplies the input signal N by the sine signal of the Nth input digital frequency synthesizer 40N, and outputs the result to the 1Nth pipeline low-pass filter 43N and the 1N-1th pipeline low-pass filter. The second input pipeline multiplier 421 multiplies the input signal 1 by the cosine signal of the first input digital frequency synthesizer 401, and outputs the result to the second pipeline low-pass filter 441 and the fifth delay compensation module 440. The fifth delay compensation module 440 then outputs the result to the 2Nth pipeline low-pass filter 44N. The second second input pipeline multiplier 422 multiplies the input signal 2 by the cosine signal of the second input digital frequency synthesizer 402, and outputs the result to the second second pipeline low-pass filter 442 and the second first pipeline low-pass filter 441. Similarly, the 2Nth input pipeline multiplier 42N multiplies the input signal N by the cosine signal from the Nth input digital frequency synthesizer 40N, and outputs the result to the 2Nth pipeline low-pass filter 44N and the 2N-1th pipeline low-pass filter. Since low-pass filters require multiple cycles of operation, they also require pipeline processing. The first pipeline low-pass filter 431, the first second pipeline low-pass filter 432, and the 1Nth pipeline low-pass filter 43N combine their two inputs to perform low-pass filtering, producing parallel X components. Similarly, the second pipeline low-pass filter 441, the second second pipeline low-pass filter 442, and the 2Nth pipeline low-pass filter 44N combine their two inputs to perform low-pass filtering, producing parallel Y components. The X component and the Y component are respectively connected to the N-parallel inverse tangent modulo operation module 450, and the N-parallel inverse tangent modulo operation module 450 performs an inverse tangent modulo operation to obtain amplitude information R, phase information Φ, X, and Y components.

[0099] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0100] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A high-frequency digital lock-in amplifier based on a parallel digital algorithm, characterized in that: The high-frequency digital lock-in amplifier includes an analog-to-digital converter module, a serial-to-parallel module, an N-parallel frequency measurement module, an N-parallel phase-locked loop module and an N-parallel input coherent demodulation module. The output end of the analog-to-digital converter module is connected to the input end of the serial-to-parallel module, the first output end of the serial-to-parallel module is connected to the input end of the N-parallel frequency measurement module, the second output end of the serial-to-parallel module is connected to the first input end of the N-parallel phase-locked loop module, the output end of the N-parallel frequency measurement module is connected to the second input end of the N-parallel phase-locked loop module, the third output end of the serial-to-parallel module is connected to the first input end of the N-parallel input coherent demodulation module, and the output end of the N-parallel phase-locked loop module is connected to the second input end of the N-parallel input coherent demodulation module, wherein: The analog-to-digital converter module is used to obtain an analog input signal and a reference signal and perform sampling processing to obtain a sampled digital input signal and a sampled digital reference signal; The serial-to-parallel module is used to perform serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals; The N parallel frequency measurement module is used to measure the frequency of the N parallel digital reference signals to obtain reference signal frequency measurement information; The N parallel phase-locked loop module is used to perform phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain frequency information and phase information of the reference signal; The N parallel input coherent demodulation module is used to demodulate the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal and the XY component information of the digital input signal.

2. The high-frequency digital lock-in amplifier according to claim 1, characterized in that: The N-parallel frequency measurement module includes an N-parallel pipelined zero-crossing detector, a delay compensation module, an N-parallel rising edge detection module, an N-parallel pipelined frequency divider and an N-parallel pipelined counter. The first output end of the N-parallel pipelined zero-crossing detector is connected to the input end of the delay compensation module, the second output end of the N-parallel pipelined zero-crossing detector is connected to the first input end of the N-parallel rising edge detection module, the output end of the delay compensation module is connected to the second input end of the N-parallel rising edge detection module, the output end of the N-parallel rising edge detection module is connected to the input end of the N-parallel pipelined frequency divider, and the output end of the N-parallel pipelined frequency divider is connected to the input end of the N-parallel pipelined counter, wherein: The N parallel pipelined zero-crossing detector is used to perform zero-crossing detection on the N parallel digital reference signals to obtain N parallel square wave reference signals; The delay compensation module and the N parallel rising edge detection module are used to convert the N parallel square wave reference signals to obtain N parallel pulse reference signals; The N-parallel pipeline frequency divider is used to divide the N-parallel pulse reference signal according to the frequency division coefficient to obtain the divided N-parallel pulse reference signal; The N parallel pipeline counter is used to count the N parallel pulse reference signals after the frequency division to obtain the reference signal frequency measurement information.

3. The high-frequency digital lock-in amplifier according to claim 2, characterized in that: The N-parallel pipeline zero-crossing detector includes a first-stage delay compensation module, a hysteresis comparator, a second-stage delay compensation module and a hysteresis decision device, wherein the first-stage delay compensation module, the hysteresis comparator, the second-stage delay compensation module and the hysteresis decision device are connected in sequence, wherein: The first-stage delay compensation module is used to perform a first compensation process on the N parallel digital reference signals to obtain N parallel digital reference signals after preliminary compensation; The hysteresis comparator is used to compare the N parallel digital reference signals after preliminary compensation to obtain the compared N parallel digital reference signals; The second-stage delay compensation module is used to perform a second compensation process on the compared N parallel digital reference signals to obtain compensated N parallel digital reference signals; The hysteresis decision device is used to make a decision on the compensated N parallel digital reference signals to obtain the N parallel square wave reference signals.

4. The high-frequency digital lock-in amplifier according to claim 1, characterized in that: The N parallel phase-locked loop module includes an N parallel reference coherent demodulation module, a frequency locker, and a phase locker. The N parallel reference coherent demodulation module, the frequency locker, and the phase locker are connected in sequence. The output end of the frequency locker and the output end of the phase locker are both connected to the input end of the N parallel reference coherent demodulation module, wherein: The frequency locker is used to obtain frequency information of the reference signal frequency measurement information; The phase locker is used to obtain phase information of the reference signal frequency measurement information; The N parallel reference coherent demodulation module is used to coherently demodulate the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal; The frequency locker and the phase locker are further configured to perform adjustments based on the phase information of the reference signal and the frequency measurement information of the reference signal to obtain the frequency information of the reference signal.

5. The high-frequency digital lock-in amplifier according to claim 4, characterized in that: The N-parallel reference coherent demodulation module includes a first N-parallel digital frequency synthesizer, a first N-parallel pipelined multiplier, a first N-parallel pipelined low-pass filter and an N-parallel inverse tangent angle calculation module, wherein the first N-parallel digital frequency synthesizer, the first N-parallel pipelined multiplier, the first N-parallel pipelined low-pass filter and the N-parallel inverse tangent angle calculation module are connected in sequence, wherein: The first N parallel digital frequency synthesizer is used to synthesize the frequency information and the phase information to obtain N parallel orthogonal triangular signals; The first N-parallel pipeline multiplier is used to multiply the N-parallel orthogonal triangular signals with the N-parallel digital reference signals to obtain N-parallel reference signal product operation results; The first N parallel pipeline low-pass filters are used to filter out double frequency terms from the product operation results of the N parallel reference signals to obtain XY component information of the reference signal; The N parallel inverse tangent angle operation modules are used to perform an inverse tangent angle operation on the XY component information of the reference signal to obtain the phase information of the reference signal.

6. The high-frequency digital lock-in amplifier according to claim 1, characterized in that: The N parallel input coherent demodulation module includes a second N parallel digital frequency synthesizer, a second N parallel pipelined multiplier, a second N parallel pipelined low-pass filter and an N parallel inverse tangent modulo operation module, wherein the second N parallel digital frequency synthesizer, the second N parallel pipelined multiplier, the second N parallel pipelined low-pass filter and the N parallel inverse tangent modulo operation module are connected in sequence, wherein: The second N parallel digital frequency synthesizer is used to perform synthesis processing according to the phase information and the frequency information of the reference signal to obtain N parallel orthogonal triangular signals with the same frequency and phase; The second N-parallel pipeline multiplier is used to perform a multiplication operation on the N parallel same-frequency and same-phase orthogonal triangular signals and the N parallel digital input signals to obtain a product operation result of the N parallel digital input signals; The second N-parallel pipeline low-pass filter is used to filter out the double frequency term of the product operation result of the N-parallel digital input signals to obtain XY component information of the digital input signal; The N-parallel inverse tangent modulo operation module is used to perform an inverse tangent modulo operation on the XY component information of the digital input signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal, and the XY component information of the digital input signal.

7. A control method for a high-frequency digital lock-in amplifier based on a parallel digital algorithm, characterized in that: The method is applied to the high-frequency digital lock-in amplifier according to any one of claims 1 to 6, and the control method comprises the following steps: Acquire an analog input signal and a reference signal and perform sampling processing to obtain a sampled digital input signal and a sampled digital reference signal; Performing serial-to-parallel processing on the sampled digital input signal and the sampled digital reference signal to obtain N parallel digital input signals and N parallel digital reference signals; Performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information; Performing phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain frequency information and phase information of the reference signal; The N parallel digital input signals are demodulated according to the frequency information and the phase information of the reference signal to obtain amplitude information of the digital input signal, phase information of the digital input signal and XY component information of the digital input signal.

8. The method according to claim 7, characterized in that The performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information includes: Performing zero-crossing detection on the N parallel digital reference signals to obtain N parallel square wave reference signals; Converting the N parallel square wave reference signals to obtain N parallel pulse reference signals; Frequency-divide the N parallel pulse reference signals according to the frequency-division coefficient to obtain N parallel pulse reference signals after frequency division; The divided N parallel pulse reference signals are counted to obtain the reference signal frequency measurement information.

9. The method according to claim 7, characterized in that The performing phase-locked adjustment on the N parallel digital reference signals according to the reference signal frequency measurement information to obtain frequency information and phase information of the reference signal includes: Acquire frequency information of the reference signal frequency measurement information and phase information of the reference signal frequency measurement information; performing coherent demodulation on the frequency information of the reference signal frequency measurement information and the phase information of the reference signal frequency measurement information to obtain the phase information of the reference signal; Adjustment is performed according to the phase information of the reference signal and the frequency measurement information of the reference signal to obtain the frequency information of the reference signal.

10. The method according to claim 7, characterized in that The demodulating process is performed on the N parallel digital input signals according to the frequency information of the reference signal and the phase information of the reference signal to obtain the amplitude information of the digital input signal, the phase information of the digital input signal, and the XY component information of the digital input signal, including: Performing synthesis processing based on the phase information of the reference signal and the frequency information of the reference signal to obtain N parallel orthogonal triangular signals with the same frequency and phase; Performing a multiplication operation on the N parallel, same-frequency, same-phase, orthogonal triangular signals with the N parallel digital input signals to obtain a product operation result of the N parallel digital input signals; Filtering out the double frequency term from the product operation result of the N parallel digital input signals to obtain XY component information of the digital input signal; An arc tangent modulo operation is performed on the XY component information of the digital input signal to obtain amplitude information of the digital input signal, phase information of the digital input signal, and XY component information of the digital input signal.

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