Capacitive load overcurrent protection method, device, equipment, system and storage medium

Abstract

The embodiment of the invention provides a capacitive load overcurrent protection method and device, an intelligent power amplification device, electronic equipment and a storage medium, and the device comprises an amplitude limiting module which is used for carrying out the amplitude limiting of a first digital signal corresponding to a source signal, so as to obtain a second digital signal, the current applied to the D-type power amplifier by the first digital signal does not exceed a current peak value which can be supported by the D-type power amplifier; the anti-resonance filtering module is used for suppressing a part of frequency components in the second digital signal according to a preset center frequency to obtain a third digital signal, the center frequency is determined according to the frequency of a formant, and the formant is generated by mutual influence between the capacitive load and a preceding-stage element of the capacitive load; and the low-pass filtering module is used for filtering the third digital signal to obtain a fourth digital signal, and the fourth digital signal is provided for the capacitive load after being processed by the D-type power amplifier.

Description

Technical Field

[0001] The present application relates to the field of load protection, and in particular to a capacitive load overcurrent protection method, device, equipment, system, and storage medium. Background Art

[0002] Class D amplifiers are widely used to drive capacitive loads such as piezoelectric speakers due to their high efficiency and low power consumption. As electronic devices continue to miniaturize, the demand for thin speakers is gradually increasing. Piezoelectric speakers are widely used because of their small size and thinness. Piezoelectric speakers are capacitive loads. Due to their capacitive load characteristics, the impedance of most piezoelectric speakers is several orders of magnitude larger than that of traditional speakers. This allows Class D amplifiers to achieve high sound pressure levels (SPL, Sound Pressure Level) by driving piezoelectric speakers with very low power. However, the high frequency of the capacitive load appears as low impedance, which will produce resonance and form voltage peaks when combined with the previous LC circuit, making it more likely to cause overcurrent problems. Therefore, in systems that use capacitive loads, such as audio amplification systems, additional measures need to be taken to protect against overcurrent. Summary of the invention

[0003] In view of this, embodiments of the present application provide a load overcurrent protection method, device, equipment, system, and storage medium, which can implement load overcurrent protection.

[0004] According to a first aspect of an embodiment of the present application, a load overcurrent protection device is provided, the device comprising: a limiting module, used to perform limiting processing on a first digital signal corresponding to a source signal to obtain a second digital signal, so that the current applied to a class D power amplifier does not exceed the current peak value that the class D power amplifier can support; an anti-resonance filtering module, used to suppress some frequency components in the second digital signal according to a predetermined center frequency to obtain a third digital signal, the center frequency is determined according to the frequency of a resonance peak, and the resonance peak is a resonance peak generated by the capacitive load and its preceding element acting together; a low-pass filtering module, used to filter the third digital signal to obtain a fourth digital signal, the fourth digital signal is used to be provided to the capacitive load after being processed by the class D power amplifier, so that the capacitive load can output an amplified signal of the source signal.

[0005] According to the second aspect of an embodiment of the present application, an intelligent power amplification device is provided, comprising: a class D power amplifier and a load overcurrent protection device as described in the first aspect, wherein a fourth digital signal output by the load overcurrent protection device enters the class D power amplifier for power amplification and is then provided to the load.

[0006] According to a third aspect of an embodiment of the present application, a load overcurrent protection device is provided, comprising: a limiting module, used to perform limiting processing on a first digital signal corresponding to a source signal to obtain a second digital signal, so that the current applied to a class D power amplifier does not exceed the current peak value that the class D power amplifier can support; a low-pass filtering module, used to filter the second digital signal to obtain a fourth digital signal, and the fourth digital signal is used to be provided to a load after being processed by the class D power amplifier, so that the load can output an amplified signal of the source signal.

[0007] According to a fourth aspect of an embodiment of the present application, a load overcurrent protection method is provided, comprising: performing limiting processing on a first digital signal corresponding to a source signal to obtain a second digital signal, so that the current applied by the second digital signal to a class D power amplifier does not exceed the current peak value that the class D power amplifier can support; suppressing some frequency components in the second digital signal according to a predetermined center frequency to obtain a third digital signal, wherein the center frequency is determined according to the frequency of a resonance peak, and the resonance peak is a resonance peak generated by the capacitive load and its preceding element acting together; filtering the third digital signal to obtain a fourth digital signal, wherein the fourth digital signal is used to be provided to the capacitive load after being processed by the class D power amplifier, so that the capacitive load can output an amplified signal of the source signal.

[0008] According to the fifth aspect of the embodiment of the present application, there is provided an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to perform operations corresponding to the load overcurrent protection method of the third aspect.

[0009] According to a sixth aspect of an embodiment of the present application, a storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the load overcurrent protection method described in the third aspect is implemented.

[0010] According to a seventh aspect of an embodiment of the present application, a computer program product is provided. When the computer program product is executed by a processor, it implements the load overcurrent protection method as described in the third aspect.

[0011] In the embodiment of the present application, the digital signal corresponding to the source signal is subjected to amplitude limiting processing through the amplitude limiting module to prevent the current applied by the signal to the class D power amplifier from exceeding the current peak value that the class D power amplifier can support, the resonance peak part in the signal is eliminated through the anti-resonance filtering module, and the signal after amplitude limiting processing is filtered through the low-pass filtering module to remove the unnecessary frequency components therein, and the fourth digital signal finally obtained is provided to the capacitive load after amplification by the class D power amplifier, so that the capacitive load can output the amplified signal of the source signal. Therefore, the embodiment of the present application can realize the capacitive load overcurrent protection suitable for the class D power amplifier through amplitude limiting, resonance peak suppression and filtering, and can effectively eliminate the resonance peak generated by the capacitive load and its front-stage element, and significantly improve the quality of the amplified signal output by the capacitive load. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0013] Figure 1 It is a schematic diagram of the structure of a capacitive load overcurrent protection circuit using a hardware solution;

[0014] Figure 2 This is a schematic structural diagram of a capacitive load overcurrent protection device according to an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure and signal transmission of a capacitive load overcurrent protection device according to an embodiment of the present application.

[0016] Figure 4 This is a schematic diagram of the principle of an anti-resonance filter module according to an embodiment of the present application;

[0017] Figure 5 A schematic diagram of the execution process of the spectrum expansion module according to an embodiment of the present application;

[0018] Figure 6 A schematic diagram of a processing flow of a limiting module according to an embodiment of the present application;

[0019] Figure 7 A schematic diagram of a processing flow of a clipping module according to another embodiment of the present application;

[0020] Figure 8 This is a schematic structural diagram of a capacitive load overcurrent protection device according to another embodiment of the present application;

[0021] Fig. 9A schematic diagram of the processing process of an adaptive control module according to an embodiment of the present application;

[0022] Fig.10 A schematic diagram of a processing flow of a sparse signal detection module according to an embodiment of the present application;

[0023] Fig.11 A schematic diagram of test results of a capacitive load overcurrent protection device according to an embodiment of the present application;

[0024] Fig.12 A schematic diagram of the structure and external connection of an intelligent power amplifier device according to an embodiment of the present application;

[0025] Fig.13 A flow chart of a capacitive load overcurrent protection method according to an embodiment of the present application;

[0026] Fig.14 It is a schematic diagram of the structure of an electronic device in yet another embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings. For ease of explanation, in the embodiments of the present application, the same reference numerals represent the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length, width and other dimensions of the various components in the embodiments of the present application shown in the accompanying drawings, as well as the overall thickness, length, width and other dimensions of the integrated device are only exemplary descriptions and should not constitute any limitation to the present application.

[0028] It should be noted that, under the premise of no conflict, the various embodiments described in this application and / or the technical features in each embodiment can be arbitrarily combined with each other, and the technical solution obtained after the combination should also fall within the protection scope of this application.

[0029] It should be understood that the specific examples in the embodiments of the present application are only intended to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the embodiments of the present application.

[0030] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0031] It should also be understood that the terms used in the embodiments of the present application and the appended claims are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. For example, the singular forms "a", "above", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0032] As used herein, terms such as "first," "second," and "third" describe various components, elements, regions, layers, and / or sections, but such components, elements, regions, layers, and / or sections should not be limited by such terms. Such terms may only be used to distinguish one component, element, region, layer, or section from another. Terms such as "first," "second," and "third" do not imply a sequence or order when used herein unless clearly indicated by the context.

[0033] Additionally, for ease of description, spatially relative terms such as "below," "lower," "above," "upper," and the like may be used herein to describe one component or member's relationship to another component or member illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly.

[0034] As electronic devices continue to miniaturize, the demand for thin speakers is gradually increasing. Piezoelectric speakers have attracted widespread attention due to their small size and thinness. Piezoelectric speakers are capacitive loads. Due to their capacitive load characteristics, the impedance of most piezoelectric speakers is several orders of magnitude larger than that of traditional speakers. This allows Class D power amplifiers to achieve high sound pressure levels (SPL) by driving piezoelectric speakers with very low power. However, the high frequencies of capacitive loads appear as low impedance, which is more prone to overcurrent problems. Therefore, in systems that use capacitive loads, such as audio amplification systems, additional measures are needed to protect the capacitive loads from high-frequency overcurrent.

[0035] In the embodiment of the present application, the digital signal corresponding to the source signal is subjected to amplitude limiting processing through the amplitude limiting module to prevent the current applied by the signal to the class D power amplifier from exceeding the current peak value that the class D power amplifier can support, the resonance peak part in the signal is eliminated through the anti-resonance filtering module, and the signal after amplitude limiting processing is filtered through the low-pass filtering module to remove the unnecessary frequency components therein, and the fourth digital signal finally obtained is provided to the capacitive load after amplification by the class D power amplifier, so that the capacitive load can output the amplified signal of the source signal. Therefore, the embodiment of the present application can realize the capacitive load overcurrent protection suitable for the class D power amplifier through amplitude limiting, resonance peak suppression and filtering, and can effectively eliminate the resonance peak generated by the capacitive load and its front-stage element, and significantly improve the quality of the amplified signal output by the capacitive load.

[0036] The high-frequency overcurrent problem of capacitive loads is mainly solved by hardware circuit solutions. Figure 1 The following diagram shows an example of the hardware circuit structure of the capacitive load overcurrent protection. Figure 1The hardware circuit structure 100 includes: a Class-DAMP, Class D Amplifier 101, a first inductor 102, a second inductor 103, a first capacitor (Cap) 104, a second capacitor 105, a power resistor 106 and a capacitive load (Piezocapacitive load) 107. The hardware circuit reduces the current on the Class-D power amplifier by connecting the power resistor 106 in series between the capacitive load 107 and the Class-D power amplifier 101, thereby solving the high-frequency overcurrent problem.

[0037] Figure 1 In the hardware circuit solution, the first inductor 102, the second inductor 103, the first capacitor 104 and the second capacitor 105 form an LC low-pass filter. The combination of the LC low-pass filter and the capacitive load 107 will produce resonance at high frequencies, forming a voltage peak. The voltage peak is the resonance peak generated by the mutual influence of the LC low-pass filter and the capacitive load 107. In physics, the resonance peak is the phenomenon in which the system responds the most at a specific frequency, which is usually related to the resonance frequency. The resonance peak will cause the Class D power amplifier to overcurrent. See Figure 1 Because the power resistor 106 as the series impedance and the structure of the hardware circuit structure 100 in the hardware solution cannot be dynamically adjusted, it is not only unable to adapt to the characteristics of the capacitive load that exhibits high impedance at low frequencies and low impedance at high frequencies, but also has poor overcurrent protection effect on the class D power amplifier. In addition, in order to protect the class D power amplifier from being damaged, it is necessary to limit the output power of the system at the same time, which is more likely to cause distortion of the high-frequency part of the system output signal, thereby affecting the output sound pressure level and output signal quality of the system.

[0038] It can be seen that the use of this hardware circuit solution to implement overcurrent protection of the load will not only increase hardware costs, increase PCB area, accelerate system power dissipation, and affect system efficiency, but also fail to adapt to the characteristics of capacitive loads that exhibit high impedance at low frequencies and low impedance at high frequencies. The overcurrent protection effect is poor and is more likely to cause distortion of the high-frequency part of the system output signal, thereby affecting the system's output sound pressure level and output signal quality.

[0039] The embodiment of the present application is implemented using a software algorithm, which can reduce hardware costs, reduce the area occupied by the PCB, and at the same time reduce power dissipation and improve system efficiency.

[0040] In addition, the embodiment of the present application may also include: a post-parametric equalization module and a spectrum expansion module implemented by a software algorithm, which performs high-frequency compensation through the post-parametric equalization module and frequency band expansion through the spectrum expansion module, which can effectively compensate for high-frequency losses and further improve the quality of the amplified signal output by the capacitive load. The post-parametric equalization module can also correct the spectrum distortion caused by the error of the anti-resonance filter.

[0041] The embodiments of the present application may be applicable to various systems including capacitive loads. For example, the embodiments of the present application may be applicable to an audio system using a piezoelectric speaker.

[0042] It should be noted that the embodiments of the present application are not only applicable to capacitive loads, but also to other loads except capacitive loads. When applied to other loads, if no resonance peak is generated, the anti-resonance filter module can be set to be turned off, and if a resonance peak may still be generated, the anti-resonance filter module can be turned on. If applied to other loads except capacitive loads, the device includes: a limiting module, which is used to perform limiting processing on the first digital signal corresponding to the source signal to obtain a second digital signal, so that the current applied to the class D power amplifier does not exceed the current peak value that the class D power amplifier can support; a low-pass filtering module, which is used to filter the second digital signal to obtain a fourth digital signal, and the fourth digital signal is used to be provided to the load after being processed by the class D power amplifier, so that the load can output an amplified signal of the source signal.

[0043] It should also be noted that the low-pass filter cutoff frequency of the low-pass filter module in the embodiment of the present application is not limited to 20KHz to filter out frequency signals other than 20KHz. If the output signal is not only suitable for human ears, the cutoff frequency of the low-pass filter module can be adjusted according to the application.

[0044] The specific implementation of the embodiments of the present application is described in detail below.

[0045] Figure 2 FIG. 1 shows an exemplary structural diagram of a capacitive load overcurrent protection device according to an embodiment of the present application. Figure 3 A schematic diagram showing the structure of a capacitive load overcurrent protection device and its signal transmission process according to an embodiment of the present application is shown.

[0046] See also Figure 2 and Figure 3The capacitive load overcurrent protection device 200 of the embodiment of the present application may include: a limiting module (Smart dynamic limiter) 201, an anti-resonance filter module (Anti-resonance filter) 202 and a low-pass filter module (LPF, Low-Pass Filter) 203, the limiting module can be used to limit the first digital signal corresponding to the source signal to obtain a second digital signal, so that the current applied to the class D power amplifier does not exceed the current peak value that the class D power amplifier can support. The anti-resonance filter module can be used to suppress some frequency components in the second digital signal according to a predetermined center frequency to obtain a third digital signal, the center frequency is determined according to the frequency of the resonance peak, and the resonance peak is a resonance peak generated by the interaction of the capacitive load and its front-stage element. The low-pass filter can be used to filter the third digital signal to obtain a fourth digital signal, and the fourth digital signal is used to be provided to the capacitive load after being processed by the class D power amplifier, so that the capacitive load can output an amplified signal of the source signal.

[0047] In the embodiment of the present application, the operating mode supported by the capacitive load overcurrent protection device 200 may include a feedforward mode and / or a feedback mode. Figure 3 If the feedback signal of the capacitive load can be received in real time, the capacitive load overcurrent protection device 200 can support both the feedback mode and the feedforward mode, and can work in either the feedback mode or the feedforward mode, and the feedforward mode and the feedback mode of the capacitive load overcurrent protection device 200 can be flexibly switched, manually switched, and / or automatically switched. If the feedback signal of the capacitive load cannot be received, the capacitive load overcurrent protection device 200 can only support the feedforward mode.

[0048] The source signal may be a signal of various types. If the capacitive load is a piezoelectric speaker, the source signal may be a sound source signal to be amplified, and the amplified signal of the source signal may be an audio amplified signal output by the piezoelectric speaker. If the capacitive load is of other types, the corresponding source signal type may also be of other types. The specific type of the source signal is not limited in the embodiments of the present application.

[0049] The first digital signal can be obtained according to the source signal. If the source signal is an analog signal, the first digital signal can be a digital signal obtained by analog-to-digital conversion of the source signal. If the source signal is a digital signal, the first digital signal can be the source signal itself, or a digital signal obtained by overall amplitude modulation of the source signal.

[0050] The feedback signal of the capacitive load can be used to indicate the output current and / or output voltage of the capacitive load. In one example, the feedback signal of the capacitive load can include the output current and / or output voltage of the capacitive load. For example, the feedback signal of the capacitive load can be a real-time output current signal or a real-time output voltage signal of the capacitive load. In a specific application, a sensor can be connected to the capacitive load, and the voltage or current signal of the capacitive load is collected in real time by a voltage or current sensor and provided to the capacitive load overcurrent protection device 200.

[0051] During the operation of the capacitive load, due to external environmental factors such as temperature and the influence of load aging due to long-term use, the load impedance will change, thus affecting the estimation accuracy. Therefore, the impedance of the capacitive load can be dynamically updated in real time through the feedback signal of the capacitive load, so as to more accurately perform overcurrent protection on the Class D power amplifier.

[0052] In some implementations, the feedback signal of the capacitive load may be a voltage and current signal (I / V sence) of the capacitive load collected by a sensor. In the feedback mode, the real-time impedance of the capacitive load may be determined using the feedback signal, and the limiting processing of the limiting module may be adjusted in real time by the impedance of the capacitive load, and the parameters of the anti-resonance filter module may be updated in real time, so that the anti-resonance filter module may more accurately eliminate the influence of the resonance of the capacitive load and the system to which it belongs, and the limiting module may adjust the limiting measures in real time in combination with the actual output of the capacitive load.

[0053] In some embodiments of the present application, the anti-resonance filter module 202 can use a peak filter, which can be used to enhance or suppress any desired frequency component. Therefore, the use of a peak filter can make the anti-resonance filter module play a role in suppressing a specific frequency (i.e., the resonance peak frequency). In one example, the anti-resonance filter module can be a second-order peak filter.

[0054] Figure 4 An exemplary block diagram of the working principle of the anti-resonance filtering module 202 is shown. Figure 4 In, z -1 represents a delay unit. When the gain G of the anti-resonance filter module 202 is greater than or equal to 0, the desired frequency component is increased. Let c B / C =c B , when the gain G is less than 0, the desired frequency component is suppressed. Let c B / C =c C . Figure 4In the figure, the input signal x(n) of the anti-resonance filter is the second digital signal output by the dynamic limiter. The input signal x(n) is converted into the intermediate signal y1(n) by A2(z). The input signal x(n) is added to the intermediate signal y1(n) and then multiplied by H0 / 2. The multiplied signal is then added to the input signal x(n) to obtain the output signal y(n). The output signal y(n) is the third digital signal. Figure 4 The intermediate variables involved are d, H0, c B 、c C The relationships shown in the following equations (1) to (5) are satisfied.

[0055]

[0056]

[0057] H0=V0-1 (3)

[0058]

[0059]

[0060] Among them, fc is the center frequency of the anti-resonance filter module, fs1 is the sampling rate of the anti-resonance filter module, G is the gain of the anti-resonance filter module, fb=fc / Q, fb is the bandwidth of the anti-resonance filter module, and Q is the Q value of the anti-resonance filter module.

[0061] pass Figure 4 It can be seen that when the anti-resonance filter module adopts a peak filter, the gain G of the anti-resonance filter module is less than 0 to eliminate the resonance peak, which plays a role in suppressing the resonance peak frequency.

[0062] In the embodiment of the present application, an anti-resonance filter module 202 is added to the capacitive load overcurrent protection device to offset the resonance peak generated by the interaction of the capacitive load and its preceding element, and can effectively eliminate the influence of the resonance peak on the quality of the capacitive load output signal.

[0063] In some embodiments of the present application, the parameters of the anti-resonance filter module 202 may include but are not limited to the center frequency, gain value and Q value (quality factor) of the anti-resonance filter module. Among them, the center frequency of the anti-resonance filter module can be determined according to the frequency of the resonance peak generated by the interaction of the capacitive load and its front-stage element (e.g., LC low-pass filter), the gain value of the anti-resonance filter module is equal to the inverse of the resonance peak value, and the Q value can be set slightly loose to ensure that the influence of the entire resonance peak can be eliminated.

[0064] In some implementations, a measuring device may be used to measure in advance the frequency value of a resonance peak generated by the interaction between a capacitive load and its preceding element (LC low-pass filter), and the center frequency of the anti-resonance filter module may be manually or automatically configured to be the frequency value of the resonance peak.

[0065] In some implementations, the center frequency of the anti-resonance filter module 202 may also be adjusted in real time according to a feedback signal of the capacitive load, and details may be found in the following embodiments.

[0066] In some embodiments of the present application, the cutoff frequency of the low-pass filter module 203 can be set as needed. For example, when the capacitive load is a piezoelectric speaker, considering that the frequency of the audio signal that can be recognized by the human ear is within 20KHz, the low-pass filter module 203 can be a low-pass filter (LPF) with a cutoff frequency of 20KHz, so as to filter out the frequency components other than 20KHz in the third digital signal through the low-pass filter module, so that the frequency of the fourth digital signal is consistent with the human ear frequency.

[0067] Figure 5 FIG. 2 shows an exemplary processing flow of the frequency band extension module 205. Figure 5 The frequency band extension module 205 may include: a harmonic unit 2051, a delay unit 2052 and a synthesis unit 2053. The input signals of the harmonic unit 2051 and the delay unit 2052 are both the fourth digital signal after frequency compensation from the post-parametric equalization module 204. The output signal of the harmonic unit 2051 is a harmonic signal. The output signal of the delay unit 2052 is a delayed fourth digital signal. The synthesis unit 2053 is used to add the harmonic signal and the delayed fourth digital signal to output the fourth digital signal after bandwidth expansion.

[0068] See also Figure 5 The harmonic unit 2051 includes a first bandpass filter FIL1, a nonlinear device (NLD), a second bandpass filter FIL2 and a scaling unit G connected in sequence. The first bandpass filter FIL1 is used to extract the frequency band component to be extended from the fourth digital signal from the post-parametric equalization module, the nonlinear device is used to generate the harmonic component of the frequency band to be extended, the second bandpass filter is used to extract the required harmonic component, and the scaling unit is used to scale the harmonic after the frequency band is extended to output a harmonic signal. Among them, the frequency band range of the first bandpass filter FIL1 is f res / 2-f res , fres is the resonance frequency of the resonance caused by the interaction between the capacitive load and the front-stage component (LC low-pass filter). The frequency band range of the second band-pass filter FIL2 can be f res ~2f res, i.e., a double frequency band. Exemplarily, FIL1 and FIL2 can be linear phase filters, respectively, and NLD can be a rectifier. The embodiment of the present application adopts a first bandpass filter FIL1, a nonlinear device (NLD, non linear device), a second bandpass filter FIL2 and a scaling unit G to obtain a harmonic signal, and its algorithm is simple, and the harmonic signal obtained by combining two bandpass filters with a nonlinear device and a scaling unit is added to the delayed fourth digital signal, which can better achieve bandwidth expansion of the fourth digital signal.

[0069] See also Figure 5 The delay unit 2052 is used to delay the fourth digital signal from the post-parametric equalization module 204 to obtain a delayed fourth digital signal, and the delayed fourth digital signal is in phase with the harmonic signal output by the harmonic unit. The delay unit can compensate for the delay generated by each filter in the harmonic unit, so that the signals of the two branches in the frequency band extension module can be in phase.

[0070] In one example, the frequency band extension module 205 can also be used to res >f s / 4(f s When the sampling rate is , the fourth digital signal is firstly up-sampled and then the frequency band is extended.

[0071] An exemplary specific implementation of the amplitude limiting module 201 in the capacitive load overcurrent device 200 is described in detail below.

[0072] The impedance parameters of the capacitive load and the preceding element are used to estimate the current magnitude when the first digital signal passes through the capacitive load. In one example, the LC low-pass filter preceding the capacitive load can be Figure 1 The circuit structure shown, that is, the LC low-pass filter in the front stage of the capacitive load may include a first inductor, a second inductor, a first capacitor and a second capacitor. Accordingly, the parameters of the LC low-pass filter may include but are not limited to the rated inductance of the first inductor, the rated inductance of the second inductor, the rated capacitance of the first capacitor, the rated capacitance of the second capacitor, etc. The parameters of the piezoelectric speaker itself may include the impedance parameters of the piezoelectric speaker.

[0073] In some implementations, the limiting module is specifically used to:

[0074] A current signal is obtained according to the first digital signal and the impedance parameters of the capacitive load and the front-stage element. The current signal is used to indicate the real-time current applied to the class D power amplifier. The equivalent impedance of the capacitive load and the front-stage element is assumed to be Z, and the voltage corresponding to the first digital signal is V, then the current signal can be obtained by I=V / Z. If the effective value of the first digital signal is greater than the predetermined current threshold, it means that the current is too large, and the limiting module will automatically open, limit the first digital signal, and obtain the second digital signal to achieve overcurrent protection for the class D power amplifier to prevent the class D power amplifier from being damaged by excessive current; if the current signal is less than or equal to the current threshold, the limiting module can be automatically closed without limiting, and the first digital signal is used as the second digital signal. Among them, the current threshold can be determined according to the current peak value that the class D power amplifier can support, and the front-stage element includes an LC low-pass filter. Therefore, the limiting module can determine in real time whether the current on the Class D power amplifier is too large based on the impedance parameters of the capacitive load and the previous-stage component and the first digital signal, and limit the first digital signal when the current on the Class D power amplifier is too large, thereby realizing dynamic limiting of the first digital signal.

[0075] In some implementations, the root mean square (RMS) value of the current signal is obtained. The use of the root mean square value can better reflect the overcurrent state of the Class D power amplifier and prevent the impact of short-term sudden changes in the current signal. At the same time, the root mean square value is more closely related to the signal loudness perceived by the human ear, which can further improve the effect of overcurrent protection of the Class D power amplifier in audio scenarios.

[0076] In some implementations, the limiting module is specifically used to:

[0077] According to the feedback signal of the capacitive load, the current value of the feedback signal of the capacitive load is obtained; the current signal is used to indicate the real-time current applied to the class D power amplifier, and the feedback signal of the capacitive load is the voltage or current signal of the capacitive load; if the current value of the feedback signal of the capacitive load is greater than the predetermined current threshold, the first digital signal is limited to obtain the second digital signal; if the current value of the feedback signal of the capacitive load is less than or equal to the current threshold, no limiting process is performed, and the first digital signal is used as the second digital signal; wherein the current threshold is determined according to the current peak value that the class D power amplifier can support. Thus, the limiting module can judge in real time whether the current on the class D power amplifier will be too large based on the feedback signal of the capacitive load, and the first digital signal is limited in the case that the current on the class D power amplifier may be too large, thereby realizing dynamic limiting of the first digital signal.

[0078] Specifically, in the feedback mode, when the current value of the feedback signal of the capacitive load is greater than a predetermined current threshold, it indicates that excessive current may occur, and the limiting module will automatically open and perform limiting processing on the first digital signal to achieve overcurrent protection of the Class D power amplifier to prevent excessive current from damaging the Class D power amplifier; when the current value of the feedback signal of the capacitive load is less than or equal to the predetermined current threshold, the limiting module can be automatically closed or remain closed, and no limiting processing is performed.

[0079] In some implementations, the root mean square value of the current value of the feedback signal of the capacitive load is obtained. The root mean square value can better reflect the overcurrent state of the class D power amplifier, prevent the influence of short-term mutation of the current signal, and further improve the effect of overcurrent protection of the class D power amplifier in the audio scene.

[0080] In some implementations, the limiting module performs limiting processing on the first digital signal to obtain the second digital signal, including:

[0081] Performing delay processing on the first digital signal to obtain a delayed signal of the first digital signal;

[0082] Limiting the current of the first digital signal to a current threshold;

[0083] Calculating a gain factor of the first digital signal according to the current threshold and the current signal;

[0084] Smoothing the gain factor to obtain a smoothed gain factor;

[0085] The smoothed gain factor is applied to the delayed signal of the first digital signal to obtain a second digital signal.

[0086] Therefore, the gain factor can be dynamically adjusted according to the amplitude of the first digital signal to achieve dynamic amplitude limiting of the first digital signal.

[0087] Figure 6 FIG. 2 shows an exemplary flow chart of the limiting module performing limiting processing in the feedforward mode. Figure 6 , an exemplary process of performing limiting processing by the limiting module in the feedforward mode may include the following steps:

[0088] Step 601, receiving a frame sequence input(n) of a first digital signal, where input(n) is a voltage sequence;

[0089] For example, the frame length of the frame sequence input(n) may be 10 ms.

[0090] Step 602, delaying the frame sequence input(n) of the first digital signal to obtain a delayed frame sequence inDelay(n);

[0091] In an example, assuming that the preset number of delayed samples is N1, the delayed frame sequence inDelay(n) of the frame sequence input(n) can be expressed as the following formula (6).

[0092] inDelay(n)=input(n–N1) (6)

[0093] The delayed sampling number N1 can be set in combination with the delayed processing time of the delayed signal obtained by delay processing of the first digital signal. Since the gain factor calculation will cause delay, the gain factor can be accurately applied to the corresponding signal in the sequence by delaying the first digital signal.

[0094] Step 603, converting the frame sequence input(n) into a current sequence x(n) according to the circuit parameters of the capacitive load;

[0095] Step 604, calculating the effective value Xrms of the current sequence x(n);

[0096] Among them, the effective value Xrms refers to the RMS value of the current sequence x(n), also known as the effective value, which can be used to characterize the energy in the signal. For example, the RMS value of the current sequence x(n) can be calculated in the time domain by first calculating the sum of the squares of all amplitudes in the current sequence x(n), then dividing the sum of the squares of all amplitudes in the current sequence x(n) by the number of samples N in the current sequence x(n), and finally taking the square root to obtain the effective value Xrms of the current sequence x(n). The number of samples N in the current sequence x(n) is the number of samples of input(n). In an example, the number of samples N can be calculated by the sampling rate and the frame length of the frame sequence input(n).

[0097] Step 605, determining whether the effective value Xrms of the current sequence x(n) is greater than a preset current threshold Ioc;

[0098] If the effective value Xrms of the current sequence x(n) is less than or equal to the current threshold Ioc, there is no need for limiting, and step 610 is executed. The gain factor g of each signal in the current sequence x(n) can be directly set to 1, and the process jumps to step 608; if the effective value Xrms of the current sequence x(n) is greater than the current threshold Ioc, limiting is required, the limiting module is started, and step 606 is continued.

[0099] In one example, the current threshold Ioc is related to the class D power amplifier, and the current threshold Ioc can be determined in combination with the situation of the class D power amplifier. That is, a slightly larger or smaller value is selected from the current peak value that the class D power amplifier can support as needed, or the current threshold Ioc is directly set to the current peak value that the class D power amplifier can support.

[0100] Step 606, limiting the current sequence x(n) to the current threshold Ioc;

[0101] Step 607, calculating the gain factor of each amplitude in the current sequence x(n);

[0102] In an example, the gain factor g of each signal in the current sequence x(n) can be calculated by the following equation (7).

[0103] g=Ioc / Xrms (7)

[0104] Wherein, Ioc represents the current threshold, and Xrms represents the effective value of the current sequence x(n).

[0105] If the current sequence x(n) has not been subjected to the amplitude limiting process in step 605 , the value of the gain factor g is 1. If the current sequence x(n) has been subjected to the amplitude limiting process in step 605 , the value of the gain factor g is less than 1.

[0106] Step 608, in order to prevent signal mutation, the gain factor g of each amplitude in the current sequence x(n) is smoothed to obtain a smoothed gain factor g_smooth;

[0107] Step 609: Apply the smoothing gain factor g_smooth to the delayed frame sequence inDelay(n) to obtain a frame sequence output(n) of the second digital signal.

[0108] In an example, the frame sequence output(n) of the second digital signal can be obtained by the following formula (8).

[0109] output(n–N1)=inDelay(n–N1)*g_smooth (8)

[0110] Here, “*” indicates multiplication.

[0111] Step 610: directly set the gain factor g of each signal in the current sequence x(n) to 1.

[0112] Figure 7 FIG. 1 shows an exemplary flow chart of the amplitude limiting module performing the amplitude limiting process in the feedback mode. Figure 6 The exemplary process of the limiting module performing limiting processing in the feedback mode may include the following steps:

[0113] Steps 701 to 702 are the same as steps 601 to 602;

[0114] Step 703, receiving a frame sequence x'(n) of a feedback signal of a capacitive load, where the frame sequence x'(n) is a current sequence;

[0115] Step 704, calculating the effective value Xrms of the frame sequence x'(n);

[0116] Step 705, determine whether the effective value Xrms of the frame sequence x'(n) is greater than the preset current threshold Ioc. If so, limiting is required, the limiting module is started, and step 706 is continued. Otherwise, limiting is not required, and step 710 is executed. The gain factor g of each signal in the current sequence x(n) can be directly set to 1, and jump to step 708;

[0117] Steps 706 to 710 are the same as steps 606 to 610.

[0118] Figure 8 Another exemplary structural diagram of the capacitive load overcurrent protection device according to an embodiment of the present application is shown. Figure 8 As shown, in some embodiments of the present application, the capacitive load overcurrent protection device may further include: an adaptive control module 206, which is used to generate an impedance curve of the capacitive load according to the feedback signal of the capacitive load, and determine the frequency of the resonance peak based on the impedance curve of the capacitive load, and adjust the center frequency of the anti-resonance filter module to the frequency of the resonance peak. The impedance curve of the capacitive load is used to indicate the impedance of the capacitive load.

[0119] When the capacitive load is working, due to the influence of external environmental factors such as temperature and the aging of the load due to long-term use, the load impedance will change, thereby affecting the estimation accuracy. By adding the adaptive control module 206, the impedance of the capacitive load can be dynamically updated in real time based on the feedback signal of the capacitive load, and the parameters of the anti-resonance filter module can be dynamically adjusted, so that the center frequency of the anti-resonance filter module can change in real time with the resonance peak frequency corresponding to the capacitive load, thereby eliminating the resonance peak more accurately, avoiding excessive high-frequency current of the class D power amplifier, and improving the quality of the output signal.

[0120] In one example, the impedance curve of the capacitive load can be used to indicate the impedance of the capacitive load at different frequencies. In one example, the impedance curve of the capacitive load can be used to indicate the impedance of the capacitive load at different operating frequencies, with the impedance of the capacitive load as a function value and the operating frequency of the capacitive load as a variable. For example, the impedance curve of the capacitive load can be expressed as Z piezo (s), s represents the operating frequency of the capacitive load, Z piezo Represents the impedance corresponding to the operating frequency s.

[0121] Fig. 9 FIG. 2 shows a schematic diagram of the processing process of the adaptive control module 206. Fig. 9 As shown, the adaptive control module 206 includes:

[0122] The extraction unit is used to extract the real-time output current I(t) and the real-time output voltage V(t) of the capacitive load from the feedback signal of the capacitive load.

[0123] An estimation unit, used to process the real-time output current I(t) of the capacitive load using the capacitive load model of the adaptive filter to obtain a real-time estimated voltage V of the capacitive load. est (t).

[0124] Specifically, the adaptive filter is an L based Laplace transform. -1 (Z piezo ) adaptive filter, where Z piezo (s) is the capacitive load model.

[0125] The adjustment unit is used to continuously update the parameters of the impedance curve using a predetermined adaptive filtering algorithm to minimize the error between the real-time output voltage of the capacitive load and the real-time estimated voltage, and adjust the parameters of the impedance curve to the parameters of the impedance curve corresponding to the minimum value of the error.

[0126] Specifically, the adaptive filtering algorithm is a Normalized Least Mean Square (NLMS) adaptive filtering algorithm.

[0127] Capacitive load model Z piezo The parameters of (s) are the real-time output voltage V(t) and the real-time estimated voltage V est The parameter when the error e(t) between (t) is the smallest. The adaptive filtering algorithm can select the Normalized Least Mean Square (NLMS) adaptive filtering algorithm.

[0128] In one example, the adaptive filter L -1 (Z piezo ) can be expressed as the following formula (9).

[0129] V est (t)=I(t)*L -1 Z piezo (s) (9)

[0130] Among them, V est (t) represents the estimated voltage information of the capacitive load, I(t) represents the real-time output current information of the capacitive load, L -1 It is expressed as Laplace transform, t represents time, Z piezo (s) represents the capacitive load model.

[0131] In one example, the real-time output voltage V(t) and the real-time estimated voltage V estThe error e(t) between (t) can be obtained by the following formula (10):

[0132] e(t)=V(t)–V est (t) (10)

[0133] Wherein, e(t) represents the error between the real-time output voltage of the capacitive load and the real-time estimated voltage.

[0134] It should be noted that the parameters of the capacitive load model are continuously updated to minimize the real-time output voltage V(t) and the real-time estimated voltage V est The error e(t) between the real-time output voltage V(t) and the real-time estimated voltage V est The error e(t) between the real-time output voltage V(t) and the real-time estimated voltage V est The embodiment of the present application does not limit the adaptive filtering algorithm used to minimize the error and the specific calculation method of the error.

[0135] The setting unit is used to combine the impedance curve with the front-stage element to obtain the frequency of the resonance peak, and adjust the center frequency of the anti-resonance filter module to the frequency of the resonance peak.

[0136] In this embodiment, there are multiple ways for the adaptive control module 206 to determine the resonance peak frequency based on the impedance curve of the capacitive load. In one example, the real-time resonance peak frequency can be obtained by Fourier transform (FFT) analysis based on the impedance curve of the capacitive load and the circuit parameters of the front-stage LC low-pass filter. Here, the circuit parameters of the front-stage LC low-pass filter can refer to the above-mentioned records and will not be repeated here.

[0137] Considering that the impedance curve may be estimated in real time using the voltage or current signal of the capacitive load, special situations such as silent signals, single-frequency signals, or sparse signals may be encountered, which may lead to errors in the impedance curve estimation.

[0138] See also Figure 8 As shown, in some embodiments of the present application, the capacitive load overcurrent protection device 200 further includes:

[0139] The first detection module 207 is used to determine whether the current frame is a mute frame or a non-mute frame according to the signal time domain energy of the current frame in the feedback signal of the capacitive load.

[0140] The adaptive control module is also used to determine the impedance curve of the capacitive load according to the non-silent frame in the feedback signal of the capacitive load.

[0141] In this embodiment, the adaptive control module 206 can be used to determine the impedance curve of the capacitive load by using the signal frame that does not belong to the silent frame in the feedback signal of the capacitive load. By adding the first detection module, the impedance curve estimation error caused by the silent signal can be avoided, making the real-time estimated impedance curve more robust.

[0142] In some implementations, the first detection module is specifically used to:

[0143] The signal time domain energy of the current frame is compared with a preset silence threshold.

[0144] If the signal time domain energy of the current frame is less than the silence threshold, the current frame is determined to be a silence frame; otherwise, the current frame is determined to be a non-silence frame.

[0145] The silence threshold may be set to an empirical value. Generally, the signal time domain energy of a silence frame is close to 0, and the specific value of the silence threshold may be flexibly set according to the actual application scenario.

[0146] In one implementation, the following method can be used to set the silence flag of the current frame: add a silence flag non_silence to the current frame, and if the current frame is determined to be a silence frame, set the value of the silence flag to 0; if the current frame is determined to be a non-silence frame, set the value of the silence flag to 1.

[0147] The silent frame determination method adopted in the embodiment of the present application requires little calculation and is easy to operate.

[0148] In some implementations, the first detection module is further configured to determine a silent segment or a non-silent segment in the feedback signal of the capacitive load according to the number of silent frames or non-silent frames;

[0149] The adaptive control module is also used to determine the impedance curve of the capacitive load according to the non-silent segment in the feedback signal of the capacitive load.

[0150] In one implementation, it can also be used to update the silent frame (or non-silent frame) count in the following manner: within a preset time period, count the number of non-silent frames (you can also choose to count the number of silent frames, which will not be repeated here), if the current frame is a non-silent frame, add 1 to the non-silent frame count, and determine whether the non-silent frame count reaches a predetermined value m. If the non-silent frame count reaches the predetermined value m, the silent segment flag bit enoughFlag can be set to 1 to indicate a non-silent segment, and the non-silent frame count can be reset to zero, otherwise the silent segment flag bit enoughFlag is set to 0 to indicate a silent segment. The length of the preset time period corresponds to the length of the non-silent segment, and is selected and set by those skilled in the art as needed.

[0151] The embodiment of the present application determines the silent segment or non-silent segment in the feedback signal of the capacitive load by the number of silent frames or non-silent frames. When there is a non-silent frame caused by noise among multiple silent frames, it will further determine whether it is a silent segment, and the non-silent frame in the silent segment will not be processed, so as to avoid the impedance curve estimation error.

[0152] See also Figure 8 As shown, in some embodiments of the present application, the capacitive load overcurrent protection device 200 further includes:

[0153] The second detection module 208 is used to determine whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the signal frequency domain energy of the current frame in the feedback signal of the capacitive load for the non-silent frame.

[0154] Alternatively, the second detection module 208 is configured to determine whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame based on the signal frequency domain energy of the current frame in the feedback signal of the capacitive load for the non-silent frame and the non-silent segment.

[0155] The adaptive control module is also used to determine the impedance curve of the capacitive load according to the non-single-frequency signal frame in the feedback signal of the capacitive load.

[0156] In this embodiment, the adaptive control module 206 can be used to determine the impedance curve of the capacitive load by using the signal frame that does not belong to the single-frequency signal frame in the feedback signal of the capacitive load. By adding the second detection module, the impedance curve estimation error caused by the single-frequency signal can be avoided, making the real-time estimated impedance curve more robust.

[0157] In addition, the embodiment of the present application first judges the silent frame in the time domain with less calculation amount, and then judges the single-frequency signal frame in the frequency domain with more calculation amount. If the signal frame does not belong to the silent frame, it will continue to judge whether it belongs to the single-frequency signal frame, thereby avoiding the increase of software algorithm calculation amount caused by the large amount of frequency domain calculation.

[0158] The second detection module is specifically used for:

[0159] Performing a windowed Fourier transform on the feedback signal of the capacitive load to obtain the maximum value of the frequency domain signal energy from the initial frequency point to the intermediate frequency point;

[0160] The frequency domain signal energy difference between adjacent frequency points is calculated, and according to the energy difference and the maximum value of the frequency domain signal energy, it is determined whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame.

[0161] The single-frequency signal frame determination method adopted in the embodiment of the present application has low computational complexity and is easy to operate.

[0162] In one implementation, the second detection module is further used to:

[0163] Determine a sparse signal in the feedback signal of the capacitive load according to the energy difference and the maximum energy value of the frequency domain signal;

[0164] The adaptive control module is further used to determine the impedance curve of the capacitive load according to the non-sparse signal in the feedback signal of the capacitive load.

[0165] The embodiment of the present application can further eliminate the influence of the sparse signal on the impedance curve of the capacitive load through the second detection module, thereby further avoiding the estimation error of the impedance curve of the capacitive load.

[0166] The specific algorithm used by the second detection module is further described below. The second detection module is specifically used for:

[0167] A windowed Fourier transform is performed on the feedback signal of the capacitive load to obtain the maximum energy value of the frequency domain signal from the initial frequency point to the intermediate frequency point and the index of the maximum energy value of the frequency domain signal.

[0168] The frequency domain signal energy difference between adjacent frequency points is calculated to obtain a first array.

[0169] The elements from the beginning to the index of the maximum frequency domain signal energy value in the first array are kept unchanged, and the inverse of the element from the index of the maximum frequency domain signal energy value to the last element is taken to obtain the second array.

[0170] The elements in the second array that are greater than 0 are kept unchanged, otherwise, they are updated to 0 to obtain the third data.

[0171] Each element in the third array is divided by the maximum frequency domain signal energy value to obtain a fourth array.

[0172] The maximum value element in the fourth array is compared with 1 to obtain a minimum value, and the minimum value is assigned to the sparse flag.

[0173] If the sparse flag sparseSigDet is 0, the current frame is a single-frequency signal frame, otherwise it is a non-single-frequency signal frame.

[0174] If the sparse flag sparseSigDet is not 0 and the sparse flag sparseSigDet is less than the sparse threshold, the current frame is a sparse signal frame, otherwise it is a non-sparse signal frame.

[0175] Specifically, those skilled in the art may set the sparse threshold to a value close to 1 as needed. The sparse threshold represents the richness of the frequency components of the signal, and the sparse flag bit of white noise is 1.

[0176] The value of the sparse flag sparseSigDet is between 0 and 1. When the value of the sparse flag sparseSigDet is 0, it indicates that the current frame is a single-frequency signal. When the value of the sparse flag sparseSigDet is 1, it indicates that the current frame is a full-frequency signal (that is, a white noise signal). The value of the sparse flag sparseSigDet other than 0 and 1 indicates that the current frame is a signal between a single-frequency signal and a full-frequency signal.

[0177] Fig.10 The following is a schematic diagram of an exemplary processing flow for a silence frame, a single-frequency signal frame, and a sparse signal frame. The processing flow is as follows:

[0178] Step 1001, obtaining the signal time domain energy of the current frame.

[0179] Step 1002, determine whether it is a silent frame based on the signal time domain energy of the current frame, if so, execute step 1012, if not, execute step 1003.

[0180] Specifically, if the frame is a silence frame, the silence flag bit non_silence = 0, otherwise the silence flag bit non_silence = 1. If non_silence = 0, it means that the current frame is a silence frame, and step 1011 is executed.

[0181] Step 1003: if the current frame is not a silence frame, update the count value of the non-silence frame (silence flag bit non_silence=1).

[0182] Specifically, a buffer of preset size is used to save the value of the non_silence flag of each frame. Assume that the buffer size is 50, that is, the array size is 50, and each element represents the state of a frame. The initial state buffer array elements are 50 zeros. If there are a total of m frames (assuming n=20) in the buffer and the non_silence flag is 1, it means that this period is a non-silent segment, otherwise it is a silent segment. The buffer follows the first-in-first-out principle, that is, each time a frame of silence flag is determined, it is placed at the end of the buffer, and the silence flag data of the previous m-2 frame is moved out of the buffer. The total number of silence flags placed in the buffer is m frames. The number of silence flags will be counted for each incoming frame, and the count value will be saved using a counter (count) variable, and the silence segment flag enoughFlag will be obtained.

[0183] Step 1004, if it is a non-silent frame, determine whether it is a non-silent segment, if so, execute step 1005, if not, execute step 1012.

[0184] Specifically, whether it is a non-silent segment can be determined by judging whether the non-silent frame count reaches a predetermined value m. For example, if there are more than m frames that are non-silent frames, it is determined to be a non-silent segment.

[0185] Specifically, when the count of the counter of the buffer is greater than or equal to m, the silent segment flag bit enoughFlag is set to 1, indicating that this period of time is a non-silent segment, otherwise the silent segment flag bit enoughFlag is set to 0.

[0186] If the current frame silence flag bit non_silence=0 (indicating that the current frame is a silence frame) or the silence segment flag bit enoughFlag=0 (indicating that this period of time is a silence segment), step 1012 is executed.

[0187] Step 1005, obtaining the signal frequency domain energy of the current frame, and determining the maximum frequency energy of the current frame.

[0188] Specifically, if the current frame silence flag non_silence=1 (indicating that the current frame is a non-silent frame) or the non-silent frame number flag enoughFlag=1 (indicating that this period is a non-silent segment), the signal frequency domain energy of the current frame is obtained to determine the maximum frequency point energy of the current frame.

[0189] Specifically, the signal of the current frame is windowed (e.g., Hanning window) and fast Fourier transformed (e.g., N=2048-point FFT processing) to calculate the signal energy from 1 to N / 2 frequency points, and obtain the maximum value of the N / 2 frequency point energy and the frequency point index imax corresponding to the maximum value.

[0190] Step 1006: Calculate the energy difference between adjacent frequency points in the current frame to obtain a first array.

[0191] The energy difference array diff is obtained by subtracting the energy of the previous frequency point from the energy of the next frequency point in the frequency domain energy of the signal obtained for each frame. Specifically, diff = bins(1:end-1)-bins(2:end), where diff represents the first array, bins(1:end-1) represents the energy array composed of all frequency points from the first frequency point to the second to last frequency point, and bins(2:end) represents the energy array composed of all frequency points from the second frequency point to the last frequency point.

[0192] Step 1007: Process the elements in the first array to obtain a second array.

[0193] The elements from the beginning to the index of the maximum frequency domain signal energy value in the first array are kept unchanged, and the inverse of the element from the index of the maximum frequency domain signal energy value to the last element is taken to obtain the second array.

[0194] Take the opposite of the second half of the energy difference values ​​in the energy difference array diff from the imax index value to the last value of the array, and then combine the first half of the energy difference values ​​in the energy difference array diff from the first value of the array to the imax index to obtain the second array diff_new.

[0195] Step 1008, calculating the maximum value of each energy difference in the second array diff_new compared with 0, and obtaining a third array er.

[0196] Step 1009: Divide each element in the third array er by the maximum value of the frequency domain signal energy in step 1005 to obtain a fourth array.

[0197] Step 1010: compare the maximum value element in the fourth array with 1 to obtain the minimum value, and assign the minimum value to the sparse flag sparseSigDet.

[0198] Step 1011, whether the sparse flag is 0, if so, execute step 1012, otherwise execute step 1013.

[0199] When the sparse flag sparseSigDet=0, the signal is a single-frequency signal, and the impedance curve is stopped from being updated.

[0200] Step 1012, stop updating the impedance curve.

[0201] Step 1013, determine whether the sparse flag is greater than the sparse threshold.

[0202] If the sparse flag sparseSigDet is not 0 and the sparse flag sparseSigDet is less than the sparse threshold, the current frame is a sparse signal frame, otherwise it is a non-sparse signal frame.

[0203] Specifically, those skilled in the art may set the sparse threshold to a value close to 1 as needed. The sparse threshold represents the richness of the frequency components of the signal, and the sparse flag bit of white noise is 1.

[0204] The value of the sparse flag sparseSigDet is between 0 and 1. When the value of the sparse flag sparseSigDet is 0, it indicates that the current frame is a single-frequency signal. When the value of the sparse flag sparseSigDet is 1, it indicates that the current frame is a full-frequency signal (that is, a white noise signal). The value of the sparse flag sparseSigDet other than 0 and 1 indicates that the current frame is a signal between a single-frequency signal and a full-frequency signal.

[0205] If not, the signal is a sparse signal, and step 1012 is executed to stop updating the impedance curve.

[0206] In some implementations, the adaptive control module 206 is further configured to:

[0207] If the difference between the current impedance value and the impedance value at the previous moment in the impedance curve of the capacitive load is less than a predetermined deviation threshold, the impedance value at the previous moment is updated to the current impedance value, otherwise the impedance value at the previous moment is maintained. The deviation threshold can be flexibly set as needed. For example, the deviation threshold can be set to an empirical value.

[0208] The adaptive control module 206 updates the impedance curve of the capacitive load in real time through an adaptive filtering algorithm. The center frequency of the anti-resonance filter can be updated in real time through the impedance of the capacitive load. This adaptive method combined with the limiting processing of the dynamic limiting module 201 can achieve adaptive dynamic overcurrent protection. At the same time, combined with the post-parametric equalization module and the band extension module, spectrum correction and high-frequency compensation can be achieved simultaneously.

[0209] The capacitive load overcurrent protection device 200 of the embodiment of the present application first performs limiting processing on the entire frequency band signal of the first digital signal of the source signal through the limiting module, uses the anti-resonance filter module to perform resonance peak suppression to eliminate the peak voltage generated by the capacitive load and its front-stage element at the resonance frequency, and outputs the fourth digital signal after filtering using the low-pass filter module. The fourth digital signal can be output as an amplified signal of the sound signal after being processed by the power amplifier and the capacitive load. Therefore, the embodiment of the present application can realize dynamic overcurrent protection of the capacitive load through the software algorithm, reduce the hardware cost, reduce the PCB occupied area, and will not dissipate power, thereby improving the efficiency of the system and improving the quality of the system output signal.

[0210] like Fig.11 As shown, the input test signal is a white noise signal with an amplitude ranging from -102dB to 30dB. The signal is not processed by the capacitive load overcurrent protection device of the embodiment of the present application, but directly passes through the audio amplifier and the LC low-pass filter and is output from the capacitive load. Fig.11 As shown in the upper middle sub-figure, taking a circuit LC parameter as an example, the resonant frequency is 16KHz, and after 16KHz, due to the low-pass effect of the LC low-pass filter, the signal shows a high-frequency gradual attenuation. If the signal is processed by the capacitive load overcurrent protection device of the embodiment of the present application, such as Fig.11 As shown in the lower middle sub-figure, we can see that signals above 0dB are compressed to 0dB, while signals below 0dB are not compressed (the threshold here is 0dB). At the same time, we can see that the resonance peak is also eliminated, and the 20Hz-20KHz spectrum can be guaranteed to be basically free of distortion.

[0211] Fig.12The structure of the intelligent power amplifier device 400 provided in the embodiment of the present application and its external schematic diagram are shown, and the intelligent power amplifier device 400 includes a class D power amplifier 300 and the capacitive load overcurrent protection device 200 mentioned above. The fourth digital signal output by the capacitive load overcurrent protection device 200 enters the class D power amplifier 300 for power amplification and is provided to the capacitive load 600.

[0212] See also Fig.12 As shown, taking the audio system as an example, the front-stage element of the capacitive load 600 is the LC low-pass filter 500 (LCLPF), the first digital signal of a sound source enters the capacitive load overcurrent protection device 200, and is processed by the capacitive load overcurrent protection device 200 to output a fourth digital signal, the fourth digital signal is amplified by the class D power amplifier 300 and enters the LC low-pass filter 500, and is processed by the LC low-pass filter 300 and enters the capacitive load 600, and is processed by the capacitive load 600 and output as the corresponding sound source amplified signal.

[0213] It should be noted that Fig.12 This is only an example. In different application scenarios, the front-stage components of the capacitive load 400 are different. This is not limited in the embodiment of the present application.

[0214] See also Fig.13 As shown, the embodiment of the present application also provides a capacitive load overcurrent protection method, the method comprising:

[0215] Step 1301, performing a limiting process on a first digital signal corresponding to a source signal to obtain a second digital signal, so that a current applied by the first digital signal to a class D power amplifier does not exceed a current peak value that can be supported by the class D power amplifier;

[0216] Step 1302, suppressing some frequency components in the second digital signal according to a predetermined center frequency to obtain a third digital signal, wherein the center frequency is determined according to the frequency of a resonance peak, and the resonance peak is a resonance peak generated by the mutual influence between the capacitive load and its preceding element;

[0217] Step 1303: Filter the third digital signal to obtain a fourth digital signal, wherein the fourth digital signal is provided to the capacitive load after being processed by a class D power amplifier.

[0218] It should be noted that the embodiments of the present application are not only applicable to capacitive loads, but also to other loads except capacitive loads. When applied to other loads, if no resonance peak is generated, step 1302 can be set not to be executed, and if a resonance peak may still be generated, step 1302 can be executed.

[0219] In some implementations, the capacitive load overcurrent protection method may further include: step 1304, performing spectrum compensation on the fourth digital signal, and the spectrum compensated fourth digital signal is processed by the class D power amplifier and provided to the capacitive load.

[0220] In some implementations, the capacitive load overcurrent protection method may further include: step 1305, performing spectrum expansion on the fourth digital signal after spectrum compensation, and the fourth digital signal after spectrum expansion is processed by the class D power amplifier and provided to the capacitive load.

[0221] In some implementations, the steps in the capacitive load overcurrent protection method are implemented using a software algorithm.

[0222] In some implementations, step 1305 includes: receiving the fourth digital signal after spectrum compensation, performing harmonic expansion on the fourth digital signal after spectrum compensation and outputting a harmonic signal; performing delay processing on the fourth digital signal after spectrum compensation to obtain a delayed fourth digital signal; adding the delayed fourth digital signal to the harmonic signal to obtain a fourth digital signal after spectrum expansion, wherein the delayed fourth digital signal is in phase with the harmonic signal; performing a first band-pass filtering on the fourth digital signal after spectrum compensation to generate a harmonic component, and the harmonic component is scaled after a second band-pass filtering to obtain the harmonic signal; the bandwidth of the first band-pass filtering is f res / 2 to f res , f res is the frequency of the resonance peak generated by the interaction of the capacitive load and the preceding element. The bandwidth of the second bandpass filter is f res To 2f res When f res >f s2 / 4, perform spectrum expansion on the fourth digital signal after up-sampling.

[0223] In some implementations, the step 1301 includes:

[0224] Obtaining a current signal according to the first digital signal, the capacitive load and the impedance parameter of the front-stage element, wherein the current signal is used to indicate a real-time current applied to the class-D power amplifier;

[0225] If the current signal is greater than a predetermined current threshold, the first digital signal is limited to obtain the second digital signal; otherwise, the first digital signal is used as the second digital signal;

[0226] The current threshold is determined according to a current peak value that can be supported by the class D power amplifier.

[0227] In some implementations, the step 1301 includes:

[0228] According to the feedback signal of the capacitive load, a current signal of the feedback signal of the capacitive load is obtained, wherein the current signal is used to indicate a real-time current applied to the class-D power amplifier, and the feedback signal of the capacitive load is a voltage and current sensing signal of the capacitive load;

[0229] If the current signal is greater than a predetermined current threshold, the first digital signal is limited to obtain the second digital signal; otherwise, the first digital signal is used as the second digital signal;

[0230] The current threshold is determined according to the current peak value that the class D power amplifier can support.

[0231] In some implementation modes, the limiting module performs limiting processing on the first digital signal to obtain the second digital signal, including:

[0232] Performing delay processing on the first digital signal to obtain a delayed signal of the first digital signal;

[0233] Limiting the current of the first digital signal to the current threshold;

[0234] Calculating a gain factor of the first digital signal according to the current threshold and the current signal;

[0235] Smoothing the gain factor to obtain a smoothed gain factor;

[0236] The smoothed gain factor is applied to the delayed signal of the first digital signal to obtain the second digital signal.

[0237] In some embodiments, the calculating the gain factor of the first digital signal based on the current threshold and the current signal includes: calculating the gain factor of the first digital signal based on the current threshold and the first digital signal, specifically: calculating the gain factor of the first digital signal according to the formula g=Ioc / Xrms, wherein g represents the gain factor, Ioc represents the current threshold, and Xrms represents the current sequence x(n) of the current signal.

[0238] In some implementations, the step 1301 further includes:

[0239] Obtaining a mean square root value of the current signal;

[0240] If the current signal is greater than a predetermined current threshold, the first digital signal is limited to obtain the second digital signal; otherwise, the first digital signal is used as the second digital signal, specifically:

[0241] If the mean square value of the current signal is greater than the predetermined current threshold, the first digital signal is limited to obtain the second digital signal; otherwise, the first digital signal is used as the second digital signal.

[0242] In some embodiments, the method further comprises:

[0243] Determining an impedance curve of the capacitive load according to a feedback signal of the capacitive load, determining a frequency of the resonance peak based on the impedance curve of the capacitive load, and adjusting a center frequency of the anti-resonance filter module to the frequency of the resonance peak;

[0244] The impedance curve of the capacitive load is used to indicate the impedance of the capacitive load at different frequencies.

[0245] In some implementations, the step of determining the impedance curve of the capacitive load according to the feedback signal of the capacitive load, determining the frequency of the resonance peak based on the impedance curve of the capacitive load, and adjusting the center frequency of the anti-resonance filter module to the frequency of the resonance peak comprises:

[0246] Extracting the real-time output current and the real-time output voltage of the capacitive load from the feedback signal of the capacitive load;

[0247] Processing the real-time output current of the capacitive load using a capacitive load model of an adaptive filter to obtain a real-time estimated voltage of the capacitive load;

[0248] Continuously updating the parameters of the impedance curve using a predetermined adaptive filtering algorithm to minimize the error between the real-time output voltage of the capacitive load and the real-time estimated voltage, and adjusting the parameters of the impedance curve to the parameters of the impedance curve corresponding to the minimum value of the error;

[0249] The impedance curve is combined with the front-stage element to obtain the frequency of the resonance peak, and the center frequency of the anti-resonance filter module is adjusted to the frequency of the resonance peak.

[0250] In some embodiments, the method further comprises:

[0251] Determining whether the current frame is a mute frame or a non-mute frame according to the signal time domain energy of the current frame in the feedback signal of the capacitive load;

[0252] An impedance curve of the capacitive load is determined according to a non-silent frame in a feedback signal of the capacitive load.

[0253] In some implementations, the determining whether the current frame is a silent frame or a non-silent frame according to the signal time domain energy of the current frame in the feedback signal of the capacitive load includes:

[0254] Comparing the signal time domain energy of the current frame with a preset silence threshold;

[0255] If the signal time domain energy of the current frame is less than the silence threshold, the current frame is determined to be a silence frame; otherwise, the current frame is determined to be a non-silence frame.

[0256] In some implementations, the determining whether the current frame is a silent frame or a non-silent frame according to the signal time domain energy of the current frame in the feedback signal of the capacitive load further includes: determining a silent segment or a non-silent segment in the feedback signal of the capacitive load according to the number of the silent frames or the non-silent frames;

[0257] An impedance curve of the capacitive load is determined according to the non-silent segment in the feedback signal of the capacitive load.

[0258] In some embodiments, the method further comprises:

[0259] For the non-silent frame, determining whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the signal frequency domain energy of the current frame in the feedback signal of the capacitive load;

[0260] An impedance curve of the capacitive load is determined according to the non-single-frequency signal frame in the feedback signal of the capacitive load.

[0261] In some implementations, the determining, for the non-silent frame, whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the signal frequency domain energy of the current frame in the feedback signal of the capacitive load, comprises:

[0262] Performing a windowed Fourier transform on the feedback signal of the capacitive load to obtain the maximum value of the frequency domain signal energy from the initial frequency point to the intermediate frequency point;

[0263] The frequency domain signal energy difference between adjacent frequency points is calculated, and according to the energy difference and the maximum value of the frequency domain signal energy, it is determined whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame.

[0264] In some implementations, the determining, for the non-silent frame, whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the signal frequency domain energy of the current frame in the feedback signal of the capacitive load, further includes:

[0265] If the current frame is a non-single-frequency signal frame, determining a sparse signal frame in the feedback signal of the capacitive load according to the energy difference and the maximum energy value of the frequency domain signal;

[0266] An impedance curve of the capacitive load is determined according to the non-sparse signal in the feedback signal of the capacitive load.

[0267] In some implementations, the calculating the frequency domain signal energy difference between adjacent frequency points, and determining whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the energy difference and the maximum frequency domain signal energy, includes:

[0268] The energy difference array is obtained by subtracting the energy of the previous frequency point from the energy of the next frequency point of the signal frequency domain energy obtained for each frame, and the energy difference array is used as the first array;

[0269] Keep the elements from the beginning to the index of the maximum energy value of the frequency domain signal in the first array unchanged, and take the inverse of the index from the maximum energy value of the frequency domain signal to the last element to obtain a second array;

[0270] Calculate the maximum value of each energy difference value in the second array compared with 0 to obtain a third array;

[0271] Dividing each element in the third array by the maximum frequency domain signal energy value to obtain a fourth array;

[0272] Compare the maximum value element in the fourth array with 1 to obtain a minimum value, and assign the minimum value to the sparse flag bit;

[0273] If the sparse flag is 0, the current frame is a single-frequency signal frame; otherwise, the current frame is a non-single-frequency signal frame.

[0274] In some implementation modes, the determining the sparse signal frame in the feedback signal of the capacitive load according to the energy difference and the maximum energy value of the frequency domain signal comprises:

[0275] If the sparse flag is less than or equal to the sparse threshold, the current frame is a sparse signal frame.

[0276] In some implementations, if the difference between the current impedance and the impedance at the previous moment in the impedance curve of the capacitive load is less than a predetermined deviation threshold, the impedance at the previous moment is updated to the current impedance, otherwise the impedance at the previous moment is maintained.

[0277] In some implementations, the capacitive load is a piezoelectric speaker, and the piezoelectric speaker outputs an amplified signal of the source signal.

[0278] In the embodiment of the present application, other technical details of the capacitive load overcurrent protection method can be found in the description of the device part above and will not be repeated here.

[0279] Based on the method described in the above embodiment, the embodiment of the present application also provides an electronic device for executing the method described in the above embodiment, referring to Fig.14 , shows a schematic diagram of the structure of an electronic device according to an embodiment of the present application. The specific embodiment of the present application does not limit the specific implementation of the electronic device.

[0280] like Fig.14 As shown, the electronic device 140 may include: a processor (processor) 1402 , a communication interface (Communications Interface) 1404 , a memory (memory) 1406 , and a communication bus 14014 .

[0281] in:

[0282] The processor 1402 , the communication interface 1404 , and the memory 1406 communicate with each other via the communication bus 14014 .

[0283] The communication interface 1404 is used to communicate with other electronic devices or servers.

[0284] The processor 1402 is used to execute the program 1410, and specifically can execute the relevant steps of the above-mentioned capacitive load overcurrent protection method.

[0285] Specifically, the program 1410 may include program codes, which include computer operation instructions.

[0286] The processor 1402 may be a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0287] The memory 1406 is used to store the program 1410. The memory 1406 includes an SRAM memory.

[0288] Program 1410 can be specifically used to enable processor 1402 to execute to implement the steps described in the above-mentioned capacitive load protection method.

[0289] The specific implementation of each step in program 1410 can refer to the corresponding description of the corresponding steps in the above-mentioned capacitive load protection method, which will not be repeated here.

[0290] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding process descriptions in the aforementioned method embodiments and will not be repeated here.

[0291] Based on the capacitive load protection method described in the above embodiment, an embodiment of the present application provides a computer storage medium on which a computer program is stored. When the program is executed by a processor, the capacitive load protection method as described above is implemented.

[0292] Based on the method described in the above embodiment, an embodiment of the present application provides a computer program product, which implements the capacitive load protection method as described above when executed by a processor.

[0293] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0294] The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the navigation method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the navigation method shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the navigation method shown herein.

[0295] Those of ordinary skill in the art will appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0296] The embodiments of the present application are described but not limited thereto. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A capacitive load overcurrent protection device, the device comprising: A limiting module, used for performing limiting processing on a first digital signal corresponding to a source signal to obtain a second digital signal, so that a current applied to a class D power amplifier does not exceed a current peak value that can be supported by the class D power amplifier; an anti-resonance filtering module, configured to suppress some frequency components in the second digital signal according to a predetermined center frequency to obtain a third digital signal, wherein the center frequency is determined according to the frequency of a resonance peak, and the resonance peak is a resonance peak generated by the interaction of the capacitive load and its preceding element; A low-pass filtering module is used to filter the third digital signal to obtain a fourth digital signal, and the fourth digital signal is used to be provided to the capacitive load after being processed by the class D power amplifier.

2. The device according to claim 1, wherein: The capacitive load overcurrent protection device is implemented by a software algorithm, the capacitive load is a piezoelectric speaker, and the piezoelectric speaker outputs an amplified signal of the source signal.

3. The device according to claim 1 or 2, wherein: Also includes: The post-parametric equalization module is used to perform spectrum compensation on the fourth digital signal. The spectrum-compensated fourth digital signal is processed by the class D power amplifier and then provided to the capacitive load.

4. The device according to claim 3, wherein: Also includes: The spectrum expansion module is used to perform spectrum expansion on the fourth digital signal processed by the post-parametric equalization module. The fourth digital signal after spectrum expansion is processed by the class D power amplifier and then provided to the capacitive load.

5. The device according to claim 4, wherein: The spectrum expansion module comprises: a harmonic unit, a delay unit and a synthesis unit, the input signals of the harmonic unit and the delay unit are both the fourth digital signal processed by the post-parametric equalization module, the harmonic unit is used to perform harmonic expansion on the fourth digital signal processed by the post-parametric equalization module and output the harmonic signal, the output signal of the delay unit is the delayed fourth digital signal, and the synthesis unit is used to add the delayed fourth digital signal to the harmonic signal to obtain a spectrum expanded fourth digital signal, wherein the delayed fourth digital signal is in phase with the harmonic signal; The harmonic unit includes: a first bandpass filter, a nonlinear device, a second bandpass filter and a scaling unit; the fourth digital signal processed by the post-parametric equalization module is input into the first bandpass filter for bandpass filtering, the signal filtered by the first bandpass filter is input into the nonlinear device, the nonlinear device generates harmonic components, the harmonic components are bandpass filtered by the second bandpass filter, and then scaled by the scaling unit to obtain the harmonic signal; The bandwidth of the first bandpass filter is f res / 2 to f res , where f res is the frequency of the resonance peak generated by the interaction of the capacitive load and the front-stage element. The bandwidth of the second bandpass filter is f res To 2f res When f res >f s2 / 4, performing up-sampling processing on the fourth digital signal processed by the post-parametric equalization module and then performing spectrum expansion.

6. The device according to claim 1, wherein: The limiting module is specifically used for: Obtaining a current signal according to the first digital signal, the capacitive load and the impedance parameter of the front-stage element, wherein the current signal is used to indicate a real-time current applied to the class-D power amplifier, and the front-stage element includes an LC low-pass filter; When the current signal is greater than a predetermined current threshold, the first digital signal is subjected to amplitude limiting processing to obtain the second digital signal; otherwise, taking the first digital signal as the second digital signal; The current threshold is determined according to a current peak value that can be supported by the class D power amplifier.

7. The device according to claim 1, wherein: The limiting module is specifically used for: Obtaining a current signal of the feedback signal of the capacitive load according to the feedback signal of the capacitive load, wherein the feedback signal of the capacitive load is a voltage signal or a current signal of the capacitive load measured by a sensor; When the current signal is greater than a predetermined current threshold, the first digital signal is limited to obtain the second digital signal; otherwise, the first digital signal is used as the second digital signal; The current threshold is determined according to a current peak value that can be supported by the class D power amplifier.

8. The device according to claim 6 or 7, wherein: The limiting module performs limiting processing on the first digital signal to obtain the second digital signal, including: performing delay processing on the first digital signal to obtain a delayed signal of the first digital signal, limiting the current of the first digital signal to the current threshold, calculating a gain factor of the first digital signal according to the current threshold and the current signal, The gain factor is smoothed to obtain a smoothed gain factor, Applying the smoothed gain factor to the delayed signal of the first digital signal to obtain the second digital signal; The step of calculating the gain factor of the first digital signal based on the current threshold and the first digital signal is specifically as follows: calculating the gain factor of the first digital signal according to the formula g=Ioc / Xrms, wherein g represents the gain factor, Ioc represents the current threshold, and Xrms represents the effective value of the current sequence x(n) of the current signal.

9. The device according to claim 6 or 7, wherein: The limiting module is also used for: Obtaining a mean square root value of the current signal; When the current signal is greater than a predetermined current threshold, the first digital signal is limited to obtain the second digital signal; otherwise, the first digital signal is used as the second digital signal, specifically: When the mean square value of the current signal is greater than the predetermined current threshold, the first digital signal is limited to obtain the second digital signal; otherwise, the first digital signal is used as the second digital signal.

10. The device according to claim 1, wherein: Also includes: An adaptive control module, configured to determine an impedance curve of the capacitive load according to a feedback signal of the capacitive load, determine a frequency of the resonance peak based on the impedance curve of the capacitive load, and adjust a center frequency of the anti-resonance filter module to the frequency of the resonance peak; The impedance curve of the capacitive load is used to indicate the impedance of the capacitive load at different frequencies.

11. The device according to claim 10, wherein: The adaptive control module comprises: An extraction unit, used for extracting a real-time output current and a real-time output voltage of the capacitive load from a feedback signal of the capacitive load; an estimating unit, configured to process the real-time output current of the capacitive load using a capacitive load model of an adaptive filter to obtain a real-time estimated voltage of the capacitive load; An adjustment unit, configured to continuously update the parameters of the impedance curve using a predetermined adaptive filtering algorithm to minimize the error between the real-time output voltage of the capacitive load and the real-time estimated voltage, and adjust the parameters of the impedance curve to the parameters of the impedance curve corresponding to the minimum value of the error; The setting unit is used to combine the impedance curve with the front-stage element to obtain the frequency of the resonance peak, and adjust the center frequency of the anti-resonance filter module to the frequency of the resonance peak.

12. The device according to claim 10, wherein: Also includes: A first detection module, configured to determine whether the current frame is a mute frame or a non-mute frame according to the signal time domain energy of the current frame in the feedback signal of the capacitive load; The adaptive control module is further used to determine the impedance curve of the capacitive load according to the non-silent frame in the feedback signal of the capacitive load; The determining, according to the signal time domain energy of the current frame in the feedback signal of the capacitive load, whether the current frame is a mute frame or a non-mute frame specifically includes: Comparing the signal time domain energy of the current frame with a preset silence threshold; When the signal time domain energy of the current frame is less than the silence threshold, the current frame is determined to be a silence frame; otherwise, the current frame is determined to be a non-silence frame.

13. The device according to claim 12, wherein: The first detection module is further used to determine the silent segment or the non-silent segment in the feedback signal of the capacitive load according to the number of the silent frames or the non-silent frames; The adaptive control module is further used to determine the impedance curve of the capacitive load according to the non-silent segment in the feedback signal of the capacitive load.

14. The device according to claim 13, wherein: Also includes: A second detection module is used to determine whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the signal frequency domain energy of the current frame in the feedback signal of the capacitive load for the non-silent frame and the non-silent segment; The adaptive control module is further used to determine the impedance curve of the capacitive load according to the non-single-frequency signal frame in the feedback signal of the capacitive load; The determining, for the non-silent frame, whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the signal frequency domain energy of the current frame in the feedback signal of the capacitive load specifically includes: Performing a windowed Fourier transform on the non-silent frame according to the feedback signal of the capacitive load to obtain the maximum value of the frequency domain signal energy from the initial frequency point to the intermediate frequency point; The frequency domain signal energy difference between adjacent frequency points is calculated, and according to the energy difference and the maximum value of the frequency domain signal energy, it is determined whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame.

15. The device according to claim 14, wherein: The second detection module is further used for: When the current frame is a non-single-frequency signal frame, determining a sparse signal frame in the feedback signal of the capacitive load according to the energy difference and the maximum value of the frequency domain signal energy; The adaptive control module is further used to determine the impedance curve of the capacitive load according to the non-sparse signal frame in the feedback signal of the capacitive load; When the difference between the current impedance and the impedance at the previous moment in the impedance curve of the capacitive load is less than a predetermined deviation threshold, the impedance at the previous moment is updated to the current impedance; otherwise, the impedance at the previous moment is maintained.

16. The device according to claim 15, wherein: The calculating the frequency domain signal energy difference between adjacent frequency points, and determining whether the current frame is a single-frequency signal frame or a non-single-frequency signal frame according to the energy difference and the maximum frequency domain signal energy, includes: The energy difference array is obtained by subtracting the energy of the previous frequency point from the energy of the next frequency point in the frequency domain of the signal obtained for each frame, and is used as the first array. The elements from the beginning to the index of the maximum energy value of the frequency domain signal in the first array remain unchanged, and the inverse of the index of the maximum energy value of the frequency domain signal to the last element is taken to obtain a second array, Calculate the maximum value of each energy difference in the second array compared with 0 to obtain a third array, Divide each element in the third array by the maximum frequency domain signal energy to obtain a fourth array, Compare the maximum value element in the fourth array with 1 to obtain the minimum value, and assign the minimum value to the sparse flag bit, When the sparse flag is 0, the current frame is a single-frequency signal frame, otherwise, the current frame is a non-single-frequency signal frame; The step of determining the sparse signal frame in the feedback signal of the capacitive load according to the energy difference and the maximum energy value of the frequency domain signal comprises: When the sparse flag is less than or equal to the sparse threshold, the current frame is a sparse signal frame.

17. An intelligent power amplifier device, comprising: A class D power amplifier and a capacitive load overcurrent protection device as described in any one of claims 1 to 16, wherein the fourth digital signal output by the capacitive load overcurrent protection device enters the class D power amplifier for power amplification and is then provided to the capacitive load.

18. A load overcurrent protection device, comprising: A limiting module, used for performing limiting processing on a first digital signal corresponding to a source signal to obtain a second digital signal, so that a current applied to a class D power amplifier does not exceed a current peak value that can be supported by the class D power amplifier; an anti-resonance filtering module, configured to suppress some frequency components in the second digital signal according to a predetermined center frequency to obtain a third digital signal, wherein the center frequency is determined according to the frequency of a resonance peak, and the resonance peak is a resonance peak generated by the interaction of the load and its preceding element; A low-pass filter module is used to filter the third digital signal to obtain a fourth digital signal, and the fourth digital signal is used to be provided to the load after being processed by the class D power amplifier. When the load is a capacitive load, the anti-resonance filter module is in a working state, and when the load is a non-capacitive load, the anti-resonance filter module is in a closed state.

19. A load overcurrent protection method, the method comprising: Performing amplitude limiting processing on a first digital signal corresponding to a source signal to obtain a second digital signal, so that a current applied by the second digital signal to a class-D power amplifier does not exceed a current peak value that can be supported by the class-D power amplifier; Suppressing some frequency components in the second digital signal according to a predetermined center frequency to obtain a third digital signal, wherein the center frequency is determined according to the frequency of a resonance peak, and the resonance peak is a resonance peak generated by the interaction of the capacitive load and its preceding element; The third digital signal is filtered to obtain a fourth digital signal, and the fourth digital signal is provided to the capacitive load after being processed by the class D power amplifier, so that the capacitive load can output an amplified signal of the source signal.

20. A storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the operation corresponding to the capacitive load overcurrent protection device according to any one of claims 1 to 16 is implemented.

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