Phase selection method and circuit for reducing errors in phase interpolator

Abstract

The invention aims to provide a phase selection method and circuit for reducing errors in a phase interpolator. The method comprises the following steps: selecting an upper limit of the phase interpolator according to a phase interpolation demand; selecting a lower limit of a phase interpolator according to a phase interpolation requirement; inputting the upper limit and the lower limit into an interpolation selection circuit, and outputting a phase interpolation by the interpolation selection circuit; when the phase interpolation requirement is changed, the upper limit or the lower limit of the interpolation selection circuit is kept unchanged, and only one of the upper limit and the lower limit is changed for phase interpolation. According to the invention, a half of logic branches are reduced and transferred to a digital control signal which does not influence the performance, and each PLL output phase only corresponds to one load, so that complete symmetry of the layout can be realized, random errors and power consumption caused by a first-stage MUX can be reduced, and better linearity is achieved when the phase demand jumps.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a phase selection method and circuit for reducing errors in a phase interpolator. Background Art

[0002] ‌Phase Interpolator (PI) is a device used to adjust the phase of the sampling clock, mainly used in clock data recovery (CDR) circuits to achieve a stable state that dynamically follows the data. ‌ The working principle of the phase interpolator is as follows: ‌Signal processing‌: The phase interpolator receives multiple signals with different phases, usually including a first signal and a second signal. These signals are processed by multiple phase splitting elements, each of which receives a corresponding signal and a control signal. ‌Phase adjustment‌: Through the control signal, the phase interpolator is able to select and process a specific signal to generate an output signal with a desired phase. This process involves fine adjustment of the sampling clock phase to ensure optimal synchronization between the clock signal and the data signal. ‌Dynamic adjustment‌: The phase interpolator ensures that the clock can dynamically follow the changes in the data during the data sampling process by continuously adjusting the clock phase, thereby reducing sampling errors and improving the accuracy of data recovery. ‌Phase interpolator plays a key role in CDR (Clock and Data Recovery) systems, especially in high-speed communications and data processing. For example, in an optical module, CDR recovers the clock information from the received optical signal to ensure that the signal at the receiving end is consistent with that at the transmitting end, thereby ensuring accurate data transmission‌.

[0003] In the high-speed clock transmission of the prior art, it is necessary to insert a high-precision phase differencer in the CDR to determine the sampling phase. Digital phase converters have gradually become the mainstream. In the traditional architecture, after the PLL generates 8 phases, the high MSB of the control signal will select two adjacent phases in the 8 phases. Then the low-order control LSB is converted into a hot code to perform the difference between the two phases. In this way, a full range of differential signals of 0-360° is obtained. In high-speed design, the 8 phases generated by the PLL are transmitted as 4 sets of differential signals. Since each signal (Φj) is connected to [Φj-1, Φj] and [Φj,Φj+1] twice during the connection process, the layout in the layout will use mesh routing to achieve approximation to reduce the relative error of each phase load. However, with the continuous increase in clock frequency, the routing of the MUX used to select the phase and the previous and next MUX has become non-negligible for the error formed by a single phase. Summary of the invention

[0004] The purpose of the present invention is to provide a phase selection method and circuit for reducing errors in a phase interpolator. The method reduces half of the logic branches and transfers them to digital control signals that do not affect performance. Each output phase of the PLL corresponds to only one load, which can achieve complete symmetry of the layout. It can also reduce the random errors and power consumption caused by the first-level MUX, and have better linearity when the phase requirement jumps.

[0005] A phase selection method for reducing error in a phase interpolator, comprising: Select the upper limit of the phase interpolator according to the phase interpolation requirements; Select the lower limit of the phase interpolator according to the phase interpolation requirements; The upper limit and the lower limit are input into an interpolation selection circuit, and the interpolation selection circuit outputs a phase interpolation; When the phase interpolation requirement changes, the upper limit or lower limit of the interpolation selection circuit is kept unchanged, and only one of the upper limit and the lower limit is changed to perform phase interpolation.

[0006] Preferably, the selecting the upper limit of the phase interpolator according to the phase interpolation requirement includes: The upper limit of the phase interpolator is selected by changing the switch of the selector in the upper limit selection circuit.

[0007] Preferably, the selecting a lower limit of the phase interpolator according to the phase interpolation requirement includes: The lower limit of the phase interpolator is selected by changing the switch of the selector in the lower limit selection circuit.

[0008] Preferably, when the phase interpolation requirement changes, keeping the upper limit or lower limit of the interpolation selection circuit unchanged and only changing one of the upper limit and the lower limit to perform phase interpolation includes: When the demand for phase interpolation becomes larger, the upper and lower limits of the interpolation selection circuit are kept unchanged, and only the smaller value of the upper and lower limits is changed to perform phase interpolation; When the phase interpolation requirement becomes smaller, the upper and lower limits of the interpolation selection circuit are kept unchanged, and only the larger value of the upper and lower limits is changed to perform phase interpolation.

[0009] A phase selection circuit for reducing errors in a phase interpolator, comprising: an upper limit selection circuit, a lower limit selection circuit and an interpolation selection circuit; The upper limit selection circuit is connected to the interpolation selection circuit and is used to select an upper limit of phase interpolation; The lower limit selection circuit is connected to the interpolation selection circuit and is used to select the lower limit of phase interpolation; The interpolation selection circuit selects a specific value from the upper limit and the lower limit of the phase interpolation according to the phase interpolation requirement to complete the phase interpolation.

[0010] Preferably, the upper limit selection circuit comprises: a first selector, a second selector, a third selector, a first NAND gate, a first XOR gate and a first XNOR gate; The positive input terminal of the first selector is connected to the 0° clock signal, the negative input terminal is connected to the 90° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The positive input terminal of the second selector is connected to the 180° clock signal, the negative input terminal is connected to the 270° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The first input terminal of the first XOR gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output signal controls the first selector and the second selector; The first input terminal of the first NAND gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output terminal is connected to the first input terminal of the first XNOR gate; The second input terminal of the first XNOR gate is connected to the S5 control signal, and the output signal controls the third selector.

[0011] Preferably, the lower limit selection circuit comprises: a fourth selector, a fifth selector and a sixth selector; The positive input terminal of the fourth selector is connected to the 45° clock signal, the negative input terminal is connected to the 135° clock signal, and the output terminal is connected to the positive input terminal of the sixth selector; The positive input terminal of the fifth selector is connected to the 225° clock signal, the negative input terminal is connected to the 315° clock signal, and the output terminal is connected to the negative input terminal of the sixth selector; S5 control signal controls the sixth selector; The S4 control signal controls the fourth selector and the fifth selector.

[0012] Preferably, the interpolation selection circuit comprises: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector and a first NOT gate; The output signal of the third selector is connected to the first input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The output signal of the sixth selector is connected to the second input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The input end of the first NOT gate is connected to the S2:0 control signal, and the output end is connected to the positive input end of the seventh selector; S2:0 control signal is connected to the negative input terminal of the seventh selector, and S3 control signal controls the seventh selector; An output signal of the seventh selector is connected to the first amplifier.

[0013] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program code, the computer program code comprises computer instructions, and when the chip executes the computer instructions, the electronic device executes a phase selection method for reducing errors in a phase interpolator.

[0014] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor executes a phase selection method for reducing errors in a phase interpolator.

[0015] The beneficial effects of the present invention are: 1. The present invention reduces half of the logic branches and transfers them to digital control signals that do not affect performance; 2. In the present invention, each output phase of the PLL corresponds to only one load, which can achieve complete symmetry of the layout and greatly reduce the difficulty of layout wiring; 3. The present invention has better linearity when the MSB jumps; 4. The present invention can reduce the random errors and power consumption caused by the first-stage selector. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A flow chart of a phase selection method for reducing errors in a phase interpolator according to the present invention; Figure 2 It is the prior art phase selection circuit diagram of the present invention; Figure 3 A phase selection circuit diagram for reducing errors in a phase interpolator according to the present invention; Figure 4 This is a schematic diagram of the prior art 175° phase selection of the present invention; Figure 5 This is a schematic diagram of the prior art 185° phase selection of the present invention; Figure 6 This is a schematic diagram of 175° phase selection of the present invention; Figure 7 It is a schematic diagram of 185° phase selection of the present invention; Figure 8 Schematic diagram of the linearity of the phase interpolator of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] In the high-speed clock transmission of the prior art, it is necessary to insert a high-precision phase differencer in the CDR to determine the sampling phase. Digital phase converters have gradually become the mainstream. In the traditional architecture, after the PLL generates 8 phases, the high MSB of the control signal will select two adjacent phases in the 8 phases. Then the low-order control LSB is converted into a hot code to perform the difference between the two phases. In this way, a full range of differential signals of 0-360° is obtained. In high-speed design, the 8 phases generated by the PLL are transmitted as 4 sets of differential signals. Since each signal (Φj) is connected to [Φj-1, Φj] and [Φj,Φj+1] twice during the connection process, the layout in the layout will use mesh routing to achieve approximation to reduce the relative error of each phase load. However, with the continuous increase in clock frequency, the routing of the MUX used to select the phase and the previous and next MUX has become non-negligible for the error formed by a single phase.

[0023] The present invention reduces half of the logic branches and transfers them to digital control signals that do not affect performance; each output phase of the PLL in the present invention corresponds to only one load, which can achieve complete symmetry of the layout and greatly reduce the difficulty of layout wiring; the present invention has better linearity when the MSB jumps; the present invention can reduce the random error and power consumption caused by the first-level selector.

[0024] Example 1 A phase selection method for reducing errors in phase interpolators, referring to Figure 1 ,include: S100, selecting an upper limit of a phase interpolator according to a phase interpolation requirement; S200, selecting a lower limit of a phase interpolator according to a phase interpolation requirement; S300, inputting the upper limit and the lower limit into an interpolation selection circuit, and the interpolation selection circuit outputs a phase interpolation; S400, when the phase interpolation requirement changes, the upper limit or the lower limit of the interpolation selection circuit is kept unchanged, and only one of the upper limit and the lower limit is changed to perform phase interpolation.

[0025] The phase interpolator generates an output phase between two or more input clock signals by mixing the phases thereof. The difference between the upper limit and the lower limit is determined by the position of the control signal. The present invention takes the 6-bit control signal S[5:0] as an example. The difference between the upper limit and the lower limit is 45°. Each control signal controls an upper limit and a lower limit with a difference of 45°. The scope of protection of the present invention includes but is not limited to upper and lower limit selection schemes controlled by other bit control signals. The resolution of the phase interpolator can be adjusted according to the actual application scenario.

[0026] Preferably, the upper limit of the phase interpolator is selected according to the phase interpolation requirement, including: The upper limit of the phase interpolator is selected by changing the switch of the selector in the upper limit selection circuit.

[0027] Dynamically adjusting the upper limit of the phase interpolator by changing the selector switch in the upper limit selection circuit can achieve flexible and efficient circuit design. The resolution, power consumption and performance of the phase interpolator can be dynamically adjusted according to actual needs. It is suitable for multi-mode or multi-scenario applications. The upper limit of the phase interpolator is changed by the selector switch to adapt to different working modes or performance requirements. A higher upper limit (high resolution) is used in high-performance mode, and a lower upper limit (low resolution) is used in low-power mode. By reusing circuit resources, hardware overhead is reduced.

[0028] Preferably, the lower limit of the phase interpolator is selected according to the phase interpolation requirement, including: The lower limit of the phase interpolator is selected by changing the switch of the selector in the lower limit selection circuit.

[0029] Dynamically adjusting the lower limit of the phase interpolator by changing the selector switch in the lower limit selection circuit can achieve flexible and efficient circuit design. This method can dynamically adjust the starting phase or minimum phase step of the phase interpolator according to actual needs, which is suitable for multi-mode or multi-scenario applications (such as clock data recovery, high-speed SerDes systems, etc.). The resolution, power consumption and performance of the phase interpolator can be dynamically adjusted according to actual needs. It is suitable for multi-mode or multi-scenario applications. The upper limit of the phase interpolator is changed by the selector switch to adapt to different working modes or performance requirements. Use a higher upper limit (high resolution) in high-performance mode and a lower upper limit (low resolution) in low-power mode. Reduce hardware overhead by reusing circuit resources.

[0030] Preferably, when the phase interpolation requirement changes, keeping the upper limit or lower limit of the interpolation selection circuit unchanged and only changing one of the upper limit and the lower limit to perform phase interpolation includes: When the demand for phase interpolation becomes larger, the upper and lower limits of the interpolation selection circuit are kept unchanged, and only the smaller value of the upper and lower limits is changed to perform phase interpolation; When the phase interpolation requirement becomes smaller, the upper and lower limits of the interpolation selection circuit are kept unchanged, and only the larger value of the upper and lower limits is changed to perform phase interpolation.

[0031] The present invention provides a phase selection scheme: taking the 6-bit control signal S[5:0] as an example, in the input signal of the final phase difference device [Φ a , Φ b ], S[5:3] controls a / b. S[2:0] controls the core part of the interpolator.

[0032] The solution in the prior art: The technical solution of the present invention: S[5:3] = 0 – [Φ 0 , Φ 45 ] 0 – [Φ 0 , Φ 45 ] 1 – [Φ 45 , Φ 90 ] 1 – [Φ 90 , Φ 45 ] 2 – [Φ 90 , Φ 135 ] 2 – [Φ 90 , Φ 135 ] 3 – [Φ 135 , Φ 180 ] 3 – [Φ 180, Φ 135 ] 4 – [Φ 180 , Φ 225 ] 4 – [Φ 180 , Φ 225 ] 5 – [Φ 225 , Φ 270 ] 5 – [Φ 270 , Φ 225 ] 6 – [Φ 270 , Φ 315 ] 6 – [Φ 270 , Φ 315 ] 7 – [Φ 315 , Φ 0 ] 7 – [Φ 0 , Φ 315 ] It can be seen that in the prior art, when the phase interpolator needs to output a value that jumps, both the upper and lower limits are changed, but in the embodiment of the present invention, there is always an upper limit or a lower limit that is not changed.

[0033] refer to Figure 2 , Figure 4 and Figure 5 ,like Figure 2 As shown, the structures of the lower limit selection circuit and the upper limit selection circuit in the prior art are the same. When phase interpolation is to be performed, as shown in FIG. Figure 4 As shown, the lower limit selection circuit and the upper limit selection circuit select the upper limit of 135° and the lower limit of 180° through the control of each selector, and then input the values ​​of the upper and lower limits into the interpolation selection circuit. The interpolation selection circuit changes the enable signal of the amplifier so that the final output phase value is 175°. When the phase needs to jump, such as Figure 5 As shown, when the phase needs to be selected from Figure 4 The 175° transition to Figure 5 When the upper limit selection circuit is 185°, there are two nodes that need to jump. Figure 5 In the figure, 1 and 2 are used to represent the upper limit of 135°. At the same time, since the structure of the lower limit selection circuit is the same as that of the upper limit selection circuit, the nodes that need to be jumped are the same when jumping. Figure 5 In the figure, 1 and 2 are used to represent the lower limit of 225°. At this time, the upper limit and lower limit of the input interpolation selection circuit are changed. If you want to select an interpolation of 185°, you need to change the values ​​of other amplifiers, that is, the third node, to output a phase of 185°. Therefore, in the prior art, three nodes need to be changed for a phase jump. Obviously, this will cause large random errors and power consumption.

[0034] In the embodiment of the present invention, the phase jump is as follows: Figure 6 and Figure 7 ,exist Figure 6 In the example, the lower limit selection circuit and the upper limit selection circuit also select the upper limit of 180° and the lower limit of 135° through the control of each selector, and then input the upper and lower limit values ​​into the interpolation selection circuit. The interpolation selection circuit changes the enable signal of the amplifier so that the final output phase value is 175°. However, in the jump process, such as Figure 7 , the selector in the upper limit selection circuit does not change, and still outputs an upper limit of 180°. Only the selector in the lower limit selection circuit is changed, and the output lower limit is 225°. At this time, the changed node is Figure 7 It is represented by 1, and then the upper limit of 180° and the lower limit of 225° are input into the interpolation selection circuit. At this time, the amplifier in the interpolation selection circuit can directly output the interpolation of 185° without jumping. It can be seen that in the present invention, only one node needs to be changed to complete the phase jump. Compared with the prior art, it has very small power consumption and error.

[0035] Example 2 A phase selection circuit for reducing errors in a phase interpolator, referring to Figure 3 , including: an upper limit selection circuit, a lower limit selection circuit and an interpolation selection circuit; The upper limit selection circuit is connected to the interpolation selection circuit and is used to select the upper limit of the phase interpolation; The lower limit selection circuit is connected to the interpolation selection circuit and is used to select the lower limit of the phase interpolation; The interpolation selection circuit selects a specific value from the upper limit and the lower limit of the phase interpolation according to the phase interpolation requirement to complete the phase interpolation.

[0036] In an embodiment of the present invention, a phase selection circuit for reducing errors in a phase interpolator is divided into three major modules, an upper limit selection circuit, a lower limit selection circuit and an interpolation selection circuit. The upper limit selection circuit is used to select the upper limit of phase interpolation, the lower limit selection circuit is used to select the lower limit of phase interpolation, and the interpolation selection circuit is used to select a specific value from the upper and lower limits of phase interpolation to complete phase interpolation.

[0037] The circuit layout of the present invention is completely symmetrical, which greatly reduces the difficulty of layout wiring.

[0038] Preferably, the upper limit selection circuit comprises: a first selector, a second selector, a third selector, a first NAND gate, a first XOR gate and a first XNOR gate; The positive input terminal of the first selector is connected to the 0° clock signal, the negative input terminal is connected to the 90° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The positive input terminal of the second selector is connected to the 180° clock signal, the negative input terminal is connected to the 270° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The first input terminal of the first XOR gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output signal controls the first selector and the second selector; The first input terminal of the first NAND gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output terminal is connected to the first input terminal of the first XNOR gate; The second input terminal of the first XNOR gate is connected to the S5 control signal, and the output signal controls the third selector.

[0039] The upper limit selection circuit is a circuit for dynamically adjusting the upper limit of the phase interpolator. The core principle is to change the upper limit of the phase interpolator by switching different interpolation coefficient bits or phase adjustment ranges through a selector switch or a multiplexer (MUX). The phase interpolation upper limit selection circuit dynamically adjusts the upper limit to optimize the behavior of the phase interpolator according to different working modes or performance requirements. In high-performance mode, a higher upper limit can provide finer phase adjustment, thereby improving the accuracy and stability of the system. For example, in a high-speed SerDes system, a higher upper limit can reduce clock jitter and improve the reliability of data transmission. In low-power mode, a lower upper limit can reduce the computational complexity and power consumption of the phase interpolator. For example, in a low-rate or low-performance requirement scenario, lowering the upper limit can significantly save power consumption. By dynamically adjusting the upper limit, circuit resources can be reused and hardware overhead can be reduced. For example, a phase interpolator that supports multiple upper limits can replace multiple independent phase interpolators, thereby saving chip area. The phase interpolation upper limit selection circuit can adapt to different application scenarios and working conditions.

[0040] For example, dynamically adjusting the upper limit can ensure the stability and reliability of the system under temperature, voltage or process changes. The upper limit selection circuit provides the benefits of flexibility, performance optimization and power consumption reduction by dynamically adjusting the upper limit of the phase interpolator. It has broad application prospects in high-speed communication systems, clock data recovery and multi-mode applications, which can realize resource reuse, adapt to multi-scenario requirements, and improve the overall performance and reliability of the system.

[0041] Preferably, the lower limit selection circuit comprises: a fourth selector, a fifth selector and a sixth selector; The fourth selector has a positive input terminal connected to the 45° clock signal, a negative input terminal connected to the 135° clock signal, and an output terminal connected to the positive input terminal of the sixth selector; The positive input terminal of the fifth selector is connected to the 225° clock signal, the negative input terminal is connected to the 315° clock signal, and the output terminal is connected to the negative input terminal of the sixth selector; S5 control signal controls the sixth selector; The S4 control signal controls the fourth selector and the fifth selector.

[0042] The phase interpolation lower limit selection circuit is a circuit for dynamically adjusting the lower limit of a phase interpolator (PI). The core principle is to change the lower limit of the phase interpolator by switching different starting phases or minimum phase steps through a selector switch or a multiplexer (MUX). Dynamic adjustment of the lower limit can optimize the behavior of the phase interpolator according to different working modes or performance requirements. For example, a lower lower limit (finer phase adjustment) is selected in high-speed mode, and a higher lower limit (reduced phase adjustment range) is selected in low-power mode. In low-lower limit mode, the phase interpolator can provide finer phase adjustment, thereby improving the accuracy and stability of the system. For example, in a high-speed SerDes system, a lower lower limit can reduce clock jitter and improve the reliability of data transmission. In high-lower limit mode, the adjustment range of the phase interpolator is reduced, thereby reducing computational complexity and power consumption. For example, in a low-rate or low-performance requirement scenario, increasing the lower limit can significantly save power consumption. By dynamically adjusting the lower limit, circuit resources can be reused and hardware overhead can be reduced. For example, a phase interpolator that supports multiple lower limits can replace multiple independent phase interpolators, thereby saving chip area. The lower limit selection circuit provides the benefits of flexibility, performance optimization, and power consumption reduction by dynamically adjusting the lower limit of the phase interpolator. It has broad application prospects in high-speed communication systems, clock data recovery, and multi-mode applications, which can realize resource reuse, adapt to multi-scenario requirements, and improve the overall performance and reliability of the system.

[0043] Preferably, the interpolation selection circuit comprises: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector and a first NOT gate; The output signal of the third selector is connected to the first input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The output signal of the sixth selector is connected to the second input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The input end of the first NOT gate is connected to the S2:0 control signal, and the output end is connected to the positive input end of the seventh selector; S2:0 control signal is connected to the negative input terminal of the seventh selector, and S3 control signal controls the seventh selector; An output signal of the seventh selector is connected to the first amplifier.

[0044] refer to Figure 8In the embodiment of the present invention, the phase jump has better linearity, while in the prior art, there will be a sudden change at the jump point when the phase jumps, and the linearity is not good enough, resulting in the circuit performance being not good enough. The circuit performance of the present invention is much better than the circuit performance of the phase interpolator in the prior art.

[0045] Example 3 An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a phase selection method for reducing errors in a phase interpolator.

[0046] Example 4 A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a phase selection method for reducing errors in a phase interpolator.

[0047] The present invention reduces half of the logic branches and transfers them to digital control signals that do not affect performance; each output phase of the PLL in the present invention corresponds to only one load, which can achieve complete symmetry of the layout and greatly reduce the difficulty of layout wiring; the present invention has better linearity when the MSB jumps; the present invention can reduce the random error and power consumption caused by the first-level selector.

[0048] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A phase selection method for reducing error in a phase interpolator, characterized in that: include: Select the upper limit of the phase interpolator according to the phase interpolation requirements; Select the lower limit of the phase interpolator according to the phase interpolation requirements; The upper limit and the lower limit are input into an interpolation selection circuit, and the interpolation selection circuit outputs a phase interpolation; The interpolation selection circuit comprises: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector and a first NOT gate; The output signal of the third selector is connected to the first input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The output signal of the sixth selector is connected to the second input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The input end of the first NOT gate is connected to the S2:0 control signal, and the output end is connected to the positive input end of the seventh selector; S2:0 control signal is connected to the negative input terminal of the seventh selector, and S3 control signal controls the seventh selector; An output signal of the seventh selector is connected to the first amplifier; When the phase interpolation requirement changes, the upper limit or lower limit of the interpolation selection circuit is kept unchanged, and only one of the upper limit and the lower limit is changed to perform phase interpolation.

2. A phase selection method for reducing errors in a phase interpolator according to claim 1, characterized in that: The upper limit of the phase interpolator selected according to the phase interpolation requirement includes: The upper limit of the phase interpolator is selected by changing the switch of the selector in the upper limit selection circuit.

3. A phase selection method for reducing errors in a phase interpolator according to claim 1, characterized in that: The lower limit of the phase interpolator selected according to the phase interpolation requirement includes: The lower limit of the phase interpolator is selected by changing the switch of the selector in the lower limit selection circuit.

4. A phase selection method for reducing errors in a phase interpolator according to claim 1, characterized in that: When the phase interpolation requirement changes, keeping the upper limit or the lower limit of the interpolation selection circuit unchanged and only changing one of the upper limit and the lower limit to perform phase interpolation includes: When the demand for phase interpolation becomes larger, the upper and lower limits of the interpolation selection circuit are kept unchanged, and only the smaller value of the upper and lower limits is changed to perform phase interpolation; When the phase interpolation requirement becomes smaller, the upper and lower limits of the interpolation selection circuit are kept unchanged, and only the larger value of the upper and lower limits is changed to perform phase interpolation.

5. A phase selection circuit for reducing errors in a phase interpolator, applied to a phase selection method for reducing errors in a phase interpolator according to claims 1-4, characterized in that: include: An upper limit selection circuit, a lower limit selection circuit and an interpolation selection circuit; The upper limit selection circuit is connected to the interpolation selection circuit and is used to select an upper limit of phase interpolation; The lower limit selection circuit is connected to the interpolation selection circuit and is used to select the lower limit of phase interpolation; The interpolation selection circuit selects a specific value from the upper limit and the lower limit of the phase interpolation to complete the phase interpolation according to the phase interpolation requirement; The phase interpolation requirement is the phase value that needs to be inserted; The upper limit selection circuit includes: a first selector, a second selector, a third selector, a first NAND gate, a first XOR gate and a first XNOR gate; The positive input terminal of the first selector is connected to the 0° clock signal, the negative input terminal is connected to the 90° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The positive input terminal of the second selector is connected to the 180° clock signal, the negative input terminal is connected to the 270° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The first input terminal of the first XOR gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output signal controls the first selector and the second selector; The first input terminal of the first NAND gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output terminal is connected to the first input terminal of the first XNOR gate; The second input terminal of the first XNOR gate is connected to the S5 control signal, and the output signal controls the third selector; The lower limit selection circuit includes: a fourth selector, a fifth selector and a sixth selector; The positive input terminal of the fourth selector is connected to the 45° clock signal, the negative input terminal is connected to the 135° clock signal, and the output terminal is connected to the positive input terminal of the sixth selector; The positive input terminal of the fifth selector is connected to the 225° clock signal, the negative input terminal is connected to the 315° clock signal, and the output terminal is connected to the negative input terminal of the sixth selector; S5 control signal controls the sixth selector; The S4 control signal controls the fourth selector and the fifth selector.

6. A phase selection circuit for reducing errors in a phase interpolator according to claim 5, characterized in that: The interpolation selection circuit comprises: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector and a first NOT gate; The output signal of the third selector is connected to the first input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The output signal of the sixth selector is connected to the second input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier respectively; The input end of the first NOT gate is connected to the S2:0 control signal, and the output end is connected to the positive input end of the seventh selector; S2:0 control signal is connected to the negative input terminal of the seventh selector, and S3 control signal controls the seventh selector; An output signal of the seventh selector is connected to the first amplifier.

7. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a phase selection method for reducing errors in a phase interpolator as described in any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a phase selection method for reducing errors in a phase interpolator as described in any one of claims 1 to 4.

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