A Phase Selection Method and Circuit for Reducing Errors in a Phase Interpolator

Abstract

The object of the present invention is to provide a phase selection method and circuit for reducing errors in a phase interpolator. The method includes: selecting the upper limit of the phase interpolator according to the phase interpolation requirement; selecting the lower limit of the phase interpolator according to the phase interpolation requirement; inputting the upper limit and the lower limit into an interpolation selection circuit, and the interpolation selection circuit outputs a phase interpolation; when the phase interpolation requirement changes, keeping either the upper limit or the lower limit of the interpolation selection circuit unchanged, and only changing one of the upper limit and the lower limit values for phase interpolation. The present invention reduces half of the logic branches and transfers them to digital control signals that do not affect performance. Moreover, each output phase of the PLL corresponds to only one load, enabling complete symmetry of the layout. It can also reduce the random error and power consumption brought by one-level MUX and has better linearity when the phase requirement jumps.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a phase selection method and circuit for reducing errors in a phase interpolator. Background Art

[0002] A phase interpolator (PI) is a device used to adjust the phase of a sampling clock, mainly used in a clock data recovery (CDR) circuit to achieve a stable state of dynamically following data. The working principle of the phase interpolator is as follows: Signal processing: The phase interpolator receives multiple signals with different phases, usually including a first signal and a second signal. These signals are processed by multiple phase splitting elements, and each phase splitting element receives the corresponding signal and control signal. Phase adjustment: Through the control signal, the phase interpolator can select and process a specific signal to generate an output signal with the desired phase. This process involves fine adjustment of the sampling clock phase to ensure the best synchronization between the clock signal and the data signal. Dynamic adjustment: The phase interpolator continuously adjusts the clock phase to ensure that the clock can dynamically follow the changes in the data during the data sampling process, thereby reducing the sampling error and improving the accuracy of data recovery. The phase interpolator plays a key role in the CDR (Clock and Data Recovery) system, especially in high-speed communication and data processing. For example, in an optical module, CDR recovers the clock information from the received optical signal to ensure that the signal at the receiving end is consistent with that at the transmitting end, thereby ensuring the accurate transmission of data.

[0003] In the prior art, in high-speed clock transmission, it is necessary to insert a high-precision phase difference interpolator in the CDR to determine the sampling phase. Digital phase converters have gradually become the mainstream. In the traditional architecture, after the PLL generates 8 phases, the high-order MSB of the control signal will select two adjacent phases from the 8 phases. Then, after the low-order control LSB is converted into a thermometric code, the difference between the two phases is calculated. In this way, an omnidirectional difference signal of 0 - 360° can be obtained. In high-speed designs, the 8 phases generated by the PLL are transmitted as 4 groups of differential signals. Since each signal (Φj) is connected to [Φj - 1, Φj] and [Φj, Φj + 1] twice during the connection process, the layout in the layout will adopt a mesh wiring to reduce the relative error of each phase load in order to achieve approximation. However, as the clock frequency continues to increase, the errors formed by the MUX for selecting the phase and the wiring of the front and rear stage MUX for a single phase become non-negligible. Summary of the Invention

[0004] The object of the present invention is to provide a phase selection method and circuit for reducing errors in a phase interpolator. This method reduces half of the logic branches and transfers them to digital control signals that do not affect performance. Moreover, each output phase of the PLL corresponds to only one load, enabling complete symmetry of the layout. It can also reduce the random error and power consumption caused by one level of MUX and has better linearity when the phase demand jumps.

[0005] A phase selection method for reducing errors in a phase interpolator, comprising:

[0006] Selecting the upper limit of the phase interpolator according to the phase interpolation requirement;

[0007] Selecting the lower limit of the phase interpolator according to the phase interpolation requirement;

[0008] Inputting the upper limit and the lower limit into an interpolation selection circuit, and the interpolation selection circuit outputs a phase interpolation;

[0009] When the phase interpolation requirement changes, keeping either the upper limit or the lower limit of the interpolation selection circuit unchanged and only changing one of the upper limit and the lower limit values for phase interpolation.

[0010] Preferably, the selecting the upper limit of the phase interpolator according to the phase interpolation requirement includes:

[0011] Selecting the upper limit of the phase interpolator by changing the switch of the selector in the upper limit selection circuit.

[0012] Preferably, the selecting the lower limit of the phase interpolator according to the phase interpolation requirement includes:

[0013] Selecting the lower limit of the phase interpolator by changing the switch of the selector in the lower limit selection circuit.

[0014] Preferably, the when the phase interpolation requirement changes, keeping either the upper limit or the lower limit of the interpolation selection circuit unchanged and only changing one of the upper limit and the lower limit values for phase interpolation includes:

[0015] When the phase interpolation requirement becomes larger, keeping the larger value of the upper limit and the lower limit of the interpolation selection circuit unchanged and only changing the smaller one of the upper limit and the lower limit for phase interpolation;

[0016] When the phase interpolation requirement becomes smaller, keeping the smaller value of the upper limit and the lower limit of the interpolation selection circuit unchanged and only changing the larger one of the upper limit and the lower limit for phase interpolation.

[0017] A phase selection circuit for reducing errors in a phase interpolator, comprising: an upper limit selection circuit, a lower limit selection circuit, and an interpolation selection circuit;

[0018] The upper limit selection circuit is connected to the interpolation selection circuit and is used to select the upper limit of the phase interpolation;

[0019] The lower limit selection circuit is connected to the interpolation selection circuit for selecting the lower limit of phase interpolation.

[0020] The interpolation selection circuit selects a specific value from the upper and lower limits of phase interpolation according to the phase interpolation requirement to complete phase interpolation.

[0021] Preferably, the upper limit selection circuit includes: a first selector, a second selector, a third selector, a first NAND gate, a first XOR gate, and a first XNOR gate;

[0022] The positive input terminal of the first selector is connected to the 0° clock signal, the negative input terminal is connected to the 90° clock signal, and the output terminal is connected to the positive input terminal of the third selector;

[0023] The positive input terminal of the second selector is connected to the 180° clock signal, the negative input terminal is connected to the 270° clock signal, and the output terminal is connected to the positive input terminal of the third selector;

[0024] The first input terminal of the first XOR gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output signal controls the first selector and the second selector;

[0025] The first input terminal of the first NAND gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output terminal is connected to the first input terminal of the first XNOR gate;

[0026] The second input terminal of the first XNOR gate is connected to the S5 control signal, and the output signal controls the third selector.

[0027] Preferably, the lower limit selection circuit includes: a fourth selector, a fifth selector, and a sixth selector;

[0028] The positive input terminal of the fourth selector is connected to the 45° clock signal, the negative input terminal is connected to the 135° clock signal, and the output terminal is connected to the positive input terminal of the sixth selector;

[0029] The positive input terminal of the fifth selector is connected to the 225° clock signal, the negative input terminal is connected to the 315° clock signal, and the output terminal is connected to the negative input terminal of the sixth selector;

[0030] The S5 control signal controls the sixth selector;

[0031] The S4 control signal controls the fourth selector and the fifth selector.

[0032] Preferably, the interpolation selection circuit includes: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector, and a first NOT gate;

[0033] The output signals of the third selector are respectively connected to the first input ends of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier;

[0034] The output signals of the sixth selector are respectively connected to the second input ends of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier and the fifth amplifier;

[0035] The input end of the first NOT gate is connected to the S2:0 control signal, and the output end is connected to the positive input end of the seventh selector;

[0036] The S2:0 control signal is connected to the negative input end of the seventh selector, and the S3 control signal controls the seventh selector;

[0037] The output signal of the seventh selector is connected to the first amplifier.

[0038] An electronic device, comprising: a chip, a processor and a memory, the memory is used for storing computer program codes, the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes a phase selection method for reducing errors in a phase interpolator.

[0039] A computer-readable storage medium stores a computer program, the computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor is caused to execute a phase selection method for reducing errors in a phase interpolator.

[0040] The beneficial effects of the present invention are as follows: 1. The present invention reduces half of the logic branches and transfers them to digital control signals that do not affect performance; 2. Each output phase of the PLL in the present invention corresponds to only one load, and complete symmetry of the layout can be achieved, which can greatly reduce the difficulty of layout wiring; 3. The present invention has better linearity when the MSB jumps; 4. The present invention can reduce the random error and power consumption brought by one-level selector. Description of the Drawings

[0041] The drawings here are incorporated into the specification and form a part of this specification, indicating the embodiments that conform to the present invention, and are used together with the specification to explain the principles of the present invention.

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 It is a flowchart of a phase selection method for reducing errors in a phase interpolator of the present invention;

[0044] Figure 2 It is a circuit diagram of the prior art phase selection of the present invention;

[0045] Figure 3 It is a circuit diagram of a phase selection for reducing errors in a phase interpolator of the present invention;

[0046] Figure 4 It is a schematic diagram of the prior art 175° phase selection of the present invention;

[0047] Figure 5 It is a schematic diagram of the prior art 185° phase selection of the present invention;

[0048] Figure 6 It is a schematic diagram of the 175° phase selection of the present invention;

[0049] Figure 7 It is a schematic diagram of the 185° phase selection of the present invention;

[0050] Figure 8 It is a schematic diagram of the linearity of the phase interpolator of the present invention. Detailed implementation manners

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0052] It should be noted that all the directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0053] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0054] In the prior art for high-speed clock transmission, it is necessary to insert a high-precision phase difference detector in the CDR to determine the sampling phase. Digital phase converters have gradually become the mainstream. In the traditional architecture, after the PLL generates 8 phases, the high-order MSB of the control signal will select two adjacent phases from the 8 phases. Then, after the low-order control LSB is converted into a thermometric code, the difference between the two phases is obtained. In this way, an omnidirectional difference signal of 0-360° is obtained. In high-speed designs, the 8 phases generated by the PLL are 4 groups of differential signals during transmission. And since each signal (Φj) is respectively connected to [Φj-1, Φj] and [Φj, Φj+1] twice during connection, the layout in the layout will adopt a mesh wiring to reduce the relative error of each phase load in order to achieve approximation. However, as the clock frequency continues to increase, the wiring of the MUX for selecting phases and the front and rear stage MUXs for a single phase becomes an error that cannot be ignored.

[0055] The present invention reduces half of the logic branches and transfers them to the digital control signals that do not affect performance; each output phase of the PLL in the present invention corresponds to only one load, and the layout can be completely symmetrical, which can greatly reduce the difficulty of layout wiring; the present invention has better linearity when the MSB jumps; the present invention can reduce the random error and power consumption brought by one-level selectors.

[0056] Embodiment 1

[0057] A phase selection method for reducing errors in a phase interpolator, referring to Figure 1 , including:

[0058] S100, selecting the upper limit of the phase interpolator according to the phase interpolation requirement;

[0059] S200, selecting the lower limit of the phase interpolator according to the phase interpolation requirement;

[0060] S300, inputting the upper limit and the lower limit into the interpolation selection circuit, and the interpolation selection circuit outputs the phase interpolation;

[0061] The S400 keeps the upper limit or the lower limit of the interpolation selection circuit unchanged when the phase interpolation requirement changes, and only changes one of the upper limit and the lower limit to perform phase interpolation.

[0062] The phase interpolator generates an output phase between two or more input clock signals by mixing their phases. The difference between the upper limit and the lower limit is determined by the position of the control signal. In this invention, taking the 6-bit control signal S[5:0] as an example, the difference between the upper limit and the lower limit is 45°. Each control signal controls a section with a difference of 45° between the upper limit and the lower limit. The scope of protection of this invention includes, but is not limited to, the upper and lower limit selection schemes controlled by other bit control signals, and the resolution of the phase interpolator can be adjusted according to the actual application scenario.

[0063] Preferably, selecting the upper limit of the phase interpolator according to the phase interpolation requirement includes:

[0064] Changing the switch of the selector in the upper limit selection circuit to select the upper limit of the phase interpolator.

[0065] Dynamically adjusting the upper limit of the phase interpolator by changing the selector switch in the upper limit selection circuit can achieve a flexible and efficient design of the circuit. The resolution, power consumption, and performance of the phase interpolator can be dynamically adjusted according to actual requirements, which is suitable for multi-mode or multi-scenario applications. By changing the upper limit of the phase interpolator through the selector switch, it can adapt to different working modes or performance requirements. A higher upper limit (high resolution) is used in the high-performance mode, and a lower upper limit (low resolution) is used in the low-power mode. By reusing circuit resources, the hardware overhead is reduced.

[0066] Preferably, selecting the lower limit of the phase interpolator according to the phase interpolation requirement includes:

[0067] Changing the switch of the selector in the lower limit selection circuit to select the lower limit of the phase interpolator.

[0068] Dynamically adjusting the lower limit of the phase interpolator by changing the selector switch in the lower limit selection circuit can achieve a flexible and efficient design of the circuit. This method can dynamically adjust the starting phase or the minimum phase step of the phase interpolator according to actual requirements, which is suitable for multi-mode or multi-scenario applications (such as clock data recovery, high-speed SerDes systems, etc.). The resolution, power consumption, and performance of the phase interpolator can be dynamically adjusted according to actual requirements, which is suitable for multi-mode or multi-scenario applications. By changing the upper limit of the phase interpolator through the selector switch, it can adapt to different working modes or performance requirements. A higher upper limit (high resolution) is used in the high-performance mode, and a lower upper limit (low resolution) is used in the low-power mode. By reusing circuit resources, the hardware overhead is reduced.

[0069] Preferably, when the phase interpolation requirement changes, keeping the upper limit or the lower limit of the interpolation selection circuit unchanged and only changing one of the upper limit and the lower limit for phase interpolation includes:

[0070] When the phase interpolation requirement increases, keeping the larger value of the upper limit and the lower limit of the interpolation selection circuit unchanged and only changing the smaller value of the upper limit and the lower limit for phase interpolation;

[0071] When the phase interpolation requirement decreases, keeping the smaller value of the upper limit and the lower limit of the interpolation selection circuit unchanged and only changing the larger value of the upper limit and the lower limit for phase interpolation.

[0072] The present invention provides a phase selection scheme: Taking the 6-bit control signal S[5:0] as an example, in the input signal of the final phase difference detector [Φ a , Φ b , S[5:3] controls a / b. S[2:0] controls the core part of the difference detector.

[0073] The scheme in the prior art: The technical scheme of the present invention:

[0074] S[5:3] = 0 – [Φ0, Φ 45 0 – [Φ0, Φ 45

[0075] 1 – [Φ 45 , Φ 90 1 – [Φ 90 , Φ 45

[0076] 2 – [Φ 90 , Φ 135 2 – [Φ 90 , Φ 135

[0077] 3 – [Φ 135 , Φ 180 3 – [Φ 180 , Φ 135

[0078] 4 – [Φ 180 , Φ 225 4 – [Φ 180 , Φ 225

[0079] 5 – [Φ 225 , Φ 270 5 – [Φ 270 , Φ 225

[0080] ​​​​​​6 – [Φ 270 , Φ 315 6 – [Φ 270 , Φ 315

[0081] 7 – [Φ 315 , Φ0] 7 – [Φ0, Φ 315

[0082] It can be seen that in the prior art, when the value to be output by the phase interpolator jumps, both the upper and lower limits change. However, in the embodiments of the present invention, there is always one upper limit or lower limit that does not change.

[0083] Refer to Figure 2 , Figure 4 and Figure 5 . As shown in Figure 2 , the structures of the lower limit selection circuit and the upper limit selection circuit in the prior art are the same. When phase interpolation is to be performed, as shown in Figure 4 , the lower limit selection circuit and the upper limit selection circuit select the upper limit of 135° and the lower limit of 180° through the control of each selector, and then input the values of the upper and lower limits into the interpolation selection circuit. The interpolation selection circuit changes the enable signal of the amplifier to make the finally output phase value 175°. When the phase needs to jump, as shown in Figure 5 , when the phase to be selected jumps from Figure 4 175° to Figure 5 185°, there are two nodes that need to jump in the upper limit selection circuit, which are represented by 1 and 2 in Figure 5 so as to select the upper limit of 135°. At the same time, since the structure of the lower limit selection circuit is the same as that of the upper limit selection circuit, when jumping, the number of nodes that need to jump is also the same, which are represented by 1 and 2 in Figure 5 so as to select the lower limit of 225°. At this time, both the upper limit value and the lower limit value input into the interpolation selection circuit are changed. If an interpolation of 185° is to be selected, the value of other amplifiers, that is, the third node, needs to be changed to output the phase of 185°. Therefore, in the prior art, three nodes need to be changed for one phase jump. Obviously, this will cause a large random error and power consumption.

[0084] In the embodiments of the present invention, the phase jump is as shown in Figure 6 and Figure 7 . In Figure 6 , the lower limit selection circuit and the upper limit selection circuit also select the upper limit of 180° and the lower limit of 135° through the control of each selector, and then input the values of the upper and lower limits into the interpolation selection circuit. The interpolation selection circuit changes the enable signal of the amplifier to make the finally output phase value 175°. However, during the jump process, as shown in Figure 7 ​​, the selector in the upper limit selection circuit remains unchanged and still outputs the upper limit of 180°. Only the selector in the lower limit selection circuit is changed to output a lower limit of 225°. At this time, the changed node is Figure 7 represented by 1, and then the upper limit of 180° and the lower limit value of 225° are input into the interpolation selection circuit. At this time, the amplifier in the interpolation selection circuit can directly output an interpolation of 185° without jumping. Thus, it can be seen that in the present invention, only one node needs to be changed to complete the phase jump. Compared with the prior art, it has very low power consumption and small error.

[0085] Embodiment 2

[0086] A phase selection circuit for reducing error in a phase interpolator, referring to Figure 3 , including: an upper limit selection circuit, a lower limit selection circuit, and an interpolation selection circuit;

[0087] The upper limit selection circuit is connected to the interpolation selection circuit and is used to select the upper limit of the phase interpolation;

[0088] The lower limit selection circuit is connected to the interpolation selection circuit and is used to select the lower limit of the phase interpolation;

[0089] The interpolation selection circuit selects a specific value from the upper limit and the lower limit of the phase interpolation according to the phase interpolation requirement to complete the phase interpolation.

[0090] In the embodiment of the present invention, a phase selection circuit for reducing error in a phase interpolator is divided into three major modules: an upper limit selection circuit, a lower limit selection circuit, and an interpolation selection circuit. The function of the upper limit selection circuit is to select the upper limit of the phase interpolation, the function of the lower limit selection circuit is to select the lower limit of the phase interpolation, and the function of the interpolation selection circuit is to select a specific value from the upper limit and the lower limit of the phase interpolation to complete the phase interpolation.

[0091] The circuit layout of the present invention is completely symmetrical, greatly reducing the difficulty of layout wiring.

[0092] Preferably, the upper limit selection circuit includes: a first selector, a second selector, a third selector, a first NAND gate, a first XOR gate, and a first XNOR gate;

[0093] The positive input terminal of the first selector is connected to the 0° clock signal, the negative input terminal is connected to the 90° clock signal, and the output terminal is connected to the positive input terminal of the third selector;

[0094] The positive input terminal of the second selector is connected to the 180° clock signal, the negative input terminal is connected to the 270° clock signal, and the output terminal is connected to the positive input terminal of the third selector;

[0095] The first input terminal of the first exclusive OR gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output signal controls the first selector and the second selector;

[0096] The first input terminal of the first NAND gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output terminal is connected to the first input terminal of the first exclusive NOR gate;

[0097] The second input terminal of the first exclusive NOR gate is connected to the S5 control signal, and the output signal controls the third selector.

[0098] The upper limit selection circuit is a circuit used to dynamically adjust the upper limit of the phase interpolator. Its core principle is to switch different interpolation coefficient bits or phase adjustment ranges through selector switches or multiplexers (MUXs), thereby changing the upper limit of the phase interpolator. Dynamically adjusting the upper limit of the phase interpolation can optimize the behavior of the phase interpolator according to different operating modes or performance requirements. In high-performance modes, a higher upper limit can provide finer phase adjustment, thereby improving the accuracy and stability of the system. For example, in high-speed SerDes systems, a higher upper limit can reduce clock jitter and improve the reliability of data transmission. In low-power modes, a lower upper limit can reduce the computational complexity and power consumption of the phase interpolator. For example, in scenarios with low data rates or low performance requirements, reducing the upper limit can significantly save power. By dynamically adjusting the upper limit, circuit resources can be reused and hardware overhead can be reduced. For example, a phase interpolator that supports multiple upper limits can replace multiple independent phase interpolators, thereby saving chip area. The phase interpolation upper limit selection circuit can adapt to different application scenarios and operating conditions.

[0099] For example, in the case of temperature, voltage, or process variations, dynamically adjusting the upper limit can ensure the stability and reliability of the system. The upper limit selection circuit provides the benefits of flexibility, performance optimization, and power reduction by dynamically adjusting the upper limit of the phase interpolator. It has broad application prospects in high-speed communication systems, clock data recovery, and multi-mode applications, enabling resource reuse, adapting to multi-scenario requirements, and improving the overall performance and reliability of the system.

[0100] Preferably, the lower limit selection circuit includes: a fourth selector, a fifth selector, and a sixth selector;

[0101] The positive input terminal of the fourth selector is connected to the 45° clock signal, the negative input terminal is connected to the 135° clock signal, and the output terminal is connected to the positive input terminal of the sixth selector;

[0102] The positive input terminal of the fifth selector is connected to the 225° clock signal, the negative input terminal is connected to the 315° clock signal, and the output terminal is connected to the negative input terminal of the sixth selector;

[0103] The S5 control signal controls the sixth selector;

[0104] The S4 control signal controls the fourth selector and the fifth selector.

[0105] The phase interpolation lower limit selection circuit is a circuit used to dynamically adjust the lower limit of a Phase Interpolator (PI). Its core principle is to switch different starting phases or minimum phase steps through selector switches or multiplexers (MUXes), thereby changing the lower limit of the phase interpolator. Dynamically adjusting the lower limit can optimize the behavior of the phase interpolator according to different operating modes or performance requirements. For example, a lower lower limit (more refined phase adjustment) is selected in high-speed modes, and a higher lower limit (reduced phase adjustment range) is selected in low-power modes. In the low lower limit mode, the phase interpolator can provide more refined phase adjustment, thereby improving the accuracy and stability of the system. For example, in a high-speed SerDes system, a lower lower limit can reduce clock jitter and improve the reliability of data transmission. In the high lower limit mode, the adjustment range of the phase interpolator is reduced, thereby reducing computational complexity and power consumption. For example, in scenarios with low data rates or low performance requirements, increasing the lower limit can significantly save power. By dynamically adjusting the lower limit, circuit resources can be reused and hardware overhead can be reduced. For example, a phase interpolator that supports multiple lower limits can replace multiple independent phase interpolators, thereby saving chip area. The lower limit selection circuit provides the benefits of flexibility, performance optimization, and power reduction by dynamically adjusting the lower limit of the phase interpolator. It has broad application prospects in high-speed communication systems, clock data recovery, and multi-mode applications, can achieve resource reuse, adapt to multi-scenario requirements, and improve the overall performance and reliability of the system.

[0106] Preferably, the interpolation selection circuit includes: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector, and a first NOT gate;

[0107] The output signal of the third selector is respectively connected to the first input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier, and the fifth amplifier;

[0108] The output signal of the sixth selector is respectively connected to the second input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier, and the fifth amplifier;

[0109] The input terminal of the first NOT gate is connected to the S2:0 control signal, and the output terminal is connected to the positive input terminal of the seventh selector;

[0110] The S2:0 control signal is connected to the negative input terminal of the seventh selector, and the S3 control signal controls the seventh selector;

[0111] The output signal of the seventh selector is connected to the first amplifier.

[0112] Reference Figure 8 In the embodiments of the present invention, the phase jump has better linearity. In the prior art, when there is a phase jump, there is a sudden change at the jump point, and the linearity is not good enough, resulting in insufficient performance of the circuit. The circuit performance of the present invention is much better than that of the phase interpolator in the prior art.

[0113] Embodiment 3

[0114] An electronic device includes: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a phase selection method for reducing errors in a phase interpolator.

[0115] Embodiment 4

[0116] A computer-readable storage medium stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a phase selection method for reducing errors in a phase interpolator.

[0117] The present invention reduces the number of logic branches by half and transfers them to digital control signals that do not affect performance; for each output phase of the PLL in the present invention, there is only one load, which can achieve complete symmetry of the layout and greatly reduce the difficulty of layout wiring; the present invention has better linearity when the MSB jumps; the present invention can reduce the random error and power consumption brought by one-level selectors.

[0118] The above are only specific embodiments of the present invention, which enable those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A phase selection method for reducing errors in a phase interpolator, characterized in that, Comprising: Selecting the upper limit of the phase interpolator according to the phase interpolation requirement; Selecting the lower limit of the phase interpolator according to the phase interpolation requirement; Inputting the upper limit and the lower limit into the interpolation selection circuit, and the interpolation selection circuit outputs the phase interpolation; The interpolation selection circuit includes: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector, and a first NOT gate; The output signals of the third selector are respectively connected to the first input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier, and the fifth amplifier; The output signals of the sixth selector are respectively connected to the second input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier, and the fifth amplifier; The input terminal of the first NOT gate is connected to the S2:0 control signal, and the output terminal is connected to the positive input terminal of the seventh selector; The S2:0 control signal is connected to the negative input terminal of the seventh selector, and the S3 control signal controls the seventh selector; The output signal of the seventh selector is connected to the first amplifier; When the phase interpolation requirement changes, keeping either the upper limit or the lower limit of the interpolation selection circuit unchanged, and only changing one of the upper limit and the lower limit for phase interpolation; When the phase interpolation requirement changes, keeping either the upper limit or the lower limit of the interpolation selection circuit unchanged, and only changing one of the upper limit and the lower limit for phase interpolation includes: When the phase interpolation requirement becomes larger, keeping the larger value of the upper limit and the lower limit of the interpolation selection circuit unchanged, and only changing the smaller value of the upper limit and the lower limit for phase interpolation; When the phase interpolation requirement becomes smaller, keeping the smaller value of the upper limit and the lower limit of the interpolation selection circuit unchanged, and only changing the larger value of the upper limit and the lower limit for phase interpolation.

2. A phase selection method for reducing errors in a phase interpolator according to claim 1, characterized in that, The selecting the upper limit of the phase interpolator according to the phase interpolation requirement includes: Selecting the upper limit of the phase interpolator by changing the switches of the selectors in the upper limit selection circuit.

3. A phase selection method for reducing errors in a phase interpolator according to claim 1, characterized in that, The selecting the lower limit of the phase interpolator according to the phase interpolation requirement includes: Selecting the lower limit of the phase interpolator by changing the switches of the selectors in the lower limit selection circuit.

4. A phase selection circuit for reducing errors in a phase interpolator, applied to a phase selection method for reducing errors in a phase interpolator as claimed in claims 1-3, characterized in that, Comprising: An upper limit selection circuit, a lower limit selection circuit, and an interpolation selection circuit; The upper limit selection circuit is connected to the interpolation selection circuit and is used to select the upper limit of the phase interpolation; The lower limit selection circuit is connected to the interpolation selection circuit and is used to select the lower limit of the phase interpolation; The interpolation selection circuit selects specific values from the upper limit and the lower limit of the phase interpolation according to the phase interpolation requirement to complete the phase interpolation; The phase interpolation requirement is the phase value to be inserted; The upper limit selection circuit includes: a first selector, a second selector, a third selector, a first NAND gate, a first XOR gate, and a first XNOR gate; The positive input terminal of the first selector is connected to the 0° clock signal, the negative input terminal is connected to the 90° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The positive input terminal of the second selector is connected to the 180° clock signal, the negative input terminal is connected to the 270° clock signal, and the output terminal is connected to the positive input terminal of the third selector; The first input terminal of the first exclusive-OR gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output signal controls the first selector and the second selector; The first input terminal of the first NAND gate is connected to the S3 control signal, the second input terminal is connected to the S4 control signal, and the output terminal is connected to the first input terminal of the first exclusive-NOR gate; The second input terminal of the first exclusive-NOR gate is connected to the S5 control signal, and the output signal controls the third selector; The lower limit selection circuit includes: a fourth selector, a fifth selector, and a sixth selector; The positive input terminal of the fourth selector is connected to the 45° clock signal, the negative input terminal is connected to the 135° clock signal, and the output terminal is connected to the positive input terminal of the sixth selector; The positive input terminal of the fifth selector is connected to the 225° clock signal, the negative input terminal is connected to the 315° clock signal, and the output terminal is connected to the negative input terminal of the sixth selector; The S5 control signal controls the sixth selector; The S4 control signal controls the fourth selector and the fifth selector.

5. The phase selection circuit for reducing errors in a phase interpolator according to claim 4, characterized in that, The interpolation selection circuit includes: a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, a seventh selector, and a first NOT gate; The output signal of the third selector is respectively connected to the first input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier, and the fifth amplifier; The output signal of the sixth selector is respectively connected to the second input terminals of the first amplifier, the second amplifier, the third amplifier, the fourth amplifier, and the fifth amplifier; The input terminal of the first NOT gate is connected to the S2:0 control signal, and the output terminal is connected to the positive input terminal of the seventh selector; The S2:0 control signal is connected to the negative input terminal of the seventh selector, and the S3 control signal controls the seventh selector; The output signal of the seventh selector is connected to the first amplifier.

6. An electronic device, characterized in that, Comprising: A chip, a processor, and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a phase selection method for reducing errors in a phase interpolator as described in any one of claims 1 to 3.

7. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, the computer program includes program instructions, and when the program instructions are executed by the processor of the electronic device, the processor is caused to execute a phase selection method for reducing errors in a phase interpolator as described in any one of claims 1 to 3.

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