Successive approximation analog-to-digital converter and sampling hold circuit and calibration method thereof

Abstract

The invention provides a successive approximation analog-to-digital converter and a sampling hold circuit and a calibration method thereof, in the sampling hold circuit, a sampling capacitor is a laminated structure formed by a plurality of MOM capacitors and is similar to a vertical 3D type MOM capacitor, so that the layout area of a capacitor array is remarkably reduced, the wiring parasitic capacitance is reduced, the matching performance of the capacitors is improved, and the sampling hold circuit and the calibration method of the successive approximation analog-to-digital converter are improved. And the overall precision and efficiency of the SAR ADC are improved.

Description

Technical Field

[0001] The invention relates to the technical field of digital-to-analog conversion, and in particular to a successive approximation analog-to-digital converter and a sampling and holding circuit and a calibration method thereof. Background Art

[0002] SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a commonly used analog-to-digital converter, which is widely used in data acquisition systems. Its working principle is based on the successive approximation algorithm, through a successive approximation register to control the internal digital-to-analog converter (DAC), gradually approximating the value of the input analog signal until the closest digital representation is found. Compared with other types of ADCs, such as flash ADCs or integrating ADCs, SAR ADCs achieve a better balance between speed and power consumption, and are suitable for medium-speed, high-resolution applications such as audio processing, sensor interfaces, and instrumentation. Due to its simple structure and easy integration, SAR ADC is widely used in portable devices and low-power applications.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In view of the problems in the prior art, the purpose of the present invention is to provide a successive approximation analog-to-digital converter and a sampling and holding circuit and a calibration method thereof, which overcome the difficulties of the prior art and can improve the overall accuracy and efficiency of the SAR ADC.

[0005] A first aspect of the present disclosure provides a sample-and-hold circuit for a successive approximation analog-to-digital converter, comprising:

[0006] A first switch module, connected to the first node and the second node, configured to be turned on under the control of a first phase level signal provided by a first clock signal terminal;

[0007] A second switch module, connected to the positive voltage signal terminal and the first node, and configured to be turned on under the control of a second phase level signal provided by the first clock signal terminal, wherein the first phase level signal and the second phase level signal are in opposite phases;

[0008] a third switch module and a clock inverter, wherein the third switch module is connected to the second node and the ground terminal, the clock inverter is connected to the first clock signal terminal, the clock inverter is configured to output a first phase level signal after flipping the second phase level signal provided by the first clock signal terminal, and the third switch module is configured to be turned on under the control of the first phase level signal;

[0009] a fourth switch module, connected to the third node and the positive voltage signal terminal, and configured to be turned on under the control of the fourth node;

[0010] A sampling capacitor connected to the second node and the third node, wherein the sampling capacitor is a stacked structure composed of a plurality of metal-oxide-metal capacitors;

[0011] a fifth switch module, connected to the third node and the fourth node, and configured to be turned on under the control of the first node;

[0012] a sixth switch module, connected to the signal input terminal and the second node, and configured to be turned on under the control of the fourth node;

[0013] a seventh switch module, connected to the signal input terminal and the signal output terminal, and configured to be turned on under the control of the fourth node;

[0014] an eighth switch module, connected to the fourth node and the fifth node, and configured to remain turned on under the control of the positive voltage signal terminal;

[0015] The ninth switch module is connected to the fifth node and the ground terminal, and is configured to be turned on under the control of the second clock signal terminal, wherein the second clock signal terminal and the first clock signal terminal are respectively connected to two-phase non-overlapping clock signals.

[0016] In some embodiments, the first switch module includes a first NMOS transistor, and the second switch module includes a first PMOS transistor;

[0017] The gates of the first NMOS transistor and the first PMOS transistor are both connected to the first clock signal terminal, and the drains are both connected to the first node;

[0018] The source of the first NMOS transistor is connected to the second node, and the source of the first PMOS transistor is connected to the positive voltage signal terminal.

[0019] In some embodiments, the third switch module includes:

[0020] The second NMOS transistor has a gate connected to the clock inverter, a drain connected to the second node, and a source connected to the ground terminal.

[0021] In some embodiments, the fourth switch module includes:

[0022] The second PMOS transistor has a gate connected to the fourth node, a source connected to the positive voltage signal terminal, and a drain connected to the third node.

[0023] In some embodiments, the fifth switch module includes:

[0024] The third PMOS transistor has a gate connected to the first node, a source connected to the fourth node, and a drain connected to the third node.

[0025] In some embodiments, the sixth switch module includes a third NMOS transistor, and the seventh switch module includes a fourth NMOS transistor;

[0026] The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the fourth node;

[0027] The source of the third NMOS transistor is connected to the second node, the source of the fourth NMOS transistor is connected to the ground terminal, and the drains of the third NMOS transistor and the fourth NMOS transistor are both connected to the signal input terminal.

[0028] In some embodiments, the eighth switch module includes a fifth NMOS transistor, and the ninth switch module includes a sixth NMOS transistor;

[0029] The gate of the fifth NMOS transistor is connected to the positive voltage signal terminal and the drain is connected to the fourth node. The source of the fifth NMOS transistor and the drain of the sixth NMOS transistor are connected to the fifth node. The source of the sixth NMOS transistor is connected to the ground terminal.

[0030] A second aspect of the present disclosure provides a successive approximation analog-to-digital converter, comprising a sampling and holding circuit for a successive approximation analog-to-digital converter of any of the above-mentioned embodiments, an analog-to-digital converter capacitor array, a comparator, and a successive approximation logic circuit connected in sequence, wherein the successive approximation logic circuit is also connected to the analog-to-digital converter capacitor array; each capacitor in the analog-to-digital converter capacitor array adopts a stacked structure composed of multiple metal-oxide-metal capacitors.

[0031] A third aspect of the present disclosure provides a calibration method for the successive approximation analog-to-digital converter of the above embodiment, comprising:

[0032] When the successive approximation analog-to-digital converter performs analog-to-digital conversion, measuring the differential nonlinearity error and the integral nonlinearity error of the output signal;

[0033] Calculating a compensation value of each capacitor in the capacitor array according to the differential nonlinear error and the integral nonlinear error, and performing capacitance value correction on the capacitor array based on the compensation value;

[0034] The compensation value is fed back to the successive approximation logic circuit, so that the successive approximation logic circuit corrects the output signal based on the compensation value to ensure that the differential nonlinearity error and the integral nonlinearity error are within a preset range.

[0035] In some embodiments, calculating the compensation value of each capacitor in the capacitor array according to the differential nonlinear error and the integral nonlinear error includes:

[0036] Calculating the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error for the differential nonlinear error and the integral nonlinear error respectively;

[0037] Determining whether the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error are beyond respective preset ranges;

[0038] If exceeded, the compensation value of each capacitor in the capacitor array is recalculated according to the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error.

[0039] In the disclosed embodiment, the sampling capacitor is a stacked structure composed of multiple MOM capacitors, similar to a vertical 3D MOM capacitor, which significantly reduces the layout area of ​​the capacitor array, reduces the parasitic capacitance of the routing, and improves the matching of the capacitors, thereby improving the overall accuracy and efficiency of the SAR ADC.

[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.

[0042] Figure 1 A circuit structure diagram of a sample-and-hold circuit provided in an embodiment of the present disclosure is shown.

[0043] Figure 2 exhibit Figure 1 The equivalent circuit diagram of the sample-and-hold circuit is shown.

[0044] Figure 3 exhibit Figure 2 The circuit layout of a unit capacitance of the sampling capacitor in the sample-and-hold circuit shown.

[0045] Figure 4 exhibit Figure 2 The overall circuit layout of the sampling capacitor in the sample-and-hold circuit is shown.

[0046] Figure 5 A circuit structure topology diagram of a successive approximation analog-to-digital converter provided by an embodiment of the present disclosure is shown.

[0047] Figure 6 Display pair Figure 5 A schematic diagram of the calibration method of the successive approximation analog-to-digital converter is shown.

[0048] Figure 7 and Figure 8 Display pair Figure 5 The following is a schematic diagram of the DNL and INL simulation results of the successive approximation analog-to-digital converter.

[0049] Fig. 9 and Fig.10 Display pair Figure 5 Schematic diagram of simulation results of process corner and fluctuating power supply voltage of successive approximation analog-to-digital converter shown.

[0050] Fig.11 Display pair Figure 5 The schematic diagram of the circuit structure for calibrating the successive approximation analog-to-digital converter is shown.

[0051] Fig.12 Display pair Figure 5 The schematic diagram of the circuit structure for calibrating the successive approximation analog-to-digital converter is shown in FIG. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0053] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0054] In addition, the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0055] In the current SAR ADC design, the sampling switch usually uses Metal-Oxide-Metal Capacitor (MOM capacitor) as a key component. MOM capacitors are ideal for SAR ADC sampling circuits due to their excellent linearity, high capacitance density, and low parasitic effects. During the sampling phase, MOM capacitors work in conjunction with the sampling switch to store the charge of the input analog signal and transfer it to the successive approximation register (SAR) during the conversion process.

[0056] Compared with traditional MOS capacitors, MOM capacitors can provide more precise capacitance values, ensuring sampling accuracy and consistency. This high-precision capacitor structure not only improves ADC conversion accuracy, but also effectively reduces power consumption and chip area, further enhancing the competitiveness of SAR ADC in portable devices and low-power applications. However, it is difficult for existing MOM capacitors to achieve the femtofarad level of capacitance required by high-speed SAR ADCs, so how to efficiently design a unit capacitor array with low capacitance, low mismatch error, and low parasitics is a very important topic.

[0057] like Figure 1 As shown, the embodiment of the present disclosure provides a sample-and-hold circuit for a successive approximation analog-to-digital converter, which includes:

[0058] A first switch module 11, connected to the first node n1 and the second node n2, and configured to be turned on under the control of a first phase level signal provided by the first clock signal terminal CLK1;

[0059] A second switch module 12, connected to the positive voltage signal terminal VDD and the first node n1, and configured to be turned on under the control of a second phase level signal provided by the first clock signal terminal CLK1, wherein the first phase level signal and the second phase level signal are in opposite phases;

[0060] A third switch module 13 and a clock inverter CKN, wherein the third switch module 13 is connected to the second node n2 and the ground terminal GND, the clock inverter CKN is connected to the first clock signal terminal CLK1, the clock inverter CKN is configured to invert the second phase level signal provided by the first clock signal terminal CLK1 and then output a first phase level signal, and the third switch module 13 is configured to be turned on under the control of the first phase level signal;

[0061] The fourth switch module 14 is connected to the third node n3 and the positive voltage signal terminal VDD, and is configured to be turned on under the control of the fourth node n4;

[0062] A sampling capacitor C1 is connected to the second node n2 and the third node n3, wherein the sampling capacitor is a stacked structure composed of a plurality of metal-oxide-metal capacitors;

[0063] A fifth switch module 15, connected to the third node n3 and the fourth node n4, and configured to be turned on under the control of the first node n1;

[0064] The sixth switch module 16 is connected to the signal input terminal V IN and the second node n2 is configured to be turned on by being controlled by the fourth node n4;

[0065] The seventh switch module 17 is connected to the signal input terminal V IN and a signal output terminal Vout, configured to be turned on by the control of the fourth node n4;

[0066] An eighth switch module 18, connected to the fourth node n4 and the fifth node n5, and configured to remain turned on under the control of the positive voltage signal terminal VDD;

[0067] The ninth switch module 19 is connected to the fifth node n5 and the ground terminal VDD, and is configured to be turned on under the control of the second clock signal terminal CLK2, wherein the second clock signal terminal CLK2 and the first clock signal terminal CLK1 are respectively connected to two-phase non-overlapping clock signals.

[0068] The working principle of the sampling and holding circuit disclosed in the present invention is that when the first clock signal terminal CLK1 provides a second phase level signal, the gate voltage bootstrap switch circuit is in a holding state. At this time, the second clock signal terminal CLK2 provides a second phase level signal, the ninth switch module 19 is turned on, the fourth node n4 is written with a low level provided by the ground terminal GND, and the fourth switch module 14 is turned on. At the same time, the first limit level signal is converted into a second phase level signal through the clock inverter CKN, triggering the third switch module 13 to turn on. In this way, the positive voltage signal terminal VDD charges the sampling capacitor C1 through the fourth switch module 14, and at the same time, the second node n2 is written with a low level of the ground terminal GND, and C1 stores the n2 low level and the n3 high level.

[0069] When the first clock signal terminal CLK1 provides a first phase level signal, the gate voltage bootstrap switch circuit is in a sampling state, the fourth switch module 14 and the third switch module 13 are closed, and the first switch module 11 is turned on. Under the action of the low level n2 stored in C1, the fifth switch module 15 is turned on, and the high level of the third node n3 is written into the fourth node n4, so that the sixth switch module 16 and the seventh switch module 17 are turned on, and Vout=V IN .

[0070] In the above-mentioned sampling and holding circuit of the embodiment of the present disclosure, the first switch module 11, the second switch module 12, the third switch module 13, the fourth switch module 14, the fifth switch module 15, the sixth switch module 16, the seventh switch module 17, the eighth switch module 18 and the ninth switch module 19 together constitute a sampling switch, specifically a gate voltage bootstrap switch circuit, which improves the sampling accuracy and switching speed of the SAR ADC and optimizes the overall conversion performance. At the same time, the sampling capacitor C1 is a stacked structure composed of multiple MOM capacitors, similar to a vertical 3D MOM capacitor, which significantly reduces the layout area of ​​the capacitor array, reduces the parasitic capacitance of the routing, and improves the matching of the capacitor, thereby improving the overall accuracy and efficiency of the SAR ADC.

[0071] MOM capacitors use the interdigital structure of the same metal layer to build capacitors. Figure 2 As shown, in the sampling capacitor C1, the first MOM capacitor C11 and the second MOM capacitor C12 form a stacked structure, and the upper and lower MOM capacitor plates are perpendicular to each other and are insulated and isolated by the dielectric layer 10. The stacked structure expands the layout area of ​​the single-layer MOM capacitor, so C11 and C122 can have a smaller layout area than the original design, and the required capacitance is achieved through the stacked structure. Figure 3 , Figure 3 A complete MOM capacitor layout for sampling capacitor C1. Figure 2 for Figure 3 A MOM capacitor layout unit in .

[0072] The SAR ADC sampling switch in the embodiment of the present disclosure adopts a gate voltage bootstrap sampling switch circuit, wherein the sampling capacitor C1 (such as Figure 1 The MOM capacitor is a 3D vertical stack of multiple metal layers. During the layout design process, the MOM capacitor adjusts the metal layer area to obtain different capacitance values. The following are the steps for creating a MOM capacitor Pcell based on the parameterized cell layout design tool:

[0073] Set parameters: Establish the parameters of the bottom metal and top metal, and set variable conditions;

[0074] Create a library (similar to the library of virtuoso): assign values ​​in the form of variables and create the libraries corresponding to each metal layer one by one, such as Figure 2 The layout of the first metal layer in the first MOM capacitor C11 and the second metal layer in the second MOM capacitor C12 generated as shown;

[0075] Setting conditions: Setting conditions for the metal layer in each layer of MOM capacitor;

[0076] Establish parameterized MOM: call all metal layers in MOM capacitor to complete parameterized MOM capacitor;

[0077] Automatically generate MOM capacitors: Generate MOM capacitors for corresponding metal layers according to specific requirements.

[0078] like Figure 4 As shown, Figure 1 An equivalent circuit diagram of the gate voltage bootstrap switch circuit shown in the figure, the first switch module 11 includes a first NMOS transistor M1, and the second switch module 12 includes a first PMOS transistor M2;

[0079] The gates of the first NMOS transistor M1 and the first PMOS transistor M2 are both connected to the first clock signal terminal CLK1, and the drains are both connected to the first node n1;

[0080] A source of the first NMOS transistor M1 is connected to the second node n2 , and a source of the first PMOS transistor M2 is connected to the positive voltage signal terminal VDD.

[0081] In this embodiment, when the first phase level signal provided by the first clock signal terminal CLK1 is at a high level, the first NMOS transistor M1 is turned on, and the first PMOS transistor M2 is turned off. Conversely, when the second phase level signal provided by CLK1 is at a low level, the first NMOS transistor M1 is turned off, and the first PMOS transistor is turned on.

[0082] In another embodiment, the first switch module selects a PMOS transistor, and the second switch module selects an NMOS transistor. At this time, the first phase level signal is a low level, and the second phase level signal is a high level.

[0083] In the embodiment of the present disclosure, the third switch module 13 includes:

[0084] The second NMOS transistor M3 has a gate connected to the clock inverter CKN, a drain connected to the second node n2, and a source connected to the ground terminal GND.

[0085] In this embodiment, the clock inverter CKN inverts the clock signal of the input first clock signal terminal CLK1. Thus, when the first clock signal terminal CLK1 provides a low level, the clock inverter CKN outputs a high level, M3 is turned on, and the sampling capacitor C1 stores the low level of the ground terminal GND.

[0086] In the embodiment of the present disclosure, the fourth switch module 14 includes:

[0087] The second PMOS transistor M4 has a gate connected to the fourth node n4, a source connected to the positive voltage signal terminal VDD, and a drain connected to the third node n3.

[0088] In this embodiment, when the fourth node n4 is at a low level, the second PMOS transistor M4 is turned on, and the positive voltage signal provided by the positive voltage signal terminal VDD is written into n3. At this time, the sampling capacitor C1 stores a high level of n3.

[0089] In the embodiment of the present disclosure, the fifth switch module 15 includes:

[0090] The third PMOS transistor M4 has a gate connected to the first node n1, a source connected to the fourth node n4, and a drain connected to the third node n3.

[0091] In this embodiment, when n1 is at a low level, the fourth PMOS transistor M4 is turned on, and the potential of n3 is written into n4.

[0092] In the embodiment of the present disclosure, the sixth switch module 16 includes a third NMOS transistor M6, and the seventh switch module 17 includes a fourth NMOS transistor M7; the gates of the third NMOS transistor M6 and the fourth NMOS transistor M7 are both connected to the fourth node n4;

[0093] The source of the third NMOS transistor M6 is connected to the second node n2, the source of the fourth NMOS transistor M7 is connected to the ground terminal GND, and the drains of the third NMOS transistor M6 and the fourth NMOS transistor M7 are both connected to the signal input terminal V IN .

[0094] In this embodiment, n4 controls M6 and M7 to be turned on and off simultaneously. When n4 is at a high level, M6 and M7 are turned on simultaneously to enter a sampling state.

[0095] In the embodiment of the present disclosure, the eighth switch module 18 includes a fifth NMOS transistor M8, and the ninth switch module 19 includes a sixth NMOS transistor M9;

[0096] The gate of the fifth NMOS transistor M8 is connected to the positive voltage signal terminal VDD and the drain is connected to the fourth node n4, the source of the fifth NMOS transistor M8 and the drain of the sixth NMOS transistor M9 are connected to the fifth node n5, the gate of the sixth NMOS transistor M9 is connected to the second clock signal terminal CLK2 and the source is connected to the ground terminal GND.

[0097] In this embodiment, M8 is connected to the positive voltage signal terminal VDD, so it remains in the on state. When the second clock signal terminal CLK2 provides a low level, M9 is turned on, and vice versa when CLK2 provides a high level, M9 is turned off. Since CLK1 and CLK2 are two-phase non-overlapping clock signals, M1 and M9 remain in opposite states.

[0098] When CLK1 is at a low level, M3, M8, M9, and M4 are turned on, M5 and M6 are turned off, and the path from the MOM capacitor to the power supply and to the ground is turned on. At this time, VDD charges the MOM capacitor:

[0099] In the above embodiment of the present disclosure, when CLK1 is at a low level and CLK2 is at a high level, M3, M8, M9, and M4 are turned on, and M5 and M6 are turned off. At this time, VDD charges C1:

[0100] When CLK1 is high and CLK2 is low, M3, M4, and M9 are turned off, M5, M6, and M7 are turned on, and Vout = V IN For M7, its gate voltage Vg=V IN +VDD, Vgs is equal to VDD. At this time, the on-resistance of M7 is a constant and will not change with the input voltage, which effectively improves the linearity of the switch.

[0101] In the disclosed embodiment, any of the above NMOS transistors is replaced by a PMOS transistor, and any of the above PMOS transistors is replaced by an NMOS transistor. At this time, by replacing CLK1 with CLK2 and replacing CLK2 with CLK1, the above gate voltage bootstrap switch circuit can also be implemented.

[0102] The present disclosure also provides a successive approximation analog-to-digital converter, such as Figure 5 As shown, it includes a sampling and holding circuit 51 for a successive approximation analog-to-digital converter according to any of the above embodiments, an analog-to-digital converter (DAC) capacitor array 52, a comparator 53 and a successive approximation logic circuit 54.

[0103] In the embodiment of the present disclosure, the DAC capacitor array 52 and the sampling capacitor C1 (such as Figure 1In the shared capacitor architecture shown in FIG. 5 , the capacitor units of the DAC capacitor array 52 also serve as the sampling capacitor C1. Thus, in the sampling phase, the capacitors of the DAC capacitor array 52 are used as the sampling capacitor C1 to store the voltage of the input signal.

[0104] Specifically, in the sample-and-hold circuit 51, the sampling capacitor C1 is used to store the input analog signal voltage. In the sampling phase, the sampling switch 511 is closed, and the voltage of the input signal is charged to the sampling capacitor C1. In the holding phase, the sampling switch 511 is opened, and the sampling capacitor C1 maintains its voltage value as the input reference signal of the subsequent DAC capacitor array 52 and the comparator 53. The DAC capacitor array 52 is used to implement a DA conversion network, which is a binary weighted capacitor array (such as Figure 5 The two columns of DAC capacitor array 52 shown are used to generate a reference voltage that gradually approaches the input signal according to the successive approximation logic, divide the reference voltage by a capacitor ratio to generate a specified reference voltage, and update the reference voltage in each successive approximation step to gradually approach the input signal voltage stored in the sampling capacitor C1.

[0105] Therefore, during the DAC conversion phase, the capacitors in the DAC capacitor array 52 are switched to the DAC function to generate the reference voltage according to the successive approximation logic.

[0106] This structure reduces the number of capacitors, reduces chip area and power consumption, and improves the overall consistency and matching of the system.

[0107] In another embodiment, the sampling capacitor and the DAC capacitor array adopt a separate capacitor architecture, the sampling capacitor and the DAC capacitor array are designed separately, the sampling capacitor is used for sampling and holding alone, and the DAC capacitor array focuses on DA conversion. This design function separation design is more flexible, and the sampling capacitor and the DAC capacitor array can be optimized independently to meet different performance requirements.

[0108] Regardless of which implementation method is used, the interaction between the sampling capacitor C1 and the DAC capacitor array 52 is as follows:

[0109] Sampling phase:

[0110] If it is a shared capacitor architecture, the DAC capacitor array 52 is temporarily used as a sampling capacitor to store the voltage of the input signal.

[0111] If it is a split capacitor architecture, the sampling capacitor C1 stores the voltage of the input signal, and the DAC capacitor array 52 remains static;

[0112] Conversion phase:

[0113] The sampling capacitor C1 (or the shared DAC capacitor array 52) uses the input signal voltage as a fixed reference;

[0114] The DAC capacitor array 52 generates a series of successive approximation reference voltages for comparison with the input signal.

[0115] The sampling capacitor C1 and the DAC capacitor array 52 are functionally responsible for signal storage and reference voltage generation, respectively. In physical implementation, the two may be independent or integrated through a shared architecture. In the shared architecture, the DAC capacitor array 52 assumes the responsibility of the sampling capacitor C1 during the sampling phase and restores its DAC function during the conversion phase. This relationship enables the SAR ADC to achieve efficient miniaturization while ensuring accuracy.

[0116] like Figure 5 As shown, the working principle of the successive approximation analog-to-digital converter is as follows:

[0117] (1) In the sampling phase, the sampling switch 511 is closed and the analog signal V is input. IN and V IP It is stored on the sampling capacitor C1, and the voltage value of the sampling capacitor C1 is the instantaneous voltage value of the current input signal.

[0118] In the holding phase, the sampling switch 511 is disconnected, and the voltage of the sampling capacitor C1 remains unchanged, serving as a comparison reference between the input signal and the reference signal.

[0119] During this process, the sample-and-hold circuit 51 outputs a fixed analog voltage (stored on the sampling capacitor C1 ) as an input signal of the comparator 53 .

[0120] Among them, in the SAR ADC circuit, V IN and V IP Usually represents the two terminals of the differential input signal, corresponding to the input analog signals mentioned above. Their specific meanings are as follows: VIP is also represented as Vin+, which represents the positive terminal of the differential input signal (Positive Input), usually connected to the positive or non-inverting terminal of the input analog signal source. IN Also represented as (Vin-), it indicates the negative end (Negative Input) of the differential input signal, which is usually connected to the negative or inverting end of the input analog signal source. Differential input signal is a common signal processing method, especially in high-precision SAR ADC. The differential input signal has strong anti-interference ability and has good suppression ability for common-mode noise, because the common-mode interference signal will cancel each other out on the two signal lines. Moreover, the linearity of the differential input signal is higher, and the differential structure can effectively reduce nonlinear distortion and improve the conversion accuracy of the ADC. In addition, the dynamic range of the differential input signal is larger, which is twice that of the single-ended signal, allowing the SAR ADC to process a wider range of input signals.

[0121] In a SAR ADC, V IP and V IN Usually used as the two ends of the input analog signal, for input analog signal sampling, the two differential input signals are sampled through the sample-and-hold circuit 51 (including the sampling switch 511 and the sampling capacitor C1) and stored on the sampling capacitor C1. Further, the differential analog signal is input to the comparator 53, compared with the reference signal generated by the DA conversion network, and further converted into the final digital signal output through the successive approximation logic circuit 54.

[0122] In this embodiment, the sampling switch 511 is composed of Figure 1 The switch modules shown are constructed together and will not be described in detail here. Please refer to the above content.

[0123] (2) The comparator 53 receives the output voltage (input analog signal) of the sampling and holding circuit 51 and the reference voltage generated by the DA conversion network (DAC) (i.e., the DAC capacitor array 52). The comparator 53 outputs a "0" or "1" as a comparison result, i.e., a logic signal, according to the magnitude of the input analog signal and the reference signal. The logic signal ("0" or "1") output by the comparator 53 is transmitted to the successive approximation logic circuit 54 for determining the digital output code bit by bit.

[0124] (3) The successive approximation logic circuit 54 determines the switching state of the DAC capacitor array 52 according to the output ("0" or "1") of the comparator 53. The successive approximation logic circuit 54 controls the DAC capacitor array 52 to generate the next reference voltage for the next comparison.

[0125] Specifically, the successive approximation logic circuit 54 outputs a control signal to drive the DAC capacitor array 52 to switch the voltage of the upper / lower plates to gradually approximate the input analog signal.

[0126] (4) The reference voltage generated by the DA conversion network is compared with the input analog signal of the sample and hold circuit 51, and the reference voltage gradually approaches the input signal in a binary weighted manner according to a successive approximation algorithm.

[0127] In this process, the DA conversion network outputs a reference voltage as one of the input signals of the comparator 53 , which is compared with the input analog signal output by the sample and hold circuit 51 .

[0128] The data stream of the SAR ADC is cyclically operated according to the following process to gradually complete the analog-to-digital conversion:

[0129] The sample and hold circuit 51 inputs the analog input signal V IN and V IP (external input), outputs a fixed analog voltage (input signal) after holding.

[0130] The comparator 53 inputs the analog signal output by the sample and hold circuit 51 and the reference voltage generated by the DAC capacitor array 52 , and outputs a logic signal (“0” or “1”) indicating the magnitude relationship between the input signal and the reference signal.

[0131] The successive approximation logic circuit 54 inputs the logic signal output by the comparator 53 and outputs a control signal to adjust the switching state of the DAC capacitor array 52 and accumulate and generate a digital output code.

[0132] The DAC capacitor array 52 inputs the control signal of the successive approximation logic circuit 54 and outputs a reference voltage for the next comparison.

[0133] Exemplarily, the successive approximation process of the data stream is described with an example (SAR ADC with 3-bit resolution):

[0134] (1) Initialization

[0135] The sample-and-hold circuit 51 captures the input analog signal V IP and V IN , after the sampling and holding is completed, it enters the holding stage;

[0136] The DA capacitor array 52 is set to an initial state and outputs a reference voltage of the highest weight bit (eg, Vref / 2).

[0137] (2) First comparison

[0138] The comparator 53 compares the voltage of the sampling capacitor C1 (input signal) with the reference voltage output by the DAC capacitor array 52:

[0139] If the input signal > Vref / 2, the comparator 53 outputs "1";

[0140] If the input signal ≤ Vref / 2, the comparator 53 outputs "0".

[0141] The successive approximation logic circuit 54 locks the value of the most significant bit (1 or 0) according to the comparison result.

[0142] (3) Second comparison

[0143] The successive approximation logic circuit 54 controls the DAC capacitor array 52 to update the reference voltage (eg, Vref / 4 or 3Vref / 4) according to the result of the first comparison.

[0144] The comparator 53 performs a second comparison and outputs a result to update the value of the second highest bit in the successive approximation logic circuit 54 .

[0145] (4) Third comparison

[0146] The DAC capacitor array 52 continues to update the reference voltage (eg, Vref / 8, 5Vref / 8, etc.).

[0147] Comparator 53 performs the last comparison and determines the value of the least significant bit.

[0148] (5) Final output

[0149] The successive approximation logic circuit 54 accumulates the comparison results of all bits and generates a final digital output code.

[0150] As described above, the various modules in the SAR ADC work together to achieve the successive approximation analog-to-digital conversion function. The data stream circulates between the sample-and-hold circuit 51, the comparator 53, the successive approximation logic circuit 54 and the DAC capacitor array 52, gradually approaching the input signal at each step until the digital output of the target resolution is completed.

[0151] In the above embodiment, the DAC capacitor array 52 is a stacked structure composed of a plurality of metal-oxide-metal capacitors. Figure 3 The multi-layer stacked MOM capacitor is shown.

[0152] like Figure 6 As shown, the embodiment of the present disclosure also provides a calibration method of a successive approximation analog-to-digital converter, which includes but is not limited to the following steps:

[0153] Step 610: When the successive approximation analog-to-digital converter performs analog-to-digital conversion, measure the differential nonlinearity error and the integral nonlinearity error of the output signal;

[0154] Step 620: Calculate a compensation value of each capacitor in the capacitor array according to the differential nonlinear error and the integral nonlinear error, and perform capacitance value correction on the capacitor array based on the compensation value;

[0155] Step 630: Feedback the compensation value to the successive approximation logic circuit, so that the successive approximation logic circuit corrects the output signal based on the compensation value to ensure that the differential nonlinearity error and the integral nonlinearity error are within a preset range.

[0156] The differential nonlinearity (DNL) reflects the error between adjacent digital output signals. If the DNL is large, some digital signals may not fully correspond to the corresponding interval of the analog input signal, resulting in missing codes. The integral nonlinearity (INL) reflects the cumulative error from the first to the last conversion code. If the INL value is too large, it means that the ADC conversion result cannot accurately reflect the changes in the input signal.

[0157] In practical applications, in SAR ADC, each capacitor value in the DAC capacitor array used for successive approximation is set according to a certain ratio. Ideally, the value of each capacitor should be accurate and matched, but in actual production, small errors in the manufacturing process (such as material inhomogeneity, geometric structure errors of capacitors, etc.) will cause the actual value of each capacitor to deviate from the expected standard value, which is reflected as mismatch error. This mismatch error will cause DNL and INL errors of SAR ADC, affecting the final conversion accuracy.

[0158] The calibration method provided in this embodiment calibrates and compensates the capacitance value of the capacitor in the DAC capacitor array, dynamically adjusts or compensates for the mismatch error, so as to ensure that the output signal of the SAR ADC can accurately reflect the input analog signal, thereby reducing the error caused by the capacitor mismatch, improving the accuracy of the SAR ADC, and reducing the error caused by the non-ideal characteristics of the DAC capacitor array. The calibrated SAR ADC has good static performance, and the DNL and INL errors are kept at a low level, avoiding missing codes and significant accuracy degradation, and improving the overall conversion accuracy of the SAR ADC.

[0159] In the embodiment of the present disclosure, when executing step 610, the actual DNL and INL errors are measured, and the degree of mismatch and its influence on conversion accuracy are analyzed according to the error relationship between the input signal and the output signal. Then, the current capacitance value of each capacitor in the DAC capacitor array is adjusted according to the DNL and INL errors. Specifically, the current capacitance value of each capacitor is fine-tuned to compensate for the DNL and INL errors.

[0160] In one implementation, calculating the compensation value of each capacitor in the capacitor array according to the differential nonlinear error and the integral nonlinear error includes:

[0161] Calculating the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error for the differential nonlinear error and the integral nonlinear error respectively;

[0162] Determining whether the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error are beyond respective preset ranges;

[0163] If exceeded, the compensation value of each capacitor in the capacitor array is recalculated according to the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error.

[0164] In this embodiment, by deriving the standard deviation of the DNL error and the INL error, the influence of the DNL error and the INL error caused by the capacitor mismatch can be calculated.

[0165] Taking DNL error as an example, the standard deviation calculation formula is:

[0166]

[0167] Where N represents the resolution, σ DNL，MAX represents the standard deviation of DNL error, C0 represents the standard value of a single capacitor, σ0 is the standard deviation of a single capacitor, indicating the degree of capacitor mismatch, and LSB represents the smallest resolvable unit. According to the 3σ principle of normal distribution, the preset range corresponding to DNL error is that the 3 standard deviations of DNL error are less than LSB / 2.

[0168] This formula derives the relationship between the standard deviation of the DNL error and the mismatch of the capacitor (especially the standard deviation of the capacitor). By adjusting the size of the unit capacitor C00, the range of the DNL error can be controlled, thereby optimizing the DAC capacitor array during the design phase to keep the DNL error within an acceptable preset range.

[0169] After calibration, the DNL and INL errors are greatly reduced and the static performance is improved because the capacitor mismatch is compensated. Figure 7 The simulation results are shown in Figure 1, where the horizontal axis represents the digital code value output by the ADC, expressed as ADC Code, and the vertical axis represents DNL. Through compensation, the maximum error of DNL is close to 0LSB, thus avoiding the missing code phenomenon (that is, there will be no input interval where some digital values ​​have no corresponding values). Figure 8 As shown in the simulation results, the INL error is compressed through compensation, and the accumulated error in the entire conversion process is also greatly reduced, thus improving the accuracy of the SAR ADC.

[0170] Therefore, the simulation results show that after calibration, the maximum and minimum values ​​of DNL and INL errors of the SAR ADC are controlled within a reasonable range, and the static performance is significantly improved.

[0171] Furthermore, in terms of dynamic performance, Fast Fourier Transform (FFT) simulation was performed on five available process corners (ss (Slow-Slow), snfp (slow normal fast), tt (Typical-Typical), fnsp (fast normal slow), ff (Fast-Fast)) and fluctuating power supply voltage (Voltage). The verification results under different process corners are as follows: Fig. 9 As shown in the figure, the signal-to-noise-and-distortion ratio (SNDR) fluctuates around 85.5dB, and the spurious-free dynamic range (SFDR) varies between 96.5dB and 102.5dB. Fig.10 The results shown show the dynamic performance under fluctuating power supply voltage. The SNDR can tolerate about ±9% power supply variation, that is, it remains near 85.2dB. The SFDR has been maintained at around 101.5dB. However, when the power supply voltage (Voltage) is reduced to 1.6V, the SFDR decreases significantly. The SAR ADC designed in the embodiment of the present disclosure has a performance improvement of about 5% compared to the SAR ADC of the related art.

[0172] As an implementation method, the present disclosure provides a circuit structure for implementing the above calibration method, such as Fig.11 As shown, the calibration circuit 55 is coupled between the DAC capacitor array 52 and the successive approximation logic circuit 54 .

[0173] Specifically, Fig.12 As shown, corresponding to the two columns of DAC capacitor arrays 52, the calibration circuit 55 includes two corresponding columns of calibration capacitor arrays 551 and 552. The DAC capacitor array 52 is used to generate the reference voltage required in the successive approximation process, and the calibration capacitor arrays 551 and 552 in the calibration circuit are used to measure and compensate for the error caused by the capacitance mismatch of the DAC capacitor array 52.

[0174] Specifically, the calibration capacitor arrays 551 and 552 in the calibration circuit 55 are used to compare the differences between the capacitor units. By comparing the output of each capacitor unit in the DAC capacitor array 52 with the reference voltage, the deviation between the actual value and the theoretical value of each capacitor unit is measured, thereby quantifying the mismatch error. Based on the measured capacitor mismatch error, the calibration circuit 55 calculates compensation factors, which can be used to dynamically adjust the behavior of the DAC capacitor array 52, or directly applied to the successive approximation logic circuit 54 (such as Fig.11to correct the reference voltage of the DAC output.

[0175] The calibration capacitor arrays 551 and 552 in the calibration circuit 55 can participate in dynamic calibration, and can reduce mismatch errors by combining digital logic to adjust the DAC capacitor array 52 in real time. In some designs, the calibration capacitor arrays 551 and 552 in the calibration circuit 55 can simulate the structure of the DAC capacitor array 52 to simulate and predict mismatch effects and provide calibration parameters for the DAC capacitor array.

[0176] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A sample-and-hold circuit for a successive approximation analog-to-digital converter, characterized in that: include: A first switch module, connected to the first node and the second node, configured to be turned on under the control of a first phase level signal provided by a first clock signal terminal; A second switch module, connected to the positive voltage signal terminal and the first node, and configured to be turned on under the control of a second phase level signal provided by the first clock signal terminal, wherein the first phase level signal and the second phase level signal are in opposite phases; a third switch module and a clock inverter, wherein the third switch module is connected to the second node and the ground terminal, the clock inverter is connected to the first clock signal terminal, the clock inverter is configured to output a first phase level signal after flipping the second phase level signal provided by the first clock signal terminal, and the third switch module is configured to be turned on under the control of the first phase level signal; a fourth switch module, connected to the third node and the positive voltage signal terminal, and configured to be turned on under the control of the fourth node; A sampling capacitor connected to the second node and the third node, wherein the sampling capacitor is a stacked structure composed of a plurality of metal-oxide-metal capacitors; a fifth switch module, connected to the third node and the fourth node, and configured to be turned on under the control of the first node; a sixth switch module, connected to the signal input terminal and the second node, and configured to be turned on under the control of the fourth node; a seventh switch module, connected to the signal input terminal and the signal output terminal, and configured to be turned on under the control of the fourth node; an eighth switch module, connected to the fourth node and the fifth node, and configured to remain turned on under the control of the positive voltage signal terminal; The ninth switch module is connected to the fifth node and the ground terminal, and is configured to be turned on under the control of the second clock signal terminal, wherein the second clock signal terminal and the first clock signal terminal are respectively connected to two-phase non-overlapping clock signals.

2. The sample-and-hold circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The first switch module includes a first NMOS transistor, and the second switch module includes a first PMOS transistor; The gates of the first NMOS transistor and the first PMOS transistor are both connected to the first clock signal terminal, and the drains are both connected to the first node; The source of the first NMOS transistor is connected to the second node, and the source of the first PMOS transistor is connected to the positive voltage signal terminal.

3. The sample-and-hold circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The third switch module comprises: The second NMOS transistor has a gate connected to the clock inverter, a drain connected to the second node, and a source connected to the ground terminal.

4. The sample-and-hold circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The fourth switch module comprises: The second PMOS transistor has a gate connected to the fourth node, a source connected to the positive voltage signal terminal, and a drain connected to the third node.

5. The sample-and-hold circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The fifth switch module comprises: The third PMOS transistor has a gate connected to the first node, a source connected to the fourth node, and a drain connected to the third node.

6. The sample-and-hold circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The sixth switch module includes a third NMOS transistor, and the seventh switch module includes a fourth NMOS transistor; The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the fourth node; The source of the third NMOS transistor is connected to the second node, the source of the fourth NMOS transistor is connected to the ground terminal, and the drains of the third NMOS transistor and the fourth NMOS transistor are both connected to the signal input terminal.

7. The sample-and-hold circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that: The eighth switch module includes a fifth NMOS transistor, and the ninth switch module includes a sixth NMOS transistor; The gate of the fifth NMOS transistor is connected to the positive voltage signal terminal and the drain is connected to the fourth node. The source of the fifth NMOS transistor and the drain of the sixth NMOS transistor are connected to the fifth node. The source of the sixth NMOS transistor is connected to the ground terminal.

8. A successive approximation analog-to-digital converter, characterized in that: The invention comprises a sampling and holding circuit for a successive approximation analog-to-digital converter, an analog-to-digital converter capacitor array, a comparator and a successive approximation logic circuit as described in any one of claims 1 to 7 connected in sequence, wherein the successive approximation logic circuit is also connected to the analog-to-digital converter capacitor array; each capacitor in the analog-to-digital converter capacitor array adopts a stacked structure composed of multiple metal-oxide-metal capacitors.

9. A method for calibrating the successive approximation analog-to-digital converter according to claim 8, characterized in that: include: When the successive approximation analog-to-digital converter performs analog-to-digital conversion, measuring the differential nonlinearity error and the integral nonlinearity error of the output signal; Calculating a compensation value of each capacitor in the capacitor array according to the differential nonlinear error and the integral nonlinear error, and performing capacitance value correction on the capacitor array based on the compensation value; The compensation value is fed back to the successive approximation logic circuit, so that the successive approximation logic circuit corrects the output signal based on the compensation value to ensure that the differential nonlinearity error and the integral nonlinearity error are within a preset range.

10. The calibration method according to claim 9, characterized in that: Calculating a compensation value of each capacitor in the capacitor array according to the differential nonlinear error and the integral nonlinear error includes: Calculating the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error for the differential nonlinear error and the integral nonlinear error respectively; Determining whether the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error are beyond respective preset ranges; If exceeded, the compensation value of each capacitor in the capacitor array is recalculated according to the standard deviation of the differential nonlinear error and the standard deviation of the integral nonlinear error.

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