Calibration method, controller, medium and product of capacitor array

Abstract

The embodiment of the present application proposes a calibration method, controller, medium and product for a capacitor array, which is applied to the field of analog-to-digital signal conversion technology and to a calibration system for a capacitor array. The system includes a basic capacitor array, multiple temperature-coding capacitor arrays and an A / D conversion module. The method includes: obtaining the residual voltage of the capacitors to be calibrated in the basic capacitor array and each temperature-coding capacitor array; performing analog-to-digital conversion on each residual voltage through the A / D conversion module to obtain a digital code for each capacitor to be calibrated; calculating the mismatch code of each capacitor to be calibrated according to the digital code through a preset mismatch code calculation formula; and calibrating the basic capacitor array and each temperature-coding capacitor array according to each mismatch code. The embodiment of the present application calibrates the basic capacitor array and each temperature-coding capacitor array through each mismatch code, thereby avoiding leakage in the capacitor array and improving the accuracy of the circuit.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital signal conversion, and in particular to a calibration method, controller, medium, and product of a capacitor array. Background Art

[0002] In the related art, mismatch calibration for conventional switched capacitor arrays generally relies on binary decoding. While this method is relatively simple to operate, it can cause all bits to briefly go high during the decoding transition. For example, in a four-bit binary code, when the code switches from 1000 to 0111, the state 1111 may briefly appear due to circuit timing limitations. This state can cause leakage in the capacitor array, adversely affecting circuit accuracy. Summary of the Invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a capacitor array calibration method, controller, medium and product, which aim to avoid leakage in the capacitor array and thus improve the accuracy of the circuit.

[0004] In a first aspect, an embodiment of the present application provides a capacitor array calibration method, which is applied to a capacitor array calibration system, the system including a basic capacitor array, multiple temperature decoding capacitor arrays, and an A / D conversion module, the method comprising:

[0005] Acquiring residual voltages of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays;

[0006] Performing analog-to-digital conversion on each of the residual voltages through the A / D conversion module to obtain a digital code for each of the capacitors to be calibrated;

[0007] Calculating the mismatch code of each capacitor to be calibrated according to the digital code using a preset mismatch code calculation formula;

[0008] The basic capacitor array and the temperature decoding capacitor arrays are calibrated according to the mismatch codes.

[0009] According to some embodiments of the present application, the system further includes a digital module, a switch logic module, and a switch module, the switch module including a plurality of switches, the plurality of switches corresponding one-to-one to the capacitors to be calibrated in the basic capacitor array and each of the temperature-coding capacitor arrays, and obtaining the residual voltage of the capacitors to be calibrated in the basic capacitor array and each of the temperature-coding capacitor arrays includes:

[0010] By means of the digital module, the switching of the output voltage of the switch logic module is controlled according to a preset control logic, and the access voltage of each of the switches is controlled according to the output voltage;

[0011] The residual voltages of the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays are obtained according to the respective access voltages.

[0012] According to some embodiments of the present application, the mismatch code of each capacitor to be calibrated is calculated according to the digital code using a preset mismatch code calculation formula, including one of the following:

[0013] When the capacitor to be calibrated belongs to a basic capacitor array, inputting the digital code into a first preset mismatch code calculation formula to obtain a mismatch code of the capacitor to be calibrated;

[0014] When the capacitor to be calibrated belongs to a temperature decoding capacitor array, the digital code is input into a second preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated.

[0015] According to some embodiments of the present application, the system further includes a register, which, after obtaining the mismatch code of each capacitor to be calibrated according to the digital code by using a preset mismatch code calculation formula, includes:

[0016] Each of the mismatch codes is stored in the register.

[0017] According to some embodiments of the present application, the first preset mismatch code calculation formula is:

[0018] ;

[0019] in, is the mismatch code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in each of the temperature decoding capacitor arrays, and n is the total number of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays.

[0020] According to some embodiments of the present application, the second preset mismatch code calculation formula is:

[0021] ;

[0022] in, is the mismatch code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in each of the temperature decoding capacitor arrays, and n is the total number of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays.

[0023] According to some embodiments of the present application, the system further includes a D / A conversion module, and the calibrating the basic capacitor array and each of the temperature decoding capacitor arrays according to each of the mismatch codes includes:

[0024] Performing digital-to-analog conversion on each of the mismatch codes through the D / A conversion module to obtain an analog signal of each of the capacitors to be calibrated;

[0025] The basic capacitor array and each of the temperature decoding capacitor arrays are calibrated according to the analog signal.

[0026] In a second aspect, an embodiment of the present application provides a controller comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the capacitance array calibration method of the first aspect described above when executing the computer program.

[0027] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the capacitance array calibration method as described in the first aspect above.

[0028] In a fourth aspect, an embodiment of the present application provides a computer program product, comprising a computer program or computer instructions, wherein the computer program or the computer instructions are stored in a computer-readable storage medium, and a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium, and the processor executes the computer program or the computer instructions, so that the computer device performs the calibration method of the capacitor array as described in the first aspect above.

[0029] According to the technical solution of the embodiment of the present application, there are at least the following beneficial effects: the embodiment of the present application proposes a calibration method, controller, medium and product for a capacitor array, which is applied to the field of analog-to-digital signal conversion technology and to a calibration system for a capacitor array. The system includes a basic capacitor array, multiple temperature-coding capacitor arrays and an A / D conversion module. The method includes: obtaining the residual voltage of the capacitor to be calibrated in the basic capacitor array and each temperature-coding capacitor array; performing analog-to-digital conversion on each residual voltage through the A / D conversion module to obtain a digital code for each capacitor to be calibrated; calculating the mismatch code of each capacitor to be calibrated according to the digital code through a preset mismatch code calculation formula; and calibrating the basic capacitor array and each temperature-coding capacitor array according to each mismatch code. The embodiment of the present application calibrates the basic capacitor array and each temperature-coding capacitor array through each mismatch code, thereby avoiding leakage in the capacitor array and improving the accuracy of the circuit.

[0030] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0032] Figure 1 1 is a schematic structural diagram of a capacitance array calibration system provided by one embodiment of the present application;

[0033] Figure 2 is a structural diagram of a capacitance array calibration system provided by another embodiment of the present application;

[0034] Figure 3 is a flow chart of a capacitance array calibration method provided by one embodiment of the present application;

[0035] Figure 4 yes Figure 3 The sub-step flow chart of step S310 is shown;

[0036] Figure 5 yes Figure 3 The sub-step flow chart of step S330 is shown;

[0037] Figure 6 yes Figure 3 The sub-step flow chart of step S340 is shown;

[0038] Figure 7 Schematic diagram of a controller for a capacitance array calibration method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0040] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0041] In the description of this application, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The terms "first" and "second" are used solely to distinguish technical features and are not to be construed as indicating or implying relative importance, or as implicitly specifying the number or order of the technical features indicated.

[0042] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0043] In some cases, mismatch calibration for traditional switched capacitor arrays often relies on binary decoding. While this method is relatively simple to operate, it can cause all bits to briefly go high during the decoding transition. For example, in a four-bit binary code, when the code switches from 1000 to 0111, circuit timing limitations may cause the state of 1111 to briefly appear. This state can cause leakage in the capacitor array, adversely affecting circuit accuracy.

[0044] Furthermore, traditional binary decoding calibration methods suffer from the problem of excessively large capacitor arrays. For an N-bit capacitor array, to ensure that differential nonlinearity errors are within acceptable limits, the selection of unit capacitors must meet specific requirements. To reduce nonlinearity errors and the complexity of the calibration circuit, traditional methods often favor larger unit capacitors. However, this approach directly increases the overall area of the capacitor array, hindering circuit miniaturization and increased integration.

[0045] Based on the above situation, the embodiments of the present application propose a calibration method, controller, medium and product for a capacitor array, aiming to avoid leakage in the capacitor array, thereby improving the accuracy of the circuit.

[0046] Various embodiments of the capacitance array calibration system of the present application will be further described below with reference to the accompanying drawings.

[0047] like Figure 1 and Figure 2 As shown, Figure 1 1 is a schematic structural diagram of a capacitance array calibration system provided by one embodiment of the present application; Figure 2 It is a structural diagram of a capacitance array calibration system provided in another embodiment of the present application.

[0048] In one embodiment, a capacitor array calibration system includes a basic capacitor array, a plurality of temperature-coding capacitor arrays, and an A / D conversion module.

[0049] It can be understood that the basic capacitor array, multiple temperature decoding capacitor arrays and the A / D conversion module are connected in sequence; illustratively, the basic capacitor array is bit1, and the multiple temperature decoding capacitor arrays are bit2, bit3 and bit4. The basic capacitor array bit1 is connected to the temperature decoding capacitor array bit2, the temperature decoding capacitor array bit2 is connected to the temperature decoding capacitor array bit4 through the temperature decoding capacitor array bit3, and the temperature decoding capacitor array bit4 is connected to the A / D conversion module.

[0050] It is understandable that the number of the above-mentioned temperature decoding capacitor arrays can be 2, 3, or 4, and can be set according to actual needs. The embodiment of the present application does not specifically limit the number of temperature decoding capacitor arrays.

[0051] It is understandable that the number of capacitors to be calibrated in the above-mentioned temperature decoding capacitor array can be 1, 2, 3, or 4, and can be set according to actual needs. The embodiment of the present application does not specifically limit the number of temperature decoding capacitor arrays.

[0052] In addition, in one embodiment, the capacitance array calibration system further includes a digital module, a switch logic module, and a switch module.

[0053] It can be understood that the switch module includes a plurality of switches, and the plurality of switches correspond one-to-one to the capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0054] It can be understood that the digital module is connected to the A / D conversion module.

[0055] In addition, in one embodiment, the capacitance array calibration system further includes a register.

[0056] It can be understood that the registers are connected to the digital modules.

[0057] In addition, in one embodiment, the capacitance array calibration system further includes a D / A conversion module.

[0058] It can be understood that the D / A conversion module is connected to the temperature decoding capacitor array.

[0059] Based on the hardware structure of the capacitor array calibration system of each of the above embodiments, various embodiments of the capacitor array calibration method of the present application are respectively proposed below.

[0060] like Figure 3 As shown, Figure 3 3 is a flowchart of a capacitance array calibration method provided by an embodiment of the present application; the capacitance array calibration method may include but is not limited to step S310, step S320, step S330 and step S340.

[0061] Step S310: Obtain the residual voltage of the capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array;

[0062] Step S320: Perform analog-to-digital conversion on each residual voltage through an A / D conversion module to obtain a digital code of each capacitor to be calibrated;

[0063] Step S330: Calculate the mismatch code of each capacitor to be calibrated according to the digital code using a preset mismatch code calculation formula;

[0064] Step S340 : calibrating the basic capacitor array and each temperature decoding capacitor array according to each mismatch code.

[0065] In one embodiment, the present invention is applied to a calibration system for a capacitor array. First, the residual voltage of the capacitors to be calibrated in the basic capacitor array and each temperature-coded capacitor array is obtained. Then, the residual voltage is converted to a digital value by an A / D conversion module to obtain a digital code for each capacitor to be calibrated. Then, the mismatch code of each capacitor to be calibrated is calculated based on the digital code using a preset mismatch code calculation formula. Finally, the basic capacitor array and each temperature-coded capacitor array are calibrated based on the mismatch codes. Therefore, the present invention calibrates the basic capacitor array and each temperature-coded capacitor array using the mismatch codes, thereby avoiding leakage in the capacitor array and improving the accuracy of the circuit.

[0066] It is understandable that the errors caused by manufacturing mismatch between the basic capacitor array and each temperature decoding capacitor array can be compensated by each mismatch code, thereby completing the calibration of the temperature decoding capacitor array.

[0067] It is understandable that when the temperature decoding capacitor array switches between codes, only one bit of the 16-bit temperature decoding will change. Therefore, using a temperature decoding capacitor array can avoid leakage in the capacitor array. At the same time, using a temperature decoding capacitor array, the DNL error per unit capacitance of an N-bit capacitor array only needs to satisfy the following formula: ,in, is the DNL standard deviation of the unit capacitor array, is the standard deviation of the manufacturing mismatch per unit capacitance.

[0068] It is understandable that using the temperature decoding capacitor array can use smaller unit capacitors, thereby reducing the capacitor array area while ensuring high accuracy.

[0069] In addition, if Figure 4 As shown, Figure 4 yes Figure 3The sub-step flow chart of step S310 is shown; regarding the above-mentioned step S310, it may include but is not limited to step S410 and step S420.

[0070] Step S410: Using a digital module, the output voltage of the switch logic module is controlled according to a preset control logic, and the access voltage of each switch is controlled according to the output voltage;

[0071] Step S420 : Obtain residual voltages of the capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array according to each access voltage.

[0072] In one embodiment, a digital module controls the switching of the output voltage of the switch logic module according to a preset control logic, thereby changing the access voltage of each switch, and further obtaining the residual voltage of the capacitor to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0073] It can be understood that the digital module controls the switch logic module to output high level and low level, thereby realizing the voltage switching of each switch between vrefp and vrefn, and then obtaining the residual voltage of the capacitor to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0074] For example, in order to obtain the residual voltage of the capacitor C_1 to be calibrated, the digital module will first output a high level to the switch S_1 to turn on vrefp, and output a low level to the remaining switches to turn on vrefn. After maintaining the state for a preset time, the residual voltage of the capacitor C_1 to be calibrated is obtained; in order to obtain the residual voltage of the capacitor C_2 to be calibrated, the digital module will first output a high level to the switch S_2 to turn on vrefp, and output a low level to the remaining switches to turn on vrefn. After maintaining the state for a preset time, the residual voltage of the capacitor C_2 to be calibrated is obtained; the method for obtaining the residual capacitance of the remaining capacitors can refer to the above-mentioned method for obtaining the residual voltages of the capacitors C_1 and C_2 to be calibrated, and will not be repeated here.

[0075] In addition, if Figure 5 As shown, Figure 5 yes Figure 3 The sub-step flow chart of step S330 is shown; regarding the above-mentioned step S330, it may include but is not limited to step S510 and step S520.

[0076] Step S510: When the capacitor to be calibrated belongs to the basic capacitor array, the digital code is input into a first preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated;

[0077] Step S520: When the capacitor to be calibrated belongs to the temperature decoding capacitor array, the digital code is input into a second preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated.

[0078] It is understandable that both the basic capacitor array and the temperature decoding capacitor array have corresponding mismatch code calculation formulas.

[0079] In addition, in one embodiment, after step S330 , the method further includes: storing each mismatch code in a register.

[0080] It is understandable that after the mismatch codes of the capacitors to be calibrated are obtained, the mismatch codes are stored in registers.

[0081] It can be understood that the calculation formula of the first preset mismatch code is: ,in, is the mismatch code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in each temperature decoding capacitor array, and n is the total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0082] For example, the mismatch code of the capacitor C_1 to be calibrated in the basic capacitor array is 1. The digital code of the capacitor C_1 to be calibrated in the basic capacitor array is 1. The digital codes of the capacitors to be calibrated C_2, C_3 to C_8 in each temperature decoding capacitor array are 2. 3 to 8. The total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array is 8. Then calculate the mismatch code of the capacitor to be calibrated C_1 by the formula Can be calculated.

[0083] It can be understood that the calculation formula for the second preset mismatch code is: ,in, is the mismatch code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in the temperature decoding capacitor array, is the digital code of the capacitor to be calibrated in each temperature decoding capacitor array, and n is the total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array.

[0084] For example, the digital codes of the capacitors to be calibrated C_2, C_3 to C_8 in each temperature decoding capacitor array are: 2. 3 to 8, the total number of capacitors to be calibrated in the basic capacitor array and each temperature decoding capacitor array is 8, then calculate the mismatch code of the capacitor to be calibrated C_2, through the formula It can be calculated that the mismatch code of the capacitor C_3 to be calibrated is calculated by the formula Can be calculated.

[0085] In addition, if Figure 6 As shown, Figure 6 yes Figure 3 The sub-step flow chart of step S340 is shown; regarding the above-mentioned step S340, it may include but is not limited to step S610 and step S620.

[0086] Step S610: Perform digital-to-analog conversion on each mismatch code through a D / A conversion module to obtain an analog signal of each capacitor to be calibrated;

[0087] Step S620: calibrate the basic capacitor array and each temperature decoding capacitor array according to the analog signal.

[0088] In one embodiment, the D / A conversion module reads the mismatch code in the register and performs digital-to-analog conversion on the mismatch code to obtain the analog signal of each capacitor to be calibrated, thereby superimposing the analog signal on the plate node of the temperature decoding capacitor array. In this way, the mismatch between the basic capacitor array and each temperature decoding capacitor array caused by process manufacturing deviation is compensated, thereby completing the calibration of the capacitor array.

[0089] Based on the calibration methods of the multi-capacitor arrays in the above-mentioned embodiments, overall embodiments of the calibration methods of the capacitor arrays of the present application are respectively proposed below.

[0090] (1) Obtaining residual voltage:

[0091] like Figure 1 As shown in the figure, a 4-bit capacitor array to be calibrated is shown. Capacitors C_2, C_3,…C_8 are the unit capacitances after temperature decoding of bits 2, 3, and 4 of the 3-bit capacitor array to be calibrated. The digital module uses the switch logic module to switch switches S1, S2,…S9 between voltages vrefp and vrefn. The residual voltages on capacitors C_1, C_2, C_3,…C_8 due to process manufacturing variations are detected at the Vp node on the top plate of the capacitor array.

[0092] (2) Treatment of residual voltage:

[0093] The A / D conversion module performs analog-to-digital conversion on the residual voltages of capacitors C_1, C_2, C_3…C_8, and obtains D_mis1 (digital code of the residual voltage of capacitor C_1 to be calibrated), D_mis2 (digital code of the residual voltage of capacitor C_2 to be calibrated)…D_mis8 (digital code of the residual voltage of capacitor C_8 to be calibrated). The digital module obtains the digital code and converts the residual voltage of each temperature decoding capacitor array to the residual voltage of each capacitor array through the formula Processing, where y = 2, 3...8, the capacitance to be calibrated C_1 of the basic capacitor array is calculated by the formula Processing is performed to obtain the mismatch codes Dcal1, Dcal2…Dcal8 of the capacitors C_1, C_2…C_8 respectively and send them to the register for storage.

[0094] (3) Mismatch code recovery:

[0095] The D / A module reads the mismatch code in the register, converts the digital signal into an analog signal, and superimposes it on the top plate node Vp of the capacitor array to compensate for the mismatch caused by process manufacturing deviations, thus completing the calibration of the capacitor array.

[0096] Based on the calibration methods of the capacitor array in the above-mentioned embodiments, various embodiments of the controller, computer-readable storage medium, and computer program product of the present application are respectively proposed below.

[0097] like Figure 7 As shown, Figure 7 Schematic diagram of a controller for a capacitance array calibration method provided by an embodiment of the present application. The controller 700 implemented in the present application includes: a processor 710, a memory 720, and a computer program stored in the memory 720 and executable on the processor 710, wherein: Figure 7 In the figure, a processor 710 and a memory 720 are taken as an example.

[0098] The processor 710 and the memory 720 may be connected via a bus or other means. Figure 7 The bus connection is taken as an example.

[0099] The memory 720 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 720 may include a high-speed random access memory and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 720 may optionally include a memory 720 remotely located relative to the processor 710, and these remote memories 720 may be connected to the controller 700 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0100] Those skilled in the art will understand that Figure 7 The device structure shown in the figure does not constitute a limitation on the controller 700, and the controller 700 may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0101] exist Figure 7In the illustrated controller 700, the processor 710 can be used to call a control program stored in the memory 720 to implement the above-described capacitor array calibration method. Specifically, the non-transient software program and instructions required to implement the capacitor array calibration method of the above-described embodiment are stored in the memory 720. When executed by the processor 710, the capacitor array calibration method of the above-described embodiment is performed.

[0102] It is worth noting that since the controller 700 of the embodiment of the present application can execute the calibration method of the capacitor array of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the controller 700 of the embodiment of the present application can refer to the specific implementation methods and technical effects of the calibration method of the capacitor array of any of the above-mentioned embodiments.

[0103] In addition, an embodiment of the present application further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the above-described capacitance array calibration method. Figures 3 to 6 The method steps in .

[0104] It is worth noting that since the computer-readable storage medium of the embodiment of the present application can execute the calibration method of the capacitor array of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer-readable storage medium of the embodiment of the present application can refer to the specific implementation methods and technical effects of the calibration method of the capacitor array of any of the above-mentioned embodiments.

[0105] In addition, an embodiment of the present application further provides a computer program product, including a computer program or computer instructions, the computer program or computer instructions being stored in a computer-readable storage medium, the processor of a computer device reading the computer program or computer instructions from the computer-readable storage medium, and the processor executing the computer program or computer instructions, so that the computer device performs the above-described capacitance array calibration method. For example, the above-described Figures 3 to 6 The method steps in .

[0106] It is worth noting that since the computer program product of the embodiment of the present application can execute the calibration method of the capacitor array of any of the above-mentioned embodiments, the specific implementation methods and technical effects of the computer program product of the embodiment of the present application can refer to the specific implementation methods and technical effects of the calibration method of the capacitor array of any of the above-mentioned embodiments.

[0107] Those skilled in the art will appreciate that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, or any suitable combination thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is well known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0108] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0110] It should also be understood that the various implementation methods provided in the embodiments of the present application can be combined arbitrarily to achieve different technical effects.

[0111] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the art can also make various equivalent modifications or substitutions under the shared conditions that do not violate the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A method for calibrating a capacitor array, characterized in that: A calibration system for a capacitor array includes a basic capacitor array, multiple temperature decoding capacitor arrays, and an A / D conversion module. The method includes: Acquiring residual voltages of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays; Performing analog-to-digital conversion on each of the residual voltages through the A / D conversion module to obtain a digital code for each of the capacitors to be calibrated; Calculating the mismatch code of each capacitor to be calibrated according to the digital code using a preset mismatch code calculation formula; calibrating the basic capacitor array and the temperature decoding capacitor arrays according to the mismatch codes; The method of calculating the mismatch code of each capacitor to be calibrated according to the digital code using a preset mismatch code calculation formula includes one of the following: When the capacitor to be calibrated belongs to a basic capacitor array, the digital code is input into a first preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated. The first preset mismatch code calculation formula is: ,in, is the mismatch code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in the basic capacitor array, is the digital code of the capacitor to be calibrated in each of the temperature decoding capacitor arrays, and n is the total number of capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays; When the capacitor to be calibrated belongs to a temperature decoding capacitor array, the digital code is input into a second preset mismatch code calculation formula to obtain the mismatch code of the capacitor to be calibrated. The second preset mismatch code calculation formula is: ,in, is the mismatch code of the capacitor to be calibrated in the temperature decoding capacitor array, The digital code of the capacitor to be calibrated in the temperature decoding capacitor array is obtained.

2. The method for calibrating a capacitor array according to claim 1, wherein: The system further includes a digital module, a switch logic module, and a switch module. The switch module includes a plurality of switches. The plurality of switches correspond one-to-one to the basic capacitor array and each capacitor to be calibrated in the temperature decoding capacitor array. Obtaining the residual voltage of the basic capacitor array and each capacitor to be calibrated in the temperature decoding capacitor array includes: By means of the digital module, the switching of the output voltage of the switch logic module is controlled according to a preset control logic, and the access voltage of each switch is controlled according to the output voltage; The residual voltages of the capacitors to be calibrated in the basic capacitor array and each of the temperature decoding capacitor arrays are obtained according to the respective access voltages.

3. The capacitance array calibration method according to claim 1, wherein: The system further includes a register, which, after obtaining the mismatch code of each capacitor to be calibrated according to the digital code by using a preset mismatch code calculation formula, includes: Each of the mismatch codes is stored in the register.

4. The method for calibrating a capacitor array according to claim 1, wherein: The system further includes a D / A conversion module, and calibrating the basic capacitor array and the temperature decoding capacitor array according to each mismatch code includes: Performing digital-to-analog conversion on each of the mismatch codes through the D / A conversion module to obtain an analog signal of each of the capacitors to be calibrated; The basic capacitor array and each of the temperature decoding capacitor arrays are calibrated according to the analog signal.

5. A controller, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the capacitance array calibration method according to any one of claims 1 to 4 when executing the computer program.

6. A computer-readable storage medium, characterized in that: Computer-executable instructions are stored, and the computer-executable instructions are used to execute the capacitance array calibration method according to any one of claims 1 to 4.

7. A computer program product comprising a computer program or computer instructions, characterized in that The computer program or the computer instructions are stored in a computer-readable storage medium, and a processor of a computer device reads the computer program or the computer instructions from the computer-readable storage medium. The processor executes the computer program or the computer instructions, so that the computer device performs the capacitance array calibration method according to any one of claims 1 to 4.

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