Sigma-Delta analog-to-digital converter and its quantization circuit

Abstract

This invention discloses a Sigma-Delta analog-to-digital converter and its quantization circuit, including an adder for providing differential positive and negative input signals; and a quantizer including multiple quantization units, each quantization unit including a first capacitor, a first capacitor group, a second capacitor group, a fourth capacitor, and a comparator. The first capacitor and the first capacitor group provide a positive input voltage to the comparator, and the second capacitor group and the fourth capacitor provide a negative input voltage to the comparator, so that the comparator outputs a quantized voltage. The first capacitor group includes multiple second capacitors, and the second capacitor group includes multiple third capacitors. The capacitance values ​​of the first and fourth capacitors are equal, and the capacitance values ​​of the second and third capacitors are equal. The capacitance value of the first capacitor is 1.5 times the capacitance value of the second capacitor, so that the threshold voltage of the quantization unit is 1.5 times that in the normal mode in jitter mode, and the number of capacitors can be reduced, thereby reducing hardware costs.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and in particular to a Sigma-Delta analog-to-digital converter and its quantization circuit. Background Technology

[0002] In recent years, the information field has placed increasingly higher demands on the performance of ADCs (Analog-to-digital converters). People have begun to focus on how to reduce static errors, and when the static error is fixed, to use dithering technology to reduce the overall quantization error of the ADC and improve the SNR (Signal-to-Noise Ratio) of the ADC.

[0003] One method used in existing Sigma-Delta ADCs to reduce the overall quantization error is to increase the overall quantization level of the quantizer in the Sigma-Delta modulator by a factor of 0.5. For an n-bit quantizer, the quantization level without dithering is -(2 n -1)ref,-(2 n -3)ref,…-ref,ref,…(2 n -3)ref,(2 n -1)ref, then the quantization level needs to be changed to -(2)ref when using dithering. n -1.5)ref,-(2 n -3.5)ref,…-0.5ref,1.5ref,…(2 n -0.5)ref.

[0004] Existing quantizers typically generate quantization levels using capacitors. A typical n-bit quantizer requires 2... n -1 quantization unit, each quantization unit requires 2 n This is achieved using a single unit capacitor C. In existing technology, to increase ref by 0.5, the quantizer needs to double all the capacitors in each quantization unit and add two more unit capacitors C, requiring a total of 2(2) units. n +1)C, for an n-bit quantizer, 2 is required. n+1 (2 n +1)C, the hardware cost is relatively high.

[0005] Therefore, a new Sigma-Delta analog-to-digital converter and its quantization circuit are needed. Summary of the Invention

[0006] In view of the above problems, the purpose of this invention is to provide a Sigma-Delta analog-to-digital converter and its quantization circuit, thereby reducing the hardware cost of the Sigma-Delta analog-to-digital converter for implementing dithering technology.

[0007] According to one aspect of the present invention, a quantization circuit for a Sigma-Delta analog-to-digital converter is provided, comprising an adder for providing differential positive and negative input signals; a quantizer comprising a plurality of quantization units, each of the quantization units comprising: a first capacitor, a first capacitor group, a second capacitor group, a fourth capacitor, and a comparator, wherein the first capacitor and the first capacitor group provide a positive input voltage to the comparator, and the second capacitor group and the fourth capacitor provide a negative input voltage to the comparator, so that the comparator outputs a quantized voltage, wherein the first capacitor group includes a plurality of second capacitors, the second capacitor group includes a plurality of third capacitors, the capacitance values ​​of the first capacitor and the fourth capacitor are equal, the capacitance values ​​of the second capacitor and the third capacitor are equal, and the capacitance value of the first capacitor is 1.5 times the capacitance value of the second capacitor.

[0008] Optionally, the quantization circuit further includes a jitter signal generation circuit for generating a jitter signal in the jitter mode of the quantization circuit and providing it to the quantization unit.

[0009] Optionally, when the quantization circuit adopts dithering mode, the first terminal of the first capacitor is selected to be connected to the common-mode voltage or ground, and the second terminal of the first capacitor is connected to the positive input terminal of the comparator; the first terminal of the second capacitor is selected to be connected to the common-mode voltage or positive input signal, and the second terminal of the second capacitor is connected to the positive input terminal of the comparator; the first terminal of the third capacitor is selected to be connected to the common-mode voltage or negative input signal, and the second terminal of the third capacitor is connected to the negative input terminal of the comparator; the first terminal of the fourth capacitor is selected to be connected to the negative reference signal or ground, and the second terminal of the fourth capacitor is connected to the negative input terminal of the comparator.

[0010] Optionally, when the quantization circuit adopts jitter mode, the first terminals of the first to fourth capacitors are selected to connect to a signal via a switch controlled by the jitter signal and / or a clock signal. In the first phase of the clock signal, the first terminal of the first capacitor is connected to the common-mode voltage, the first terminal of the second capacitor is connected to the common-mode voltage, the first terminal of the third capacitor is connected to the common-mode voltage, and the first terminal of the fourth capacitor is connected to the negative reference signal. In the second phase of the clock signal, the first terminal of the first capacitor is grounded, the first terminal of the second capacitor is connected to the positive input signal, the first terminal of the third capacitor is connected to the negative input signal, and the first terminal of the fourth capacitor is grounded.

[0011] Optionally, the number of second capacitors in the first capacitor bank is 2. n-1 There are 1, and the number of third capacitors in the second capacitor group is 2. n-1 , where n represents the number of bits in the quantizer.

[0012] Optionally, the number of second capacitors in the first capacitor bank is 2. n-1 -1, the number of third capacitors in the second capacitor group is 2. n-1 -1, where n represents the number of bits in the quantizer.

[0013] Optionally, the quantization circuit switches between the jitter mode and the normal mode by changing the connection method of the first capacitor, the fourth capacitor, and the first terminal of one of the second capacitors of the quantization unit.

[0014] Optionally, when the quantization circuit adopts the normal mode, the first terminals of the first capacitor and the fourth capacitor are always grounded, and the first terminal of one of the second capacitors in the second capacitor group is selectively connected to a positive reference signal or a positive input signal. The first terminals of the first to fourth capacitors are selected to be connected to the signal by a switch controlled by the clock signal. In the first phase of the clock signal, the first terminal of one of the second capacitors is connected to a positive reference voltage, and in the second phase of the clock signal, the first terminal of one of the second capacitors is connected to a positive input signal.

[0015] Optionally, the average value of the positive reference signal and the negative reference signal is equal to the average value of the positive input signal and the negative input signal, and the common-mode voltage is the average value of the positive reference signal and the negative reference signal.

[0016] According to another aspect of the present invention, a Sigma-Delta analog-to-digital converter is provided, comprising a Sigma-Delta modulator including cascaded multi-stage modulation circuits; and a quantization circuit as described above.

[0017] The present invention provides a Sigma-Delta analog-to-digital converter and its quantization circuit. The Sigma-Delta analog-to-digital converter includes a cascaded multi-stage modulation circuit and a quantization circuit. The quantization circuit includes an adder and a quantizer. The quantizer has multiple quantization units. Each quantization unit includes a first capacitor, a first capacitor group, a second capacitor group, and a fourth capacitor. The first capacitor group includes multiple second capacitors, and the second capacitor group includes multiple third capacitors. The capacitance values ​​of the first capacitor and the fourth capacitor are equal, and the capacitance values ​​of the second capacitor and the third capacitor are equal. The capacitance value of the first capacitor is 1.5 times that of the second capacitor. This allows the threshold voltage of the quantization unit to be 1.5 times that of the quantization unit in jitter mode to be 1.5 times that in normal mode, and it can reduce the number of capacitors, thereby reducing hardware costs.

[0018] Furthermore, the quantization unit provided in this application only needs to change the first terminal voltage of the first capacitor, the fourth capacitor, and one of the second capacitors when switching between jitter mode and normal mode, so the circuit structure is relatively simple. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 This diagram illustrates the structure of a quantization unit that does not employ dithering technology in the prior art.

[0021] Figure 2 This diagram illustrates the structure of a quantization unit employing dithering technology in the prior art.

[0022] Figure 3 A schematic diagram of the structure of a Sigma-Delta modulator according to an embodiment of the present invention is shown;

[0023] Figures 4a-4b A schematic diagram of the quantization unit according to a first embodiment of the present invention is shown;

[0024] Figure 5 A schematic diagram of the quantization unit according to a second embodiment of the present invention is shown. Detailed Implementation

[0025] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0026] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0027] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0028] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0029] Figure 1 A schematic diagram of a quantization cell in the prior art that does not employ dithering technology is shown. See also Figure 1 The quantization unit 100 includes capacitors C1 and C2. n-1 -1 capacitor C2, 2 n-1 A capacitor C3 and a comparator 10 are used, wherein the capacitance values ​​of capacitors C1, C2 and C3 are equal, all being unit capacitance C.

[0030] The first terminal of capacitor C1 is connected to either the positive reference signal refp or the positive input signal inp according to a clock signal. The second terminal of capacitor C1 is connected to the positive input terminal of comparator 10. The first terminal of capacitor C2 is connected to either the common-mode voltage cm or the positive input signal inp according to the clock signal. The second terminal of capacitor C2 is connected to the positive input terminal of comparator 10. The first terminal of capacitor C3 is connected to either the common-mode voltage cm or the negative input signal inm according to the clock signal. The second terminal of capacitor C3 is connected to the negative input terminal of comparator 10.

[0031] In the first phase (phase 1) of the clock signal, the first terminal of capacitor C1 is connected to the positive reference signal refp, and the first terminals of capacitors C2 and C3 are connected to the common-mode voltage cm. In the second phase (phase 2) of the clock signal, the first terminal of capacitor C1 is connected to the positive input signal inp, the first terminal of capacitor C2 is connected to the positive input signal inp, and the first terminal of capacitor C3 is connected to the negative input signal inm. Here, refp + refm = inp + inm = 2 * cm, where refm represents the negative reference signal, and the positive and negative input signals inp and inm are the differential output signals of the adder connected to the quantizer in the Sigma-Delta modulator.

[0032] According to the charge distribution principle, when the clock signal changes from the first phase to the second phase, the change in the voltage difference between the positive and negative input voltages of comparator 10 is:

[0033] △(op-om)=[2 n (inp-inm)-(refp-refm)] / 2 n =(2 n in-ref) / 2 n

[0034] Where op represents the positive input voltage of comparator 10, om represents the negative input voltage of comparator 10, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0035] Figure 2 A schematic diagram of a quantization unit employing dithering technology in the prior art is shown. See also... Figure 2 The quantization unit 200 adds capacitors C4 and C5 with a capacitance of unit capacitance C to the quantization unit 100, and sets the number of capacitors C2 to 2. n -2, set the quantity of capacitor C3 to 2. nThe capacitance values ​​of capacitors C1-C3 are all set to 2C. The connection method of capacitors C1-C3 is the same as that of quantization unit 100, and will not be described again here.

[0036] The first terminal of capacitor C4 is connected to either the positive reference signal refp or ground gnd, depending on the clock signal and the jitter signal. The second terminal of capacitor C4 is connected to the positive input terminal of comparator 10. The first terminal of capacitor C5 is connected to either the common-mode voltage cm or ground gnd, depending on the clock signal. The second terminal of capacitor C5 is connected to the negative input terminal of comparator 10.

[0037] In the first phase of the clock signal, the first terminal of capacitor C4 is connected to the positive reference signal refp, and the first terminal of capacitor C5 is connected to the common-mode voltage cm. In the second phase of the clock signal, the first terminals of capacitor C4 and capacitor C5 are grounded at gnd.

[0038] According to the charge distribution principle, when the clock signal changes from the first phase to the second phase, the change in voltage difference between the positive and negative input voltages of comparator 10 is:

[0039] △(op-om)=[2 n (inp-inm)-1.5(refp-refm)] / (2 n +1)=(2 n in-1.5ref) / (2 n +1)

[0040] Where op represents the positive input voltage of comparator 10, om represents the negative input voltage of comparator 10, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0041] In summary, although quantization unit 200 increases the threshold voltage of the quantization level ref by 0.5 times compared to the threshold voltage of quantization unit 100, making it 1.5ref, the required unit capacitance is (2 n+1 The capacitance of +2C is more than twice that of the quantization unit 100 without dithering, resulting in higher hardware costs. The main reason the quantization unit 200 requires so much capacitance is that a 0.5C capacitor is not readily available. Therefore, this invention provides a new quantization unit to solve the aforementioned problems.

[0042] Figure 3 A schematic diagram of the structure of a Sigma-Delta modulator according to an embodiment of the present invention is shown.

[0043] The Sigma-Delta modulator is an important component of the Sigma-Delta ADC. See also Figure 3 The Sigma-Delta modulator provided in this embodiment of the invention includes a cascaded first-order modulation circuit 3000, a second-order modulation circuit 2000, and a quantization circuit 1000. The first-order modulation circuit 3000 includes gain amplifiers b1-b3, adder Σ1, and integrator 3100. The second-order modulation circuit 2000 includes adder Σ2 and integrator 2100 connected in sequence. The quantization circuit 1000 includes adder Σ3 and quantizer 1100 connected in sequence. Adder Σ3 provides differential positive input signal inp and negative input signal inm to quantizer 1100. Quantizer 1100 has multiple quantization units; the number of quantization units is related to the number of bits in the quantizer. An n-bit quantizer typically has 2... n Each quantization unit.

[0044] In addition, the Sigma-Delta modulator also includes a jitter signal generator (not shown in the figure). In the jitter mode of the quantization circuit 1000, the jitter signal generator produces a jitter signal and provides it to the quantization unit.

[0045] Figures 4a-4b A schematic diagram of a quantization unit according to a first embodiment of the present invention is shown. The quantization circuit provided in this embodiment of the invention has a dithering mode and a normal mode. Figure 4a This diagram illustrates the application of the quantization unit 300 in jitter mode. Figure 4b A schematic diagram of the quantization unit 300 applied in normal mode is shown.

[0046] See Figure 4a The quantization unit 300 includes capacitor C11, a first capacitor group, a second capacitor group, capacitor C14, and comparator 20. The first capacitor group includes two capacitors. n-1 The first capacitor is C12, and the second capacitor group includes 2... n-1 Capacitor C13, capacitors C11 and C14 have equal capacitance values, and capacitors C12 and C13 have equal capacitance values. Specifically, capacitor C11 has a capacitance value of 1.5 times the unit capacitance C, and capacitor C12 has a capacitance value of the unit capacitance C. Comparator 20 generates an output signal DOP based on its positive input voltage op and negative input voltage om.

[0047] The first terminal of capacitor C11 is selected to be connected to the common-mode voltage cm or ground gnd. The second terminal of capacitor C11 is connected to the positive input terminal of comparator 20. The first terminal of capacitor C12 is selected to be connected to the common-mode voltage cm or the positive input signal inp. The second terminal of capacitor C12 is connected to the positive input terminal of comparator 20. The first terminal of capacitor C13 is selected to be connected to the common-mode voltage cm or the negative input signal inm. The second terminal of capacitor C13 is connected to the negative input terminal of comparator 20. The first terminal of capacitor C14 is selected to be connected to the negative reference signal refm or ground. The second terminal of capacitor C14 is connected to the negative input terminal of comparator 20. The positive input signal inp and the negative input signal inm are the differential output signals provided by adder Σ3, where refp + refm = inp + inm = 2 * cm. For example, in jitter mode, the first terminals of capacitors C11-C14 are selected to be connected to the signals via a switch controlled by the clock signal and / or jitter signal.

[0048] In the first phase of the clock signal, the first terminal of capacitor C11 is connected to the common-mode voltage cm, the first terminal of capacitor C12 is connected to the common-mode voltage cm, the first terminal of capacitor C13 is connected to the common-mode voltage cm, and the first terminal of capacitor C14 is connected to the negative reference signal refm. In the second phase of the clock signal, the first terminal of capacitor C11 is grounded at gnd, the first terminal of capacitor C12 is connected to the positive input signal inp, the first terminal of capacitor C13 is connected to the negative input signal inm, and the first terminal of capacitor C14 is grounded at gnd.

[0049] In the first phase of the clock signal, comparator 20 internally resets its positive input voltage op and negative input voltage om, making the positive input voltage op and negative input voltage om equal. When the clock signal changes from the first phase to the second phase, the change in capacitor charge is mainly reflected in the difference in voltage between the positive and negative input terminals of comparator 20, specifically:

[0050] In the first phase of the clock signal, the charge at the positive input terminal of comparator 20 is:

[0051] Q1p=(2 n-1 +1.5)C×(op1-cm)

[0052] In the first phase of the clock signal, the charge at the negative input of comparator 20 is:

[0053] Q1m=2 n-1 C×(om1-cm)+1.5C×(om1-refm)

[0054] In the second phase of the clock signal, the charge at the positive input terminal of comparator 20 is:

[0055] Q2p = 2 n-1C×(op2-inp)+1.5C×(op2-0)

[0056] In the second phase of the clock signal, the charge at the negative input of comparator 20 is:

[0057] Q2m=2 n-1 C×(om2-inm)+1.5C×(om2-0)

[0058] According to the principle of charge distribution, Q1p = Q2p, Q1m = Q2m, thus we get:

[0059] (op2-om2)-(op1-om1)=[2 n (inp-inm)-1.5(refp-refm)] / (2 n +3)=(2 n

[0060] in-1.5ref) / (2 n +3)

[0061] Where op1 represents the positive input voltage of the first phase comparator 20 of the clock signal, om1 represents the negative input voltage of the first phase comparator 20 of the clock signal, op2 represents the positive input voltage of the second phase comparator 20 of the clock signal, om2 represents the negative input voltage of the second phase comparator 20 of the clock signal, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0062] When quantization unit 300 switches from jitter mode to normal mode, see [link to relevant documentation]. Figure 4b At this point, the second capacitor bank can be considered as consisting of (2 n-1 -1) This consists of capacitor C121 and capacitor C122. The quantization unit 300 switches from jitter mode to normal mode simply by switching the voltages at the first terminals of capacitors C11, C122, and C14, keeping the first terminals of C11 and C14 constantly grounded (gnd), and selecting either the positive reference signal (refp) or the positive input signal (inp) based on the clock signal. Specifically, in the first phase of the clock signal, the first terminal of capacitor C122 is connected to the positive reference signal (refp), and in the second phase of the clock signal, the first terminal of capacitor C122 is connected to the positive input signal (inp). For example, in normal mode, the first terminals of capacitors C11-C14 select the signal to be connected via a switch controlled by the clock signal.

[0063] According to the principle of charge conservation in capacitors, in the normal mode of quantization unit 300, when the clock signal changes from the first phase to the second phase, the change in voltage difference between the positive and negative input voltages of comparator 20 is:

[0064] (op2-om2)-(op1-om1)=[2 n (inp-inm)-1.5(refp-refm)] / (2 n +3)=(2 n

[0065] in-ref) / (2 n +3)

[0066] Where op1 represents the positive input voltage of the first phase comparator 20 of the clock signal, om1 represents the negative input voltage of the first phase comparator 20 of the clock signal, op2 represents the positive input voltage of the second phase comparator 20 of the clock signal, om2 represents the negative input voltage of the second phase comparator 20 of the clock signal, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0067] In summary, the quantization unit 300 provided in this embodiment of the invention can achieve a threshold voltage of ref in normal mode and a threshold voltage of 1.5ref in jitter mode. Furthermore, it only requires the addition of two 1.5C capacitors to the quantization unit 100, saving 2 compared to the prior art quantization unit 200. n-1 The single capacitor reduces circuit cost. Furthermore, switching between jitter mode and normal mode only requires changing the connection of the first terminals of the three capacitors, thus reducing circuit complexity.

[0068] Figure 5 A schematic diagram of the quantization unit according to a second embodiment of the present invention is shown.

[0069] See Figure 4 and Figure 5 The quantization unit 300 provided in the first embodiment of the present invention has a basically the same structure as the quantization unit 400 provided in the second embodiment, the difference being that the first capacitor group of the quantization unit 400 only includes 2 n-1 - One capacitor C12, the second capacitor group only includes 2 n-1 -1 capacitor C13, therefore, the quantization unit 400 has one less capacitor C12 and one less capacitor C13 compared to the quantization unit 300.

[0070] In jitter mode, according to the principle of charge conservation, when the clock signal changes from the first phase to the second phase, the change in voltage difference between the positive and negative input voltages of comparator 20 is:

[0071] (op2-om2)-(op1-om1)=[(2 n +1)(inp-inm)-1.5(refp-refm)] / (2 n +1)

[0072] =[(2 n +1)in-1.5ref] / (2 n +1)

[0073] Where op1 represents the positive input voltage of the first phase comparator 20 of the clock signal, om1 represents the negative input voltage of the first phase comparator 20 of the clock signal, op2 represents the positive input voltage of the second phase comparator 20 of the clock signal, om2 represents the negative input voltage of the second phase comparator 20 of the clock signal, inp represents the positive input signal, inm represents the negative input signal, refp represents the positive reference signal, refm represents the negative reference signal, in represents inp-inm, and ref represents refp-refm.

[0074] Although quantization unit 400 reduces the number of capacitors by two compared to quantization unit 300, it requires more switches in actual implementation. Therefore, when the area of ​​a single switch is large, the solution of quantization unit 300 is better than that of quantization unit 400.

[0075] In addition, quantization unit 400 can also be applied to normal mode. The specific principle is the same as when quantization unit 300 is applied to normal mode, so it will not be repeated here.

[0076] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A quantization circuit for a Sigma-Delta analog-to-digital converter, comprising: An adder is used to provide differential positive and negative input signals; A quantizer includes multiple quantization units, each of which includes: The system comprises a first capacitor, a first capacitor group, a second capacitor group, a fourth capacitor, and a comparator. The first capacitor and the first capacitor group provide a positive input voltage to the comparator, and the second capacitor group and the fourth capacitor provide a negative input voltage to the comparator, so that the comparator outputs a quantized voltage. A jitter signal generation circuit is used to generate a jitter signal in the jitter mode of the quantization circuit and provide it to the quantization unit. The first capacitor group includes multiple second capacitors, the second capacitor group includes multiple third capacitors, the capacitance values ​​of the first capacitor and the fourth capacitor are equal, the capacitance values ​​of the second capacitor and the third capacitor are equal, and the capacitance value of the first capacitor is 1.5 times the capacitance value of the second capacitor. When the quantization circuit uses dithering mode The first terminal of the first capacitor is connected to either the common-mode voltage or ground, and the second terminal of the first capacitor is connected to the positive input terminal of the comparator. The first terminal of the second capacitor is connected to either a common-mode voltage or a positive input signal, and the second terminal of the second capacitor is connected to the positive input terminal of the comparator. The first terminal of the third capacitor is selectively connected to either the common-mode voltage or the negative input signal, and the second terminal of the third capacitor is connected to the negative input terminal of the comparator. The first terminal of the fourth capacitor is either connected to the negative reference signal or grounded, and the second terminal of the fourth capacitor is connected to the negative input terminal of the comparator.

2. The quantization circuit according to claim 1, wherein, When the quantization circuit uses jitter mode, the first terminals of the first to fourth capacitors select the signal to be connected via a switch, which is controlled by the jitter signal and / or a clock signal. In the first phase of the clock signal, the first terminal of the first capacitor is connected to the common-mode voltage, the first terminal of the second capacitor is connected to the common-mode voltage, the first terminal of the third capacitor is connected to the common-mode voltage, and the first terminal of the fourth capacitor is connected to the negative reference signal. In the second phase of the clock signal, the first terminal of the first capacitor is grounded, the first terminal of the second capacitor is connected to the positive input signal, the first terminal of the third capacitor is connected to the negative input signal, and the first terminal of the fourth capacitor is grounded.

3. The quantization circuit according to claim 2, wherein, The number of second capacitors in the first capacitor bank is 2. There are 1, and the number of third capacitors in the second capacitor group is 2. , where n represents the number of bits in the quantizer.

4. The quantization circuit according to claim 2, wherein, The number of second capacitors in the first capacitor bank is 2. -1, the number of third capacitors in the second capacitor group is 2. -1, where n represents the number of bits in the quantizer.

5. The quantization circuit according to claim 2, wherein, The quantization circuit switches between the jitter mode and the normal mode by changing the connection method of the first capacitor, the fourth capacitor, and the first terminal of one of the second capacitors of the quantization unit.

6. The quantization circuit according to claim 5, wherein, When the quantization circuit adopts the normal mode, the first terminals of the first capacitor and the fourth capacitor are always grounded, and the first terminal of one of the second capacitors in the second capacitor group is selectively connected to either a positive reference signal or a positive input signal. The first terminal of the first to fourth capacitors is selected by a switch to connect to the signal. The switch is controlled by the clock signal. In the first phase of the clock signal, a positive reference voltage is connected to the first terminal of one of the second capacitors, and in the second phase of the clock signal, a positive input signal is connected to the first terminal of one of the second capacitors.

7. The quantization circuit according to claim 6, wherein, The average value of the positive reference signal and the negative reference signal is equal to the average value of the positive input signal and the negative input signal, and the common-mode voltage is the average value of the positive reference signal and the negative reference signal.

8. A Sigma-Delta analog-to-digital converter, comprising a Sigma-Delta modulator, said Sigma-Delta modulator comprising: Cascaded multi-stage modulation circuits; as well as The quantization circuit as described in any one of claims 1-7.

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