Data type conversion module, processor, equipment and method

Abstract

The invention discloses a data type conversion module, a processor, equipment and a method, and relates to the technical field of chips. The data type conversion module comprises an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding negation circuit, an exponent bit generation circuit and an output selection circuit. The input selection circuit and the shift data generation circuit are used for correspondingly generating first data used for shifting and data needing to be used and referenced in the data type conversion process according to different data type conversion conditions. A subsequent circuit can generate output data of which the data type conversion is completed based on the data. The data type conversion module can be used for converting data among various different data types, so that a function of converting different data types by using the shared shift circuit and the rounding negation circuit is realized, hardware resources are saved, and the size of a processor chip is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of chip technology, and in particular to a data type conversion module, processor, device, and method. Background Art

[0002] Converting data to different data types is a basic data processing operation in the field of artificial intelligence. Therefore, in AI (Artificial Intelligence) processors, data type conversion circuits are often integrated to perform the above conversion operations.

[0003] In response to different data type conversion situations, in related technologies, multiple sets of different and independent circuits are often designed in the AI ​​processor to enable data to be converted between multiple data types. For example, in response to the two situations of converting single-precision floating-point numbers to half-precision floating-point numbers and converting single-precision floating-point numbers to integer numbers, two sets of independent circuits are designed in the AI ​​processor to perform the above two different conversion operations.

[0004] However, the above solution requires stacking corresponding hardware computing resources for each set of data type conversion circuits in the processor chip, resulting in a waste of hardware resources and an expansion of the chip size. Summary of the invention

[0005] The embodiment of the present application provides a data type conversion module, processor, device and method. The technical solution provided by the embodiment of the present application is as follows:

[0006] According to one aspect of an embodiment of the present application, there is provided a data type conversion module applied to a processor, the data type conversion module comprising: an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding circuit, an exponent bit generation circuit, and an output selection circuit;

[0007] The input selection circuit is used to determine first data according to input data and a data type of the input data, wherein the first data is used for shift processing;

[0008] The shift data generating circuit is used to generate shift direction information, shift quantity information and leading zero information according to the input data, the data type of the input data and the conversion type information, wherein the conversion type information is used to indicate whether to convert the input data between two data types, the shift direction information is used to indicate the shift direction corresponding to the first data, the shift quantity information is used to indicate the number of bits to shift the first data, and the leading zero information is used to indicate the number of leading zeros of the first data;

[0009] The shift circuit is used to shift the first data according to the shift quantity information to obtain the shifted first data;

[0010] The shift selection circuit is used to select second data from the shifted first data according to the shift direction information, where the second data is obtained by shifting the first data according to the shift direction corresponding to the first data;

[0011] The rounding circuit is used to perform inversion and addition processing on the second data according to the conversion type information to obtain third data;

[0012] The exponent bit generating circuit is used to generate exponent bit data according to the shift direction information, the leading 0 information, the input data, the data type of the input data and the conversion type information; wherein the exponent bit data is used to indicate the exponent bit of the output data when the data type of the output data is a floating point number;

[0013] The output selection circuit is used to determine the output data according to the third data, the exponent bit data, the sign bit of the input data and the data type of the output data.

[0014] According to one aspect of an embodiment of the present application, a processor is provided, wherein the processor includes the data type conversion module as described above.

[0015] According to one aspect of an embodiment of the present application, a computer device is provided, the computer device comprising a processor, and the processor comprising the data type conversion module as described above.

[0016] According to one aspect of an embodiment of the present application, a data type conversion method based on a data type conversion module is provided, wherein the data type conversion module comprises: an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding circuit, an exponent bit generation circuit, and an output selection circuit; the method comprises:

[0017] The input selection circuit determines first data according to input data and a data type of the input data, wherein the first data is used for shift processing;

[0018] The shift data generating circuit generates shift direction information, shift quantity information and leading zero information according to the input data, the data type of the input data and the conversion type information, wherein the conversion type information is used to indicate whether to convert the input data between two data types, the shift direction information is used to indicate the shift direction corresponding to the first data, the shift quantity information is used to indicate the number of bits to shift the first data, and the leading zero information is used to indicate the number of leading zeros of the first data;

[0019] The shift circuit shifts the first data according to the shift quantity information to obtain the shifted first data;

[0020] The shift selection circuit selects second data from the shifted first data according to the shift direction information, where the second data is obtained by shifting the first data according to the shift direction corresponding to the first data;

[0021] The rounding circuit performs inversion and addition processing on the second data according to the conversion type information to obtain third data;

[0022] The exponent bit generating circuit generates exponent bit data according to the shift direction information, the leading 0 information, the input data, the data type of the input data and the conversion type information; wherein the exponent bit data is used to indicate the exponent bit of the output data when the data type of the output data is a floating point number;

[0023] The output selection circuit determines the output data according to the third data, the exponent bit data, the sign bit of the input data, and the data type of the output data.

[0024] The technical solution provided by the embodiments of the present application includes at least the following beneficial effects:

[0025] The data type conversion module is designed to include an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding circuit, an exponent bit generation circuit, and an output selection circuit. The input selection circuit can determine the first data for shift processing according to the input data and the data type of the input data. The shift data generation circuit can generate data that needs to be used and referenced in the data type conversion process according to the input data, the data type of the input data, and the conversion type information. The shift circuit can shift the first data according to the shift quantity information generated by the shift data generation circuit. The shift selection circuit can select the corresponding second data from the shifted first data according to the shift direction information generated by the shift data generation circuit. The rounding circuit can perform subsequent processing of shift operations such as inversion and addition on the second data. The exponent bit generation circuit can generate the exponent bit corresponding to the floating point number when the output data is a floating point number. The input selection circuit can finally obtain the output data after the data type conversion is completed according to the data determined by the above circuits. The data type conversion module can be used to convert data between a variety of different data types, and realizes the use of shared shift circuits and rounding circuits to achieve different data type conversion functions, saving hardware resources and reducing the size of the processor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a hardware structure diagram of a processor for data type conversion provided by an embodiment of the present application;

[0027] Figure 2 is a schematic diagram of a data type conversion module applied to a processor provided by an embodiment of the present application;

[0028] Figure 3 is a schematic diagram of an input selection circuit provided by an embodiment of the present application;

[0029] Figure 4 is a schematic diagram of a left-shift data generation circuit provided by an embodiment of the present application;

[0030] Figure 5 is a schematic diagram of a right-shift data generation circuit provided by an embodiment of the present application;

[0031] Figure 6 is a schematic diagram of a rounding circuit provided by an embodiment of the present application;

[0032] Figure 7 is a schematic diagram of an exponent bit generation circuit provided by an embodiment of the present application;

[0033] Figure 8 It is a flowchart of a data type conversion method based on a data type conversion module provided by an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0035] Artificial intelligence is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that machines have the functions of perception, reasoning and decision-making.

[0036] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. Basic artificial intelligence technologies generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, pre-trained models are also called large models and basic models. After fine-tuning, they can be widely used in downstream tasks in various major directions of artificial intelligence. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0037] With the research and advancement of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless cars, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (AI Generated Content, AIGC), conversational interaction, smart medical care, smart customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0038] The technical solution of this application mainly relates to the development and design of AI processors in artificial intelligence technology, and mainly to data type conversion modules applied to processors.

[0039] The data type conversion operation performed on data, also known as the precision conversion operation, is a basic data processing operation in the field of artificial intelligence. Especially when it comes to quantization and dequantization steps, it is particularly important to be able to quickly convert different data types. Therefore, in AI processor chips, floating-point and fixed-point precision conversion circuits are often integrated in the vector processing unit to support precision conversion operations on vector data, thereby improving the performance of precision conversion instructions.

[0040] The data type conversion operation (i.e., precision conversion operation) involved in the embodiments of the present application may include fixed-point to floating-point, floating-point to fixed-point, and conversion between floating-point types of different precisions. Further, taking the three data types of single-precision floating point (Full Precise Float Point, FP32), half-precision floating point (Half Precision Floating Point, FP16) and signed 32-bit integer (32bit integer, int32) as examples, they may correspond to the following 6 different data type conversion situations.

[0041] 1. Convert from single-precision floating-point type to signed 32-bit integer type.

[0042] 2. Convert half-precision floating point data to signed 32-bit integer data.

[0043] 3. Convert a signed 32-bit integer to a single-precision floating point.

[0044] 4. Convert a signed 32-bit integer to a half-precision floating point.

[0045] 5. Convert from single-precision floating point to half-precision floating point.

[0046] 6. Convert from half-precision floating point to single-precision floating point.

[0047] In the related art, for the above six different data type conversion situations, six separate precision conversion circuits are designed in the processor chip. However, the above six separate circuits have similar structures (such as circuits for performing shift operations), and there is a large space for optimizing shared hardware resources.

[0048] This application uses a unified shared circuit to replace the above 6 sets of separate precision conversion circuits through the optimization method of circuit resource sharing, which can reduce the hardware resource usage of the processor, effectively control the chip size, and thus improve the product competitiveness of the processor chip.

[0049] Please refer to Figure 1 , which shows a hardware structure diagram of a processor for data type conversion provided by an embodiment of the present application. The processor includes an instruction decoder, a data type conversion module, a data load storage execution unit (Load Store Unit) and a memory (Buffer).

[0050] The instruction parser is used to parse the operation instructions received by the processor. In the embodiment of the present application, the instruction parser is used to parse the data type conversion (precision conversion) instruction. The memory is used to store the data to be converted, and the data load storage execution unit is used to obtain the data to be converted from the memory and return the data after the data type conversion is completed to the memory.

[0051] The data type conversion module is used to perform data type conversion on the data to be converted according to the data type conversion instruction obtained by parsing the instruction parser. In some embodiments, the data type conversion module can convert the data type of the data to be converted from floating point type to integer type, or from integer type to floating point type, or convert the data type of the data to be converted between floating point types of different precisions. For the specific structure of the data type conversion module, please refer to the embodiments below, which will not be described here.

[0052] Based on the above hardware structure design, data can be converted between multiple data types.

[0053] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor may be implemented in at least one of the following hardware forms: DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI processor for processing computing operations related to machine learning.

[0054] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory is used to store a computer program, which is configured to be executed by one or more processors to implement the data type conversion method based on the above-mentioned data type conversion module.

[0055] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the computer device, and may include more or less components than shown in the figure, or combine some components, or adopt a different component arrangement.

[0056] Please refer to Figure 2 , which shows a schematic diagram of a data type conversion module applied to a processor provided by an embodiment of the present application. The data type conversion module can be a unit of a pure hardware structure, which can be set on the chip of the processor. The data type conversion module includes: an input selection circuit 10, a shift data generation circuit 20, a shift circuit 30, a shift selection circuit 40, a rounding circuit 50, an exponent bit generation circuit 60 and an output selection circuit 70.

[0057] The input selection circuit 10 is used to determine first data according to input data and the data type of the input data, and the first data is used for shift processing.

[0058] Input data refers to data used by the input data type conversion module for data type conversion, that is, the data to be converted in the above embodiment. The data type of the input data may include single-precision floating point, half-precision floating point, and signed 32-bit integer data types.

[0059] For example, please refer to Figure 3 , the input port signal of the input selection circuit 10 may include 32-bit input data din[31:0], and two data type indication signals din_is_f32 and din_is_s32. Among them, when din_is_f32 is 1, it indicates that the data type of the input data is a single-precision floating point type. When din_is_f32 is 0, it indicates that the data type of the input data is not a single-precision floating point type. When din_is_s32 is 1, it indicates that the data type of the input data is a (signed) 32-bit integer. When din_is_s32 is 0, it indicates that the data type of the input data is not a 32-bit integer. The output port signal of the input selection circuit 10 may include the first data x[31:0].

[0060] In addition, it should be noted that in the embodiments of the present application, for the convenience of explanation, the data from bit b to bit a is represented in the form of [a:b], where a and b are both integers greater than or equal to 0. For example, for 32-bit input data din, din[31:0] can represent the complete input data, and din[23:0] represents the 0th bit (the 1st bit) to the 23rd bit (the 24th bit) of the input data. Similarly, for a certain bit of data, the present application represents it in the form of [c], where c is an integer greater than or equal to 0. For example, for 32-bit input data din, din[0] represents the 0th bit (i.e., the first bit) of the input data. In addition, the present application also represents m-bit binary data with a value of n as m'bn, where m and n are both integers greater than or equal to 0. For example, 2'b0 is 00, and 1'b1 is 1. Further, in the embodiments of the present application, splicing between data can be represented in the form of {A,B}, where A and B are the spliced ​​data. For example, {2'b0,din[23:0]} concatenates 00 with the lower 23 bits of the input data.

[0061] In some embodiments, please refer to Figure 3 The input selection circuit 10 includes: an integer data processing circuit, a floating point data processing circuit and a third selection circuit.

[0062] The integer data processing circuit is used for converting the input data into an absolute value form to obtain integer input data.

[0063] In some embodiments, the integer data processing circuit is used to determine the input data as integer input data when the sign bit of the input data is 0.

[0064] In some embodiments, the integer data processing circuit is used to, when the sign bit of the input data is 1, invert the input data and then add 1 to obtain the integer input data.

[0065] In the embodiment of the present application, a data sign bit of 0 may also be expressed as positive data, and a data sign bit of 1 may also be expressed as negative data.

[0066] To negate data means to negate the value of each bit of the data. For example, negating the data 101 will give the data 010. For integer input data, when the sign bit of the input data is 1, that is, the input data is negative, the input data needs to be negated and added with one to be converted into an absolute value.

[0067] The function of the integer data processing circuit is to convert the input data into an absolute value form for shifting when the data type of the input data is an integer. An integer number is composed of a value bit and a sign bit. For 32-bit integer data, in some embodiments, the highest bit is the sign bit and the lower 31 bits are the value bits. In other embodiments, the highest 17 bits are the sign bit and the lower 15 bits are the value bits.

[0068] In some embodiments, please refer to Figure 3 , when the data type of the input data is a 32-bit integer, the highest bit din

[31] (i.e., the 32nd bit) of the input data can be used as the sign bit. The above integer data processing circuit can include two selectors, which are respectively used to select whether to invert the input data and whether to add 1 to the input data. The above selection logic can be expressed by the following formula: integer input data s[31:0]=din

[31] ? ~din[31:0]+1:din[31:0]. That is, first determine whether the sign bit din

[31] is 1. If it is 1, then ~din[31:0]+1 is selected as the integer input data. If it is 0, then din[31:0] is selected as the integer input data. Among them, "?" is the selection symbol. When the value on the left of "?" is 1, the data before the ":" symbol is selected. When the value on the left of "?" is 0, the data after the ":" symbol is selected. "~" is the inversion symbol, indicating that the data after "~" is inverted.

[0069] The floating point data processing circuit is used to perform mantissa processing on the input data according to the data type of the input data to obtain mantissa input data.

[0070] In order from the highest bit to the lowest bit, a floating point number consists of a sign bit, an exponent bit (also called an exponent code or exponent bit), and a mantissa bit (also called a decimal point). For a single-precision floating point number, in order from the highest bit to the lowest bit, it includes 1 sign bit, 8 exponent bits, and 23 mantissa bits. For a half-precision floating point number, in order from the highest bit to the lowest bit, it includes 1 sign bit, 5 exponent bits, and 10 mantissa bits. In addition, when a half-precision floating point number is represented by 32 bits, it can be regarded as the upper 17 bits as the sign bit, and the number of exponent bits and mantissa bits remains unchanged.

[0071] In some embodiments, the floating point data processing circuit is used to concatenate 1 with the lower 23 bits of the input data to obtain mantissa input data when the data type of the input data is a single precision floating point type.

[0072] In some embodiments, the floating point data processing circuit is used to concatenate 1 with the lower 10 bits of the input data to obtain mantissa input data when the data type of the input data is not a single precision floating point type.

[0073] The function of the floating point data processing circuit is to extract the mantissa of the input data when the data type of the input data is a floating point type, and to splice the hidden bit 1 as the second data for shifting. In the current floating point number standard, a floating point number can be represented by F=(-1) s ×2 E ×1.f, where s is the value of the floating point sign bit, E is related to the exponent bit of the floating point number, f is the mantissa bit of the floating point number, and the 1 in 1.f is the hidden bit omitted in the actual representation of the floating point number. Before the shift is performed, the present application adds the hidden bit 1 back to ensure the integrity of the floating point value.

[0074] In some embodiments, please refer to Figure 3 The floating-point data processing circuit may include a selector for selecting floating-point input data. The selection logic of the selector may be expressed by the following formula: floating-point input data f[31:0]=din_is_f32?{8'b0,1'b1,din[22:0]}:{21'b0,1'b1,din[9:0]}. That is, when din_is_f32 is 1, {8'b0,1'b1,din[22:0]} is selected as the floating-point input data, and when din_is_f32 is 0, {21'b0,1'b1,din[9:0]} is selected as the floating-point input data, wherein 8'b0 is 0 represented by 8 bits of binary, 1'b1 is 1 represented by 1 bit of binary, and {8'b0,1'b1,din[22:0]} is the result of concatenating 1 with the lower 23 bits of the input data. 21'b0 is 0 represented by 21 bits in binary, and {21'b0,1'b1,din[9:0]} is the result of concatenating 1 with the lower 10 bits of the input data.

[0075] The third selection circuit is used to select one of the integer input data and the mantissa input data as the first data according to the data type of the input data.

[0076] In some embodiments, the third selection circuit is used to determine the integer input data as the first data when the data type of the input data is an integer.

[0077] In some embodiments, the third selection circuit is used to determine the mantissa input data as the first data when the data type of the input data is not an integer.

[0078] In some embodiments, please refer to Figure 3The third selection circuit may include a selector, the selector being used to select the first data x[31:0] from the integer input data s[31:0] and the mantissa input data f[31:0]. The selection logic of the selector may be expressed by the following formula: first data x[31:0]=din_is_s32?s[31:0]:f[31:0]. That is, when din_is_s32 is equal to 1, s[31:0] is selected as the first data, and when din_is_s32 is equal to 0, f[31:0] is selected as the first data.

[0079] Please refer to Figure 2 After the input selection circuit determines the first data x[31:0], it will be provided to the shift circuit 30 for shifting.

[0080] In summary, the input selection circuit 10 can determine the corresponding first data according to different data types of the input data, so that the data type conversion module can be used to convert data between a variety of different data types.

[0081] The shift data generating circuit 20 is used to generate shift direction information, shift quantity information and leading 0 information according to input data, data type of the input data and conversion type information.

[0082] The conversion type information is used to indicate whether to convert the input data between two data types. For example, it can indicate whether to convert the input data from a 32-bit integer to a single-precision floating point, or whether to convert the input data from a single-precision floating point to a 32-bit integer.

[0083] The shift direction information is used to indicate the shift direction corresponding to the first data, the shift quantity information is used to indicate the number of bits to be shifted for the first data, and the leading 0 information is used to indicate the number of leading 0s of the first data. The leading 0 of the data refers to the 0 from the highest bit of the data to the 0 before the first 1 for binary data. For example, for the data 0010, the number of leading 0s is 2. In addition, it should be noted that the leading 0 information does not necessarily indicate the number of leading 0s of the complete first data, and the leading 0 information can also be used to indicate the number of leading 0s of some bits of the first data.

[0084] Please refer to Figure 2 In some embodiments, the shift data generating circuit 20 includes: a left shift data generating circuit and a right shift data generating circuit, the shift quantity information includes left shift quantity information and right shift quantity information, and the leading 0 information includes left shift leading 0 information and right shift leading 0 information.

[0085] The left shift quantity information is used to indicate the number of bits to be left-shifted for the first data, the right shift quantity information is used to indicate the number of bits to be right-shifted for the first data, the left shift leading 0 information and the right shift leading 0 information are respectively used to indicate the number of leading 0s in different parts of the first data.

[0086] The left shift data generating circuit is used to generate left shift quantity information and left shift leading 0 information according to input data and conversion type information.

[0087] For example, please refer to Figure 4 , the input port signal of the left shift data generation circuit may include 32-bit input data din[31:0], and four conversion type information fp_to_s32, s32_to_f16, s32_to_f32 and f32_to_s32. When fp_to_s32 is 1, it indicates that the data type of the input data is converted from floating point to 32-bit integer. When fp_to_s32 is 0, it indicates that the data type of the input data is not converted from floating point to 32-bit integer. When s32_to_f16 is 1, it indicates that the data type of the input data is converted from 32-bit integer to half-precision floating point. When s32_to_f16 is 0, it indicates that the data type of the input data is not converted from 32-bit integer to half-precision floating point. When s32_to_f32 is 1, it indicates that the data type of the input data is converted from a 32-bit integer to a single-precision floating point type, and when s32_to_f32 is 0, it indicates that the data type of the input data is not converted from a 32-bit integer to a single-precision floating point type. When f32_to_s32 is 1, it indicates that the data type of the input data is converted from a single-precision floating point type to a 32-bit integer, and when f32_to_s32 is 0, it indicates that the data type of the input data is not converted from a single-precision floating point type to a 32-bit integer. The output port signal of the left-shift data generation circuit may include left-shift quantity information L[4:0] and left-shift leading 0 information L0[4:0].

[0088] In some embodiments, please refer to Figure 4 The left-shift data generation circuit includes: a first detection circuit, a second detection circuit, a left-shift number generation circuit and a first selection circuit.

[0089] The first detection circuit is used to obtain first leading 0 information according to the lower 24 bits of the input data.

[0090] The first leading 0 information is used to indicate the number of leading 0s in the absolute value of the lower 24 bits of the input data. When the data type of the input data is converted from a 32-bit integer to a single-precision floating point, if the absolute value of the input data is less than 2 to the power of 24, the first data needs to be left shifted. At this time, the number of leading 0s in the lower 24 bits of the input data is the corresponding number of left shifts.

[0091] In some embodiments, the first detection circuit is used to perform leading 0 detection on the lower 24 bits of the inverted input data when the sign bit of the input data is 1, so as to obtain first leading 0 information.

[0092] In some embodiments, the first detection circuit is used to perform leading 0 detection on the lower 24 bits of the input data when the sign bit of the input data is 0, so as to obtain first leading 0 information.

[0093] For example, please refer to Figure 4 , the first detection circuit may include a selector and a 24-bit leading 0 detection unit. The selector is used to select whether to invert the lower 24 bits din[23:0] of the input data according to the sign bit din

[31] of the input data. The 24-bit leading 0 detection unit is used to perform leading 0 detection on the data abs1[23:0] output by the selector to obtain the first leading 0 information L1[5:0]. It should be noted that, in some embodiments, for the leading 0 information, its highest bit can be used to indicate whether all bits of the detected data are all 0. In this case, the highest bit can be called the all-zero bit of the leading 0 information. The all-zero bit is 1, indicating that the detected data is all 0, and the all-zero bit is 0, indicating that the detected data is not all 0. For example, if L1[5:0]=1XXXXX, it indicates that the lower 24 bits of the input data are all 0, where X is 0 or 1. If L1[5:0]=000001, it indicates that the lower 24 bits of the input data have a leading 0.

[0094] The second detection circuit is used to obtain second leading 0 information according to the lower 11 bits of the input data.

[0095] The second leading 0 information is used to indicate the number of leading 0s in the absolute value of the lower 11 bits of the input data. When the data type of the input data is converted from a 32-bit integer to a half-precision floating point, if the absolute value of the input data is less than 2 to the 11th power, the first data needs to be shifted left. Alternatively, when the data type of the input data is converted from a half-precision floating point to a single-precision floating point, if the input data is a non-standard floating point number with all exponent bits being 0, the first data needs to be shifted left. In the above two cases, the number of leading 0s in the lower 11 bits of the input data is the corresponding number of left shifts.

[0096] In some embodiments, the second detection circuit is used to perform leading 0 detection on the lower 11 bits of the inverted input data when the data type of the input data is converted from a 32-bit integer to a half-precision floating point and the sign bit of the input data is 1, to obtain second leading 0 information.

[0097] In some embodiments, the second detection circuit is used to perform leading 0 detection on the lower 10 bits of the input data after splicing with 0 without converting the data type of the input data from a 32-bit integer to a half-precision floating point, or the sign bit of the input data is not 0, to obtain second leading 0 information.

[0098] It should be noted that in the above scheme, 0 is concatenated with the lower 10 bits of the input data in order to simulate that the input data is a non-standard half-precision floating point number, that is, the hidden bit of the mantissa of the input data is set to 0. In other embodiments, the second detection circuit may not concatenate 0 with the lower 10 bits of the input data, and adopt the same structure as the first detection circuit to directly perform leading 0 detection on the lower 11 bits of the input data.

[0099] For example, please refer to Figure 4 The second detection circuit may include a selector and an 11-bit leading 0 detection unit. The selector is used to select 11-bit data abs2[10:0] for leading 0 detection from the lower 11 bits of the inverted input data ~din[10:0] and the lower 10 bits of the input data concatenated with 0 {1'b0,din[9:0]} according to the sign bit din

[15] of the input data (at this time, the input data din[31:15] can be regarded as the sign bit) and the conversion type information s32_to_f16. The 11-bit leading 0 detection unit is used to perform leading 0 detection on the data abs2[10:0] output by the selector to obtain the second leading 0 information L2[4:0].

[0100] A left shift bit number generating circuit is used to generate first quantity information based on the upper 8 bits of the input data except the sign bit. The first quantity information is used to indicate the number of bits of the first data left shifted when the data type of the input data is converted from a single-precision floating point type to a 32-bit integer type and the absolute value of the input data is greater than 2 to the power of 24.

[0101] The left shift bit number generating circuit is also used to generate second quantity information based on the upper 5 bits of the input data except the sign bit. The second quantity information is used to indicate the number of bits of the first data left shifted when the data type of the input data is converted from a half-precision floating point type to a 32-bit integer type and the absolute value of the input data is greater than 2 to the 11th power.

[0102] For example, please refer to Figure 4The left shift number generation circuit may include two left shift number generation units. The two left shift number generation units are respectively used to: generate the first quantity information Lm1[4:0] according to the high 8 bits din[30:23] of the input data excluding the sign bit (when the input data is a single-precision floating point type, for 32-bit input data, the sign bit is din

[31] ). Generate the second quantity information Lm2[3:0] according to the high 5 bits din[14:10] of the input data excluding the sign bit (when the input data is a half-precision floating point type, for 32-bit input data, the sign bit is din[31:15]).

[0103] Further, the first quantity information generating unit may calculate the first quantity information by the following formula: Lm1[4:0]=(din[30:23]-127)-24. The second quantity information generating unit may calculate the second quantity information by the following formula: Lm2[3:0]=(din[14:10]-15)-11.

[0104] The first selection circuit is used to select one of the first leading 0 information and the second leading 0 information as the left-shifted leading 0 information according to the conversion type information.

[0105] In some embodiments, the first selection circuit is used to determine the first leading 0 information as left-shifted leading 0 information when the data type of the input data is converted from a 32-bit integer to a single-precision floating point.

[0106] In some embodiments, the first selection circuit is used to determine the second leading 0 information as left-shifted leading 0 information without converting the data type of the input data from a 32-bit integer to a single-precision floating point.

[0107] The first selection circuit is further used to select one of the left-shift leading 0 information, the first quantity data and the second quantity data as the left-shift quantity information according to the conversion type information.

[0108] In some embodiments, the first selection circuit is further configured to determine the first quantity information as the first intermediate information when a data type of the input data is converted from a single-precision floating point type to a 32-bit integer type.

[0109] In some embodiments, the first selection circuit is further configured to determine the second quantity information as the first intermediate information without converting the data type of the input data from a single-precision floating point type to a 32-bit integer type.

[0110] In some embodiments, the first selection circuit is further configured to determine the first intermediate information as left shift amount information when the data type of the input data is converted from a floating point type to a 32-bit integer type.

[0111] In some embodiments, the first selection circuit is further configured to determine the left shift leading 0 information as the left shift amount information without converting the data type of the input data from a floating point type to a 32-bit integer type.

[0112] For example, please refer to Figure 4 The first selection circuit may include three selectors, which are respectively used to: select the left-shifted leading 0 information L0[4:0] from the first leading 0 information L1[5:0] and the second leading 0 information L2[4:0] according to the conversion type information s32_to_f32 (when s32_to_f16 is 1, select L1[4:0], when s32_to_f16 is 0, select {1'b0, L2[3:0]}). Select the left-shifted intermediate information Lz1[4:0] from the first quantity information Lm1[4:0] and the second quantity information Lm2[3:0] according to the conversion type information f32_to_s32 (when f32_to_s32 is 1, select Lm1[4:0], when f32_to_s32 is 0, select {1'b0, Lm2[3:0]}). According to the conversion type information fp_to_s32, the left shift amount information L[4:0] is selected from the left shift leading 0 information L0[4:0] and the left shift middle information Lz1[4:0] (when fp_to_s32 is 1, select Lz1[4:0], when fp_to_s32 is 0, select L0[4:0]).

[0113] Please refer to Figure 2 After the left shift data generation circuit generates the left shift leading 0 information L0[4:0], it will be provided to the exponent bit generation circuit 60 to generate the output data exponent bit. After the left shift data generation circuit generates the left shift quantity information L[4:0], it will be provided to the left shift circuit included in the shift circuit 30 for shifting.

[0114] It can be seen that the left-shift data generation circuit can generate corresponding left-shift quantity information and left-shift leading 0 information according to the conversion type information and for various different needs to left-shift the first data, thereby enabling the data type conversion module to be used to convert data between various different data types.

[0115] The right shift data generating circuit is used to generate right shift quantity information, right shift leading 0 information and shift direction information according to input data, data type of the input data and conversion type information.

[0116] For example, please refer to Figure 5The input port signal of the right shift data generation circuit includes the partial bit number of the input data din[31:23] and din[15:10], two data type indication signals din_is_f32 and din_is_s32, and two conversion type information s32_to_f32 and f32_to_s32. The output port signal of the right shift data generation circuit includes the right shift quantity information R[4:0], the right shift leading 0 information R0[4:0] and the shift direction information sel.

[0117] In some embodiments, please refer to Figure 5 The right shift data generating circuit includes: a third detection circuit, a fourth detection circuit, a right shift number generating circuit, a second selection circuit and a direction determining circuit ( Figure 5 not shown).

[0118] The third detection circuit is used to obtain third leading 0 information and third quantity information according to the upper 8 bits of the input data except the sign bit, wherein the third quantity information is used to indicate the number of bits of the first data right shifted when the data type of the input data is converted from a 32-bit integer to a single-precision floating point type and the absolute value of the input data is not less than 2 to the power of 24 (i.e., the most significant bit of the absolute value of the input data needs to be right shifted to the 24th bit). The third leading 0 information is used to indicate the number of leading 0s of the absolute value of the upper 8 bits of the input data except the sign bit.

[0119] In some embodiments, the third detection circuit is used to perform a leading 0 detection on the upper 8 bits of the inverted input data except the sign bit when the sign bit of the input data is 1, to obtain the third leading 0 information. Alternatively, when the sign bit of the input data is 0, the leading 0 detection is performed on the upper 8 bits of the input data except the sign bit, to obtain the third leading 0 information. Further, the third detection circuit is also used to invert the third leading 0 information to obtain the third quantity information.

[0120] For example, please refer to Figure 5 The third detection circuit may include a selector and an 8-bit leading 0 detection and inversion unit. The selector is used to select whether to invert the high 8 bits din[30:23] of the input data except the sign bit according to the sign bit din

[31] of the input data. The selection logic of the selector can be expressed by the following formula: abs3[7:0]=din

[31] ? ~din[30:23]:din[30:23]. The 8-bit leading 0 detection and inversion unit is used to perform leading 0 detection on the 8-bit data abs3[7:0] output by the selector to obtain the third leading 0 information. And the third leading 0 information is inverted to obtain the third quantity information Rm1[2:0].

[0121] In the embodiment of the present application, when the input data is negative, each detection circuit directly inverts part of the bits of the first data and then performs a leading 0 detection. It is not necessary to invert the first data and add 1 to convert it into a correct absolute value form. The addition operation in the leading 0 detection process is removed, thereby reducing the timing of the entire data type conversion module, so that the module can operate at a higher frequency.

[0122] In addition, it should be noted that, since the embodiment of the present application removes the addition operation in the leading 0 detection process, the generated leading 0 information may have a 1-bit error. For example, 110 is negated to 001, and the number of leading 0s is 2, while the correct value of its absolute value is 010, and the number of leading 0s is 1. At this time, the leading 0 information has an error. In the data type conversion module, the shift circuit 30 can detect the error, and the exponent bit generation circuit 60 can eliminate the error, which will be further introduced in the following embodiments.

[0123] In some embodiments, the 8-bit leading 0 detection and inversion unit can obtain the third leading 0 information and the third quantity information through the following steps.

[0124] 1. For 8-bit data abs3[7:0], two leading 0 information and two all-zero information are generated with each two bits as a group. The two leading 0 information are used to indicate the number of leading 0s for each two bits, and the two all-zero information are used to indicate whether each two bits are all 0.

[0125] Two leading zero information lzd1[3:0]={abs3[7],abs3[5],abs3[3],abs3[1]}, two all-zero information all1[3:0]={(abs3[7:6]==2'b0),(abs3[5:4]==2'b0),(abs3[3:2]==2'b0),(abs3[1:0]==2'b0)}. Among them, == is the judgment symbol. When the left side of the symbol == is equal to the right side, the value of the corresponding formula is 1, otherwise the value is 0.

[0126] 2. For the 8-bit data abs3[7:0], four bits of leading 0 information and four bits of all-zero information are generated with each four bits as a group. The four bits of leading 0 information are used to indicate the number of leading 0s in each four bits, and the four bits of all-zero information are used to indicate whether each four bits are all 0.

[0127] Four-bit leading zero information lzd2[3:0]={all1[3]?{1'b1,lzd1[2]}:{1'b0,lzd1[3]},all1[1]?{1'b1,lzd1[0]}:{1'b0,lzd1[1]}}, four-bit all-zero information all2[1:0]={all1[3]&all1[2],all1[2]&all1[1]}, where & is an AND operator.

[0128] 3. According to the four bits of leading 0 information and the four bits of all-zero information, the third leading 0 information is obtained.

[0129] The third leading zero information R1[2:0]={all2[1]?{1'b1,lzd2[1:0]}:{1'b0,lzd2[3:2]}}.

[0130] 4. Invert the third leading 0 information to obtain the third quantity information Rm1[2:0].

[0131] That is, Rm1[2:0]=~R1[2:0].

[0132] In some embodiments, all-zero information all0 can be obtained based on four-bit all-zero information, alll0=all2[1]&all2[0], and all0 can be spliced ​​before the third leading 0 information as the all-zero bit of the third leading 0 information to indicate whether the 8-bit data abs3[7:0] is all 0.

[0133] The fourth detection circuit is used to obtain fourth leading 0 information and fourth quantity information based on the upper 4 bits of the input data except the sign bit. The fourth quantity information is used to indicate the number of bits of the first data to be right shifted when the data type of the input data is converted from a 32-bit integer to a half-precision floating point and the absolute value of the input data is not less than 2 to the 11th power (that is, the most significant bit of the absolute value of the input data needs to be right shifted to the 11th bit).

[0134] In some embodiments, the fourth detection circuit is used to perform a leading 0 detection on the upper 4 bits of the inverted input data except the sign bit when the sign bit of the input data is 1, to obtain fourth leading 0 information. Alternatively, when the sign bit of the input data is 0, the leading 0 detection is performed on the upper 4 bits of the input data except the sign bit, to obtain fourth leading 0 information. Further, the fourth detection circuit is also used to invert the fourth leading 0 information to obtain fourth quantity information.

[0135] For example, please refer to Figure 5, the fourth detection circuit may include a selector and a 4-bit leading 0 detection and inversion unit. The selector is used to select whether to invert the high 4 bits din[14:11] of the input data except the sign bit according to the sign bit din

[15] of the input data (at this time, only the case where the value of the input data does not overflow the numerical range of the half-precision floating point type is considered, that is, the sign bit of the input data is din[31:15], and the numerical bit is din[14:0]). The 4-bit leading 0 detection and inversion unit is used to perform leading 0 detection on the 4-bit data abs4[3:0] output by the selector to obtain the fourth leading 0 information. And the fourth leading 0 information is inverted to obtain the fourth quantity information Rm2[1:0].

[0136] In addition, it should be noted that, since the half-precision floating-point data has 5 exponent bits, and the fourth detection circuit uses 4 leading 0 detection, after the fourth leading 0 information is inverted to obtain the fourth quantity information, the fourth quantity information can be added by 1 to obtain the correct shift number to avoid shift errors. Alternatively, when the right shift circuit in the shift circuit 30 performs shifting according to the right shift quantity information, when the data type of the input data is converted from a 32-bit integer to a half-precision floating point, an additional one bit can be shifted to avoid shift errors.

[0137] a right shift bit number generating circuit, used for generating fifth number information according to the upper 8 bits of the input data except the sign bit, the fifth number information being used for indicating the number of bits of the first data to be right shifted when the data type of the input data is converted from a single-precision floating point type to a half-precision floating point type;

[0138] When converting the data type of input data from single-precision floating point to half-precision floating point, the first data will not be left-shifted. There are two cases of right-shifting: one is that the value of the input data is within the normalized half-precision floating point value range, in which case the first data can be directly right-shifted by 13 bits. The other is that the value of the input data is within the non-normalized half-precision floating point value range, in which case the input data needs to be normalized, that is, the first data needs to be additionally shifted.

[0139] In some embodiments, the judgment condition for additional shifting is neg1=((din[30:23]-127+15)<=0), that is, when (din[30:23]-127+15) is not greater than 0, the first data needs additional shifting, and when (din[30:23]-127+15) is greater than 0, the first data does not need additional shifting.

[0140] Further, the fifth quantity information Rm3[4:0]=neg1?-(din[30:23]-127+15)+1+13:13=neg1?~din[30:23]+127:13.

[0141] The right shift bit number generating circuit is also used to generate sixth quantity information and first indication information based on the upper 8 bits of the input data except the sign bit, the sixth quantity information is used to indicate the number of bits of the first data to be right shifted when the data type of the input data is converted from a single-precision floating point type to a 32-bit integer type and the absolute value of the input data is not greater than 2 to the power of 24, and the first indication information is used to indicate whether the absolute value of the input data is not greater than 2 to the power of 24 when the data type of the input data is a single-precision floating point type.

[0142] In some embodiments, the first indication information can be expressed in the form of neg2=((din[30:23]-127)<=24). That is, when the data type of the input data is a single-precision floating point type, when (din[30:23]-127) is not greater than 24, neg2 is 1, indicating that the absolute value of the input data is not greater than 2 to the power of 24; when (din[30:23]-127) is greater than 24, neg2 is 0, indicating that the absolute value of the input data is greater than 2 to the power of 24. Further, the sixth quantity information Rm4[4:0]=(24-(din[30:23]-127)).

[0143] The right shift bit generation circuit is also used to generate seventh quantity information and second indication information based on the upper 5 bits of the input data except the sign bit. The seventh quantity information is used to indicate the number of bits of the first data to be right shifted when the data type of the input data is converted from half-precision floating point to 32-bit integer and the absolute value of the input data is not greater than 2 to the 11th power. The second indication information is used to indicate whether the absolute value of the input data is not greater than 2 to the 11th power when the data type of the input data is half-precision floating point.

[0144] In some embodiments, the second indication information can be expressed in the form of neg3=((din[14:10]-15)<=11). That is, when the data type of the input data is a half-precision floating point type, when (din[14:10]-15) is not greater than 11, neg3 is 1, indicating that the absolute value of the input data is not greater than 2 to the 11th power; when (din[14:10]-15) is greater than 11, neg3 is 0, indicating that the absolute value of the input data is greater than 2 to the 11th power. Further, the seventh quantity information Rm5[3:0]=(11-(din[14:10]-15).

[0145] For example, please refer to Figure 5The right shift bit generation circuit may include three right shift bit generation units, which are respectively used to: obtain the judgment condition neg1 and the fifth quantity information Rm3[4:0] according to din[30:23] (when the input data is a single-precision floating point type, din[30:23] is the upper 8 bits of the input data excluding the sign bit). Obtain the first indication information neg2 and the sixth quantity information Rm4[4:0] according to din[30:23]. Obtain the second indication information neg3 and the seventh quantity information Rm5[3:0] according to din[14:10] (when the input data is a half-precision floating point type, din[14:10] is the upper 5 bits of the input data excluding the sign bit).

[0146] The second selection circuit is used to select one of the third quantity information, the fourth quantity information, the fifth quantity information, the sixth quantity information and the seventh quantity information as the right shift quantity information according to the conversion type information and the data type of the input data.

[0147] For example, please refer to Figure 5 The second selection circuit may include four selectors, which are respectively used to: select the first intermediate information Rz1[2:0] from the third quantity information Rm1[2:0] and the fourth quantity information Rm2[1:0] according to the conversion type information s32_to_f32, and the corresponding selection logic can be expressed by the following formula: Rz1[2:0]=s32_to_f32?Rm1[2:0]:Rm2[1:0]. Select the second intermediate information Rz2[4:0] from the fifth quantity information Rm3[4:0] and the sixth quantity information Rm4[4:0] according to the conversion type information f32_to_s32, and the corresponding selection logic can be expressed by the following formula: Rz2[4:0]=f32_to_s32?Rm4[4:0]:Rm3[4:0]. According to the data type indication signal din_is_f32, the third intermediate information Rz3[4:0] is selected from the second intermediate information Rz2[4:0] and the seventh quantity information Rm5[3:0]. The corresponding selection logic can be expressed by the following formula: Rz3[4:0]=din_is_f32?Rz2[4:0]:Rm5[3:0]. According to the data type indication signal din_is_s32, the right shift quantity information R[4:0] is selected from the first intermediate information Rz1[2:0] and the third intermediate information Rz3[4:0]. The corresponding selection logic can be expressed by the following formula: R[4:0]=din_is_s32?Rz1[2:0]:Rz3[4:0].

[0148] It should be noted that during the data selection process of the selector, the number of bits of the input data and output data of the selector can be aligned by splicing or deleting 0 bits of the input data or output data of the selector, which will not be elaborated in this application.

[0149] The second selection circuit is further used to select one of the third leading 0 information and the fourth leading 0 information as the right-shifted leading 0 information according to the conversion type information.

[0150] For example, please refer to Figure 5 The selector in the second selection circuit is used to select the right-shifted leading 0 information R0[4:0] from the third leading 0 information R1[3:0] and the fourth leading 0 information R2[2:0] according to the conversion type information s32_to_f32. The selection logic can be expressed by the following formula: R0[4:0]=s32_to_f32?R1[3:0]:R2[2:0]. Among them, R1[3], R2[2] and R0[4] are all zero bits of the leading 0 information.

[0151] The direction determination circuit is used to determine the shift direction information according to the right shift leading 0 information, the first indication information, the second indication information, the conversion type information and the data type of the input data.

[0152] In some embodiments, when the data type of the input data is a 32-bit integer and the all-zero bits of the right-shifted leading 0 information are inverted to 1, the shift direction information indicates that the right shift is the shift direction corresponding to the first data.

[0153] In some embodiments, when the data type of the input data is converted from a single-precision floating point type to a half-precision floating point type, the shift direction information indicates that right shift is the shift direction corresponding to the first data.

[0154] In some embodiments, when the data type of the input data is converted from a single-precision floating point type to a 32-bit integer type and the absolute value of the input data is not greater than 2 to the power of 24, the shift direction information indicates that the right shift is the shift direction corresponding to the first data.

[0155] In some embodiments, when the data type of the input data is converted from half-precision floating point to 32-bit integer and the absolute value of the input data is not greater than 2 to the 11th power, the shift direction information indicates that the right shift is the shift direction corresponding to the first data.

[0156] In some embodiments, the shift direction information can be determined by the following formula: sel = ~R0[4] & din_is_s32 | f32_to_f16 | neg2 & f32_to_s32 | neg3 & f16_to_s32. Here, sel is the shift direction information, R0[4] is the all-zero bit of the leading zero information before right shift, "|" is the OR operator. When sel is 1, it indicates that the right shift is the shift direction corresponding to the first data; when sel is 0, it indicates that the left shift is the shift direction corresponding to the first data.

[0157] Please refer to Figure 2 , after the right shift data generation circuit generates the leading zero information R0[4:0] before right shift, it will provide it to the exponent bit generation circuit 60 for generating the exponent bits of the output data. After the right shift data generation circuit generates the right shift quantity information R[4:0], it will provide it to the right shift circuit included in the shift circuit 30 for shifting. After the right shift data generation circuit generates the shift direction information sel, it will provide it to the shift selection circuit 40 for selecting the second data.

[0158] It can be seen that the right shift data generation circuit can generate the corresponding right shift quantity information and leading zero information before right shift for various situations of right shifting the first data according to the conversion type information and the data type of the input data, so that the data type conversion module can be used to convert data between multiple different data types. Moreover, the right shift data generation circuit can also determine the shift direction information, thus determining the correct shift direction for the data type conversion module.

[0159] In summary, the shift data generation circuit 20 including the left shift data generation circuit and the right shift data generation circuit can generate the relevant information required for left shifting and right shifting the first data in various different data type conversion situations, providing a basis for converting data between multiple data types.

[0160] The shift circuit 30 is used to shift the first data according to the shift quantity information to obtain the shifted first data.

[0161] In some embodiments, please refer to Figure 2 , the shift circuit 30 includes a left shift circuit and a right shift circuit.

[0162] The left shift circuit is used to perform a left shift process on the first data according to the left shift quantity information to obtain the left-shifted first data.

[0163] In some embodiments, the left shift circuit left shifts the first data by the number of bits indicated by the left shift data information to obtain the left-shifted first data. That is, the left-shifted first data Lx[31:0] = x[31:0] << L[4:0], where << is the left shift symbol.

[0164] The left shift circuit is further used to obtain left shift error information according to the first data after the left shift, and the left shift error information is used to indicate whether there is an error in the left shift leading 0 information.

[0165] Since the left-shift data generation circuit in the embodiment of the present application only inverts the negative integer data and does not perform an add-1 operation, the left-shifted leading 0 information may count one more leading 0 than the actual situation. Accordingly, the first data after the left shift may be left-shifted one more place than the actual situation.

[0166] In some embodiments, the left shift circuit is used to determine that there is an error in the left shift leading 0 information when the data type of the input data is converted from a 32-bit integer to a single-precision floating point and the 25th bit (i.e., Lx

[24] ) of the first data after the left shift is 1.

[0167] In some embodiments, the left shift circuit is used to determine that there is an error in the left shift leading 0 information when the data type of the input data is converted from a 32-bit integer to a half-precision floating point and the 12th bit (i.e., Lx

[11] ) of the first data after the left shift is 1.

[0168] In some embodiments, the left-shift error information Le=s32_to_f32&Lx

[24] |s32_to_f16&Lx

[11] , wherein Le is 1 indicating that there is an error in the left-shift leading 0 information, and Le is 0 indicating that there is no error in the left-shift leading 0 information.

[0169] A right shift circuit, used for performing right shift processing on the first data with rounding bits and sticky bits added thereto according to the right shift amount information, to obtain the first data after right shift;

[0170] The rounding bit and the sticky bit are initially 0. During the shifting process, they are added after the lowest bit of the first data to record the data shifted out during the shifting process of the first data. Furthermore, during the shifting process of the first data, when the lowest bit of the data is right shifted, it will be moved to the rounding bit. All data shifted out of the rounding bit will be ORed and placed in the sticky bit.

[0171] In some embodiments, the right shift circuit right-shifts the first data with the rounding bit and the sticky bit added thereto by the number of bits indicated by the right shift data information to obtain the first data after right shift, i.e., {Rx[31:0], R, S}={x[31:0], 2'b0}>>R[4:0], where >> is the right shift symbol, Rx[31:0] is the first data after right shift, R is the rounding bit after shifting, and S is the sticky bit after shifting.

[0172] In some embodiments, since the right-shift data generation circuit uses a 4-bit leading 0 detection, the right-shift circuit is used to right-shift the first data with rounding bits and sticky bits added by n+1 bits when converting the data type of the input data from a 32-bit integer to a half-precision floating point, to obtain the first data after right shift, where n is the number of bits indicated by the right-shift quantity information.

[0173] The right shift circuit is also used to obtain right shift error information according to the first data after right shift, and the right shift error information is used to indicate whether there is an error in the right shift leading 0 information.

[0174] Since the right-shift data generation circuit in the embodiment of the present application only inverts the negative integer data and does not perform an add-1 operation, the right-shifted leading 0 information may count one more leading 0 than the actual situation. Accordingly, the first data after the right shift may be right-shifted one place less than the actual situation.

[0175] In some embodiments, the right shift circuit is used to determine that there is an error in the right shift leading 0 information when the data type of the input data is converted from a 32-bit integer to a single-precision floating point and the 25th bit (i.e., Rx

[24] ) of the first data after the right shift is 1.

[0176] In some embodiments, the right shift circuit is used to determine that there is an error in the right shift leading 0 information when the data type of the input data is converted from a 32-bit integer to a half-precision floating point and the 12th bit (i.e., Rx

[11] ) of the first data after the right shift is 1.

[0177] In some embodiments, the right shift error information Re=s32_to_f32&Rx

[24] |s32_to_f16&Rx

[11] , wherein Re being 1 indicates that there is an error in the right shift leading 0 information, and Re being 0 indicates that there is no error in the right shift leading 0 information.

[0178] Please refer to Figure 2 After obtaining the first data Lx[31:0] after the left shift, the left shift circuit will provide it to the shift selection circuit 40 for selection. After obtaining the left shift error information Le, the left shift circuit will provide it to the exponent bit generation circuit 60 for correction. Similarly, after obtaining the first data Rx[31:0] after the right shift, the right shift circuit will provide it to the shift selection circuit 40 for selection. After obtaining the right shift error information Re, the right shift circuit will provide it to the exponent bit generation circuit for correction.

[0179] In summary, the shift circuit 30 can not only be used to shift the first data, but also be used to detect whether there is an error in the leading 0 information, thereby optimizing the timing of the data type conversion module and ensuring the accuracy of the output data.

[0180] The shift selection circuit 40 is used to select second data from the shifted first data according to the shift direction information, where the second data is obtained by shifting the first data in the shift direction corresponding to the first data.

[0181] In some embodiments, the shift selection circuit is used to select one of the first data after left shift and the first data after right shift as the second data according to the shift direction information.

[0182] In some embodiments, the shift selection circuit is a selector, and the selection logic of the selector can be expressed as the following formula: second data Y[31:0]=sel?Rx[31:0]:Lx[31:0].

[0183] Please refer to Figure 2 After obtaining the second data Y[31:0], the shift selection circuit 40 provides it to the rounding and negation circuit 50 for negation and addition processing. In addition, it should be noted that when the shift direction corresponding to the first data is right shift, the second data also carries two additional bits, namely the rounding bit and the sticking bit in the above embodiment.

[0184] The rounding and negation circuit 50 is used to perform inversion and addition processing on the second data according to the conversion type information to obtain the third data.

[0185] For example, please refer to Figure 6 The input port signal of the rounding and negating circuit 50 may include the second data Y[31:0] (which may carry rounding bits and sticky bits), three output type indication signals dout_is_s32, dout_is_f32, dout_is_f16, and floating point sign indication information fs. Among them, if dout_is_s32 is 1, it indicates that the data type of the output data is a 32-bit integer, and if dout_is_s32 is 0, it indicates that the data type of the output data is not a 32-bit integer. If dout_is_f32 is 1, it indicates that the data type of the output data is a single-precision floating point, and if dout_is_f32 is 0, it indicates that the data type of the output data is not a single-precision floating point. If dout_is_f16 is 1, it indicates that the data type of the output data is a half-precision floating point, and if dout_is_f16 is 0, it indicates that the data type of the output data is not a half-precision floating point. The output port signal of the rounding and negating circuit 50 may include the third data Z[31:0] and overflow indication information ovf.

[0186] The above output type indication signal and floating point sign indication information can be obtained according to the conversion type information. Further, fs can be calculated by the following formula: fs = f32_to_s32&din

[31] | f16_to_s32&din

[15] , that is, when fs is 1, it indicates that the data type of the input data is converted from floating point to 32-bit integer, and the sign bit of the input data is 1. When fs is 0, it indicates that the data type of the input data is not converted from floating point to 32-bit integer, or the sign bit of the input data is 0.

[0187] In some embodiments, please refer to Figure 6 The rounding circuit 50 includes an inversion circuit, an addition circuit and an overflow judgment circuit ( Figure 6 not shown).

[0188] The inversion circuit is used to invert the second data according to the conversion type information and the sign bit of the input data to obtain the intermediate data.

[0189] In some embodiments, the inversion circuit is used to invert the second data to obtain intermediate data when the data type of the input data is converted from floating point to integer and the sign bit of the input data is 1 (corresponding to the above-mentioned case where fs is 1).

[0190] In some embodiments, the negation circuit is used to determine the second data as intermediate data without converting the data type of the input data from floating point to integer, or when the sign bit of the input data is 0 (corresponding to the above-mentioned case where fs is 0).

[0191] In some embodiments, the negation circuit is used to select whether to negate the second data according to the floating-point sign indication information.

[0192] For example, please refer to Figure 6 The inversion circuit includes a selector, which is used to select whether to invert the second data Y[31:0] according to the floating point sign indication information fs. The selection logic of the selector can be expressed by the following formula: intermediate data Y1=fs?~Y[31:0]:Y[31:0].

[0193] It can be seen that when the input data is a negative floating point type and the output data is an integer type, the negation circuit can invert the mantissa bits of the shifted input data, thereby converting the input data into an integer type.

[0194] The adding circuit is used to add the intermediate data according to the value of the protection bit, the value of the rounding bit and the value of the sticky bit corresponding to the second data to obtain the third data, wherein the protection bit refers to the lowest bit of the second data, and the rounding bit and the sticky bit are arranged in sequence after the protection bit and are used to record the data shifted out during the shifting process of the first data.

[0195] In some embodiments, the adding circuit is used to determine whether the second data needs to be carried according to the value of the protection bit, the value of the rounding bit and the value of the sticky bit.

[0196] In some embodiments, the round-to-nearest rounding method can be used to determine whether the second data needs to be carried. Specifically, the carry value ren can be calculated by the following formula: ren = R & (G|S), where R is the rounding bit, G is the protection bit, and S is the sticky bit. When ren is 1, it indicates that the second data needs to be carried, and when ren is 0, it indicates that the second data does not need to be carried. It should be noted that in an embodiment of the present application, if the second data does not carry the rounding bit and the sticky bit (that is, corresponding to the case of shifting the first data left), the above-mentioned rounding bit and the sticky bit can be directly regarded as 0.

[0197] In some embodiments, please refer to Figure 6 The addition circuit includes a carry determination unit and a selector. The carry determination unit is used to calculate the carry value ren and perform an XOR operation on the carry value ren and the floating point sign indication information fs to obtain a judgment value pen. The selector is used to select whether to add the intermediate data Y1 according to the judgment value pen. The selection logic is as follows: the third data Z[31:0]=pen? (Y1+1):Y1.

[0198] When converting input data from floating point type to integer type, due to the different representation methods of these two data types, if the input floating point data is negative, the second data needs to be inverted and added 1, and the second data may also need to be carried, so it is necessary to discuss whether to add 1 to the intermediate data according to different situations.

[0199] In some embodiments, the adding circuit is used to determine the intermediate data as the third data when the second data needs to be carried and the intermediate data is obtained by inverting the second data.

[0200] In the above case, since the intermediate data is obtained by negating the second data, when the second data needs to be carried, the intermediate data needs to be borrowed. At this time, the addition of 1 after negating the second data is offset by the borrow, so the intermediate data is directly determined as the third data.

[0201] In the above case, the value of ren is 1, the value of rs is 1, and the judgment value pen obtained by performing an XOR operation on 1 and 1 is 0, indicating that there is no need to add a value to the intermediate data.

[0202] In some embodiments, the adding circuit is used to add 1 to the value of the intermediate data to obtain the third data when the second data does not need to be carried and the intermediate data is obtained by inverting the second data.

[0203] In the above case, since the second data does not need to be carried and the intermediate data does not need to be borrowed, the intermediate data can be added by 1 to obtain the third data.

[0204] In the above case, the value of ren is 0, the value of rs is 1, and the judgment value pen obtained by performing an XOR operation on 0 and 1 is 1, indicating that the intermediate data needs to be added.

[0205] In some embodiments, the adding circuit is used to add 1 to the value of the intermediate data to obtain the third data when the second data needs to be carried and the intermediate data is the second data.

[0206] In the above case, since the intermediate data is the second data, when the second data needs to be carried, the intermediate data can be directly increased by 1.

[0207] In the above case, the value of ren is 1, the value of rs is 0, and the judgment value pen obtained by performing an XOR operation on 1 and 0 is 1, indicating that the intermediate data needs to be added.

[0208] In some embodiments, the adding circuit is used to determine the intermediate data as the third data when the second data does not need to be carried and the intermediate data is the second data.

[0209] In the above case, since the intermediate data is the second data, when the second data does not need to be carried, the intermediate data does not need to be added with 1.

[0210] In the above case, the value of ren is 0, the value of rs is 0, and the judgment value pen obtained by performing an XOR operation on 0 and 0 is 0, indicating that there is no need to add a value to the intermediate data.

[0211] It can be seen that the adding circuit can adapt to different data type conversion situations and correctly add the second data.

[0212] The overflow judgment circuit is used to obtain overflow indication information according to the data type of the output data and the third data, and the overflow indication information is used to indicate whether the third data overflows.

[0213] Overflow of the third data means that when the output data is a floating point type, the value of the third data exceeds the value that can be represented by the mantissa of the floating point data (i.e., exceeds the value that can be represented by the mantissa combined with the hidden bit 1). In the embodiment of the present application, since the overflow of the third data is caused by the addition of 1 by the value-adding circuit, the overflow is at most one bit.

[0214] In some embodiments, the overflow determination circuit is used to determine that the third data overflows when the data type of the output data is a single-precision floating point type and the 25th bit of the third data is 1.

[0215] In some embodiments, the overflow determination circuit is used to determine that the third data overflows when the data type of the output data is a half-precision floating point type and the 12th bit of the third data is 1.

[0216] In some embodiments, the overflow indication information can be obtained by the following formula: overflow indication information ovf=Z

[24] &dout_is_f32|Z

[11] &dout_is_f16, wherein when ovf is 1, it indicates that the third data overflows, and when ovf is 0, it indicates that the third data does not overflow. In addition, when the output data is an integer, that is, when dout_is_s32 is 1, it can be directly determined that the third data does not overflow.

[0217] Please refer to Figure 2 After the rounding-off circuit 50 generates the third data Z[31:0], it is provided to the output selection circuit 70 for generating output data.

[0218] In summary, the rounding circuit 50 can selectively perform inversion and addition processing on the shifted data, thereby ensuring that the data type conversion module can be used for conversion between multiple data types. In addition, the rounding circuit can also detect whether the third data overflows, thereby ensuring the accuracy of the output data.

[0219] The exponent bit generating circuit 60 is used to generate exponent bit data according to the shift direction information, the leading 0 information, the input data, the data type of the input data and the conversion type information.

[0220] The exponent bit data is used to indicate the exponent bit of the output data when the data type of the output data is a floating point number.

[0221] For example, please refer to Figure 7 The input port signals of the exponent bit generating circuit 60 include: partial bit numbers din[30:23] and din[14:10] of the input data, overflow indication information ovf, shift direction information sel, left shift error information Le, right shift error information Re, left shift leading 0 information L0[4:0], right shift leading 0 information R0[4:0], data type indication signal din_is_s32 and conversion type information s32_to_f16. The input port signals of the exponent bit generating circuit 60 include exponent bit data exp[7:0].

[0222] In some embodiments, please refer to Figure 7 The exponent bit generation circuit includes a left shift exponent bit generation circuit, a right shift exponent bit generation circuit and a fourth selection circuit.

[0223] The left shift exponent bit generating circuit is used to generate left shift exponent bit data according to left shift leading 0 information, conversion type information, input data and the data type of the input data.

[0224] In some embodiments, the left-shift exponent bit generating circuit is used to obtain a first exponent value according to the left-shift leading 0 information and the first set value when the data type of the first data is converted from a 32-bit integer to a single-precision floating point type. The first exponent value is used to generate the left-shift exponent bit data.

[0225] In this case, the first index value sum1=24-L0[4:0]-127=~L0[4:0]-102, wherein -102 is the first set value.

[0226] In some embodiments, the left-shift exponent bit generation circuit is used to obtain a first exponent value according to left-shift leading 0 information and a second set value when converting the data type of the first data from a 32-bit integer to a half-precision floating point.

[0227] In this case, the first index value sum1=11-L0[3:0]-15=~L0[3:0]-3, wherein -3 is the second set value.

[0228] In some embodiments, when the data type of the first data is converted from half-precision floating point to single-precision floating point, a first exponent value is obtained according to left-shift leading 0 information, high 5 bits of the input data excluding the sign bit, and a third set value.

[0229] In this case, the first index value sum1=din[14:10]-15+127-13-L0[4:0]=-L0[4:0]+(din[14:10]+126), wherein 126 is the third setting value.

[0230] It can be seen that the left-shift exponent bit generating circuit can determine different first exponent values ​​according to different data type conversion conditions, thereby generating different left-shift exponent bit data.

[0231] In some embodiments, the left-shift exponent bit generating circuit is further used to add 1 to the first exponent value to obtain left-shift exponent bit data when there is an error in the left-shift leading 0 information.

[0232] In some embodiments, the left-shift exponent bit generating circuit is further configured to determine the first exponent value as the left-shift exponent bit data when there is no error in the left-shift of the leading 0 information.

[0233] It can be seen that the left-shift exponent bit generation circuit can avoid the error caused by the left-shift leading 0 information and generate accurate left-shift exponent bit data.

[0234] For example, please refer to Figure 7 The left shift exponent bit generation circuit includes an adder, two selectors located before the adder, and a selector located after the adder. The selector located before the adder is used to determine the first added value add1[7:0] from the first set value -102, the second set value -3, and the sum of din[14:10] and the third set value 126 (din[14:10]+126) according to the conversion type information s32_to_f16 and the data type indication signal din_is_s32. The corresponding selection logic can be expressed by the following formula: add1[7:0]=din_is_s32?(s32_to_f16?-3:-102):din[14:10]+126. The adder can be used to add the inverted left-shifted leading 0 information ~L0[4:0] to the first added value add1[7:0] to obtain the first exponent value sum1[7:0], that is, sum1[7:0]=~L0[4:0]+add1[7:0]. The selector located after the adder can be used to select whether to add 1 to the first exponent value sum1 according to the left-shifted error information Le, and its selection logic is: left-shifted exponent bit data Lexp=Le? sum1+1:sum1.

[0235] The right shift exponent bit generating circuit is used to generate right shift exponent bit data according to right shift leading 0 information, conversion type information, input data and the data type of the input data.

[0236] In some embodiments, the right-shift exponent bit generating circuit is used to obtain a second exponent value according to the right-shift leading 0 information and the fourth set value when the data type of the first data is converted from a 32-bit integer to a single-precision floating point. The second exponent value is used to generate the right-shift exponent bit data.

[0237] In this case, the second index value sum2=24+R0[4:0]-127=R0[4:0]-103, wherein -103 is the fourth setting value.

[0238] In some embodiments, the right shift exponent bit generation circuit is used to obtain a second exponent value according to right shift leading 0 information and a fifth set value when the data type of the first data is converted from a 32-bit integer to a half-precision floating point.

[0239] In this case, the second index value sum2=11+R0[1:0]-15=R0[1:0]-4, wherein -4 is the fifth setting value.

[0240] In some embodiments, when the data type of the first data is converted from single-precision floating point to half-precision floating point, a second exponent value is obtained according to the right-shift leading 0 information, the upper 8 bits of the input data excluding the sign bit, and the sixth set value.

[0241] In this case, sum2=din[30:23]-127+15-13+R0[4:0]=R0[4:0]+(din[30:23]-125), wherein -125 is the sixth setting value.

[0242] It can be seen that the right-shift exponent bit generating circuit can determine different second exponent values ​​according to different data type conversion situations, thereby generating different right-shift exponent bit data.

[0243] In some embodiments, the right-shift exponent bit generation circuit is used to add 1 to the second exponent value to obtain right-shift exponent bit data when there is an error in the right-shift leading 0 information or when the third data overflows.

[0244] In some embodiments, the right-shift exponent bit generation circuit is used to determine the first exponent value as the right-shift exponent bit data when there is no error in the right-shift leading 0 information and the third data does not overflow.

[0245] It can be seen that the right-shift exponent bit generation circuit can avoid the errors caused by the right-shift leading 0 information and the third data overflow, and generate accurate right-shift exponent bit data.

[0246] For example, please refer to Figure 7 The right shift exponent bit generation circuit includes an adder, two selectors located before the adder, and a selector located after the adder. The selector located before the adder is used to determine the second added value add2[7:0] from the fourth set value -103, the fifth set value -4, and the sum of din[30:23] and the sixth set value -125 (din[30:23]-125) according to the conversion type information s32_to_f16 and the data type indication signal din_is_s32. The corresponding selection logic can be expressed by the following formula: add2[7:0]=din_is_s32?(s32_to_f16?-4:-103):din[30:23]-125. The adder can be used to add the right shift leading 0 information R0[4:0] to the second added value add2[7:0] to obtain the second exponent value sum2[7:0], that is, sum2[7:0]=R0[4:0]+add2[7:0]. The selector located after the adder can be used to select whether to add 1 to the second exponent value sum2 according to the right shift error information Le and the overflow indication information ovf, and its selection logic is: right shift exponent bit data Rexp=(Re|ovf)? sum2+1:sum2.

[0247] The fourth selection circuit is used to select one of the left-shifted exponent bit data and the right-shifted exponent bit data as the exponent bit data according to the shift direction information.

[0248] For example, please refer to Figure 7 The fourth selection circuit includes a selector, which is used to select the exponent bit data from the left-shifted exponent bit data Lexp and the right-shifted exponent bit data Rexp according to the shift direction information sel, and the selection logic bit is: the exponent bit data exp[7:0]=sel?Rexp:Lexp.

[0249] Please refer to Figure 2 After the exponent bit generation circuit 60 generates the exponent bit data exp[7:0], it is provided to the output selection circuit 70 to generate output data.

[0250] To summarize, when the data type of the output data is a floating point type, the exponent bit generation circuit 60 can generate corresponding exponent bits according to the different precisions (single precision and half precision) of the floating point type and the shift direction corresponding to the first data, thereby enabling the data type conversion module to have the ability to convert integer numbers into floating point numbers of different precisions.

[0251] The output selection circuit 70 is used to determine the output data according to the third data, the exponent bit data, the sign bit of the input data and the data type of the output data.

[0252] In some embodiments, the output selection circuit 70 is configured to determine the third data as the output data when the data type of the output data is an integer.

[0253] In some embodiments, the output selection circuit 70 is used to concatenate the sign bit, exponent bit data and third data of the input data to obtain the output data when the data type of the output data is a floating point type.

[0254] Exemplarily, when the data type of the output data is half-precision floating point, the sign bit 0 of the input data, the exponent bit data exp[4:0]=00111, and the third data Z[9:0]=0100000100 are concatenated to obtain the half-precision floating point output data dout[15:0]=0001110100000100.

[0255] In some embodiments, the output data dout may be determined by the following formula: dout=dout_is_f16?{sign,exp[4:0],Z[9:0]}:dout_is_f32?{sign,exp[7:0],Z[22:0]}:Z[31:0], where sign is the sign bit of the input data.

[0256] In some embodiments, the output selection circuit 70 is used to determine the maximum value of the data type in the overflow direction as the output data when the value of the input data overflows the numerical range corresponding to the data type of the output data.

[0257] Exemplarily, if the data type of the output data is half-precision floating point, when the value of the input data is greater than the maximum value 65504 that can be represented by the half-precision floating point data, 65504 represented by the half-precision floating point data is determined as the output data.

[0258] In some embodiments, please refer to Figure 2 The output selection circuit includes an overflow detection circuit and an output circuit. The overflow detection circuit is used to detect whether the value of the input data overflows the numerical range corresponding to the data type of the output data. The output circuit is used to determine the output data according to the detection result of the overflow detection circuit.

[0259] In summary, the output selection circuit 70 can support the output of multiple different types of data, and select the correct output data according to the data type of the output data and the numerical overflow of the input data.

[0260] The technical solution provided by the embodiment of the present application is designed to include an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding circuit, an exponent bit generation circuit and an output selection circuit. Among them, the input selection circuit can determine the first data for shift processing according to the input data and the data type of the input data. The shift data generation circuit can generate data that needs to be used and referenced in the data type conversion process according to the input data, the data type of the input data and the conversion type information. The shift circuit can shift the first data according to the shift quantity information generated by the shift data generation circuit. The shift selection circuit can select the corresponding second data from the shifted first data according to the shift direction information generated by the shift data generation circuit. The rounding circuit can perform subsequent processing of shift operations such as negation and addition on the second data. The exponent bit generation circuit can generate the exponent bit corresponding to the floating point number when the output data is a floating point number. The input selection circuit can finally obtain the output data after the data type conversion is completed according to the data determined by the above circuits. The data type conversion module can be used to convert data between a variety of different data types, and realizes the use of shared shift circuits and rounding circuits to achieve different data type conversion functions, saving hardware resources and reducing the size of the processor chip.

[0261] The following is an embodiment of the method of the present application. For details not described in detail in the embodiment of the method of the present application, please refer to the above embodiment of the data type conversion module.

[0262] Please refer to Figure 8 , which shows a flow chart of a data type conversion method based on a data type conversion module provided by an embodiment of the present application, the method is applied to the data type conversion module applied to the processor introduced above, the data type conversion module includes: an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding circuit, an exponent bit generation circuit and an output selection circuit. The method may include at least one of the following steps 810 to 870.

[0263] Step 810: The input selection circuit determines first data according to the input data and the data type of the input data, and the first data is used for shift processing.

[0264] In some embodiments, the input selection circuit includes: an integer data processing circuit, a floating point data processing circuit and a third selection circuit. Step 810 includes at least one of the following sub-steps 812 to 816.

[0265] In sub-step 812, the integer data processing circuit converts the input data into an absolute value form to obtain integer input data.

[0266] In sub-step 814, the floating-point data processing circuit performs mantissa processing on the input data according to the data type of the input data to obtain mantissa input data.

[0267] In some embodiments, when the data type of the input data is a single-precision floating point type, the floating-point data processing circuit concatenates 1 with the lower 23 bits of the input data to obtain mantissa input data.

[0268] In some embodiments, when the data type of the input data is not a single-precision floating point type, 1 is concatenated with the lower 10 bits of the input data to obtain the mantissa input data.

[0269] In sub-step 816, the third selection circuit selects one of the integer input data and the mantissa input data as the first data according to the data type of the input data.

[0270] Step 820: The shift data generating circuit generates shift direction information, shift quantity information and leading 0 information according to the input data, the data type of the input data and the conversion type information.

[0271] The conversion type information is used to indicate whether to convert the input data between two data types, the shift direction information is used to indicate the shift direction corresponding to the first data, the shift quantity information is used to indicate the number of bits to shift the first data, and the leading 0 information is used to indicate the number of leading 0s in the first data.

[0272] In some embodiments, the shift data generating circuit includes: a left shift data generating circuit and a right shift data generating circuit, the shift quantity information includes left shift quantity information and right shift quantity information, and the leading 0 information includes left shift leading 0 information and right shift leading 0 information. Step 820 includes at least one of the following sub-steps 822 to 824.

[0273] In sub-step 822, the left-shift data generation circuit generates left-shift quantity information and left-shift leading 0 information according to the input data and the conversion type information.

[0274] In some embodiments, the left-shift data generation circuit includes: a first detection circuit, a second detection circuit, a left-shift number generation circuit, and a first selection circuit. Sub-step 822 may include at least one of the following steps.

[0275] 1. The first detection circuit obtains the first leading 0 information according to the lower 24 bits of the input data.

[0276] 2. The second detection circuit obtains the second leading 0 information according to the lower 11 bits of the input data.

[0277] 3. The left shift bit number generating circuit generates first quantity information based on the upper 8 bits of the input data excluding the sign bit. The first quantity information is used to indicate the number of bits of the first data to be left shifted when the data type of the input data is converted from a single-precision floating point type to a 32-bit integer type and the absolute value of the input data is greater than 2 to the power of 24.

[0278] 4. The left shift bit number generating circuit generates second quantity information based on the high 5 bits of the input data except the sign bit. The second quantity information is used to indicate the number of bits of the first data left shifted when the data type of the input data is converted from a half-precision floating point type to a 32-bit integer type and the absolute value of the input data is greater than 2 to the 11th power.

[0279] 5. The first selection circuit selects one of the first leading 0 information and the second leading 0 information as the left-shifted leading 0 information according to the conversion type information.

[0280] 6. The first selection circuit selects one of the left-shift leading 0 information, the first quantity data, and the second quantity data as the left-shift quantity information according to the conversion type information.

[0281] In sub-step 824, the right shift data generation circuit generates right shift quantity information, right shift leading 0 information and shift direction information according to the input data, the data type of the input data and the conversion type information.

[0282] In some embodiments, the right shift data generation circuit includes: a third detection circuit, a fourth detection circuit, a right shift number generation circuit, a second selection circuit, and a direction determination circuit. Sub-step 824 includes at least one of the following steps.

[0283] 1. The third detection circuit obtains third leading 0 information and third quantity information based on the high 8 bits of the input data except the sign bit. The third quantity information is used to indicate the number of bits of the first data to be right shifted when the data type of the input data is converted from a 32-bit integer to a single-precision floating point and the absolute value of the input data is not less than 2 to the power of 24.

[0284] In some embodiments, when the sign bit of the input data is 1, the third detection circuit performs a leading 0 detection on the upper 8 bits of the inverted input data except the sign bit to obtain third leading 0 information.

[0285] In some embodiments, when the sign bit of the input data is 0, the third detection circuit performs leading 0 detection on the upper 8 bits of the input data except the sign bit to obtain third leading 0 information.

[0286] In some embodiments, the third detection circuit inverts the third leading 0 information to obtain third quantity information.

[0287] 2. The fourth detection circuit obtains fourth leading 0 information and fourth quantity information based on the high 4 bits of the input data except the sign bit. The fourth quantity information is used to indicate the number of bits of the first data to be right shifted when the data type of the input data is converted from a 32-bit integer to a half-precision floating point and the absolute value of the input data is not less than 2 to the 11th power.

[0288] 3. The right shift bit generation circuit generates fifth quantity information based on the upper 8 bits of the input data except the sign bit. The fifth quantity information is used to indicate the number of bits of the first data to be right shifted when the data type of the input data is converted from single-precision floating point to half-precision floating point.

[0289] 4. The right shift bit number generating circuit generates sixth quantity information and first indication information based on the upper 8 bits of the input data except the sign bit. The sixth quantity information is used to indicate the number of bits by which the first data is right shifted when the data type of the input data is converted from a single-precision floating point type to a 32-bit integer type and the absolute value of the input data is not greater than 2 to the power of 24. The first indication information is used to indicate whether the absolute value of the input data is not greater than 2 to the power of 24 when the data type of the input data is a single-precision floating point type.

[0290] 5. The right shift bit generation circuit generates seventh quantity information and second indication information based on the upper 5 bits of the input data except the sign bit. The seventh quantity information is used to indicate the number of bits of the first data to be right shifted when the data type of the input data is converted from half-precision floating point to 32-bit integer and the absolute value of the input data is not greater than 2 to the 11th power. The second indication information is used to indicate whether the absolute value of the input data is not greater than 2 to the 11th power when the data type of the input data is half-precision floating point.

[0291] 6. The second selection circuit selects one of the third quantity information, the fourth quantity information, the fifth quantity information, the sixth quantity information and the seventh quantity information as the right shift quantity information according to the conversion type information and the data type of the input data.

[0292] 7. The second selection circuit selects one of the third leading 0 information and the fourth leading 0 information as the right-shifted leading 0 information according to the conversion type information.

[0293] 8. The direction determination circuit determines the shift direction information according to the right shift leading 0 information, the first indication information, the second indication information, the conversion type information and the data type of the input data.

[0294] Step 830: The shift circuit shifts the first data according to the shift quantity information to obtain the shifted first data.

[0295] In some embodiments, the shift circuit includes a left shift circuit and a right shift circuit. Step 830 includes at least one of the following sub-steps 832-838.

[0296] In sub-step 832, the left shift circuit performs a left shift process on the first data according to the left shift amount information to obtain the left-shifted first data.

[0297] In sub-step 834, the left shift circuit obtains left shift error information according to the first data after the left shift, and the left shift error information is used to indicate whether there is an error in the left shift leading 0 information.

[0298] In sub-step 836, the right shift circuit performs right shift processing on the first data to which the rounding bit and the sticky bit are added according to the right shift amount information to obtain the first data after right shift.

[0299] In sub-step 838, the right shift circuit obtains right shift error information according to the first data after right shift, and the right shift error information is used to indicate whether there is an error in the right shift leading 0 information.

[0300] Step 840: The shift selection circuit selects the second data from the shifted first data according to the shift direction information.

[0301] The second data is obtained by shifting the first data in a shift direction corresponding to the first data.

[0302] Step 850: the rounding circuit performs inversion and addition processing on the second data according to the conversion type information to obtain third data.

[0303] In some embodiments, the rounding circuit includes: an inversion circuit, an addition circuit, and an overflow determination circuit. Step 850 includes at least one of the following sub-steps 852 to 856.

[0304] In sub-step 852, the negation circuit negates the second data according to the conversion type information and the sign bit of the input data to obtain intermediate data.

[0305] In some embodiments, when the data type of the input data is converted from a floating point type to an integer type and the sign bit of the input data is 1, the negation circuit negates the second data to obtain the intermediate data.

[0306] In some embodiments, the negation circuit determines the second data as intermediate data when the data type of the input data is not converted from a floating point type to an integer type or the sign bit of the input data is 0.

[0307] In sub-step 854, the adding circuit adds the intermediate data according to the value of the guard bit, the value of the rounding bit and the value of the sticky bit corresponding to the second data to obtain the third data, wherein the guard bit refers to the lowest bit of the second data, and the rounding bit and the sticky bit are arranged in sequence after the guard bit to record the data shifted out during the shifting process of the first data.

[0308] In some embodiments, the adding circuit determines whether the second data needs to be carried according to the value of the protection bit, the value of the rounding bit and the value of the sticky bit.

[0309] In some embodiments, when the second data needs to be carried and the intermediate data is obtained by inverting the second data, the adding circuit determines the intermediate data as the third data.

[0310] In some embodiments, when the second data does not need to be carried and the intermediate data is obtained by inverting the second data, the adding circuit adds 1 to the value of the intermediate data to obtain the third data.

[0311] In some embodiments, when the second data needs to be carried and the intermediate data is the second data, the adding circuit adds 1 to the value of the intermediate data to obtain the third data.

[0312] In some embodiments, when the second data does not need to be carried and the intermediate data is the second data, the adding circuit determines the intermediate data as the third data.

[0313] Sub-step 856, the overflow judgment circuit is used to obtain overflow indication information according to the data type of the output data and the third data, and the overflow indication information is used to indicate whether the third data overflows.

[0314] Step 860: the exponent bit generation circuit generates exponent bit data according to the shift direction information, the leading 0 information, the input data, the data type of the input data, and the conversion type information.

[0315] In some embodiments, the exponent bit generation circuit includes: a left shift exponent bit generation circuit, a right shift exponent bit generation circuit and a fourth selection circuit. Step 860 includes at least one of the following sub-steps 862 to 866.

[0316] Sub-step 862, a left shift exponent bit generating circuit is used to generate left shift exponent bit data according to the left shift leading 0 information, the conversion type information, the input data and the data type of the input data.

[0317] In some embodiments, the left-shift exponent bit generating circuit converts the data type of the first data from a 32-bit integer to a single-precision floating point type, and obtains a first exponent value according to the left-shift leading 0 information and a first set value. The first exponent value is used to generate left-shift exponent bit data.

[0318] In some embodiments, the left-shift exponent bit generation circuit obtains the first exponent value according to the left-shift leading 0 information and the second set value when converting the data type of the first data from a 32-bit integer to a half-precision floating point.

[0319] In some embodiments, when the left-shift exponent bit generation circuit converts the data type of the first data from half-precision floating point to single-precision floating point, it obtains a first exponent value based on the left-shift leading 0 information, the high 5 bits of the input data excluding the sign bit, and the third set value.

[0320] In some embodiments, when there is an error in the left-shifted leading 0 information, the first exponent value is increased by 1 to obtain the left-shifted exponent bit data.

[0321] In some embodiments, when there is no error in left-shifting the leading 0 information, the first exponent value is determined as the left-shifted exponent bit data.

[0322] Sub-step 864, a right shift exponent bit generating circuit is used to generate right shift exponent bit data according to the right shift leading 0 information, the conversion type information, the input data and the data type of the input data.

[0323] In some embodiments, the right-shift exponent bit generation circuit obtains the second exponent value according to the right-shift leading 0 information and the fourth set value when converting the data type of the first data from a 32-bit integer to a single-precision floating point.

[0324] In some embodiments, the right shift exponent bit generation circuit obtains the second exponent value according to the right shift leading 0 information and the fifth set value when converting the data type of the first data from a 32-bit integer to a half-precision floating point.

[0325] In some embodiments, when the right shift exponent bit generation circuit converts the data type of the first data from single-precision floating point to half-precision floating point, it obtains a second exponent value based on the right shift leading 0 information, the high 8 bits of the input data excluding the sign bit, and the sixth set value.

[0326] In some embodiments, when there is an error in the right-shift leading 0 information or the third data overflows, the right-shift exponent bit generation circuit adds 1 to the second exponent value to obtain the right-shift exponent bit data.

[0327] In some embodiments, the right-shift exponent bit generation circuit determines the first exponent value as the right-shift exponent bit data when there is no error in right-shifting the leading 0 information and the third data does not overflow.

[0328] In sub-step 866, the fourth selection circuit selects one of the left-shifted exponent bit data and the right-shifted exponent bit data as the exponent bit data according to the shift direction information.

[0329] The exponent bit data is used to indicate the exponent bit of the output data when the data type of the output data is a floating point number.

[0330] Step 870: The output selection circuit determines the output data according to the third data, the exponent bit data, the sign bit of the input data, and the data type of the output data.

[0331] In some embodiments, the output selection circuit determines the third data as the output data when the data type of the output data is an integer.

[0332] In some embodiments, when the data type of the output data is a floating point type, the output selection circuit concatenates the sign bit, exponent bit data and third data of the input data to obtain the output data.

[0333] In some embodiments, when the value of the input data overflows the numerical range corresponding to the data type of the output data, the output selection circuit determines the maximum value of the data type in the overflow direction as the output data.

[0334] An exemplary embodiment of the present application further provides a processor, which includes the data type conversion module introduced in the above embodiment.

[0335] An exemplary embodiment of the present application further provides a computer device, the computer device comprising a processor, and the processor comprising the data type conversion module introduced in the above embodiment.

[0336] Optionally, the processor is an AI processor, or other processor that requires the use of a data type conversion module, which is not limited in this application.

[0337] Optionally, the computer device can be a server, or a terminal device such as a mobile phone, a tablet computer, a vehicle-mounted terminal, a wearable device, a smart home device, or any device that is applied to a processor, such as a robot or a base station, and this application does not limit this.

[0338] It should be noted that before collecting the user's relevant data and during the process of collecting the user's relevant data, this application can display a prompt interface, pop-up window or output voice prompt information. The prompt interface, pop-up window or voice prompt information is used to prompt the user that its relevant data is currently being collected, so that this application only starts to execute the relevant steps of obtaining the user's relevant data after obtaining the user's confirmation operation on the prompt interface or pop-up window. Otherwise (that is, when the user's confirmation operation on the prompt interface or pop-up window is not obtained), the relevant steps of obtaining the user's relevant data are terminated, that is, the user's relevant data is not obtained. In other words, all user data collected by this application (including data to be converted into data types) are processed strictly in accordance with the requirements of relevant national laws and regulations. The informed consent or separate consent of the subject of personal information is obtained only with the user's consent and authorization. The subsequent data use and processing behavior is carried out within the scope of authorization of laws and regulations and the subject of personal information, and the collection, use and processing of relevant user data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0339] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0340] The above are merely exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data type conversion module applied to a processor, characterized in that: The data type conversion module includes: an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding circuit, an exponent bit generation circuit and an output selection circuit; The input selection circuit is used to determine first data according to input data and a data type of the input data, wherein the first data is used for shift processing; The shift data generating circuit is used to generate shift direction information, shift quantity information and leading zero information according to the input data, the data type of the input data and the conversion type information, wherein the conversion type information is used to indicate whether to convert the input data between two data types, the shift direction information is used to indicate the shift direction corresponding to the first data, the shift quantity information is used to indicate the number of bits to shift the first data, and the leading zero information is used to indicate the number of leading zeros of the first data; The shift circuit is used to shift the first data according to the shift quantity information to obtain the shifted first data; The shift selection circuit is used to select second data from the shifted first data according to the shift direction information, where the second data is obtained by shifting the first data according to the shift direction corresponding to the first data; The rounding circuit is used to perform inversion and addition processing on the second data according to the conversion type information to obtain third data; The exponent bit generating circuit is used to generate exponent bit data according to the shift direction information, the leading 0 information, the input data, the data type of the input data and the conversion type information; wherein the exponent bit data is used to indicate the exponent bit of the output data when the data type of the output data is a floating point number; The output selection circuit is used to determine the output data according to the third data, the exponent bit data, the sign bit of the input data and the data type of the output data.

2. The data type conversion module according to claim 1, characterized in that: The shift data generating circuit comprises: a left shift data generating circuit and a right shift data generating circuit, the shift quantity information comprises left shift quantity information and right shift quantity information, and the leading 0 information comprises left shift leading 0 information and right shift leading 0 information; The left-shift data generating circuit is used to generate the left-shift quantity information and the left-shift leading 0 information according to the input data and the conversion type information; The right shift data generating circuit is used to generate the right shift quantity information, the right shift leading 0 information and the shift direction information according to the input data, the data type of the input data and the conversion type information.

3. The data type conversion module according to claim 2, characterized in that: The left-shift data generating circuit comprises: a first detection circuit, a second detection circuit, a left-shift number generating circuit and a first selection circuit; The first detection circuit is used to obtain first leading 0 information according to the lower 24 bits of the input data; The second detection circuit is used to obtain second leading 0 information according to the lower 11 bits of the input data; The left shift bit number generating circuit is used to generate first quantity information according to the upper 8 bits of the input data except the sign bit, wherein the first quantity information is used to indicate the number of bits of the first data left shifted when the data type of the input data is converted from a single-precision floating point type to a 32-bit integer type and the absolute value of the input data is greater than 2 to the 24th power; The left shift bit number generating circuit is further used to generate second quantity information according to the upper 5 bits of the input data except the sign bit, wherein the second quantity information is used to indicate the number of bits of the first data left shift when the data type of the input data is converted from a half-precision floating point type to a 32-bit integer type and the absolute value of the input data is greater than 2 to the 11th power; The first selection circuit is used to select one of the first leading 0 information and the second leading 0 information as the left-shifted leading 0 information according to the conversion type information; The first selection circuit is further used to select one of the left-shift leading 0 information, the first quantity data and the second quantity data as the left-shift quantity information according to the conversion type information.

4. The data type conversion module according to claim 2, characterized in that: The right-shift data generating circuit comprises: a third detection circuit, a fourth detection circuit, a right-shifted data generating circuit, a second selection circuit and a direction determining circuit; The third detection circuit is used to obtain third leading 0 information and third quantity information according to the upper 8 bits of the input data except the sign bit, wherein the third quantity information is used to indicate the number of bits of the first data to be right-shifted when the data type of the input data is converted from a 32-bit integer to a single-precision floating point type and the absolute value of the input data is not less than 2 to the 24th power; The fourth detection circuit is used to obtain fourth leading 0 information and fourth quantity information according to the upper 4 bits of the input data except the sign bit, wherein the fourth quantity information is used to indicate the number of bits of the first data to be right-shifted when the data type of the input data is converted from a 32-bit integer to a half-precision floating point type and the absolute value of the input data is not less than 2 to the 11th power; The right shift bit number generating circuit is used to generate fifth quantity information according to the upper 8 bits of the input data except the sign bit, and the fifth quantity information is used to indicate the number of bits of the first data right shifted when the data type of the input data is converted from single-precision floating point type to half-precision floating point type; The right shift bit number generating circuit is further used to generate sixth quantity information and first indication information according to the upper 8 bits of the input data except the sign bit, the sixth quantity information is used to indicate the number of bits of the first data right shift when the data type of the input data is converted from a single-precision floating point type to a 32-bit integer type and the absolute value of the input data is not greater than 2 to the power of 24, and the first indication information is used to indicate whether the absolute value of the input data is not greater than 2 to the power of 24 when the data type of the input data is a single-precision floating point type; The right shift bit number generating circuit is further used to generate seventh quantity information and second indication information according to the upper 5 bits of the input data except the sign bit, the seventh quantity information is used to indicate the number of bits of the first data right shift when the data type of the input data is converted from a half-precision floating point type to a 32-bit integer type and the absolute value of the input data is not greater than 2 to the 11th power, and the second indication information is used to indicate whether the absolute value of the input data is not greater than 2 to the 11th power when the data type of the input data is a half-precision floating point type; The second selection circuit is used to select one of the third quantity information, the fourth quantity information, the fifth quantity information, the sixth quantity information and the seventh quantity information as the right shift quantity information according to the conversion type information and the data type of the input data; The second selection circuit is further used to select one of the third leading 0 information and the fourth leading 0 information as the right-shifted leading 0 information according to the conversion type information; The direction determination circuit is used to determine the shift direction information according to the right shift leading 0 information, the first indication information, the second indication information, the conversion type information and the data type of the input data.

5. The data type conversion module according to claim 4, characterized in that: The third detection circuit is used for: When the sign bit of the input data is 1, a leading 0 detection is performed on the upper 8 bits of the inverted input data except the sign bit to obtain the third leading 0 information; or, When the sign bit of the input data is 0, performing leading 0 detection on the upper 8 bits of the input data except the sign bit to obtain the third leading 0 information; The third leading 0 information is inverted to obtain the third quantity information.

6. The data type conversion module according to claim 2, characterized in that: The shift circuit comprises: a left shift circuit and a right shift circuit; The left shift circuit is used to perform a left shift process on the first data according to the left shift amount information to obtain the left-shifted first data; The left shift circuit is further used to obtain left shift error information according to the first data after the left shift, and the left shift error information is used to indicate whether there is an error in the left shift leading 0 information; The right shift circuit is used to perform right shift processing on the first data with rounding bits and sticky bits added according to the right shift amount information to obtain the first data after right shift; The right shift circuit is further used to obtain right shift error information according to the first data after the right shift, and the right shift error information is used to indicate whether there is an error in the right shift leading 0 information.

7. The data type conversion module according to claim 2, characterized in that: The exponent bit generation circuit comprises: a left shift exponent bit generation circuit, a right shift exponent bit generation circuit and a fourth selection circuit; The left-shift exponent bit generating circuit is used to generate left-shift exponent bit data according to the left-shift leading 0 information, the conversion type information, the input data and the data type of the input data; The right shift exponent bit generating circuit is used to generate right shift exponent bit data according to the right shift leading 0 information, the conversion type information, the input data and the data type of the input data; The fourth selection circuit is used to select one of the left-shifted exponent bit data and the right-shifted exponent bit data as the exponent bit data according to the shift direction information.

8. The data type conversion module according to claim 7, characterized in that: The left-shift exponent bit generating circuit is used for: When the data type of the first data is converted from a 32-bit integer to a single-precision floating point type, a first exponent value is obtained according to the left-shift leading 0 information and a first set value; or, When the data type of the first data is converted from a 32-bit integer to a half-precision floating point type, a first exponent value is obtained according to the left-shift leading 0 information and the second set value; or, When the data type of the first data is converted from a half-precision floating point type to a single-precision floating point type, a first exponent value is obtained according to the left-shift leading 0 information, high 5 bits of the input data excluding the sign bit, and a third set value; The first exponent value is used to generate the left-shifted exponent bit data.

9. The data type conversion module according to claim 8, characterized in that: The left-shift exponent bit generating circuit is further used for: In the case where there is an error in the left-shift leading 0 information, adding 1 to the first exponent value to obtain the left-shift exponent bit data; or, In the case that there is no error in the left-shifted leading 0 information, the first exponent value is determined as the left-shifted exponent bit data.

10. The data type conversion module according to claim 7, characterized in that: The right-shift exponent bit generating circuit is used for: When the data type of the first data is converted from a 32-bit integer to a single-precision floating point type, a second exponent value is obtained according to the right-shift leading 0 information and a fourth set value; or, When the data type of the first data is converted from a 32-bit integer to a half-precision floating point type, a second exponent value is obtained according to the right-shift leading 0 information and a fifth set value; or, When the data type of the first data is converted from a single-precision floating point type to a half-precision floating point type, a second exponent value is obtained according to the right-shift leading 0 information, the upper 8 bits of the input data excluding the sign bit, and a sixth set value; The second exponent value is used to generate the right-shifted exponent bit data.

11. The data type conversion module according to claim 10, characterized in that: The right-shift exponent bit generating circuit is further used for: In the case where there is an error in the right-shift leading 0 information or the third data overflows, adding 1 to the second exponent value to obtain the right-shift exponent bit data; or, When there is no error in the right-shifted leading 0 information and the third data does not overflow, the first exponent value is determined as the right-shifted exponent bit data.

12. The data type conversion module according to claim 1, characterized in that: The input selection circuit includes: an integer data processing circuit, a floating point data processing circuit and a third selection circuit; The integer data processing circuit is used to convert the input data into an absolute value form to obtain integer input data; The floating point data processing circuit is used to perform mantissa processing on the input data according to the data type of the input data to obtain mantissa input data; The third selection circuit is used to select one of the integer input data and the mantissa input data as the first data according to the data type of the input data.

13. The data type conversion module according to claim 12, characterized in that: The floating point data processing circuit is used for: When the data type of the input data is a single-precision floating point type, concatenate 1 with the lower 23 bits of the input data to obtain the mantissa input data; or; When the data type of the input data is not a single-precision floating point type, 1 is concatenated with the lower 10 bits of the input data to obtain the mantissa input data.

14. The data type conversion module according to claim 1, characterized in that: The rounding circuit includes: an inversion circuit, an addition circuit and an overflow judgment circuit; The inversion circuit is used to invert the second data according to the conversion type information and the sign bit of the input data to obtain intermediate data; The adding circuit is used to add the intermediate data according to the value of the protection bit, the value of the rounding bit and the value of the sticky bit corresponding to the second data to obtain the third data, wherein the protection bit refers to the lowest bit of the second data, and the rounding bit and the sticky bit are arranged in sequence after the protection bit and are used to record the data shifted out during the shifting process of the first data; The overflow judgment circuit is used to obtain overflow indication information according to the data type of the output data and the third data, and the overflow indication information is used to indicate whether the third data overflows.

15. The data type conversion module according to claim 14, characterized in that: The negation circuit is used for: When the data type of the input data is converted from a floating point type to an integer type and the sign bit of the input data is 1, inverting the second data to obtain the intermediate data; or, When the data type of the input data is not converted from a floating point type to an integer type, or the sign bit of the input data is 0, the second data is determined as the intermediate data.

16. The data type conversion module according to claim 14, characterized in that: The value-added circuit is used for: Determining whether the second data needs to be carried according to the value of the protection bit, the value of the rounding bit, and the value of the sticky bit; When the second data needs to be carried and the intermediate data is obtained by inverting the second data, determining the intermediate data as the third data; or, When the second data does not need to be carried and the intermediate data is obtained by inverting the second data, adding 1 to the value of the intermediate data to obtain the third data; or, When the second data needs to be carried and the intermediate data is the second data, adding 1 to the value of the intermediate data to obtain the third data; or, When the second data does not need to be carried and the intermediate data is the second data, the intermediate data is determined as the third data.

17. The data type conversion module according to claim 1, characterized in that: The output selection circuit is used for: When the data type of the output data is an integer, determining the third data as the output data; or, When the data type of the output data is a floating point type, concatenating the sign bit of the input data, the exponent bit data and the third data to obtain the output data; or, When the value of the input data overflows the numerical range corresponding to the data type of the output data, the maximum value of the data type in the overflow direction is determined as the output data.

18. A processor, characterized in that: The processor includes a data type conversion module as described in any one of claims 1 to 17.

19. A computer device, characterized in that: The computer device includes a processor, and the processor includes a data type conversion module as described in any one of claims 1 to 17.

20. A data type conversion method based on a data type conversion module, characterized in that: The data type conversion module includes: an input selection circuit, a shift data generation circuit, a shift circuit, a shift selection circuit, a rounding circuit, an exponent bit generation circuit and an output selection circuit; the method includes: The input selection circuit determines first data according to input data and a data type of the input data, wherein the first data is used for shift processing; The shift data generating circuit generates shift direction information, shift quantity information and leading zero information according to the input data, the data type of the input data and the conversion type information, wherein the conversion type information is used to indicate whether to convert the input data between two data types, the shift direction information is used to indicate the shift direction corresponding to the first data, the shift quantity information is used to indicate the number of bits to shift the first data, and the leading zero information is used to indicate the number of leading zeros of the first data; The shift circuit shifts the first data according to the shift quantity information to obtain the shifted first data; The shift selection circuit selects second data from the shifted first data according to the shift direction information, where the second data is obtained by shifting the first data according to the shift direction corresponding to the first data; The rounding circuit performs inversion and addition processing on the second data according to the conversion type information to obtain third data; The exponent bit generating circuit generates exponent bit data according to the shift direction information, the leading 0 information, the input data, the data type of the input data and the conversion type information; wherein the exponent bit data is used to indicate the exponent bit of the output data when the data type of the output data is a floating point number; The output selection circuit determines the output data according to the third data, the exponent bit data, the sign bit of the input data, and the data type of the output data.

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