Method and device for indicating fault state

Abstract

The invention provides a method and a device for indicating a fault state, which can improve the utilization rate of a logic channel. The method comprises: a first device determines N alignment mark (AM) groups, the N AM groups comprising first indication information, the first indication information being used for indicating fault states of R receiving logic channels of the first device, and each AM group in the N AM groups being composed of M pieces of AMGL information; in the ith period of N periods, the first device respectively sends M pieces of AMGL information forming the ith AM group to a second device on M sending logic channels, the N periods are in one-to-one correspondence with the N AM groups, and M is an integer greater than or equal to 1; the N AM groups are used for the second equipment to align data sent by the first equipment on the M sending logic channels through the N periods.

Description

[0001] This application is a divisional application. The application number of the original application is 201910480929.1, and the original application date is June 4, 2019. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of communications, and more particularly, to a method and device for indicating a fault state in the field of communications. Background Art

[0003] With the rapid development of network technology, the requirements for data transmission rate and transmission quality are getting higher and higher. Multi-lane (MLD) is generally used in Ethernet to achieve high-speed and high-quality transmission. However, when multi-channel data is transmitted, if some channels fail, all channels will be unavailable, which will reduce the utilization rate of the channels. In order to improve the utilization rate of the channels, it is necessary to isolate the faulty channels and continue to transmit data on the remaining channels. Generally, only the receiving end of the channel can detect alarms. Therefore, the sending end needs to know which channels of the receiving end are faulty, and take isolation measures for the faulty channels together with the receiving end to ensure the normal transmission of the remaining channels. Therefore, there is an urgent need for a method to enable the sending end to know the fault status of the channel to ensure the improvement of the utilization rate of the channel. Summary of the invention

[0004] The present application provides a method and device for indicating a fault status, which can improve the utilization rate of a channel.

[0005] In a first aspect, a method for indicating a fault status is provided, comprising: a first device determines N alignment marker (AM) groups, the N AM groups include first indication information, the first indication information is used to indicate a fault status of R receiving logical channels of the first device, each of the N AM groups is composed of M alignment marker group channel AMGL information; in the i-th cycle of N cycles, the first device sends M AMGL information constituting the i-th AM group to a second device on M sending logical channels, respectively, wherein the N cycles correspond one-to-one to the N AM groups, the N AM groups are used by the second device to align data sent by the first device on the M sending logical channels through the N cycles, M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

[0006] Therefore, in the embodiment of the present application, the fault state of the receiving logical channel of the first device is indicated by the first indication information in the AM group, so that the second device learns the fault state of the receiving logical channel of the first device, which helps the second device to process the sending logical channel corresponding to the faulty receiving logical channel of the first device, for example, to isolate or disconnect it. In this way, the first device and the second device can continue to send and receive data on the remaining logical channels without faults, so that the utilization rate of the logical channels can be improved. Furthermore, by indicating the fault state of the receiving logical channel of the first device through the first indication information in the AM group, additional signaling overhead can be avoided on the basis of compatibility with existing protocols.

[0007] One of the M sending logical channels sends one alignment marker group lane (AMGL) information, that is, the M sending logical channels correspond to the M AMGL information one by one. The M sending logical channels may be valid non-faulty sending logical channels.

[0008] One AM group can be sent through one cycle on M sending logical channels, and N AM groups can be sent through N cycles. When N=1, the first indication information included in one AM group sent through one cycle can indicate the fault status of R receiving logical channels of the first device; when N is greater than 1, the first indication information included in multiple AM ​​groups sent through multiple cycles can indicate the fault status of R receiving logical channels of the first device, that is, multiple AM ​​groups include one first indication information in total.

[0009] In some possible implementations, there is no limitation on the form of the first indication information. In other words, the first indication information carried in the N AM groups may be a value obtained without any operation based on the value indicating the fault status of the R receiving logical channels, or may be a value obtained after some operation. For example, the operation may be an exclusive OR operation or a scrambling operation.

[0010] In some possible implementations, the size relationship between R and M is not limited, and R can be greater than M, R can be smaller than M, or R can be equal to M.

[0011] In some possible implementations, the fault state may be a fault or no fault. In other words, the first indication information is used to indicate which receiving logical channels of the R receiving logical channels of the first device have faults and which have no faults. Optionally, the fault state of each of the R receiving logical channels is no fault, or the fault state of each of the R receiving logical channels is a fault, or the fault state of some of the R receiving logical channels is a fault and the fault state of the remaining logical channels is no fault.

[0012] In some possible implementations, each of the N AM groups may be composed of an integer number of code blocks, each code block has the same size, and the composition of each AM group is different at different Ethernet speeds. For example, for a 200G Ethernet interface, an AM group of the IEEE802.3 specification is composed of 4 257-bit code blocks. For another example, for a 400G Ethernet interface, an AM group of the IEEE802.3 specification is composed of 8 257-bit code blocks. For another example, for Ethernet interfaces of other speeds, an AM group is composed of several code blocks of several bits, and the composition of the AM group is determined according to specific needs.

[0013] In some possible implementations, each of the N AM groups may be composed of an integer number of code blocks, each code block has the same size, and each AM group includes a different number of code blocks in different situations, that is, the code blocks included in each AM group are related to the number of currently valid transmitting logical channels. For example, for 200G Ethernet speed, when all 8 transmitting logical channels are free of faults, an AM group is composed of 4 257-bit code blocks (M=8 at this time); when 3 of the 8 transmitting logical channels fail, there are only 5 valid logical channels. At this time, an AM group includes AMs of 5 transmitting logical channels, and the AM group can be reduced to 3 257-bit code blocks (M=5 at this time).

[0014] In some possible implementations, the first AMGL information among the M AMGL information includes a first alignment mark AM, the second AMGL information among the M AMGL information includes a second AM and a padding bit, the third AMGL information among the M AMGL information includes a third AM, a padding bit, and a status domain bit, and the first AM, the second AM, and the third AM include unique padding bits. That is, some of the AMGL information among the M AMGL information only includes AM, some of the AMGL information includes both AM and padding bits, and some of the AMGL information includes AM, padding bits, and status domain bits. In other words, for one cycle, some of the M sending logical channels only send AM, some of the sending logical channels send both AM and padding bits, and some of the sending logical channels send both AM, padding bits, and status domain bits. For example, for 200G or 400G Ethernet reception, some of the 8 or 16 sending logical channels only send AM, some of the sending logical channels send both AM and padding bits, and some of the sending logical channels send both AM, padding bits, and status domain bits.

[0015] In some possible implementations, the first AMGL information among the M AMGL information includes the fourth AM, and the second AMGL information among the M AMGL information includes the fifth AM and padding bits. That is, some of the AMGL information among the M AMGL information only includes AM, and some of the AMGL information includes both AM and padding bits. In other words, for one cycle, some of the M sending logical channels only send AM, and some of the sending logical channels send both AM and padding bits. For example, for a 100G Ethernet interface, some of the 4 sending logical channels only send AM, and some of the sending logical channels send both AM and padding bits.

[0016] In some possible implementations, an AM group includes at least one of the first AMGL information, the second AMGL information, and the third AMGL information.

[0017] In some possible implementations, Q AMGL information among the M AMGL information constituting each AM group among the N AM groups include the first indication information, wherein L·R=N·P·Q, P is the number of bits of each AMGL information among the Q AMGL information occupied by the first indication information, and L, P and Q are positive integers.

[0018] In some possible implementations, before the first device sends M AMGL information constituting the i-th AM group to the second device respectively on M sending logical channels, the method also includes: the first device sends M AMGL information constituting the first AM group to the second device respectively on the M sending logical channels, the first AM group includes second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, the first indication information is carried in the first bit field of the Q AMGL information, and the second indication information is carried in the first bit field of at least part of the AMGL information among the M AMGL information constituting the first AM group.

[0019] In some possible implementations, L=1, P=1, Q=1, and the first indication information is carried in the reserved bits of the status fields of the Q AMGL information. For example, N=4, R=4; for another example, N=8, R=8; for another example, N=16, R=16.

[0020] In some possible implementations, L=1, N=1, Q=1, and the first indication information is carried in the padding bits of the Q AMGL information. For example, P=4, R=4; for another example, P=8, R=8; for another example, P=16, R=16.

[0021] In some possible implementations, N=1, P=R, and the first indication information carries the padding bits of each AMGL information in the Q AMGL information. For example, P=8, Q=8, L=8; for another example, P=16, Q=16, L=16.

[0022] In some possible implementations, R=N·P, and the first indication information carries the padding bits of each AMGL information in the Q AMGL information. For example, L=16, Q=16, R=16, N=8, P=2; for another example, L=8, Q=8, R=8, N=4, P=2.

[0023] In some possible implementations, the padding bits are unique padding bits.

[0024] In some possible implementations, the first device sends M AMGL information constituting the i-th AM group to the second device on M sending logical channels respectively, including: the first device distributes the M AMGL information constituting the i-th AM group to the M sending logical channels; the first device sends the M AMGL information constituting the i-th AM group to the receiving physical channel of the second device on the sending physical channels corresponding to the M sending logical channels.

[0025] In some possible implementations, the M transmitting logical channels and the R receiving logical channels are physical coding sublayer channels PCSL or forward error correction channels FECL.

[0026] In a second aspect, a method for indicating a fault status is provided, comprising: in the i-th cycle of N cycles, a second device receives M AMGL information constituting the i-th AM group sent by a first device on M sending logical channels, the N AM groups corresponding to the N cycles include first indication information, the first indication information is used to indicate the fault status of R receiving logical channels of the first device, each AM group in the N AM groups is composed of M alignment mark group channel AMGL information, and the N AM groups are used by the second device to align the data sent by the first device on the M sending logical channels through the N cycles; the second device determines the faulty receiving logical channel among the R receiving logical channels according to the first indication information, M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

[0027] In some possible implementations, Q AMGL information out of the M AMGL information constituting each AM group out of the N AM groups include the first indication information, wherein L·R=N·P·Q, P is the number of bits of each AMGL information out of the Q AMGL information occupied by the first indication information, and L, P and Q are positive integers.

[0028] In some possible implementations, before the second device receives M pieces of AMGL information constituting the i-th AM group sent by the first device on M sending logical channels, the method further includes:

[0029] The second device receives M pieces of AMGL information constituting a first AM group respectively sent by the first device on the M sending logical channels, the first AM group includes second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, the first indication information is carried in a first bit field of the Q pieces of AMGL information, and the second indication information is carried in the first bit field of at least part of the AMGL information among the M pieces of AMGL information constituting the first AM group;

[0030] Among them, the second device receives M AMGL information constituting the i-th AM group sent by the first device on M sending logical channels, including: the second device receives the M AMGL information constituting the i-th AM group sent by the first device on M sending logical channels according to the second indication information.

[0031] In some possible implementations, L=1, P=1, Q=1, and the first indication information is carried in the reserved bits of the status fields of the Q AMGL information; wherein the second device determines the faulty receiving logical channel among the M receiving logical channels according to the first indication information, including: the second device determines the faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the reserved bits of the status fields of the Q AMGL information.

[0032] In some possible implementations, L=1, N=1, Q=1, and the first indication information is carried in the padding bits of the Q AMGL information; wherein the second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information, including:

[0033] The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the filling bits of the Q AMGL information.

[0034] In some possible implementations, N=1, P=R, and the first indication information carries the filling bit of each AMGL information in the Q AMGL information; wherein, the second device determines the faulty receiving logical channel in the M receiving logical channels according to the first indication information, including: the second device determines the faulty receiving logical channel in the M receiving logical channels according to the first indication information carried by the filling bit of each AMGL information in the Q AMGL information.

[0035] In some possible implementations, R=N·P, and the first indication information carries the padding bits of each AMGL information in the Q AMGL information;

[0036] The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information, including:

[0037] The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by a padding bit of each AMGL information in the Q AMGL information.

[0038] In some possible implementations, the padding bits are unique padding bits.

[0039] In some possible implementations, the second device receives M pieces of AMGL information constituting an i-th AM group and sent by the first device on M sending logical channels, including:

[0040] The second device receives, on a receiving physical channel, M pieces of AMGL information constituting an i-th AM group, which are sent by the first device on physical channels corresponding to the M sending logical channels;

[0041] The second device transmits the M AMGL information of the i-th AM group to the M receiving logical channels of the second device.

[0042] In some possible implementations, the M transmitting logical channels of the first device, the R receiving logical channels of the first device, and the M receiving logical channels of the second device are physical coding sublayer channels PCSL or forward error correction channels FECL.

[0043] In some possible implementations, the first AMGL information among the M AMGL information includes a first alignment mark AM, the second AMGL information among the M AMGL information includes a second AM and a padding bit, the third AMGL information among the M AMGL information includes a third AM, a padding bit and a status domain bit, and the first AM, the second AM and the third AM include a unique padding bit; or

[0044] The first AMGL information among the M AMGL information includes the fourth AM, and the second AMGL information among the M AMGL information includes the fifth AM and padding bits.

[0045] In a third aspect, the present application provides a device for indicating a fault state, which is used to implement the method in the first aspect and / or any possible implementation thereof. The device may be a network device, or a device in a network device, or a device that can be used in combination with a network device. In one design, the device may include a module corresponding to executing the method / operation / step / action described in the first aspect and / or any possible implementation thereof, and the module may be a hardware circuit, or software, or a combination of a hardware circuit and software. In one design, the device may include a processing unit and a transceiver unit.

[0046] In a fourth aspect, the present application provides a device for indicating a fault state, which is used to implement the method in the second aspect and / or any possible implementation thereof. The device may be a network device, or a device in a network device, or a device that can be used in combination with a network device. In one design, the device may include a module corresponding to executing the method / operation / step / action described in the second aspect and / or any possible implementation thereof, and the module may be a hardware circuit, or software, or a combination of a hardware circuit and software. In one design, the device may include a processing unit and a transceiver unit.

[0047] In a fifth aspect, the present application provides a device for indicating a fault state, the device comprising a processor for implementing the method described in the above first aspect and / or any possible implementation thereof. The device may also include a memory, optionally, the memory is used to store instructions, and when the processor executes the instructions stored in the memory, the method described in the above first aspect and / or any possible implementation thereof may be implemented. The device may also include a communication interface, the communication interface is used for the device to communicate with other devices, and illustratively, the communication interface may be a transceiver, circuit, bus, module, pin or other type of communication interface.

[0048] In a sixth aspect, the present application provides a device for indicating a fault state, the device comprising a processor for implementing the method described in the second aspect and / or any possible implementation thereof. The device may also include a memory, optionally, the memory is used to store instructions, and when the processor executes the instructions stored in the memory, the method described in the second aspect and / or any possible implementation thereof may be implemented. The device may also include a communication interface, and the communication interface is used for the device to communicate with other devices.

[0049] In a seventh aspect, the present application provides a system for indicating a fault state, the system comprising the device provided in the third aspect and the device provided in the fourth aspect; or

[0050] The system includes the device provided in the fifth aspect and the device provided in the sixth aspect;

[0051] In an eighth aspect, the present application provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the computer executes the method in the above aspects and any possible designs thereof.

[0052] In a ninth aspect, the present application provides a chip, including a processor. The processor is used to execute the method in the above aspects and any possible implementation thereof.

[0053] Optionally, the chip further includes a memory, and the memory is coupled to the processor.

[0054] Further optionally, the chip also includes a communication interface.

[0055] In a tenth aspect, the present application provides a computer program product, comprising a computer program code, which, when executed on a computer, enables the computer to execute the methods in the above aspects and any possible designs thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic diagram of the system architecture provided in an embodiment of the present application.

[0057] Figure 2 It is a schematic diagram of the processing process of the physical layer provided in an embodiment of the present application.

[0058] Figure 3 It is a format diagram of the AM of the 200G or 400G Ethernet technology provided in the embodiment of the present application.

[0059] Figure 4 This is a format diagram of the AM of the 100G Ethernet technology provided in an embodiment of the present application.

[0060] Figure 5 It is a schematic diagram of the physical channel and the logical channel provided in the embodiment of the present application.

[0061] Figure 6 It is a schematic diagram of a method for indicating a fault status provided in an embodiment of the present application.

[0062] Figure 7 It is a schematic block diagram of a device for indicating a fault status provided in an embodiment of the present application.

[0063] Figure 8 It is a schematic block diagram of another device for indicating a fault status provided by an embodiment of the present application.

[0064] Fig. 9 It is a schematic block diagram of another device for indicating a fault status provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] With the development of the network, the requirements for network traffic are getting higher and higher. For example, there are currently 100G (100,000 megabits per second), 200G (200,000 megabits per second) and 400G (400,000 megabits per second) Ethernet technologies. With the development of the network, higher requirements will be placed on Ethernet speed. Figure 1 In the system architecture diagram shown, the first device and the second device are connected through several physical channels, and multiple physical channels are transmitted in parallel, which can improve the speed of Ethernet. For example, the physical channel can be a high-speed bus, such as a physical medium such as copper wire or optical fiber, so that the first device and the second device can be electrically interconnected through copper wire. For example, for 200G Ethernet technology, the first device and the second device can be connected through 8 physical channels, 4 physical channels, 2 physical channels, or 1 physical channel; for another example, for 400G Ethernet technology, the first device and the second device can be connected through 16 physical channels, 8 physical channels, 4 physical channels, 2 physical channels, or 1 physical channel. For another example, for 100G Ethernet technology, the first device and the second device are connected through 4 physical channels, 2 physical channels, or 1 physical channel.

[0066] The first device and the second device can be chips or units or physical devices with transceiver functions. If the first device sends data, the second device receives the data; if the second device sends data, the first device receives the data, and the first device's sending physical channel corresponds to the second device's receiving physical channel one-to-one; the second device's sending physical channel corresponds to the first device's receiving physical channel one-to-one. The following description takes the first device as the sending end and the second device as the receiving end as an example.

[0067] In Ethernet technology, data processing is mainly divided into data link layer and physical layer processing. The embodiments of the present application relate to the processing of the physical layer. Figure 2 The following is a schematic diagram of the processing process of the physical layer provided in the embodiment of the present application. Figure 2As shown, the first device receives an Ethernet frame from the data link layer, and the Ethernet frame reaches the media access control (MAC) layer and the coordination sublayer (RS). The MAC layer verifies the Ethernet frame, and the verified bits are sent to the physical coding sublayer (PCS) sublayer through the RS sublayer according to some kind of media independent interface (xMII). The PCS sublayer receives the relevant bits from the xMII and encodes and rate matches according to a specific first size bit block. After encoding and rate matching, the code block of the first size bit block is further encoded into a serial code block stream of the second size bit block according to the encoding rule. The serial code block stream of the second size bit block is inserted with an alignment marker (AM) group after scrambling. The AM group also contains several second size bit blocks. After inserting the AM group, forward error correction (FEC) encoding is performed on the serial multiple second-size bit blocks and check bits are added. Then, the second-size bit block code blocks are distributed to several physical coding sublayer channels (physical coding sublayer lanes, PCSL) or forward error correction coding channels (forwarding error correction lanes, FECL) according to a certain number of bits through distribution and interleaving. Each AMGL information that constitutes the AM group will be distributed on each PCSL or FECL. The bits on the PCSL or FECL can be sent to the second device through the physical medium access sublayer (physical medium attachment, PMA) and the physical medium dependent sublayer (physical medium dependent). For example, the aforementioned physical channel can be Figure 2 The part where the PMA is connected to the PMD and the PMD can be called a physical channel. The second device receives the bits sent by the first device through the PMD and PMA, and uses the AMGL on each PCSL or FECL to first lock and then align the channels. After alignment, the channels are reordered, and then the data on the ordered channels are taken out in sequence to obtain a serial bit stream, and then the serial bit stream is FEC decoded to form a serial code block stream of bit blocks of the second size, and the AM group in the serial code block stream is removed, and then the serial code block stream after the AM group is removed is descrambled and reversely transcoded to obtain a serial code block stream of bit blocks of the first size, and the serial code block stream of the first size bit blocks is decoded and rate matched and sent to the RS sublayer and MAC layer, and the data is transmitted to the data link layer through the MAC layer.

[0068] Figure 2 In the description, different Ethernet technologies have different first-size bit blocks and second-size bit blocks. For example, for 200G or 400G, the first-size bit block is 64 bits (bit, B) / 66B, the second-size bit block is 256B / 257B, and the AM group consists of 4 or 8 257B code blocks. For 100G, the first-size bit block is 64B / 66B, the second-size bit block is 256B / 257B, and the AM group consists of 5 257B code blocks.

[0069] It should be noted that for ease of understanding, Figure 2 The processing flow of the Ethernet interface is only briefly described. In specific applications, other processing processes may be added, or the above processing processes may not be included. For example, for 40G and 100G Ethernet interfaces, the processes of 256B / 257B transcoding, FEC encoding, and FEC decoding may not be included. For different Ethernet technologies, the processing process is different. For example, for 200G and 400G Ethernet technologies, the processes of FEC encoding and FEC decoding may be included, and FEC is located inside the PCS sublayer. For 40G and 100G Ethernet technologies, the processes of 256B / 257B transcoding, FEC encoding, and FEC decoding may be included, or the processes of 256B / 257B transcoding, FEC encoding, and FEC decoding may not be included. When 40G and 100G Ethernet technologies include the processes of 256B / 257B transcoding, FEC encoding, and FEC decoding, the FEC sublayer is located between the PCS and PMA sublayers as an independent sublayer.

[0070] The following is a brief description of the terms used in the embodiments of the present application.

[0071] AM group, an AM group can be several 257B code blocks. An AM group consists of M AMGL information, a transmission logical channel can send one AMGL information, and M transmission logical channels can send M AMGL information. For example, for 200G Ethernet technology, the AM group is 4 257B code blocks, and the 4 257B code blocks are composed of 8 120-bit and 65-bit padding bits and 3-bit status fields (4*257=120*8+65+3), where the 3-bit status field includes 1-bit reserved bit; for another example, for 400G Ethernet technology, the AM group is 8 257B code blocks, and the 8 257B code blocks are composed of 16 120-bit and 133-bit padding bits and 3-bit status fields (8*257=120*16+133+3), where the 3-bit status field includes 1-bit reserved bit. For another example, for 100G Ethernet technology, an AM group is 5 257B code blocks, and the 5 257B code blocks are composed of 20 64-bit bits and 5 padding bits (5*257=20*64+5).

[0072] For 200G and 400G Ethernet technologies, several 257B code blocks of the AM group are distributed to multiple logical channels according to symbols (10 bits). For example, for a 200G Ethernet interface, the 4 257B code blocks of the AM group consist of 8 120-bit blocks, 65-bit padding bits, and 3-bit status fields (4*257=120*8+65+3), as shown in Table 1. i To represent a symbol (10 bits), the first 10 bits (a0) of the 8 120 bits are distributed to the sending logical channel with channel number 0, the second 10 bits (a1) are distributed to the sending logical channel with channel number 1, and so on. The eighth 10 bits (a7) are distributed to the sending logical channel with channel number 7, and the ninth 10 bits (a8) are distributed to the sending logical channel with channel number 0, and so on. The 8 120 bits (a 0， ……a 95 ) is distributed to the first 11 symbols of each transmit logical channel. Then the first 10 bits (a 96 ) is distributed to the sending logical channel with channel number 0. The second 10 bits (a 97 ) is distributed to the sending logical channel with channel number 1. The third 10 bits (a 98 ) is distributed to the sending logical channel with channel number 2. The fourth 10 bits (a 99 ) is distributed to the sending logical channel with channel number 3, and the fifth 10 bits (a 100 ) is distributed to the sending logical channel with channel number 4, and the sixth 10 bits (a 101) is distributed to the sending logical channel with channel number 5. In this way, 60 bits of the 65-bit padding bits have been distributed to the first 6 channels, and the remaining 5 bits of padding bits and 3 bits of status field are distributed to the sending logical channel with channel number 6, that is, a 102 It includes 5 bits of padding bits and 3 bits of status field. That is, a0, a8, ... a are sent on the sending logical channel with channel number 0. 88 、a 96， a0, a8...a 88 、a 96 It can be called an AMGL message, where a0, a8, ... a 88 It can be called an AM, a 96 The sending logical channel with channel number 1 sends a1, a9, ... a 89 、a 97， a1, a9...a 89 、a 97 It can be called an AMGL message, where a1, a9, ... 89 It can be called an AM, a 97 The sending logic channel with channel number 2 sends a2 and a 10 ……a 90 、a 98， a2、a 10 ……a 90 、a 98 It can be called an AMGL message, where a2, a 10 ……a 90 It can be called an AM, a 98 The sending logic channel with channel number 3 sends a3 and a 11 ……a 91 、a 99， a3、a 11 ……a 91 、a 99 It can be called an AMGL message, where a3, a 11 ……a 91 It can be called an AM, a 99 The sending logic channel with channel number 4 sends a4 and a 12 ……a 92 、a 100， a4、a 12 ……a 92 、a 100 It can be called an AMGL message, where a4, a 12 ……a 92 It can be called an AM, a 100The sending logic channel with channel number 5 sends a5 and a 13 ……a 93 、a 101， a5、a 13 ……a 93 、a 101 It can be called an AMGL message, where a5, a 13 ……a 93 It can be called an AM, a 101 The sending logic channel with channel number 6 sends a6 and a 14 ……a 94 、a 102， a6、a 14 ……a 94 、a 102 It can be called an AMGL message, where a6, a 14 ……a 94 It can be called an AM, a 102 It consists of 8 bits in total, including 5 bits of padding and 3 bits of status field. 15 ……a 95， a7、a 15 ……a 95 It can be called an AMGL message, which only includes an AM of a7, a 15 ……a 95 .

[0073] Table 1

[0074]

[0075]

[0076] The AMGL information sent on each transmit logical channel includes AM. For 200G and 400G Ethernet technologies, the format of AM is as follows: Figure 3As shown, CM in CM0, CM1, CM2, CM3, CM4 and CM5 represents a common marker. UM in UM0, UM1, UM2, UM3, UM4 and UM5 represents a unique marker. UP in UP0, UP1 and UP2 represents unique padding. UP0, UP1, UP2 carry unique padding bits and each occupies 8 bits. In each transmitting logical channel, CM0, CM1, CM2, CM3, CM4 and CM5 are the same. The UM0, UM1, UM2, UM3, UM4 and UM5 of any two transmitting logical channels and UP0, UP1 and UP2 are different. UM0, UM1, UM2, UM3, UM4 and UM5 are used to uniquely identify an AM. For 100G and 40G Ethernet technologies, the format of AM is as follows Figure 4 As shown, M in M0, M1, M2, M3, M4, M0, M5, and M6 represents a marker, and BIP in BIP3 and BIP7 represents a bit interleave parity. BIP3 or BIP7 can also be a padding field.

[0077] The forms of AM of Ethernet technologies of other speeds are similar to those of 200G and 400G, or may vary from those of 200G and 400G. To avoid redundancy, examples are not given here one by one.

[0078] The form of the AM group for 100G Ethernet technology is similar to that of the AM group for 200G and 400G. The difference is that for 100G Ethernet technology, the AM group is 5 257B, and the 5 257B consists of 20 64-bit and 5-bit padding bits (5*257=20*64+5), that is, in 100G Ethernet technology, the AMGL information distributed on the sending logical channel does not include the status field. In other words, some AMGL information distributed on the sending logical channel includes AM, and some AMGL information distributed on the sending logical channel includes AM and padding bits. If the 100G Ethernet technology does not include the FEC encoding and FEC decoding process, it is distributed to each sending logical channel in units of 64B.

[0079] The forms of AM groups of Ethernet technologies of other speeds are similar to those of 200G and 400G, or may vary from those of 200G and 400G. To avoid redundancy, examples are not given here one by one.

[0080] Logical channel. The logical channel in this application may refer to a physical coding sublayer lane (PCSL) or a forward error correction lane (FECL). For example, for 200G and 400G Ethernet interfaces, the logical channel may be referred to as PCSL or FECL. For another example, for a 100G (without FEC) Ethernet interface, the logical channel may be referred to as a PCSL channel; for a 100G (with FEC) Ethernet interface, the logical channel may be referred to as a FECL channel.

[0081] Physical channel, the physical channel is connected to the logical channel through an electrical bus, and the physical channel can be a high-speed bus. For example, the physical channel can be Figure 2 The part where the PMA and PMD are connected and the PMD can be called a physical channel.

[0082] The correspondence between the physical channels and logical channels of the first device and the second device can be that a logical channels correspond to b physical channels, a=b*c, a, b, c are positive integers, c logical channels correspond to one physical channel, and the distributor of the first device distributes the code block stream to each logical channel according to the symbol. If one or more logical channels correspond to one physical channel, the data on the logical channel can be sent to the corresponding physical channel. The second device receives the data sent by the b physical channels of the first device through b physical channels, and then the receiver distributes the data of one physical channel to c logical channels. For example, Figure 5 As shown, for a 200G Ethernet interface, there can be 8 parallel logical channels, and the bits on two logical channels can be distributed to one physical channel. Each logical channel transmits 25G of payload data. Two logical channels correspond to one physical channel, and one physical channel transmits 50G of payload data.

[0083] For the sending logical channels and receiving logical channels, if the first device has d sending logical channels and d receiving logical channels, then the second device has d receiving logical channels and d sending logical channels. The data on the d sending logical channels of the first device are sent to the d receiving logical channels of the second device, and the data on the d sending logical channels of the second device are sent to the d receiving logical channels of the first device. In other words, the number of sending and receiving logical channels of each device is the same, and the number of sending and receiving logical channels of the sending and receiving devices is the same. For example, if the first device has 4 sending logical channels, then the first device has 4 receiving logical channels, the second device has 4 receiving logical channels, and the second device has 4 sending logical channels.

[0084] In the existing Ethernet technology, if part of the receiving logical channel of the transmitting end or the receiving end fails, the entire link at both ends of the transmitting and receiving ends cannot transmit data, which will seriously reduce the utilization rate of the logical channel. Therefore, it is necessary for the transmitting and receiving ends to isolate the faulty transmitting and receiving logical channel and continue to use the non-faulty transmitting and receiving logical channel to transmit data. In view of this, when the receiving end detects a channel failure, the embodiment of the present application can use the AM group to carry the first indication information during transmission to indicate the fault state of its receiving logical channel at the other end. In this way, both ends of the transmitting and receiving ends can isolate or disconnect the faulty logical channel, thereby improving the utilization rate of the channel.

[0085] The following description is made by taking the transmitting end as the first device and the receiving end as the second device as an example.

[0086] Figure 6 A method 100 for indicating a fault state provided in an embodiment of the present application is shown. The method 100 includes:

[0087] S110, the first device determines N alignment mark AM groups, the N AM groups include first indication information, the first indication information is used to indicate the fault status of R receiving logical channels of the first device, and each of the N AM groups consists of M alignment mark group channel AMGL information.

[0088] Each of the N AM groups may be composed of an integer number of code blocks, each code block has the same size, and the composition of each AM group is different for different Ethernet speeds. For example, for a 200G Ethernet interface, an AM group is composed of 4 257-bit code blocks. For another example, for a 400G Ethernet interface, an AM group is composed of 8 257-bit code blocks. For another example, for a 100G Ethernet interface, an AM group is composed of 5 257-bit code blocks. For Ethernet interfaces of other speeds, an AM group is composed of several code blocks of several bits, and the composition of the AM group is determined according to specific needs.

[0089] It should be noted that the fault status can be a fault or no fault. In other words, the first indication information is used to indicate which receiving logical channels of the R receiving logical channels of the first device have faults and which have no faults. Optionally, the fault status of each of the R receiving logical channels is no fault, or the fault status of each of the R receiving logical channels is a fault, or the fault status of some of the R receiving logical channels is a fault and the fault status of the remaining logical channels is no fault.

[0090] It should also be noted that, from the aforementioned relationship between the physical channel and the logical channel, a physical channel failure can cause a logical channel failure, but a logical channel failure does not necessarily cause a physical channel failure. For example, if a logical channel corresponds to a physical channel, a physical channel failure can cause a logical channel failure, and a logical channel failure can also cause a physical channel failure. For another example, if two logical channels 1 and 2 correspond to a physical channel, a physical channel failure can cause both logical channels 1 and 2 to fail, but a failure in logical channel 1 will not affect the connection relationship between logical channel 2 and the physical channel. In other words, the failure of the logical channel mentioned in the embodiments of the present application may be a failure of the logical channel itself, or a failure of the logical channel caused by a physical channel failure.

[0091] Optionally, before S110, when the first device determines that there is a faulty receiving logical channel among the R receiving logical channels, the first device executes S110. Optionally, the first device may also trigger the execution of S120 according to a period or certain specific rules. In other words, the embodiment of the present application does not limit the conditions for triggering S110, and S110 may be triggered when the first device determines that there is a faulty receiving logical channel, or, regardless of whether there is a faulty receiving logical channel, S110 may be triggered according to certain rules or according to a specific time.

[0092] If the first device does not receive data from a certain receiving logical channel within a preset time, it can be regarded that the receiving logical channel has a fault. For example, the preset time can be a plurality of consecutive cycles.

[0093] S120, in the i-th cycle of N cycles, the first device sends M AMGL information constituting the i-th AM group to the second device on M sending logical channels respectively, and the second device receives the M AMGL information constituting the i-th AM group sent by the first device on the M sending logical channels, wherein the N cycles correspond one-to-one to the N AM groups, and the N AM groups are used by the second device to align the data sent by the first device on the M sending logical channels through the N cycles, M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

[0094] The first device and the second device execute S120 N times, and the AMGL information constituting the N AM groups can be sent to the second device. For the convenience of description, only the i-th cycle is described here. The actual sending process can be: in each cycle of the N cycles, the first device sends the M AMGL information constituting each AM group to the second device on the M sending logical channels. That is, the N AM groups sent through N cycles on the M sending logical channels can indicate the fault status of the R receiving logical channels of the first device.

[0095] As an optional embodiment, the M transmitting logical channels and the R receiving logical channels are PCSL or FECL.

[0096] As an optional embodiment, S120 includes: the first device distributes the M AMGL information constituting the i-th AM group to the M sending logical channels; the first device sends the M AMGL information constituting the i-th AM group to the receiving physical channel of the second device on the sending physical channels corresponding to the M sending logical channels. That is, according to the relationship between the aforementioned logical channels and physical channels, the first device needs to distribute the M AMGL information to the M sending logical channels first, and there is a corresponding relationship between the M sending logical channels and the physical channels. Correspondingly, the M AMGL information is sent to the receiving physical channel of the first device through the sending physical channels corresponding to the M sending logical channels, and the receiving physical channel of the first device transfers the M AMGL information to the corresponding logical channels.

[0097] It should be noted that one of the M sending logical channels sends one alignment marker group lane (AMGL) information, that is, the M sending logical channels correspond to the M AMGL information one by one.

[0098] It should also be noted that, on M sending logical channels, one AM group can be sent through one cycle, and N AM groups can be sent through N cycles. When N=1, that is, the first indication information included in one AM group sent through one cycle can indicate the fault status of R receiving logical channels of the first device; when N is greater than 1, that is, the first indication information included in multiple AM ​​groups sent through multiple cycles can indicate the fault status of R receiving logical channels of the first device, that is, multiple AM ​​groups include one first indication information in total.

[0099] The following describes the M AMGL information constituting an AM group in two cases.

[0100] Case 1: The first AMGL information in the M AMGL information includes the first alignment marker AM. The second AMGL information in the M AMGL information includes the second AM and padding bits. The third AMGL information in the M AMGL information includes the third AM, padding bits and status field bits. The first AM, the second AM and the third AM include unique padding bits, for example, the unique padding field is Figure 3UP0, UP1, UP2 in the M AMGL information. That is, some of the AMGL information in the M AMGL information only includes AM, some of the AMGL information includes both AM and padding bits, and some of the AMGL information includes AM, padding bits, and status domain bits. In other words, for one cycle, some of the M sending logical channels only send AM, some of the sending logical channels send both AM and padding bits, and some of the sending logical channels send both AM, padding bits, and status domain bits. For example, for 200G or 400G Ethernet reception, some of the 8 or 16 sending logical channels only send AM, some of the sending logical channels send both AM and padding bits, and some of the sending logical channels send both AM, padding bits, and status domain bits.

[0101] For example, the AMGL information sent on the sending logical channel with channel number 7 in Table 1 is the first AMGL information. The first AMGL information only includes an AM with the number of a7, a 15 ……a 95 For another example, the AMGL information sent on the sending logical channels with channel numbers 0-5 in Table 1 is the second AMGL information, and the second AMGL information includes both AM and padding bits. Taking the sending logical channel with channel number 0 as an example, the AMGL information sent on the sending logical channel with channel number 0 includes an AM of a0, a8...a 88 Also includes padding bits a 96 For another example, the AMGL information sent on the sending logical channel with channel number 6 in Table 1 is the third AMGL information, and the AMs included in the third AMGL information are a6, a 14 ……a 94 And the padding bits and status field bits included are a 102 .

[0102] Of course, in the case where an AM group includes the first AMGL information, the second AMGL information and the third AMGL information, optionally, an AM group includes at least one of the first AMGL information, the second AMGL information and the third AMGL information. That is, which AMGL information an AM group includes can be determined as needed.

[0103] In case 2, the first AMGL information in the M AMGL information includes the fourth AM, and the second AMGL information in the M AMGL information includes the fifth AM and padding bits. That is, some of the AMGL information in the M AMGL information only includes AM, and some of the AMGL information includes both AM and padding bits. In other words, for one cycle, some of the M sending logical channels only send AM, and some of the sending logical channels send both AM and padding bits.

[0104] For example, for a 100G Ethernet interface, some of the four sending logical channels send only AM, and some of the sending logical channels send both AM and padding bits.

[0105] Of course, the M AMGL information constituting an AM group is not limited to the above two cases, but may also be other cases, which is not limited in the embodiment of the present application.

[0106] In the embodiment of the present application, there is no limitation on the form of the first indication information. In other words, the first indication information carried in the N AM groups may be a value obtained without any operation based on the value indicating the fault status of the R receiving logical channels, or may be a value obtained after some operation. For example, the operation may be an XOR operation or a scrambling operation. The XOR operation or the scrambling operation is described below by example.

[0107] XOR operation:

[0108] For example, in 200G Ethernet technology, assuming that the first indication information is carried in the unique filling bit UP0 of the AM of each AMGL information, when the first indication information is not sent, the original code of UP0 of the AM in the AMGL information on the jth sending logical channel is UP0j, and when all of the 8 receiving logical channels are not faulty, the receiving logical channel status is Ls={0,0,0,0,0,0,0,0}, then the code of UP0 of the AM in the AMGL information on the jth sending logical channel constituting the first indication information becomes RLs=Ls⊕UP0j, that is, the code RLs=Ls⊕UP0j of UP0 on the jth sending logical channel is part of the first indication information (the jth sending logical channel and other sending logical channels are used to send the first indication information) or all (if only the jth sending logical channel is used to send the first indication information). For example, when the first indication information is not sent, the original code of UP0 of AM in the AMGL information on the jth sending logical channel is 0x05, then RLs = 0x00 ⊕ 0x05 = 0x05. For another example, when the first indication information is not sent, the original code of UP0 of AM in the AMGL information on the jth sending logical channel is 0x04, then RLs = 0x00 ⊕ 0x04 = 0x04. For another example, suppose that the second logical channel among the 8 sending logical channels is faulty. At this time, the fault status of the logical channel is Ls = {0,1,0,0,0,0,0,0,0}. When the first indication information is not sent, the original code of UP0 of AM in the AMGL information on the j-th sending logical channel is 0x05, then RLs = 0x02⊕0x05=0x07. When the second device receives the code of UP0 of AM in the AMGL information on the j-th sending logical channel as 0x07, the second device determines that the fault status of the receiving logical channel of the first device is RLs = 0x05⊕0x07=0x02 based on the original code of UP0 of AM in the AMGL information on the j-th sending logical channel as 0x05. The second device can know that the second device receiving logical channel of the first device is faulty.

[0109] Scrambling operation:

[0110] For example, in 200G Ethernet technology, assuming that the first indication information is carried in the unique filling bit UP0 of the AM of each AMGL information, the first device performs a scrambling operation on the values ​​of the fault status of the R receiving logical channels, for example, using the frame synchronization scrambling polynomial 1+X 6 +X7 (International Telecommunication Union Telecommunication Standardization Department 707 specification) performs scrambling operation on the values ​​of the fault status of R receiving logical channels, sends the scrambled values ​​to the corresponding sending logical channels, and the second device descrambles the scrambled values ​​to obtain the fault status of the R receiving logical channels.

[0111] The relationship between the first indication information and the N AM groups is introduced below in accordance with cases a), b), c), and d).

[0112] As an optional embodiment, Q AMGL information among the M AMGL information constituting each AM group in the N AM groups include the first indication information, wherein L·R=N·P·Q, P is the number of bits of each AMGL information in the Q AMGL information occupied by the first indication information, L, P and Q are positive integers, and optionally, L can be understood as the L-fold repetition rate of the fault state of the R receiving logical channels. It should be noted that the embodiment of the present application does not limit the relationship between L, R, P, N and Q, and the relationship L·R=N·P·Q may be satisfied, or it may not be satisfied. In actual applications, L, R, P, N and Q can be determined according to actual needs.

[0113] L, P, Q, R and N are discussed in the following situations:

[0114] a), L=1, P=1, Q=1. At this time, R=N, that is, only one bit in the AMGL information on a sending logical channel in one cycle indicates the fault state of a receiving logical channel. In other words, only one AMGL information among the M AMGL information constituting an AM group carries one bit of the first indication information to indicate the fault state of a receiving logical channel. Then, N cycles are required to indicate the fault states of R (R=N) receiving logical channels. For example, these N cycles can be N consecutive cycles or N cycles according to a certain rule, such as N cycles at equal intervals.

[0115] For example, for 100G Ethernet technology, there are 4 receiving FECLs, then an AMGL message of each AM group in the 4 AM groups of 4 cycles sent by the first device carries one bit of the first indication information, so that a total of 4 bits are used to indicate the fault status of the 4 receiving FECLs.

[0116] For another example, for 200G Ethernet technology, there are 8 receiving FECLs or PCSLs. Then an AMGL message of each AM group in the 8 AM groups of 8 cycles sent by the first device carries one bit of the first indication information. In this way, a total of 8 bits are used to indicate the fault status of the 8 receiving FECLs or PCSLs.

[0117] For another example, for 400G Ethernet technology, there are 16 receiving FECLs or PCSLs. Then an AMGL message of each AM group in the 16 AM groups of 16 cycles sent by the first device carries one bit of the first indication information. In this way, a total of 16 bits are used to indicate the fault status of the 16 receiving FECLs or PCSLs.

[0118] Optionally, in case a), the first indication information is carried in the reserved bits of the status field of the Q AMGL information. For example, for 200G Ethernet technology, bit

[1025] of an AM group is a reserved bit, and bit

[1025] of each AM group of N AM groups can be used to carry the fault status of R (R = N) receiving channels. Optionally, in case a), the first indication information is carried in the filling bits of the Q AMGL information. For example, the filling bit can be the only filling bit. That is, in case a), a total of N bits can carry the fault status of R (R = N) receiving logical channels through one bit in an AMGL information in each cycle in N cycles. The bit can be a reserved bit of the status, a filling bit, a only filling bit, or other bits. This is not limited to this embodiment of the present application.

[0119] b), L=1, N=1, Q=1, the first indication information is carried on the filling bits of the Q AMGL information. At this time, R=P, the fault status of R (R=P) receiving logical channels is indicated by P bits in the AMGL information on a sending logical channel in one cycle. In other words, only one AMGL information among the M AMGL information constituting an AM group carries P bits of the first indication information to indicate the fault status of R (R=P) receiving logical channels, and only one cycle is needed to indicate the fault status of R receiving logical channels.

[0120] For example, for 100G Ethernet technology, there are 4 receiving FECLs, and the 4 bits of one AMGL information in one AM group sent by the first device in one cycle indicate the fault status of the 4 receiving FECLs. For example, the filling bits [1280-1283] of one AM group are used to indicate the fault status of the 4 FECLs.

[0121] For another example, for 200G Ethernet technology, there are 8 receiving FECLs or PCSLs, then the 8 bits of an AMGL information of an AM group in one cycle sent by the first device indicate the fault status of the 8 receiving FECLs. For example, the filling bits bit[960-967] of an AM group are used to indicate the fault status of the 8 FECLs. For another example, the filling bits bit

[960] , bit

[970] , bit

[980] , bit

[990] , bit

[1000] , bit

[1010] , bit

[1020] and bit

[1023] of an AM group are used to indicate the fault status of the 8 FECLs. Alternatively, the UP0, UP1 or UP2 of an AM can be used to indicate the fault status of the 8 FECLs, where UP0, UP1 or UP2 is 8 bits.

[0122] For another example, for 400G Ethernet technology, there are 16 receiving FECLs or PCSLs, and the first device sends 16 bits of AMGL information of one AM group in one cycle to indicate the fault status of the 16 receiving FECLs or PCSLs. For example, the filling bits bit [1920-1935] or filling bits bit

[1920] , bit

[1930] , bit

[1940] , bit

[1950] , bit

[1960] , bit

[1970] , bit

[1980] , bit

[1990] , bit

[2000] , bit

[2010] , bit

[2020] , bit

[2030] , bit

[2040] , bit

[2050] , bit

[2051] and bit

[2052] of one AM group are used to indicate the fault status of the 16 FECLs. Alternatively, UP0 and UP1 (16 bits in total), or UP0 and UP2 (16 bits in total), or UP1 and UP2 (16 bits in total) of an AM may be used to indicate the fault status of 16 FECLs, wherein UP0 or UP1 or UP2 is 8 bits.

[0123] Optionally, in case b), the first indication information is carried on a padding bit of the Q AMGL information, and the padding bit may be the only padding bit.

[0124] In cases a) and b), a bit is used to indicate the fault status of a receiving logical channel. The fault status of multiple receiving logical channels can be indicated through multiple cycles in case a), or multiple bits of an AMGL information on a sending logical channel in one cycle in case b) can be used to indicate the fault status of multiple receiving logical channels. In the case that there is no fault in the sending logical channel, the method of cases a) and b) can not only indicate the fault status of multiple receiving logical channels, but also one logical channel is indicated by only one bit, which can save signaling overhead. However, in the case that the sending logical channel may also have a fault, that is, when several bits in the AMGL information on a certain sending logical channel indicate the fault status of the receiving logical channel, and the sending logical channel happens to also fail, it is possible that the second device cannot know the fault status of the receiving logical channel of the first device. Therefore, it is necessary to send the first indication information to the second device on multiple sending logical channels among the M sending logical channels. Therefore, the following cases c) and d) are derived.

[0125] c), N=1, P=R, the first indication information is carried by the filling bits of each AMGL information in the Q AMGL information, one AMGL information corresponds to one sending logical channel, in other words, the first indication information is carried by using the same number of filling bits (P=R) of the AMGL information on each sending logical channel in the Q sending logical channels in one cycle. At this time, L=Q, AMGL information is sent on several sending logical channels, and the second device can receive several times the repetition rate of the fault status of the R receiving logical channels.

[0126] For 200G Ethernet technology, there are 8 receiving FECLs or PCSLs. The first device sends 8 bits of part or all of the 8 AMGL information of an AM group in one cycle to indicate the fault status of the 8 receiving FECLs or PCSLs, as shown below:

[0127] Example 1: UP0, UP1 or UP2 of each of the 8 AMs of the 8 AMGL information constituting an AM group is used to indicate the fault status of 8 FECLs or PCSLs, wherein UP0, UP1 or UP2 is 8 bits, at which time Q=8, P=R=8, L=8, and in the case that there is no fault in the sending logical channel, the second device can receive 64 (8*8) bits of first indication information to indicate the fault status of the 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has an 8-fold repetition rate. If there is a fault in a sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 56 (7*8) bits of first indication information to indicate the fault status of the 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a 7-fold repetition rate.

[0128] In example 1, 8 bits may also be padding bits.

[0129] Example 2: 8 bits of UP0, UP1 or UP2 of each of the 4 AMs of the 4 AMGL information constituting an AM group are used to indicate the fault status of 8 FECLs or PCSLs, where UP0, UP1 or UP2 is 8 bits, and at this time Q=4, P=R=8, L=4. In the case that there is no fault in the sending logical channel, the second device can receive 32 bits of first indication information to indicate the fault status of the 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 4 times. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 24 bits of first indication information to indicate the fault status of the 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 3 times.

[0130] In Example 2, the 8 bits may also be padding bits.

[0131] Example 3: 8 bits of UP0, UP1 or UP2 of each AM in the 5 AMGL information of an AM group are used to indicate the fault status of 8 FECLs or PCSLs, where UP0, UP1 or UP2 is 8 bits. At this time, Q=5, P=R=8, and L=5. When there is no fault in the sending logical channel, the second device can receive 40 bits of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 5 times. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 32 bits of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 4 times.

[0132] In Example 3, the 8 bits may also be padding bits.

[0133] For 400G Ethernet technology, there are 16 receiving FECLs or PCSLs, and the first device sends 16 bits of part or all of the 16 AMGL information of one AM group in one cycle to indicate the fault status of the 16 receiving FECLs or PCSLs. For example:

[0134] Example 1: UP0 and UP1 (16 bits in total), or UP0 and UP2 (16 bits in total), or UP1 and UP2 (16 bits in total) of each of the 16 AMs of the 16 AMGL information constituting an AM group are used to indicate the fault status of 16 FECLs or PCSLs, wherein UP0 or UP1 or UP2 is 8 bits, at which time Q=16, P=R=16, and L=16. In the case where there is no fault in the sending logical channel, the second device can receive 256 (16*16) bits of first indication information to indicate the fault status of the 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 16 times. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 240 (16*15) bits of first indication information to indicate the fault status of the 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 15 times.

[0135] Example 2: UP0 and UP1 (16 bits in total), or UP0 and UP2 (16 bits in total), or UP1 and UP2 (16 bits in total) of each AM in 8 AMGL information of 16 AMGL information constituting an AM group are used to indicate the fault status of 16 FECLs or PCSLs, wherein UP0 or UP1 or UP2 is 8 bits, at this time Q=8, P=R=16, L=8, and in the case that there is no fault in the sending logical channel, the second device can receive 128 (16*8) bits of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has an 8-fold repetition rate. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 112 (16*7) bits of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a 7-fold repetition rate.

[0136] Example 3: UP0 and UP1 (16 bits in total), or UP0 and UP2 (16 bits in total), or UP1 and UP2 (16 bits in total) of each AM in 4 AMGL information of 16 AMGL information constituting an AM group are used to indicate the fault status of 16 FECLs or PCSLs, wherein UP0 or UP1 or UP2 is 8 bits, at this time Q=4, P=R=16, L=4, and in the case that there is no fault in the sending logical channel, the second device can receive 64 (16*4) bits of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 4 times. If there is a fault in a sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 48 (16*3) bits of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 3 times.

[0137] d) R = N·P, the first indication information carries the filling bits of each AMGL information in the Q AMGL information. One AMGL information corresponds to one sending logical channel. In other words, the P filling bits of the AMGL information on each sending logical channel in the Q sending logical channels are used in N cycles to carry the fault status of the R receiving logical channels. At this time, L = Q, and the AMGL information is sent on several sending logical channels, so the second device can receive several times the repetition rate of the fault status of the R receiving logical channels.

[0138] For 200G Ethernet technology, there are 8 receiving FECLs or PCSLs, and some or all of the bits of the 8 AMGL information of each AM group of N AM groups of N cycles sent by the first device indicate the fault status of the 8 receiving FECLs or PCSLs, as shown below:

[0139] Example 1: 2 bits of UP0 or UP1 or UP2 of each AM in the 8 AMs of the 8 AMGL information of each AM group constituting 4 AM groups are used to indicate the fault status of 8 FECLs or PCSLs, wherein UP0 or UP1 or UP2 is 8 bits, at this time R=8, Q=8, P=2, N=4, L=8, and in the case that there is no fault in the sending logical channel, the second device can receive 64 bits (8*2*4) of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has an 8-fold repetition rate. If there is a fault in a sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 56 (7*2*4) bits of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a 7-fold repetition rate.

[0140] In example 1, 2 bits may also be padding bits.

[0141] Example 2: 1 bit of each AM in the 8 AMs of the 8 AMGL information of each AM group constituting 8 AM groups is used (the 1 bit can be a filling bit, or the only filling bit or the reserved bit of the status field) to indicate the fault status of 8 FECLs or PCSLs. At this time, R=8, Q=8, P=1, N=8, L=8. In the case that there is no fault in the sending logical channel, the second device can receive 64 bits (8*1*8) of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has an 8-fold repetition rate. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 56 (8*2*7) bits of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a 7-fold repetition rate.

[0142] Example 3: 4 bits of UP0 or UP1 or UP2 of each of the 6 AMs in the 6 AMGL information of the 8 AMGL information of each AM group constituting 2 AM groups are used to indicate the fault status of 8 FECLs or PCSLs, wherein UP0 or UP1 or UP2 is 8 bits, at this time R=8, Q=6, P=4, N=2, L=6, and in the case that there is no fault in the sending logical channel, the second device can receive 48 bits (6*2*4) of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 6 times. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 40 (5*2*4) bits of first indication information to indicate the fault status of 8 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 5 times.

[0143] In Example 3, the 4 bits may also be padding bits.

[0144] For 400G Ethernet technology, there are 16 receiving FECLs or PCSLs, and some or all of the bits of the 16 AMGL information of each AM group of N AM groups of N cycles sent by the first device indicate the fault status of the 16 receiving FECLs or PCSLs, as shown below:

[0145] Example 1: 4 bits of UP0, UP1 or UP2 of each of the 16 AMGL information of 16 AMs of each AM group constituting 4 AM groups are used to indicate the fault status of 16 FECLs or PCSLs, wherein UP0, UP1 or UP2 is 8 bits, and at this time R=16, Q=16, P=4, N=4, L=16. In the case that there is no fault in the sending logical channel, the second device can receive 256 bits (4*4*16) of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 16 times. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 240 (4*4*15) bits of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 15 times.

[0146] In example 1, 4 bits may also be padding bits.

[0147] Example 2: Utilize 2 bits of UP0 or UP1 or UP2 of each AM in the 16 AMGL information of each AM group that constitutes 8 AM groups to indicate the fault status of 16 FECLs or PCSLs. At this time, R=16, Q=16, P=2, N=8, L=16. In the case that there is no fault in the sending logical channel, the second device can receive 256 bits (2*8*16) of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 16 times. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 240 (2*8*15) bits of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a repetition rate of 15 times.

[0148] In Example 2, the 4 bits may also be padding bits.

[0149] Example 3: 8 bits of UP0, UP1 or UP2 of each of the 8 AMs in 8 AMGL information of the 16 AMGL information of each AM group constituting 2 AM groups are used to indicate the fault status of 16 FECLs or PCSLs. At this time, R=16, Q=8, P=8, N=2, and L=8. In the case that there is no fault in the sending logical channel, the second device can receive 128 bits (2*8*8) of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has an 8-fold repetition rate. If there is a fault in one sending logical channel, the AMGL information sent on the sending logical channel cannot be received by the second device, and the second device can only receive 112 (2*8*7) bits of first indication information to indicate the fault status of 16 receiving FECLs or PCSLs, and the fault status of each receiving FECL or PCSL has a 7-fold repetition rate.

[0150] In Example 3, the 8 bits may also be padding bits.

[0151] As an optional embodiment, in the aforementioned case a), N=R, that is, the number of receiving logical channels is equal to the number of cycles. In case d), the number of receiving logical channels is equal to the number of cycles multiplied by the number of bits of the first indication information in each AMGL information. That is, as long as N in cases a) and d) is greater than 1, that is, the first device needs multiple cycles to send the first indication information to the second device, therefore, it is necessary to trigger the start of N cycles. Of course, when N is equal to 1, the start of N cycles can also be triggered. As an optional embodiment, before S120, the method also includes: the first device sends M AMGL information constituting a first AM group to the second device on the M sending logical channels respectively, the AM group includes the second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, the first indication information is carried in the first bit field of the Q AMGL information, and the second indication information is carried in the first bit field of at least part of the AMGL information in the M AMGL information constituting the first AM group. The first AM group does not belong to the aforementioned N AM groups, that is, before sending the first indication information, it is necessary to carry the second indication information in the first AM group to instruct the second device to receive the M AMGL information constituting the i-th AM group sent by the first device on M sending logical channels according to the second indication information, and obtain the first indication information in the M AMGL information.

[0152] For example, in the example of case a), the first indication information is carried in the reserved bits of the status field of the Q AMGL information, and the second indication information is also carried in the reserved bits of the Q AMGL information of the first AM group. One receiving logical channel corresponds to one bit, and the second indication information also occupies one bit. In the 100G example of case a), the first device uses 1 reserved bit in the status field of each AM group of 5 consecutive cycles of 5 AM groups, a total of 5 bit sequences to transmit "remote defect indication (RDI)" and send it to the second device. The first AM group of the 5 AM groups is the first AM group, and the remaining 4 AM groups are the aforementioned N AM groups, that is, N=4 at this time. 5-bit sequence: the first bit identifies the "start of the remote defect sequence", and the subsequent four bits represent the remote defect status of the 4 FECLs in order, "1" means a remote defect occurs, and "0" means no fault. In the 200G example of case a), the first device uses a reserved bit in the status field of 9 AM groups in 9 consecutive cycles to transmit a "remote defect indication" and send it to the second device. The first AM group of the 9 AM groups is the first AM group, and the remaining 8 AM groups are the aforementioned N AM groups, that is, N=8 at this time. 9-bit sequence: the first bit identifies the "start of the remote defect sequence", and the subsequent 8 bits represent the remote defect status of 8 FECLs or PCSLs in order, "1" indicates a remote defect occurs, and "0" indicates no fault. In the 400G example of case a), the first device uses a reserved bit in the status field of 17 AM groups in 17 consecutive cycles to transmit a "remote defect indication" and send it to the second device. The first AM group of the 17 AM groups is the first AM group, and the remaining 16 AM groups are the aforementioned N AM groups, that is, N=16 at this time. 17-bit sequence: the first bit identifies the "beginning of the remote defect sequence", and the subsequent 16 bits represent the remote defect status of 16 FECL or PCSL in order, "1" means a remote defect occurs, and "0" means no fault. The remote defect indication here. It can also be called a remote fault status indication. The remote defect indication here. It can also be called a remote fault status indication.

[0153] For example, in the example of case d), the first indication information carries the padding bit of each AMGL information in the Q AMGL information, and the second indication information also carries the unique padding bit of the Q AMGL information in the first AM group. The first indication information carries the unique padding bit of each AMGL information in the Q AMGL information, and the second indication information also carries the padding bit of the Q AMGL information in the first AM group. In the example 1 of 200G Ethernet in case d), the first device uses 2 bits of UP0 or UP1 or UP2 of each AM in 8 AMs of 8 AMGL information of each AM group of 5 AM groups in 5 consecutive cycles, and a total of 8 10-bit sequences are used to transmit the "remote defect indication" and send it to the second device. The first AM group of the 5 AM groups is the first AM group, and the remaining 4 AM groups are the aforementioned N AM groups, that is, N=4 at this time. Each 10-bit sequence: the first two bits indicate the "start of the remote defect sequence", and the subsequent 8 bits represent the remote defect status of 8 FECL or PCSL in order, "1" means a remote defect occurs, and "0" means no fault. In the second example of 200G Ethernet in case d), the first device uses 1 bit of each of the 8 AMs of the 8 AMGL information of each AM group of 9 AM groups in 9 consecutive cycles, and a total of 8 9-bit sequences are used to transmit the "remote defect indication (RDI)" and send it to the second device. The first AM group of the 9 AM groups is the first AM group, and the remaining 8 AM groups are the aforementioned N AM groups, that is, N = 8 at this time. For each 9-bit sequence: the first bit indicates the "start of the remote defect sequence", and the subsequent 8 bits represent the remote defect status of 8 FECL or PCSL in order, "1" means a remote defect occurs, and "0" means no fault. In the third example of 200G Ethernet in case d), the first device uses 4 bits of each of the 6 AMs of the 6 AMGL information of each AM group of 3 AM groups in 3 consecutive cycles, and a total of 6 12-bit sequences are used to transmit the "remote defect indication (RDI)" and send it to the second device. The first AM group of the 3 AM groups is the first AM group, and the remaining 2 AM groups are the aforementioned N AM groups, that is, N = 2 at this time. Each 8-bit sequence: the first 4 bits indicate the "start of the remote defect sequence", and the subsequent 8 bits represent the remote defect status of 8 FECL or PCSL in order, "1" means a remote defect occurs, and "0" means no fault.In the first example of 400G Ethernet in case d), the first device uses 4 bits of each of the 16 AMs of the 16 AMGL information of each AM group of 5 consecutive cycles, and a total of 16 20-bit sequences are used to transmit the "remote defect indication" and send it to the second device. The first AM group of the 5 AM groups is the first AM group, and the remaining 4 AM groups are the aforementioned N AM groups, that is, N = 4 at this time. Each 20-bit sequence: the first 4 bits indicate the "start of the remote defect sequence", and the subsequent 16 bits represent the remote defect status of 16 FECL or PCSL in order, "1" means a remote defect occurs, and "0" means no fault. In the second example of 400G Ethernet in case d), the first device uses 2 bits of each of the 16 AMs of the 16 AMGL information of each AM group of 9 AM groups in 9 consecutive cycles, and a total of 16 18-bit sequences are used to transmit the "remote defect indication" and send it to the second device. The first AM group of the 9 AM groups is the first AM group, and the remaining 8 AM groups are the aforementioned N AM groups, that is, N = 8 at this time. Each 18-bit sequence: the first 2 bits indicate the "start of the remote defect sequence", and the subsequent 16 bits represent the remote defect status of 16 FECL or PCSL in order, "1" means a remote defect occurs, and "0" means no fault. In the third example of 400G Ethernet in case d), the first device uses 8 bits of each of the 8 AMs of the 8 AMGL information of each AM group of 3 AM groups in 3 consecutive cycles, and a total of 16 24-bit sequences are used to transmit the "remote defect indication" and send it to the second device. The first AM group of the 3 AM groups is the first AM group, and the remaining 2 AM groups are the aforementioned N AM groups, that is, N = 2 at this time. Each 24-bit sequence: the first 8 bits indicate the "start of the remote defect sequence", and the subsequent 16 bits represent the remote defect status of 16 FECL or PCSL in order, "1" means a remote defect occurs, and "0" means no fault.

[0154] It should be noted that the aforementioned situations a), b), c) and d) are only described by way of example. The relationship between the first indication information and the N AM groups only needs to satisfy L·R=N·P·Q. The first indication information can be carried in the filling bit or the only filling bit of the AMGL information or the reserved bit of the status field as needed. The first indication information can also be carried in other bits of the AMGL information, and the embodiments of the present application are not limited thereto.

[0155] It should also be noted that, in order to save signaling overhead, one bit indicates the fault status of a receiving logical channel. In actual applications, several bits may indicate the fault status of a receiving logical channel, and the embodiments of the present application do not limit this.

[0156] The relationship between R and M is described in five cases below:

[0157] Case 1: If R is equal to M, that is, the first indication information included in the N AM groups sent on the M sending logical channels is used to indicate the fault status of the receiving logical channels with the same number as the sending logical channels. The first indication information is sent for the first time through method 100 to indicate the fault status of the R receiving logical channels for the first time. For example, R=M=8. When the first indication information in the N AM groups is sent for the first time, if the first indication information value is 00110000, it corresponds to the fault status of 8 receiving logical channels, where "0" indicates that the receiving logical channel has no fault and "1" indicates that the receiving logical channel has a fault, that is, the second device can determine the fault of the third and fourth (the first receiving logical channel corresponds to the first bit value of 00110000 from left to right, the second receiving logical channel corresponds to the third bit value of 00110000 from left to right...the eighth receiving logical channel corresponds to the eighth bit value of 00110000 from left to right) sending logical channels of the first device through the first indication information.

[0158] Case 2: If R is equal to M, and the fault states of the M receiving logical channels indicated previously were all fault-free, when the indication is continued next time, the fault states of the R receiving logical channels are continued to be indicated through the first indication information. For example, R=M=8, and the value of the first indication information is 00000000 in the last indication. The second device determines that none of the 8 receiving logical channels has a fault according to the first indication information. During this indication, if the value of the first indication information is 00110000, "0" indicates that the receiving logical channel has no fault, and "1" indicates that the receiving logical channel has a fault, that is, the second device can determine through the first indication information that the third and fourth (the first receiving logical channel corresponds to the first bit value of 00110000 from left to right, the second receiving logical channel corresponds to the third bit value of 00110000 from left to right...the eighth receiving logical channel corresponds to the eighth bit value of 00110000 from left to right) sending logical channels of the first device have faults.

[0159] Case three, if R is equal to M, in any process of indicating a fault status, the first indication information indicates the fault status of R receiving logical channels. Even if there is a receiving logical channel among the R receiving logical channels that has been processed or not processed for the fault indicated last time. If the value of the first indication information is 00110000, where "0" indicates that the receiving logical channel has no fault and "1" indicates that the receiving logical channel has a fault, that is, the second device can determine through the first indication information that the third and fourth (the first receiving logical channel corresponds to the first bit value of 00110000 from left to right, the second receiving logical channel corresponds to the third bit value of 00110000 from left to right... the eighth receiving logical channel corresponds to the eighth bit value of 00110000 from left to right) sending logical channels of the first device are faulty, the third sending logical channel may be a sending logical channel that has failed before and is still in a faulty state at this time, and the fourth sending logical channel may be the sending logical channel that has failed this time.

[0160] Case 4: If R is less than M, that is, at this time, MR receiving logical channels may be isolated due to a fault, that is, in a non-working state. When indicating, there is no need to indicate the fault state of the receiving logical channels in the isolated state, but only the fault state of the sending logical channels that have not been isolated. For example, M=8, R=6, and 2 receiving logical channels have been isolated in a faulty state. During this indication, the first indication information only needs to indicate the fault state of the 6 receiving logical channels that have not been isolated. The value of the first indication information is 110000, where "0" indicates that the receiving logical channel has no fault and "1" indicates that the receiving logical channel has a fault. That is, the second device can determine the fault of the first and second receiving (the first channel corresponds to the first bit value of 110000 from left to right, the second channel corresponds to the third bit value of 110000 from left to right...the sixth channel corresponds to the sixth bit value of 110000 from left to right) logical channels of the first device that have not been isolated through the first indication information.

[0161] Case 5: If R is greater than M, the first indication information sent by the sending logical channel that is less than the number of receiving logical channels can indicate the fault status of the sending logical channel. For example, for 200G Ethernet technology, R=8, M=6, at this time, there are only 6 valid non-faulty sending logical channels, and the first indication information needs to indicate the fault status of all receiving logical channels. The first indication information value is 00110000, where "0" indicates that the receiving logical channel has no fault, and "1" indicates that the receiving logical channel has a fault, that is, the second device can determine the fault of the third and fourth (the first receiving logical channel corresponds to the first bit value of 00110000 from left to right, the second receiving logical channel corresponds to the second bit value of 00110000 from left to right... the eighth channel corresponds to the eighth bit value of 00110000 from left to right) receiving logical channels of the first device through the first indication information. When the next indication occurs, if the fault of the third receiving logical channel of the first device disappears and the fault of the fourth receiving logical channel still exists, the value of the first indication information sent by the first device to the second device is 00010000. The second device can determine through the first indication information that the fault of the third logical channel of the first device disappears and the fault of the fourth receiving logical channel of the first device still exists.

[0162] S130: The second device determines a faulty receiving logical channel among the R receiving logical channels according to the first indication information.

[0163] Optionally, the method 100 further includes: the first device processes a faulty receiving logical channel among the R receiving logical channels; after S130, the second device processes a sending logical channel corresponding to the faulty receiving logical channel of the first device. In other words, if the receiving logical channel of the first device is faulty, the sending logical channel of the second device sending the receiving logical channel data to the first device can also be regarded as faulty and needs to be processed, that is, both the sending and receiving ends of the entire logical channel of the first device and the second device need to be processed. For example, the processing includes isolation or disconnection. Optionally, after the first device processes the faulty receiving logical channel and the second device processes the sending logical channel corresponding to the faulty receiving logical channel of the first device, it can be detected that the fault disappears, for example, the channel can be manually detected, and after the fault disappears, the first device and the second device are notified, that is, the faulty sending and receiving logical channel of the first device and the second device are notified that the faulty sending and receiving logical channel has been restored. For another example, the second device inserts a specified pseudo-random sequence into the sending logical channel corresponding to the faulty receiving logical channel of the first device. After the first device can detect a specific pseudo-random sequence in the faulty receiving logical channel, it can be considered that the fault of this sending and receiving logical channel disappears.

[0164] For example, for 200G Ethernet technology, the second device has 8 sending logical channels, and the first device has 8 receiving logical channels corresponding to the 8 sending logical channels of the second device. When the first device determines that the second receiving logical channel among the 8 receiving logical channels is faulty, the value of the first indication information sent to the second device is 01000000. After the second device obtains the first indication information, it determines its second sending logical channel corresponding to the second receiving logical channel of the first device as the faulty sending logical channel, that is, the second device does not send data on the second sending logical channel, and the first device does not receive data on the second receiving logical channel. The first device and the second device send and receive data on the remaining sending and receiving logical channels. After the fault of the second receiving logical channel disappears, the third receiving logical channel has a fault. The value of the first indication information sent by the first device to the second device is 00100000. After the second device obtains the first indication information, it determines the third sending logical channel corresponding to the third receiving logical channel of the first device as the faulty sending logical channel, that is, the second device does not send data on the third sending logical channel, and the first device does not receive data on the third receiving logical channel. The first device and the second device send and receive data on the remaining sending and receiving logical channels.

[0165] Combination of the above Figures 1 to 6 , describes in detail the method for indicating a fault state provided by an embodiment of the present application, and the following is combined with Figures 7 to 9 , describes in detail a device for indicating a fault status provided in an embodiment of the present application.

[0166] Figure 7 A schematic block diagram of a device 200 for indicating a fault state provided in an embodiment of the present application is shown. The device 200 may correspond to the first device described in the above method, or may correspond to a chip or component of the first device. In addition, each module or unit in the device 200 may be used to execute each action or processing process performed by the first device in the above method, such as Figure 7 As shown, the device 200 for indicating a fault state may include a processing unit 210 and a transceiver unit 220 .

[0167] The processing unit 210 is configured to determine N alignment mark AM groups, wherein the N AM groups include first indication information, wherein the first indication information is used to indicate a fault state of R receiving logical channels of the device, and each of the N AM groups is composed of M alignment mark group channel AMGL information;

[0168] The transceiver unit 220 is used to send M AMGL information constituting the i-th AM group to the second device on M sending logical channels in the i-th cycle of N cycles, wherein the N cycles correspond one-to-one to the N AM groups, and the N AM groups are used by the second device to align the data sent by the device on the M sending logical channels through the N cycles, M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

[0169] As an optional embodiment, Q AMGL information among the M AMGL information constituting each AM group in the N AM groups include the first indication information, wherein L·R=N·P·Q, P is the number of bits of each AMGL information among the Q AMGL information occupied by the first indication information, and L, P and Q are positive integers.

[0170] As an optional embodiment, the transceiver unit 220 is further configured to:

[0171] Before sending M AMGL information constituting the i-th AM group to the second device respectively on the M sending logical channels, M AMGL information constituting the first AM group are sent to the second device respectively on the M sending logical channels, the first AM group includes second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, the first indication information is carried in the first bit field of the Q AMGL information, and the second indication information is carried in the first bit field of at least part of the AMGL information among the M AMGL information constituting the first AM group.

[0172] As an optional embodiment, L=1, P=1, Q=1, and the first indication information is carried in the reserved bits of the status fields of the Q AMGL information.

[0173] As an optional embodiment, L=1, N=1, Q=1, and the first indication information is carried in the filling bits of the Q AMGL information.

[0174] As an optional embodiment, N=1, P=R, and the first indication information carries the padding bits of each AMGL information in the Q AMGL information.

[0175] As an optional embodiment, R=N·P, and the first indication information carries the padding bits of each AMGL information in the Q AMGL information.

[0176] As an optional embodiment, the padding bit is the only padding bit.

[0177] As an optional embodiment, the transceiver unit 220 is specifically used to: distribute the M AMGL information constituting the i-th AM group to the M sending logical channels; and send the M AMGL information constituting the i-th AM group to the receiving physical channel of the second device on the sending physical channels corresponding to the M sending logical channels.

[0178] As an optional embodiment, the M sending logical channels and the R receiving logical channels are physical coding sublayer channels PCSL or forward error correction channels FECL.

[0179] As an optional embodiment, the first AMGL information among the M AMGL information includes a first alignment mark AM, the second AMGL information among the M AMGL information includes a second AM and a padding bit, the third AMGL information among the M AMGL information includes a third AM, a padding bit and a status domain bit, and the first AM, the second AM and the third AM include a unique padding bit; or

[0180] The first AMGL information among the M AMGL information includes the fourth AM, and the second AMGL information among the M AMGL information includes the fifth AM and padding bits.

[0181] It should be understood that the specific process of each unit in the device 200 executing the above corresponding steps can be found in the description of the method embodiment in the previous text, and for the sake of brevity, it is not repeated here.

[0182] Figure 8 A schematic block diagram of a device 300 for indicating a fault state provided in an embodiment of the present application is shown. The device 300 may correspond to the second device described in the above method, or may correspond to a chip or component of the second device. In addition, each module or unit in the device 300 may be used to execute each action or processing process performed by the second device in the above method, such as Figure 8 As shown, the device 300 for indicating a fault state may include a transceiver unit 310 and a processing unit 320 .

[0183] The transceiver unit 310 is used to receive, in the i-th cycle of N cycles, M AMGL information constituting the i-th AM group sent by the first device on M sending logical channels, the N AM groups corresponding to the N cycles include first indication information, the first indication information is used to indicate the fault status of R receiving logical channels of the first device, each AM group in the N AM groups is composed of M alignment mark group channel AMGL information, and the N AM groups are used by the second device to align the data sent by the first device on the M sending logical channels through the N cycles;

[0184] The processing unit 320 is used to determine a faulty receiving logical channel among the R receiving logical channels according to the first indication information, where M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

[0185] As an optional embodiment, Q AMGL information among the M AMGL information constituting each AM group in the N AM groups include the first indication information, wherein L·R=N·P·Q, P is the number of bits of each AMGL information among the Q AMGL information occupied by the first indication information, and L, P and Q are positive integers.

[0186] As an optional embodiment, the transceiver unit 310 is further used to: before receiving the M AMGL information constituting the i-th AM group sent by the first device on the M sending logical channels, receive the M AMGL information constituting the first AM group respectively sent by the first device on the M sending logical channels, the first AM group includes second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, the first indication information is carried in the first bit field of the Q AMGL information, and the second indication information is carried in the first bit field of at least part of the AMGL information in the M AMGL information constituting the first AM group;

[0187] The processing unit 320 is specifically configured to: receive, according to the second indication information, M pieces of AMGL information constituting the i-th AM group and sent by the first device on M sending logical channels.

[0188] As an optional embodiment, L=1, P=1, Q=1, and the first indication information is carried in the reserved bits of the status fields of the Q AMGL information;

[0189] The processing unit 320 is specifically configured to determine a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the reserved bits of the status fields of the Q AMGL information.

[0190] As an optional embodiment, L=1, N=1, Q=1, and the first indication information is carried in the padding bits of the Q AMGL information;

[0191] The processing unit 320 is specifically configured to determine a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the filling bits of the Q AMGL information.

[0192] As an optional embodiment, N=1, P=R, and the first indication information carries the padding bits of each AMGL information in the Q AMGL information;

[0193] The processing unit 320 is specifically configured to determine a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the padding bit of each AMGL information among the Q AMGL information.

[0194] As an optional embodiment, R=N·P, and the first indication information carries the padding bits of each AMGL information in the Q AMGL information;

[0195] The processing unit 320 is specifically configured to determine a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the padding bit of each AMGL information among the Q AMGL information.

[0196] As an optional embodiment, the padding bit is the only padding bit.

[0197] As an optional embodiment, the transceiver unit 310 is specifically configured to:

[0198] receiving, on a receiving physical channel, M pieces of AMGL information constituting an i-th AM group, which are sent by the first device on physical channels corresponding to the M sending logical channels;

[0199] The M AMGL information of the i-th AM group is delivered to the M receiving logical channels of the second device.

[0200] As an optional embodiment, the M sending logical channels of the first device, the R receiving logical channels of the first device and the M receiving logical channels of the apparatus are physical coding sublayer channels PCSL or forward error correction channels FECL.

[0201] As an optional embodiment, the first AMGL information among the M AMGL information includes a first alignment mark AM, the second AMGL information among the M AMGL information includes a second AM and a padding bit, the third AMGL information among the M AMGL information includes a third AM, a padding bit and a status domain bit, and the first AM, the second AM and the third AM include a unique padding bit; or

[0202] The first AMGL information among the M AMGL information includes the fourth AM, and the second AMGL information among the M AMGL information includes the fifth AM and padding bits.

[0203] It should be understood that the specific process of each unit in the device 300 executing the above corresponding steps can be found in the description of the method embodiment in the previous text, and for the sake of brevity, it is not repeated here.

[0204] The device 200 of each of the above schemes has the function of implementing the corresponding steps performed by the first device in the above method, and the device 300 of each of the above schemes has the function of implementing the corresponding steps performed by the second device in the above method; the function can be implemented by hardware or software, or by hardware executing the corresponding software implementation. The hardware or software includes one or more modules corresponding to the above functions; for example, the sending unit can be replaced by a communication interface, the receiving unit can be replaced by a communication interface, and other units, such as the determination unit, can be replaced by a processor to respectively perform the sending and receiving operations and related processing operations in each method embodiment. In an embodiment of the present application, the communication interface of a device is used for the device to communicate with other devices. Exemplarily, the communication interface can be a transmitter, a receiver, a transceiver, a circuit, a bus, a module, a pin or other types of communication interfaces, which are not limited in the embodiments of the present application.

[0205] In the specific implementation process, the processor can be used to perform, for example, but not limited to, baseband related processing, and the communication interface can be used to perform, for example, but not limited to, information interaction. The above-mentioned devices can be respectively arranged on chips independent of each other, or at least partially or completely arranged on the same chip. For example, the processor can be further divided into an analog baseband processor and a digital baseband processor, wherein the analog baseband processor can be integrated with the communication interface on the same chip, and the digital baseband processor can be arranged on an independent chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with a variety of application processors (such as but not limited to a graphics processor, a multimedia processor, etc.) on the same chip. Such a chip can be called a system on chip (system on chip, SOC). Whether each device is independently arranged on different chips or integrated on one or more chips often depends on the specific needs of the product design. The embodiment of the present application does not limit the specific implementation form of the above-mentioned devices.

[0206] It can be understood that the processor involved in the aforementioned embodiment can execute program instructions through a hardware platform having a processor and a communication interface to respectively implement the functions involved in any design in the aforementioned embodiment of the present application. Based on this, Fig. 9As shown, an embodiment of the present application provides a schematic block diagram of a device 400 for indicating a fault state, and the device 400 includes: a processor 410, a communication interface 420, and a memory 430. Among them, the processor 410, the communication interface 420, and the memory 430 are coupled to communicate with each other, the memory 430 is used to store instructions, and the processor 410 is used to execute the instructions stored in the memory 430 to control the communication interface 420 to send signals and / or receive signals. The coupling in the embodiment of the present application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, and is used for information exchange between devices, units or modules.

[0207] Among them, in a possible implementation, if the device 400 is a first device, the processor 410 is used to determine N alignment mark AM groups, the N AM groups include first indication information, the first indication information is used to indicate the fault status of R receiving logical channels of the device, and each of the N AM groups is composed of M alignment mark group channel AMGL information; the communication interface 420 is used to send M AMGL information constituting the i-th AM group to the second device on M sending logical channels in the i-th cycle of N cycles, wherein the N cycles correspond one-to-one to the N AM groups, and the N AM groups are used by the second device to align the data sent by the device on the M sending logical channels through the N cycles, M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

[0208] In one possible implementation, if the apparatus 400 is a second device, the communication interface 420 is used to receive, in the i-th cycle of N cycles, M AMGL information constituting the i-th AM group sent by the first device on M sending logical channels, the N AM groups corresponding to the N cycles include first indication information, the first indication information is used to indicate the fault status of R receiving logical channels of the first device, each of the N AM groups is composed of M alignment mark group channel AMGL information, and the N AM groups are used by the second device to align the data sent by the first device on the M sending logical channels through the N cycles; the processor 410 is used to determine a faulty receiving logical channel among the R receiving logical channels according to the first indication information, M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

[0209] It should be understood that the embodiments of the present application Figure 7 Device in or Figure 8 The device can be Fig. 9 The device 400 in the embodiment is implemented and can be used to execute each step and / or process corresponding to the first device and the second device in the above method embodiment.

[0210] It is understandable that the methods, processes, operations or steps involved in the various designs described in the embodiments of the present application can be implemented in a one-to-one manner through computer software, electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. For example, considering the good versatility, low cost, and hardware and software decoupling, it can be implemented by executing program instructions. For example, considering the system performance and reliability, it can be implemented by using dedicated circuits. Ordinary technicians can use different methods to implement the described functions for each specific application, which is not limited here.

[0211] According to the method provided in the embodiment of the present application, the present application also provides a computer program product, which includes: computer program code, when the computer program code is run on a computer, the computer executes the method in the above embodiment. The various embodiments in the present application can also be combined with each other.

[0212] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable medium, which stores program code. When the program code runs on a computer, the computer executes the method in the above embodiments.

[0213] In the embodiments of the present application, it should be noted that the method embodiments described above in the embodiments of the present application can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In the implementation process, the steps of the method embodiments described above can be completed by hardware integrated logic circuits or software instructions in the processor. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0214] It can be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. There are many different types of RAM, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct rambus RAM (DRRAM).

[0215] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0216] The terms "first", "second", etc. that appear in this application are only used to distinguish different objects. "First" and "second" themselves do not limit the actual order or function of the objects they modify. Any embodiment or design described as "exemplary", "example", "for example", "optionally" or "in some implementations" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of these words is intended to present related concepts in a specific way.

[0217] Various messages / information / equipment / network elements / systems / devices / operations / and other objects that may appear in this application are named. It is understandable that these specific names do not constitute a limitation on the relevant objects. The names may change with factors such as scenarios, contexts, or usage habits. The understanding of the technical meaning of the technical terms in this application should be mainly determined from the functions and technical effects embodied / executed in the technical solutions.

[0218] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product may include one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital user (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic disk), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0219] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0220] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. In the embodiments of the present application, under the premise of no logical contradiction, the embodiments can be referenced to each other, for example, the methods and / or terms between the method embodiments can be referenced to each other, for example, the functions and / or terms between the device embodiments can be referenced to each other, for example, the functions and / or terms between the device embodiments and the method embodiments can be referenced to each other.

[0221] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0222] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0223] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0224] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for indicating a fault condition, characterized in that: include: The first device determines N alignment mark AM groups, the N AM groups include first indication information, the first indication information is used to indicate the fault status of R receiving logical channels of the first device, and each AM group in the N AM groups is composed of M alignment mark group channel AMGL information; In the i-th cycle of N cycles, the first device sends M AMGL information constituting the i-th AM group to the second device on M sending logical channels respectively, wherein the N cycles correspond one-to-one to the N AM groups, and the N AM groups are used by the second device to align the data sent by the first device on the M sending logical channels through the N cycles, M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

2. The method according to claim 1, characterized in that: Q AMGL information among the M AMGL information constituting each AM group among the N AM groups include the first indication information, wherein L·R=N·P·Q, P is the number of bits of each AMGL information among the Q AMGL information occupied by the first indication information, L, P and Q are positive integers, and L indicates the repetition rate of the fault status of the R receiving logical channels.

3. The method according to claim 1, characterized in that Q pieces of AMGL information among the M pieces of AMGL information constituting each AM group among the N AM groups include the first indication information, and before the first device sends the M pieces of AMGL information constituting the i-th AM group to the second device on the M sending logical channels respectively, the method further includes: The first device sends M AMGL information constituting a first AM group to the second device on the M sending logical channels respectively, the first AM group includes second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, the first indication information is carried in the first bit field of the Q AMGL information, and the second indication information is carried in the first bit field of at least part of the AMGL information among the M AMGL information constituting the first AM group.

4. The method according to claim 2, characterized in that: L=1, P=1, Q=1.

5. The method according to claim 4, characterized in that The first indication information is carried in the reserved bits of the status fields of the Q AMGL information.

6. The method according to claim 2, characterized in that L=1, N=1, Q=1.

7. The method according to claim 6, characterized in that The first indication information is carried in the filling bits of the Q AMGL information.

8. The method according to claim 2, characterized in that: N=1, P=R.

9. The method according to claim 8, characterized in that The first indication information carries the padding bits of each AMGL information in the Q AMGL information.

10. The method according to claim 2, characterized in that R=N·P.

11. The method according to claim 10, characterized in that The first indication information carries the padding bits of each AMGL information in the Q AMGL information.

12. The method according to any one of claims 1 to 11, characterized in that The first AMGL information among the M AMGL information includes a first alignment mark AM, the second AMGL information among the M AMGL information includes a second AM and a padding bit, the third AMGL information among the M AMGL information includes a third AM, a padding bit and a status domain bit, and the first AM, the second AM and the third AM include a unique padding bit; or The first AMGL information among the M AMGL information includes the fourth AM, and the second AMGL information among the M AMGL information includes the fifth AM and padding bits.

13. A method for indicating a fault condition, characterized in that: include: In the i-th cycle of N cycles, the second device receives M AMGL information constituting the i-th AM group sent by the first device on the M sending logical channels, the N AM groups corresponding to the N cycles include first indication information, the first indication information is used to indicate the fault status of the R receiving logical channels of the first device, each AM group in the N AM groups is composed of M alignment mark group channel AMGL information, and the N AM groups are used by the second device to align data sent by the first device on the M sending logical channels through the N cycles; The second device determines a faulty receiving logical channel among the R receiving logical channels according to the first indication information, where M, N and R are positive integers, and i is a positive integer greater than 0 and less than or equal to N.

14. The method according to claim 13, characterized in that Q AMGL information among the M AMGL information constituting each AM group among the N AM groups include the first indication information, wherein L·R=N·P·Q, P is the number of bits of each AMGL information among the Q AMGL information occupied by the first indication information, L, P and Q are positive integers, and L indicates the repetition rate of the fault status of the R receiving logical channels.

15. The method according to claim 13, characterized in that Q pieces of AMGL information among the M pieces of AMGL information constituting each AM group in the N AM groups include the first indication information, and before the second device receives the M pieces of AMGL information constituting the i-th AM group sent by the first device on the M transmission logical channels, the method further includes: The second device receives M pieces of AMGL information constituting a first AM group respectively sent by the first device on the M sending logical channels, the first AM group includes second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, the first indication information is carried in a first bit field of the Q pieces of AMGL information, and the second indication information is carried in the first bit field of at least part of the AMGL information among the M pieces of AMGL information constituting the first AM group; The second device receives M AMGL information constituting the i-th AM group sent by the first device on M sending logical channels, including: The second device receives, according to the second indication information, M pieces of AMGL information constituting the i-th AM group and sent by the first device on M sending logical channels.

16. The method according to claim 14, characterized in that L=1, P=1, Q=1.

17. The method according to claim 16, characterized in that The first indication information is carried in the reserved bit of the status field of the Q AMGL information; The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information, including: The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the reserved bits of the status fields of the Q AMGL information.

18. The method according to claim 14, characterized in that L=1, N=1, Q=1.

19. The method according to claim 18, characterized in that The first indication information is carried in the padding bits of the Q AMGL information; The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information, including: The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by the filling bits of the Q AMGL information.

20. The method according to claim 14, characterized in that N=1, P=R.

21. The method according to claim 20, characterized in that The first indication information carries a padding bit of each AMGL information in the Q AMGL information; The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information, including: The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by a padding bit of each AMGL information in the Q AMGL information.

22. The method according to claim 14, characterized in that R=N·P.

23. The method according to claim 22, characterized in that The first indication information carries a padding bit of each AMGL information in the Q AMGL information; The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information, including: The second device determines a faulty receiving logical channel among the M receiving logical channels according to the first indication information carried by a padding bit of each AMGL information in the Q AMGL information.

24. The method according to any one of claims 13 to 23, characterized in that The first AMGL information among the M AMGL information includes a first alignment mark AM, the second AMGL information among the M AMGL information includes a second AM and a padding bit, the third AMGL information among the M AMGL information includes a third AM, a padding bit and a status domain bit, and the first AM, the second AM and the third AM include a unique padding bit; or The first AMGL information among the M AMGL information includes the fourth AM, and the second AMGL information among the M AMGL information includes the fifth AM and padding bits.

25. A first device for indicating a fault condition, characterized in that: include: A processing unit, configured to perform processing-related operations in the method of any one of claims 1 to 12; A transceiver unit, used to perform operations related to receiving and / or sending in the method according to any one of claims 1 to 12.

26. A second device for indicating a fault condition, characterized in that: include: A processing unit, configured to perform processing-related operations in the method of any one of claims 13 to 24; A transceiver unit, used to perform operations related to receiving and / or sending in the method according to any one of claims 13 to 24.

27. A system, characterized in that: Includes the first device of claim 25 and the second device of claim 26.

28. A computer-readable storage medium storing computer instructions, which, when executed, cause a device to execute the method according to any one of claims 1 to 24.

29. A computer program product, comprising a computer program code, which, when executed, causes a device to perform the method according to any one of claims 1 to 24.

30. A chip comprising a processor, wherein the processor is configured to execute the method of any one of claims 1 to 24.

31. A method for indicating a fault condition, characterized in that: include: The first device determines N alignment mark AM groups, wherein the N AM groups include a first AM group; The first device sends M AMGL information constituting a first AM group to the second device on M sending logical channels respectively, the first AM group includes second indication information, the second indication information is used to indicate that the N AM groups include the first indication information, and the first indication information is used to indicate the fault status of R receiving logical channels of the first device.

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