Method and system for executing post quantum cryptography calculation task and terminal equipment

Abstract

The invention relates to the technical field of quantum cryptography, in particular to a post quantum cryptography calculation task execution method and system and terminal equipment, and the method comprises the steps: obtaining a post quantum cryptography calculation task instruction; field splitting is carried out on the post quantum cryptographic calculation task instruction to obtain a target field, and the target field is converted into a corresponding identifier based on a preset command identification table; matching a plurality of execution instructions corresponding to the identifier according to a data mapping rule, and combining the plurality of execution instructions into an instruction sequence; executing the instruction sequence to complete the post quantum cryptography calculation task; different instruction sets are converted by means of field splitting, identification conversion and data mapping rules, so that the converted instructions can be identified and executed by the post quantum cryptography chip; and meanwhile, when the main processor of the terminal equipment adapts to different post quantum cryptography chips, the use of different instruction sets can be met, the chip configuration process is simplified, and the chip integration convenience is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum cryptography, and in particular to a method, system and terminal device for executing a post-quantum cryptographic computing task. Background Art

[0002] Quantum computers are developing rapidly. In the next 10 to 30 years, quantum computing power that can crack the existing public key encryption system may appear. Post-quantum migration is already a problem that many countries and companies are solving. At present, the global Internet of Things is developing rapidly, not only covering daily life areas such as smart cities, smart medical care, Internet of Vehicles, and smart homes, but also developing rapidly in smart manufacturing, military and other fields. Most of the Internet of Things is connected by small terminal devices. These terminal devices do not have the ability to resist quantum computer attacks, resulting in poor data transmission security of terminal devices, which greatly affects the entire Internet of Things ecosystem. In order to enable terminal devices to have the ability to resist quantum computer attacks, we adopt the method of integrating post-quantum cryptographic chips on terminal devices. Different post-quantum cryptographic chips in the existing technology have different instruction sets. When the same main processor on the terminal device sends instructions for post-quantum cryptographic computing tasks to the post-quantum cryptographic chip, different instruction formats need to be used for different post-quantum cryptographic chips. When it is impossible to adapt to different post-quantum cryptographic chips, the instruction format is quickly switched. Summary of the invention

[0003] The present invention provides an integrated system and terminal device of a post-quantum cryptographic chip, which are used to solve the problem in the prior art that the main processor cannot quickly adapt to different instruction sets when adapting to different post-quantum cryptographic chips and cannot provide a general solution for chip integration.

[0004] The embodiment of this specification provides a method for executing a post-quantum cryptographic computing task, including:

[0005] Obtain post-quantum cryptographic computing task instructions;

[0006] Performing field splitting on the post-quantum cryptographic computing task instruction to obtain a target field;

[0007] Convert the target field into a corresponding identifier based on a preset command identification table;

[0008] Matching a plurality of execution instructions corresponding to the identifier according to a data mapping rule, and combining the plurality of execution instructions into an instruction sequence;

[0009] Execute the instruction sequence to complete the post-quantum cryptographic computing task.

[0010] Optionally, before obtaining the post-quantum cryptographic computing task instruction, the method further includes:

[0011] Establish the correspondence between identifiers and fields;

[0012] The corresponding relationship is stored in the form of the preset command identification table.

[0013] Optionally, before obtaining the post-quantum cryptographic computing task instruction, the method further includes:

[0014] Establishing a data mapping rule between an identifier and an execution instruction; wherein each identifier corresponds to a plurality of execution instructions having an execution order;

[0015] The data mapping rules are stored in the form of an instruction mapping table.

[0016] Optionally, the post-quantum cryptography computing task instruction is a quantum cryptography computing task instruction in a preset format, and the post-quantum cryptography computing task instruction consists of multiple fields.

[0017] Optionally, the step of performing field splitting on the post-quantum cryptographic computing task to obtain a target field includes:

[0018] The fields in the quantum cryptography calculation task of the preset format are offset according to the field length to split out the target field.

[0019] Optionally, matching a plurality of execution instructions corresponding to the identifier according to a data mapping rule includes:

[0020] According to the data mapping rule, a plurality of execution instructions corresponding to the identifier are matched in the instruction mapping table.

[0021] Optionally, combining a plurality of execution instructions into an instruction sequence includes:

[0022] The plurality of execution instructions are combined according to the execution order of the plurality of execution instructions to form an instruction sequence.

[0023] Optionally, after combining the plurality of execution instructions into an instruction sequence, the method further includes:

[0024] The instruction sequence is cached using a cache area.

[0025] The embodiment of this specification provides a system for executing a post-quantum cryptographic computing task, including:

[0026] A main processor, used to provide post-quantum cryptographic computing task instructions;

[0027] A preprocessing module, used for performing field splitting on the post-quantum cryptographic computing task instruction to obtain a target field;

[0028] A target field conversion module, used to convert the target field into a corresponding identifier based on a preset command identifier table;

[0029] An execution instruction matching module, used for matching a plurality of execution instructions corresponding to the identifier according to a data mapping rule, and combining the plurality of execution instructions into an instruction sequence;

[0030] A post-quantum cryptographic chip is used to execute the instruction sequence to complete the post-quantum cryptographic computing task.

[0031] An embodiment of the present specification provides a terminal device, including an execution system for applying the post-quantum cryptographic computing task as described above.

[0032] Its beneficial effect is that: the application first obtains the post-quantum cryptographic computing task instruction; then, the post-quantum cryptographic computing task instruction is field-splitting to obtain the target field, and the target field is converted into a corresponding identifier based on a preset command identification table; then, several execution instructions corresponding to the identifier are matched according to the data mapping rule, and several execution instructions are combined into an instruction sequence; finally, the instruction sequence is executed to complete the post-quantum cryptographic computing task. By utilizing field splitting, identification conversion and data mapping rules to realize the conversion of different instruction sets, the converted instructions can be recognized and executed by the post-quantum cryptographic chip; at the same time, when the main processor of the terminal device is adapted to different post-quantum cryptographic chips, it can meet the use of different instruction sets, simplify the chip configuration process, and improve the convenience of chip integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0034] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0035] Figure 1 A flowchart of a method for executing a post-quantum cryptographic computing task provided in an embodiment of this specification;

[0036] Figure 2 A schematic diagram of the structure of a post-quantum cryptographic computing task execution system provided in an embodiment of this specification;

[0037] Figure 3 A block diagram of the power consumption management structure of a system for executing a post-quantum cryptographic computing task provided in an embodiment of this specification;

[0038] Figure 4 A schematic diagram of the principle of a terminal device provided in an embodiment of this specification. DETAILED DESCRIPTION

[0039] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0040] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0041] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0042] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0043] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0044] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0045] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0046] Reference Figure 1 A flowchart of a method for executing a post-quantum cryptographic computing task provided in an embodiment of the present specification includes: S101: obtaining a post-quantum cryptographic computing task instruction; S102: performing field splitting on the post-quantum cryptographic computing task instruction to obtain a target field; S103: converting the target field into a corresponding identifier based on a preset command identification table; S104: matching a plurality of execution instructions corresponding to the identifier according to a data mapping rule, and combining the plurality of execution instructions into an instruction sequence; S105: executing the instruction sequence to complete the post-quantum cryptographic computing task.

[0047] In an optional embodiment, before obtaining the post-quantum cryptographic computing task instruction, it is necessary to first establish a correspondence between the identifier and the field, that is, each field has a corresponding identifier, for example, the identifier corresponding to the field "DSA1" is "0a0001", and the identifier corresponding to the field "key generation" is "0b0001". Then, according to the correspondence, it is stored in the form of a preset command identification table. The preset command identification table takes Table 1 as an example:

[0048] algorithm Logo operate Logo DSA1 0a0001 Key Generation 0b0001 DSA2 0a0002 Key derivation 0b0002 KEM1 0a1001 sign 0b0003 KEM2 0a1002 verify 0b0004 Encapsulation 0b0005 Decapsulation 0b0006

[0049] Table 1

[0050] The preset command identification table provides data support for the subsequent target field identification conversion, thereby realizing the conversion of different instruction sets, so that the converted instructions can be recognized and run by the post-quantum cryptographic chip, making the main processor universally applicable when facing chips with different instruction sets.

[0051] Afterwards, a data mapping rule between the identifier and the execution instruction is established; and the data mapping rule is stored in the form of an instruction mapping table. Each identifier corresponds to a number of execution instructions with an execution order. In order to realize the execution of the post-quantum cryptographic computing task instruction in the future, the data mapping rule between the identifier and the execution instruction can be used to match the execution instruction corresponding to the post-quantum cryptographic computing task instruction, and the execution instruction is used as the instruction executed by the post-quantum cryptographic chip. At this time, the execution instruction is an instruction that can be recognized by the post-quantum cryptographic chip, so it can be directly executed.

[0052] Specifically, when the main processor receives a post-quantum cryptographic computing task, it will send a post-quantum cryptographic computing task instruction to the post-quantum cryptographic chip. Before sending it to the post-quantum cryptographic chip, it needs to go through a preprocessing process, that is, first split the cryptographic computing task instruction into fields to obtain the target field. For example, if the target field is "DSA1", "DSA2", "KEM1", the target field can be converted into the corresponding identifier "0a0001", "0a0002", "KEM1" through the preset command identification table, where the name of the algorithm is not specifically written in Table 1. After the target field is converted into these identifiers, several execution instructions corresponding to the identifier are matched in the instruction mapping table according to the data mapping rules, and several execution instructions are combined into an instruction sequence, and then the instruction sequence is copied to the buffer. When the post-quantum cryptographic chip is ready, the instruction sequence is transmitted to the post-quantum cryptographic chip for execution, thereby completing the execution of the post-quantum cryptographic computing task. By using field splitting, identification conversion and data mapping rules to achieve the conversion of different instruction set architectures, the converted instructions can be recognized and run by the post-quantum cryptographic chip, so that the main processor has universal applicability when facing chips with different instruction sets.

[0053] Optionally, the post-quantum cryptography computing task instruction is a quantum cryptography computing task instruction in a preset format, and the post-quantum cryptography computing task instruction consists of multiple fields.

[0054] Specifically, the field splitting of the post-quantum cryptography computing task to obtain the target field includes: offsetting the field in the quantum cryptography computing task of the preset format according to the field length to split the target field. The post-quantum cryptography computing task instruction sent by the main processor has a fixed format. For example, the post-quantum cryptography computing task instruction is [op1, op2, addr1, addr2], with 4 fields, each with a fixed length. When the field is split, this instruction is offset according to the field length, and op1 and op2 are taken out to achieve the field splitting, thereby obtaining the target field. The acquisition of the target field is achieved in the above manner, providing support for the subsequent matching of the target field and the identifier.

[0055] Optionally, combining the plurality of execution instructions into an instruction sequence includes: combining the plurality of execution instructions into the instruction sequence according to an execution order of the plurality of execution instructions.

[0056] In an optional embodiment, the execution instructions have an execution order, and several execution instructions are combined according to the execution order of the several execution instructions to form an instruction sequence, and the instruction sequence is cached in a cache area. When the post-quantum cryptographic chip is ready, the instruction sequence is taken out from the cache area and several execution instructions in the instruction sequence are executed in sequence. After completing the execution of the quantum cryptographic calculation task instructions, the main processor has universal applicability when facing chips with different instruction sets.

[0057] Reference Figure 2 In the execution system of a post-quantum cryptographic computing task provided in the embodiment of this specification, the post-quantum cryptographic computing task instruction provided by the main processor 201 is first split into fields by the preprocessing module 202 to obtain the target field; then, the target field conversion module 203 converts the target field into a corresponding identifier based on the preset command identification table; thereafter, the execution instruction matching module 204 matches a number of execution instructions corresponding to the identifier according to the data mapping rule, and combines the several execution instructions into an instruction sequence; finally, the post-quantum cryptographic chip 205 executes the instruction sequence to complete the post-quantum cryptographic computing task. By utilizing field splitting, identification conversion and data mapping rules to realize the conversion of different instruction set architectures, the converted instructions can be recognized and run by the post-quantum cryptographic chip, so that the main processor has universal applicability when facing chips with different instruction sets.

[0058] Optionally, the system further includes:

[0059] A corresponding relationship establishing module, used for establishing a corresponding relationship between an identifier and a field;

[0060] The command identification table storage module is used to store the corresponding relationship in the form of the preset command identification table.

[0061] Optionally, the system further includes:

[0062] A data mapping rule establishment module, used to establish a data mapping rule between an identifier and an execution instruction; wherein each identifier corresponds to a plurality of execution instructions having an execution order;

[0063] The instruction mapping table storage module is used to store the data mapping rules in the form of an instruction mapping table.

[0064] Optionally, the post-quantum cryptography computing task instruction is a quantum cryptography computing task instruction in a preset format, and the post-quantum cryptography computing task instruction consists of multiple fields.

[0065] Optionally, the preprocessing module 202 includes:

[0066] A preprocessing unit is used to offset the fields in the quantum cryptography calculation task of a preset format according to the field length to split out the target field.

[0067] Optionally, the execution instruction matching module 204 includes:

[0068] An execution instruction matching unit is used to match a plurality of execution instructions corresponding to the identifier in the instruction mapping table according to the data mapping rule.

[0069] Optionally, the execution instruction matching module 204 further includes:

[0070] The execution instruction combination unit is used to combine several execution instructions according to the execution order of the several execution instructions to form an instruction sequence.

[0071] Optionally, the system further includes:

[0072] A cache area is used to cache the instruction sequence.

[0073] Regarding the device in the above embodiment, the process of executing the operation in each step has been described in detail in the embodiment of the method, and will not be elaborated here.

[0074] In order to ensure that the post-quantum cryptographic chip is in a state of low power consumption and normal operation, this application provides the following Figure 3The power management structure block diagram of a post-quantum cryptographic computing task execution system shown in the figure includes a main processor 1 for sending a post-quantum cryptographic computing task; a power consumption detection module 2 for receiving the current data provided by the post-quantum cryptographic chip 5 and the execution status of the post-quantum cryptographic computing task, and calculating the power consumption of the post-quantum cryptographic chip 5 according to the current data; a clock management unit 3 for adjusting the clock signal frequency required by the post-quantum cryptographic chip 5 according to the power consumption and the execution status; and a voltage management unit 4 for adjusting the voltage required by the post-quantum cryptographic chip 5 according to the power consumption and the execution status. The system also includes: a phase-locked loop 6, a voltage regulator 7 and a power supply 8; the clock management unit 3 adjusts the clock signal frequency produced by the phase-locked loop 6 according to the power consumption and the execution status; the voltage management unit 4 controls the voltage regulator 7 to adjust the voltage produced by the power supply 8 according to the power consumption and the execution status.

[0075] In an optional embodiment, after the terminal device is integrated with the post-quantum cryptographic chip 5, the clock signal frequency and voltage required by the post-quantum cryptographic chip for different post-quantum cryptographic computing tasks are different. In order to ensure that the power consumption of the post-quantum cryptographic chip 5 is minimized when executing the post-quantum cryptographic computing task, it is necessary to adaptively adjust the clock signal frequency and voltage required by the post-quantum cryptographic chip 5. For this reason, the present application proposes an integrated system of post-quantum cryptographic chips. First, the main processor 1 sends a post-quantum cryptographic computing task to the post-quantum cryptographic chip 5. After the post-quantum cryptographic chip 5 confirms that it has received the post-quantum cryptographic computing task, when the post-quantum cryptographic computing task does not require the main processor 1 to provide data, such as the post-quantum cryptographic computing task is post-quantum key generation, at this time, the post-quantum cryptographic chip 5 only needs to run the internal post-quantum key algorithm. Taking the post-quantum cryptographic computing task as post-quantum key generation as an example, in the process of the post-quantum cryptographic chip 5 running the internal post-quantum key algorithm, that is, when the power consumption detection module 2 receives the execution state of the post-quantum key generation and is at the beginning of the task execution, the power consumption detection module 2 will transmit a control signal to the clock management unit 3, so that the clock management unit 3 controls the phase-locked loop 6 according to the first preset clock signal frequency to produce the first preset clock signal frequency and transmit it to the post-quantum cryptographic chip 5. At the same time, the power consumption detection module 2 will transmit a control signal to the voltage management unit 4, so that the voltage management unit 4 controls the voltage regulator 7 according to the first preset voltage to adjust the power supply 8 to produce the first preset voltage and transmit it to the post-quantum cryptographic chip 5. Then, the post-quantum cryptographic chip 5 starts to execute the post-quantum key algorithm based on the first preset clock signal frequency and the first preset voltage to generate the post-quantum key. Among them, the first preset clock signal frequency and the first preset voltage are the initial required clock signal frequency and voltage for the post-quantum cryptographic chip 5 to perform the post-quantum cryptographic computing task. It should be noted that the clock signal frequency is not limited to the phase-locked loop 6, and can also be other devices that can generate clock signal frequencies, which are not limited here.

[0076] Afterwards, the power consumption detection module 2 receives that the execution state of the post-quantum key generation has changed from the start of task execution to the task execution, and the power consumption detection module 2 starts to collect the current data of the post-quantum cryptographic chip 5 in real time, and calculates the current power consumption of the post-quantum cryptographic chip 5 in real time based on the current data; the clock management unit 3 determines the change value of the clock signal frequency based on the current power consumption of the post-quantum cryptographic chip 5, the current clock signal frequency of the post-quantum cryptographic chip 5, and the clock signal frequency of the post-quantum cryptographic chip in the previous cycle, and adjusts the current clock signal frequency produced by the phase-locked loop 6 based on the change value of the clock signal frequency, and applies the adjusted current clock signal frequency to the next cycle of the post-quantum cryptographic chip 5 running the post-quantum key generation task; at the same time, the voltage management unit 4 determines the change value of the current voltage based on the current power consumption of the post-quantum cryptographic chip 5, the current voltage of the post-quantum cryptographic chip 5, and the voltage of the post-quantum cryptographic chip 5 in the previous cycle, and controls the voltage regulator 7 to adjust the current voltage produced by the power supply 8 based on the change value of the voltage, and applies the adjusted current voltage to the next cycle of the post-quantum cryptographic chip 5 running the post-quantum key generation task. The power consumption detection module 2 collects the current data of the post-quantum cryptographic chip 5 in real time to calculate the power consumption, and adjusts the clock signal frequency and voltage acting on the post-quantum cryptographic chip 5 in real time according to the calculation results. This satisfies the terminal device's requirements for low power consumption, realizes the rational use of resources, and achieves long-term standby work. At the same time, the post-quantum cryptographic chip with post-quantum cryptographic algorithm function is integrated into the terminal device, so that the terminal device can run the post-quantum cryptographic algorithm in the communication process, and ensures that the communication process between terminals can resist quantum computer attacks. Among them, the post-quantum cryptographic chip 5 runs the post-quantum cryptographic calculation task periodically, and each process executed in the post-quantum cryptographic chip 5 according to the post-quantum cryptographic calculation task can also be regarded as a time node, and each time node is used instead of the period to adjust the clock signal frequency and voltage of the post-quantum cryptographic chip 5.

[0077] Finally, when the post-quantum cryptographic chip 5 completes the post-quantum key generation task, the post-quantum cryptographic chip 5 will send a task completion signal to the main processor 1 and the power consumption detection module 2. The main processor 1 will issue a post-quantum key storage instruction to the post-quantum cryptographic chip 5 based on the task completion signal, so that the post-quantum key generated by the post-quantum cryptographic chip 5 when performing the post-quantum key generation task is stored in the key storage area for subsequent use in data signing, data encryption, etc.

[0078] At the same time, the power consumption detection module 2 will time the time after the task is executed, and compare the time with the first preset time, and control the clock management unit 3 and the voltage management unit 3 based on the comparison result. Specifically, when the time is greater than the first preset time and less than the second preset time, the clock management unit 3 controls the phase-locked loop 6 to produce the second preset clock signal frequency according to the second preset clock signal frequency and transmits it to the post-quantum cryptographic chip 5; at the same time, the voltage management unit 4 controls the voltage regulator 7 to adjust the power supply 8 to produce the second preset voltage according to the second preset voltage and transmit it to the post-quantum cryptographic chip 5; wherein the second preset clock signal frequency is less than the first preset clock signal frequency, and the second preset voltage is less than the first preset voltage.

[0079] For example, assuming that the first preset time is 10ms, the second preset time is 20ms, the timing time is 15ms, and the timing time is between the first preset time and the second preset time, it can be determined that the post-quantum cryptographic chip 5 does not need to continue working, and the post-quantum cryptographic chip 5 can be adjusted to a dormant state. Specifically, the clock management unit 3 controls the phase-locked loop 6 to produce a second preset clock signal frequency according to the second preset clock signal frequency and transmits it to the post-quantum cryptographic chip 5; at the same time, the voltage management unit 4 controls the voltage regulator 7 to adjust the power supply 8 according to the second preset voltage to produce the second preset voltage and transmit it to the post-quantum cryptographic chip 5. The post-quantum cryptographic chip 5 runs the post-quantum cryptographic chip 5 based on the second preset clock signal frequency and the second preset voltage, so that the post-quantum cryptographic chip 5 is in a dormant state, wherein the second preset clock signal frequency is less than the first preset clock signal frequency, and the second preset voltage is less than the first preset voltage, which indicates that the clock signal frequency and voltage in the dormant state are lower than the clock signal frequency and voltage required for the post-quantum cryptographic chip 5 to perform the post-quantum cryptographic computing task. By using the above method, it is determined whether the post-quantum cryptographic chip 5 has entered a dormant state and the clock signal frequency and voltage are adjusted, thereby achieving rational utilization of resources and long-term standby operation.

[0080] In an optional embodiment, when the time is greater than a second preset time, the clock management unit 3 is further used to control the phase-locked loop 6 to be turned off; the voltage management unit 4 is further used to control the voltage regulator 7 to turn off the power supply 8.

[0081] In an optional embodiment, for example, assuming that the first preset time is 10ms, the second preset time is 20ms, and the timing time is 21ms, and the timing time is greater than the second preset time, it can be determined that the post-quantum cryptographic chip 5 does not need to continue to sleep, and the post-quantum cryptographic chip 5 can be adjusted to a closed state. Specifically, the clock management unit 3 controls the phase-locked loop 6 to turn off; at the same time, the voltage management unit 4 controls the voltage regulator 7 to turn off the power supply 8, so as to achieve the effect of turning off the post-quantum cryptographic chip 5. By the above method, it is determined whether the post-quantum cryptographic chip 5 enters the closed state and adjusts the clock signal frequency and voltage to achieve reasonable use of resources.

[0082] Optionally, the system further includes: a current acquisition circuit 9, which is used to collect current data of the post-quantum cryptographic chip and transmit the current data to the power consumption detection module.

[0083] In an optional embodiment, in order to realize the collection of current data of the post-quantum cryptographic chip 5 by the power consumption detection module, the current data of the post-quantum cryptographic chip is collected by using the current collection circuit 9, so as to facilitate the subsequent power consumption calculation of the post-quantum cryptographic chip. It should be noted that the collection of current data of the post-quantum cryptographic chip is not limited to the current collection circuit 9, but can also be other devices or circuits capable of current collection, which is not limited here; and the current collection circuit 9 is a conventional circuit in the prior art, which will not be described in detail here.

[0084] In an optional embodiment, when the power consumption of the post-quantum cryptographic chip 5 is greater than the preset safety power consumption, the power consumption detection module 2 controls the clock management unit 3 to turn off the phase-locked loop 6 and controls the voltage regulator 7 to turn off the power supply 8 by controlling the voltage management unit 4. The preset safety power consumption is the maximum value of the power consumption of the post-quantum cryptographic chip 5 when it is running. When the power consumption of the post-quantum cryptographic chip 5 calculated by the power consumption detection module 2 is greater than the preset safety power consumption, it indicates that the post-quantum cryptographic chip 5 is abnormal, and the post-quantum cryptographic chip 5 is directly turned off. At the same time, the power consumption detection module 2 reports the abnormal information of the post-quantum cryptographic chip 5 to the main processor 1, and the main processor 1 records the abnormal information and notifies the management personnel to perform abnormal inspection of the post-quantum cryptographic chip 5 to prevent the post-quantum cryptographic chip 5 from giving wrong results of the post-quantum cryptographic calculation task when it is running.

[0085] In an optional embodiment, when the post-quantum cryptographic computing task is to encrypt or sign a certain data using the post-quantum cryptographic chip 5, the post-quantum cryptographic chip 5 sends a signal that the post-quantum cryptographic chip 5 is ready, i.e., a ready signal, to the main processor 1 through the communication interface; thereafter, the main processor 1 sends the data to be encrypted or the data to be signed to the post-quantum cryptographic chip 5 through the communication interface, and finally, the post-quantum cryptographic chip 5 performs the post-quantum cryptographic computing task to encrypt the encrypted data or sign the signed data, and sends a done signal to the main processor 1 after completing the post-quantum cryptographic computing task; finally, the main processor 1 sends a data storage instruction to the post-quantum cryptographic chip 5 based on the done signal, and stores the encrypted data or signed data in the data storage area through the communication interface. This application integrates the post-quantum cryptographic chip 5 with the post-quantum cryptographic algorithm function into the terminal device, so that the terminal device can run the post-quantum cryptographic algorithm in the communication process, and ensures that the communication process between the terminals can resist quantum computer attacks.

[0086] Reference Figure 4 A terminal device 01 provided in an embodiment of this specification includes an execution system 02 for applying the post-quantum cryptographic computing task as described above.

[0087] The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the present invention is not inherently related to any specific computer, virtual device or electronic device, and various general devices can also implement the present invention. The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0088] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0089] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for executing a post-quantum cryptographic computing task, characterized in that: include: Obtain post-quantum cryptographic computing task instructions; Performing field splitting on the post-quantum cryptographic computing task instruction to obtain a target field; Convert the target field into a corresponding identifier based on a preset command identification table; Matching a plurality of execution instructions corresponding to the identifier according to a data mapping rule, and combining the plurality of execution instructions into an instruction sequence; Execute the instruction sequence to complete the post-quantum cryptographic computing task.

2. The system according to claim 1, characterized in that Before obtaining the post-quantum cryptographic computing task instruction, the method further includes: Establish the correspondence between identifiers and fields; The corresponding relationship is stored in the form of the preset command identification table.

3. The system according to claim 1, characterized in that Before obtaining the post-quantum cryptographic computing task instruction, the method further includes: Establishing a data mapping rule between an identifier and an execution instruction; wherein each identifier corresponds to a plurality of execution instructions having an execution order; The data mapping rules are stored in the form of an instruction mapping table.

4. The system according to claim 1, characterized in that The post-quantum cryptographic computing task instruction is a quantum cryptographic computing task instruction in a preset format, and the post-quantum cryptographic computing task instruction consists of multiple fields.

5. The system according to claim 4, characterized in that The step of performing field splitting on the post-quantum cryptographic computing task to obtain a target field includes: The fields in the quantum cryptography calculation task of the preset format are offset according to the field length to split out the target field.

6. The system according to claim 3, characterized in that The matching of a plurality of execution instructions corresponding to the identifier according to the data mapping rule includes: According to the data mapping rule, a plurality of execution instructions corresponding to the identifier are matched in the instruction mapping table.

7. The system according to claim 3, characterized in that The combining of a plurality of execution instructions into an instruction sequence comprises: The plurality of execution instructions are combined according to the execution order of the plurality of execution instructions to form an instruction sequence.

8. The method according to claim 1, characterized in that After combining the plurality of execution instructions into an instruction sequence, the method further comprises: The instruction sequence is cached using a cache area.

9. A post-quantum cryptographic computing task execution system, characterized in that: include: A main processor, used to provide post-quantum cryptographic computing task instructions; A preprocessing module, used for performing field splitting on the post-quantum cryptographic computing task instruction to obtain a target field; A target field conversion module, used to convert the target field into a corresponding identifier based on a preset command identifier table; An execution instruction matching module, used for matching a plurality of execution instructions corresponding to the identifier according to a data mapping rule, and combining the plurality of execution instructions into an instruction sequence; A post-quantum cryptographic chip is used to execute the instruction sequence to complete the post-quantum cryptographic computing task.

10. A terminal device, characterized in that: A system for executing a post-quantum cryptographic computing task as claimed in claim 9 is included.

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