Load current source module for reading image sensor, reading system and imaging equipment

Abstract

The invention discloses a load current source module for reading an image sensor, a reading system and imaging equipment, and relates to the technical field of image sensors. The negative impedance conversion circuit is used for generating negative resistance or negative capacitance, and the negative resistance or negative capacitance is counteracted with parasitic resistance or parasitic capacitance of the VSL; and a charging and discharging acceleration circuit. The load current source module is internally provided with the negative impedance conversion circuit and the charging and discharging acceleration circuit, on one hand, negative impedance generated by the negative impedance conversion circuit is used for counteracting parasitic capacitance and parasitic resistance existing in VSL signal establishment, so that the small signal establishment speed is accelerated; and on the other hand, the charging and discharging acceleration circuit provides a large transient current so as to accelerate the large signal establishment speed. In other words, the load current source module does not change the action point design of the main current mirror circuit, and the establishment time of the VSL can be effectively shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a load current source module for reading out an image sensor, a readout system and an imaging device. Background Art

[0002] The ADC (A / D Converter) in the existing CMOS image sensor is composed of a load current source array, a comparator array and a counter array. Among them, the load current source array is responsible for providing a constant current for the source follower of the pixel array; during the signal readout process of the pixel array, the charge in the PD (Photon Diode) needs to be transferred to the FD (Floating Diffusion) to reduce the FD voltage; further, the pixel array output signal VSL (Vertical Signal Line) is reduced through the pixel SF (Source Follower).

[0003] In the above readout process, since the VSL drop process is affected by the parasitic resistance and capacitance of the metal wiring and the equivalent output impedance of SF, the VSL drop process will be slowed down, so that the entire image sensor needs to spend time waiting for VSL to completely drop to a stable level during the readout process. The time consumed in this process is called the VSL settling time.

[0004] At present, for the traditional image sensor structure, if you want to speed up the VSL setup time, you often increase the bias current of the load current source: on the one hand, the transconductance of the SF of the pixel array is increased to reduce its equivalent output impedance; on the other hand, during the large signal establishment period, increasing the bias current of the load current source can speed up the large signal establishment speed.

[0005] However, the above method has the problems that increasing the bias current of the load current source often leads to an increase in the power consumption of the overall analog circuit and an increase in the difficulty of designing the DC action point of the load current source. Summary of the invention

[0006] The purpose of the present invention is to solve the disadvantage in the prior art that increasing the bias current of the load current source easily leads to increased power consumption, and to propose a load current source module for image sensor readout, a readout system and an imaging device.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, the present invention provides a load current source module for reading out an image sensor, wherein the load current source module is electrically connected to a pixel array in a pixel driving module, and comprises: A current mirror circuit, the current mirror circuit is electrically connected to the pixel driving module, and the current mirror circuit is used to provide a bias current; Wherein, the current mirror circuit comprises: a cascode current mirror or two N-channel field effect transistors; A negative impedance conversion circuit, wherein the negative impedance conversion circuit is used to generate a negative resistance or a negative capacitance to offset the parasitic resistance or capacitance of the VSL itself; Wherein, the negative impedance conversion circuit comprises: an amplifier, the amplifier is in a negative feedback state; A charge and discharge acceleration circuit is used to provide charge and discharge current during the VSL establishment period.

[0008] In some feasible solutions, the current mirror circuit further includes: Two N-channel field effect transistors are connected via a common source and a common gate, the gates of the N-channel field effect transistors connected via a common source and a common gate are connected to a bias voltage, and the sources of the N-channel field effect transistors connected via a common source and a common gate are electrically connected to a pixel driving module, a negative impedance conversion circuit, and a charge and discharge acceleration circuit, respectively.

[0009] In some feasible solutions, the charge and discharge acceleration circuit includes: A voltage-current conversion circuit, one end of which is connected to a drain power supply voltage, and the voltage-current conversion circuit is used for performing voltage-current conversion; A current amplifying circuit is electrically connected to the voltage-current conversion circuit, and is used to amplify the voltage-current conversion current.

[0010] In some feasible solutions, the voltage-current conversion circuit includes: A first P-channel field effect transistor, one end of which is connected to a drain power supply voltage, and the first P-channel field effect transistor is used to provide a current source; a second P-channel field effect transistor, one end of which is also connected to a drain power supply voltage, and the second P-channel field effect transistor is used to provide a bias current; A capacitor, the capacitor is arranged at one side of the second P-channel field effect transistor, the capacitor is electrically connected to the second P-channel field effect transistor, and the capacitor is a bypass capacitor of the second P-channel field effect transistor; a third P-channel field effect transistor, wherein a gate of the third P-channel field effect transistor is connected to a vertical signal line signal output node, and a source of the third P-channel field effect transistor is connected to the second P-channel field effect transistor; A first N-channel field effect transistor, wherein the first N-channel field effect transistor is connected to the second P-channel field effect transistor, and the first N-channel field effect transistor is connected to a drain of the third P-channel field effect transistor; A second N-channel field effect transistor, wherein the second N-channel field effect transistor and the first N-channel field effect transistor form a current mirror.

[0011] In some feasible solutions, the amplifier is an operational amplifier, and the negative impedance conversion circuit further includes: A first resistor, the first resistor is electrically connected to the non-inverting input terminal of the amplifier; a second resistor, the second resistor being electrically connected to the inverting input terminal of the amplifier; A third resistor is electrically connected to the inverting input terminal of the amplifier, and the third resistor is connected in parallel with the second resistor.

[0012] In some feasible solutions, the negative impedance conversion circuit further includes: A first capacitor, wherein the first capacitor replaces the first resistor, and the first capacitor is electrically connected to the non-inverting input terminal of the amplifier.

[0013] In some feasible solutions, the amplifier is a common-gate amplifier, and the negative impedance conversion circuit further includes: A first capacitor, one end of which is electrically connected to the pixel driving module; a fourth P-channel field effect transistor, wherein a source of the fourth P-channel field effect transistor is electrically connected to the pixel driving module and is electrically connected to the first capacitor, and a gate of the fourth P-channel field effect transistor is connected to a bias voltage; A third N-channel field effect transistor, wherein a gate of the third N-channel field effect transistor is electrically connected to a bias voltage, and a source of the third N-channel field effect transistor is electrically connected to a drain of the fourth P-channel field effect transistor.

[0014] In some feasible solutions, the common gate amplifier is replaced by a source follower, and the negative impedance conversion circuit further includes: a fourth N-channel field effect transistor, wherein the fourth N-channel field effect transistor replaces the fourth P-channel field effect transistor, a gate of the fourth N-channel field effect transistor is electrically connected to a pixel driving module, a drain of the fourth N-channel field effect transistor is connected to a power supply, and a source of the fourth N-channel field effect transistor is electrically connected to a drain of the third N-channel field effect transistor; One end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit.

[0015] In a second aspect, the present invention provides an image sensor readout system, which uses an image sensor readout load current source module as described in any one of the first aspects, and the readout system further includes: A pixel noise detection module, the pixel noise detection module is electrically connected to the pixel driving module, and the pixel noise detection module is used to detect the pixel array in the pixel driving module; A reference slope generating module, wherein the reference slope generating module is electrically connected to the pixel driving module; A comparator, the comparator being electrically connected to the load current source module and the reference ramp generating module respectively; a counter, the counter being electrically connected to the comparator; A data transmission module is electrically connected to the counter.

[0016] In a third aspect, the present invention further provides an imaging device, which uses an image sensor readout load current source module described in any one of the first aspects or an image sensor readout system described in the second aspect.

[0017] The beneficial effects of the present invention are: The present invention allows the load current source module to have a negative impedance conversion circuit and a charge-discharge acceleration circuit built inside. On the one hand, the negative impedance generated by the negative impedance conversion circuit is used to offset the parasitic capacitance and parasitic resistance existing in the signal establishment of VSL, so as to accelerate the establishment speed of small signals; on the other hand, the charge-discharge acceleration circuit provides a larger transient current to accelerate the establishment speed of large signals. That is, the load current source module in the present application does not change the action point design of the main current mirror circuit, and can effectively accelerate the establishment time of VSL. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the working connection of a load current source module for image sensor readout provided in an embodiment of the present invention; Figure 2 It is a schematic diagram of the structure of a pixel array portion in a pixel driving module provided in an embodiment of the present invention; Figure 3 A schematic diagram of a vertical signal line node VSL lowering process provided in an embodiment of the present invention; Figure 4 A schematic diagram of the connection between a load current source module for reading out an image sensor and a pixel array in a pixel driving module provided in an embodiment of the present invention; Figure 5 A schematic diagram of the connection of a current mirror circuit of a load current source module for image sensor readout provided in an embodiment of the present invention; Figure 6 A schematic diagram of a negative impedance conversion circuit connection for generating a negative resistance in a load current source module for reading an image sensor provided in an embodiment of the present invention; Figure 7A schematic diagram of a negative impedance conversion circuit connection for generating negative capacitance in a load current source module for image sensor readout provided in an embodiment of the present invention; Figure 8 A schematic diagram of the connection of a negative impedance conversion circuit including a common-gate amplifier in a load current source module for image sensor readout provided in an embodiment of the present invention; Fig. 9 The present invention is a schematic diagram of the connection of a negative impedance conversion circuit including a source follower in a load current source module for image sensor readout provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing in the full text includes three parallel schemes. Taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0023] Reference Figures 1 to 9 The purpose of the present invention is to solve the disadvantage of the prior art that increasing the bias current of the load current source easily leads to increased power consumption, and a load current source module for image sensor readout is proposed. The load current source module is internally constructed with a negative impedance conversion circuit 1062 and a charge and discharge acceleration circuit 1063. On the one hand, the negative impedance generated by the negative impedance conversion circuit 1062 is used to offset the parasitic capacitance and parasitic resistance that affect the VSL establishment speed, so as to accelerate the small signal establishment speed; on the other hand, the charge and discharge acceleration circuit 1063 provides a larger transient current to accelerate the large signal establishment speed. That is, the load current source module in this application does not change the action point design of the main current mirror circuit, and can effectively accelerate the establishment time of VSL.

[0024] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4As shown, a load current source module for image sensor readout, the load current source module 106 is electrically connected to the pixel array 100 in the pixel driving module 101, and the load current source module 106 is used to cooperate with the pixel array 100 in the pixel driving module 101 to establish a large signal and a small signal. Among them, the pixel array 100 in the pixel driving module 101 can be composed of a plurality of pixel units, and the pixel units include: a photodiode 1001, an N-channel field effect transistor 1002, an N-channel field effect transistor 1003, an N-channel field effect transistor 1004, and an N-channel field effect transistor 1005. When exposed to light, the photodiode 1001 completes photoelectric conversion, which generates photogenerated electrons. When resetting, the gate connection signal RST of the N-channel field effect transistor 1003 is set high, the N-channel field effect transistor 1003 is turned on, and the potential of the floating diffusion point FD (FloatingDiffusion) 1006 is reset to a level slightly lower than the power supply VDD, and then the RST signal is set low to end the reset operation. When reading the signal, the gate connection signal TX of the N-channel field effect transistor 1002 is set high, and the N-channel field effect transistor 1002 is turned on. Since the potential of the floating diffusion point FD1006 is higher than the positive end of the photodiode 1001 at this time, the photogenerated electrons generated by the photodiode 1001 move to the floating diffusion point FD1006 through the N-channel field effect transistor 1002, causing its voltage to drop. At this time, if the pixel row where the pixel unit is located is in the readout state, the gate connection signal SEL of the N-channel field effect transistor 1005 is set high, and the N-channel field effect transistor 1004 is in the source follower working state when the N-channel field effect transistor 1005 is turned on. When the potential of the floating diffusion point FD1006 decreases, it causes the vertical signal line node VSL1007 to also decrease by a voltage slightly less than the voltage change of the floating diffusion point FD1006; at this time, the voltage change of the vertical signal line node VSL1007 corresponds to the signal amount brought by the photogenerated electrons. Therefore, Figure 2 In the pixel unit readout process shown in FIG. 1 , the gate connection signal TX of the N-channel field effect transistor 1002 is connected to the vertical signal line node VSL1007. Figure 3As shown. That is, when TX is set high, the N-channel field effect transistor 1002 is turned on, and the vertical signal line node VSL1007 begins to decline, and its decline establishment period can be divided into two parts: a large signal establishment period and a small signal establishment period. Here, in order to facilitate the circuit connection description of the load current source module in the present application and the pixel unit in the pixel driving module, a group of pixel units are used as an example connection. In addition, the metal wiring parasitic resistance 1101 of the vertical signal line node VSL1007 can be represented by a resistor R0, and its metal wiring parasitic capacitance 1102 can be represented by a capacitor C0, and the load current source can be represented by an ideal current source 1104, and the vertical signal line node connected to the load current source 1104 is VSL_OUT1103.

[0025] Reference Figures 5 and 6 As shown, specifically, the load current source module includes: a current mirror circuit 1061, a negative impedance conversion circuit 1062 and a charge and discharge acceleration circuit 1063, the current mirror circuit 1061 is electrically connected to the pixel driving module 101, and the current mirror circuit 1061 is used to provide a bias current; wherein, the current mirror circuit 1061 includes: a cascode current mirror or two N-channel field effect transistors; specifically, the current mirror circuit can be composed of two N-channel field effect transistors (that is, including: N-channel field effect transistor 10611 and N-channel field effect transistor 10612) connected through a cascode connection, the gate of the N-channel field effect transistor connected through a cascode connection is connected to a bias voltage, and the source of the N-channel field effect transistor connected through a cascode connection is electrically connected to the pixel driving module 101, the negative impedance conversion circuit 1062, and the charge and discharge acceleration circuit 1063. That is, the gates of the two N-channel field effect transistors connected through a cascode connection are connected to VB2 and VB1 respectively, as the bias voltage of the cascode current mirror. Then the vertical signal line output node VSL_OUT1103 is connected to the negative impedance conversion circuit 1062 and the charge and discharge acceleration circuit 1063. It should be noted that the negative impedance conversion circuit 1062 and the charge and discharge acceleration circuit 1063 can be connected to the vertical signal line output node VSL_OUT1103 at the same time, or they can be connected to the vertical signal line output node VSL_OUT1103 separately when only one of them is provided. Among them, the negative impedance conversion circuit 1062 is used to generate negative resistance or negative capacitance, which offsets the parasitic resistance 1101 or parasitic capacitance 1102 of VSL itself; the charge and discharge acceleration circuit 1063 is used to provide charge and discharge current during the establishment of VSL. In order to achieve the negative impedance conversion circuit 1062 to generate negative impedance and offset the parasitic capacitance 1101 and parasitic resistance 1102 existing in the signal establishment of VSL, so as to accelerate the establishment speed of small signals; and to allow the charge and discharge acceleration circuit 1063 to provide a larger transient current to accelerate the establishment speed of large signals.

[0026] Reference Figure 6 As shown, when the negative impedance conversion circuit 1062 is used to generate a negative resistance to offset the parasitic resistance when VSL is established, the negative impedance conversion circuit 1062 includes: a first resistor 10621, a second resistor 10623, a third resistor 10624 and an operational amplifier 10622. The first resistor 10621 is electrically connected to the non-inverting input terminal of the operational amplifier 10622; the second resistor 10623 is electrically connected to the inverting input terminal of the operational amplifier 10622; the third resistor 10624 is electrically connected to the inverting input terminal of the operational amplifier 10622, and the third resistor 10624 is connected in parallel with the second resistor 10623. That is, in the negative impedance conversion circuit 1062 of this embodiment, the operational amplifier 10622 forms a negative feedback connection with the second resistor 10623 and the third resistor 10624, and its closed-loop gain is (R1+R2) / R2, where R1 is the second resistor 10623 and R2 is the third resistor 10624. Therefore, when the voltage change at the positive input terminal of the operational amplifier 10622 is Vin=V1, the voltage change at its output terminal is: Vout=(R1+R2) / R2*V1; at this time, the input current flowing through the first resistor 10621 is: Iin=(Vin-Vout) / R_NI=-R1 / R2*V1 / R_NI, R_NI is the first resistor 10621; It can be seen that in this embodiment, the negative impedance conversion circuit 1062 has an equivalent input resistance of -R2 / R1 times R_NI. When the value of R2 / R1*R_NI is equal to the parasitic resistance 1101 of the vertical signal line node VSL1007, the equivalent input impedance of the negative impedance conversion circuit 1062 cancels out the parasitic resistance 1101.

[0027] Here, in order to facilitate the understanding of the above content, an example is given, for example: when the parasitic resistance R0=20KΩ, R2=10KΩ, R1=500Ω, R_NI=1KΩ, the equivalent input impedance of the negative impedance conversion circuit 1062 is Zin=-20KΩ, thereby effectively reducing the load of the vertical signal line node VSL1007 and speeding up the establishment of small signals. It should be noted that when R2 / R1>1, the equivalent input impedance of the negative impedance conversion circuit 1062 is a negative resistance; when R2 / R1<1, the equivalent input impedance of the negative impedance conversion circuit 1062 is a positive resistance.

[0028] Reference Figure 6In the charge and discharge acceleration circuit 1063 of this embodiment, all field effect transistors operate in a saturated state. Specifically, the charge and discharge acceleration circuit 1063 includes: a voltage-current conversion circuit and a current amplifier circuit, one end of the voltage-current conversion circuit is connected to a drain power supply voltage, and the voltage-current conversion circuit is used to perform voltage-current conversion; the current amplifier circuit is electrically connected to the voltage-current conversion circuit, and the current amplifier circuit is used to amplify the voltage-current conversion current. In this embodiment, the voltage-current conversion circuit includes: a first P-channel field effect transistor 10636, a second P-channel field effect transistor 10631, a capacitor 10632, a third P-channel field effect transistor 10633, a first N-channel field effect transistor 10634, and a second N-channel field effect transistor 10635. One end of the first P-channel field effect transistor 10636 is connected to a drain power supply voltage, and the first P-channel field effect transistor 10636 is used to provide a current source; one end of the second P-channel field effect transistor 10631 is also connected to a drain power supply voltage, and the second P-channel field effect transistor 10631 is used to provide a bias current; the capacitor 10632 is arranged on one side of the second P-channel field effect transistor 10631, and the capacitor 10632 is electrically connected to the second P-channel field effect transistor 10631. The capacitor 10632 is a bypass capacitor of the second P-channel field effect transistor 10631 (i.e., reducing the second P-channel field effect transistor 106 31); the gate of the third P-channel field effect transistor 10633 is connected to the vertical signal line signal output node VSL_OUT1103, the source of the third P-channel field effect transistor 10633 is connected to the second P-channel field effect transistor 10631; the first N-channel field effect transistor 10634 is connected to the second P-channel field effect transistor 10631, the first N-channel field effect transistor 10634 is connected to the drain of the third P-channel field effect transistor 10633; the second N-channel field effect transistor 10635 and the first N-channel field effect transistor 10634 form a current mirror. In this embodiment, the first P-channel field effect transistor 10636 and the second P-channel field effect transistor 10631 can act as a current source, and the capacitor 10632 can serve as a bypass capacitor of the second P-channel field effect transistor 10631. The second P-channel field effect transistor 10631 provides bias current for the third P-channel field effect transistor 10633 and the first N-channel field effect transistor 10634 .The gate of the third P-channel field effect transistor 10633 is connected to the vertical signal line output node VSL_OUT1103, and the drain of the third P-channel field effect transistor 10633 and the first N-channel field effect transistor 10634, the first N-channel field effect transistor 10634 and the second N-channel field effect transistor 10635 form a current mirror, and the current mirror ratio is determined by the ratio of the width-to-length ratio of the second N-channel field effect transistor 10635 to the width-to-length ratio of the first N-channel field effect transistor 10634. The current of the first P-channel field effect transistor 10636 as a current source is set to be slightly equal to the saturation current of the second N-channel field effect transistor 10635. During the falling establishment process of the vertical signal line output node VSL_OUT1103, the gate voltage of the third P-channel field effect transistor 10633 drops by ΔV. At this time, the third P-channel field effect transistor 10633 acts as a source follower, and its source voltage will drop. At this time, the capacitor 10632, which acts as a bypass capacitor, acts as a current source to provide a transient current ΔI=C1*dΔV / dt for the second P-channel field effect transistor 10631. The transient current is amplified by the current mirror composed of the first N-channel field effect transistor 10634 and the second N-channel field effect transistor 10635, and its amplification factor is as described above, which is the ratio of the width-to-length ratio of the second N-channel field effect transistor 10635 to the first N-channel field effect transistor 10634:. K=(W / L)_10635 / (W / L)_10634.

[0029] Therefore, it can be known that the transient output current generated by the drain of the second N-channel field effect transistor 10635 is K*ΔI. Since the first P-channel field effect transistor 10636 is set to a constant current working state, the transient current K*ΔI will be provided by the load capacitor through the vertical signal line output node VSL_OUT1103; if the current of the current source is set to I, then in this embodiment, the current flowing out of the load capacitor during the large signal establishment period can be expressed as I+K*ΔI, and its size can be adjusted by adjusting the capacitance value of the capacitor and the current mirror ratio K. Therefore, in this embodiment, the charge and discharge acceleration circuit 1063 speeds up the large signal establishment speed of the vertical signal line output node VSL_OUT1103 by increasing the transient current flowing out of the load capacitor during the large signal establishment period.

[0030] Reference Figure 7As shown, when the negative impedance conversion circuit 1062 generates a negative resistance to offset the parasitic resistance when VSL is established, the introduction of the first resistor 10621 may increase the thermal noise on the vertical signal line input node VSL on the one hand, and on the other hand, the negative resistance of the first resistor 10621 may cause circuit oscillation. Therefore, in some feasible schemes, the negative impedance conversion circuit also includes: a first capacitor 10625, the first capacitor 10625 replaces the first resistor 10621, and the first capacitor 10625 is electrically connected to the in-phase input terminal of the operational amplifier 10622. That is, by setting the first capacitor 10625 in the negative impedance conversion circuit 1062, the first capacitor 10625 generates a negative capacitance to offset the parasitic capacitance when VSL is established, so as to accelerate the establishment of VSL. Among them, the rest of the structure is the same as Figure 6 In this embodiment, during the establishment process of the vertical signal line node VSL1007 falling, when the voltage change at the positive input terminal of the operational amplifier 10622 is Vin=V1, its output terminal Vout=(R1+R2) / R2*V1, as in the first embodiment, the equivalent input current flowing through the first capacitor 10625 at this time is: Iin=(Vin-Vout)*s*C_NI=-R1 / R2*V1*s*C_NI; Wherein, s represents a complex variable, whose unit is rad / s, and C_NI is the first capacitor 10625.

[0031] Therefore, it can be calculated that the equivalent input impedance of the negative impedance conversion circuit 1062 is: Zin=Vin / Iin=-R2 / R1*(1 / (s*C_NI)); As can be seen from the above formula, in this embodiment, the negative impedance conversion circuit 1062 has an equivalent input capacitance of -R2 / R1 times the first capacitor 10625. When the value of R2 / R1*C_NI is equal to the parasitic capacitance 1102 of the vertical signal line node VSL1007, the equivalent input impedance of the negative impedance conversion circuit 1062 and the parasitic capacitance 1102 are offset.

[0032] Here, in order to facilitate the understanding of the above content, an example is given. For example, when the parasitic capacitance C0=2pF, R2=10KΩ, R1=500Ω, C_NI=100fF are taken, and the equivalent input impedance of the negative impedance conversion circuit 1062 is: Zin=-(1 / s*2p)Ω, and the impedance of the parasitic capacitance 1102 is Zc0=(1 / s*2p)Ω; by offsetting Zin and Zc0, the load of the vertical signal line node VSL1007 is effectively reduced, and the speed of small signal establishment is accelerated. It should be noted that when R2 / R1>1, the equivalent input impedance of the negative impedance conversion circuit 1062 is expressed as a negative capacitor; when R2 / R1<1, the equivalent input impedance of the negative impedance conversion circuit 1062 is expressed as a positive capacitor. In this embodiment, by replacing the negative resistor in the negative impedance conversion circuit 1062 with a negative capacitor, the same acceleration of the small signal establishment process is achieved, but the risk of image quality deterioration due to the thermal noise of the resistor is avoided.

[0033] Reference Figure 8 ,exist Figure 6 and Figure 7 In the embodiment, although the operational amplifier 10622 using the negative feedback connection realizes the offsetting of the negative resistance or negative capacitance of the negative impedance conversion circuit 1062 and the parasitic resistance 1101 or the parasitic capacitance 1102, in actual application, the operational amplifier 10622 itself may introduce noise, and also increase the circuit area and power consumption. In some feasible schemes, the amplifier may be a common-gate amplifier. Specifically, in the present embodiment, the negative impedance conversion circuit 1062 may be composed of a first capacitor 10625, a fourth P-channel field effect transistor 10626, and a third N-channel field effect transistor 10627. One end of the first capacitor 10625 is electrically connected to the pixel driving module 101; the source of the fourth P-channel field effect transistor 10626 is electrically connected to the pixel driving module 101, and is electrically connected to the first capacitor 10625, and the gate of the fourth P-channel field effect transistor 10626 is connected to a bias voltage; the gate of the third N-channel field effect transistor 10627 is electrically connected to a bias voltage, and the source of the third N-channel field effect transistor 10627 is electrically connected to the drain of the fourth P-channel field effect transistor 10626. In this embodiment, the negative impedance conversion circuit 1062 can be composed of the first capacitor 10625, the fourth P-channel field effect transistor 10626, and the third N-channel field effect transistor 10627. The charge and discharge acceleration circuit 1063 can be connected with Figure 6 and Figure 7They are consistent, so no more details will be elaborated here. Specifically, in the negative impedance conversion circuit 1062, the source of the fourth P-channel field effect transistor 10626 is connected to one end of the vertical signal line output node VSL_OUT1 103 and the first capacitor 10625. The gate is connected to the bias voltage VB5, and the drain is connected to the third N-channel field effect transistor 10627 and the other end of the first capacitor 10625. The gate of the third N-channel field effect transistor 10627 is connected to the bias voltage VB6 and is used as a current source. The DC current of the fourth P-channel field effect transistor 10626 is set to be slightly equal to that of the third N-channel field effect transistor 10627. At this time, the fourth P-channel field effect transistor 10626 is used as a common-gate amplifier with a current source load. Then, when the vertical signal line output node VSL_OUT1 103 drops by Vin = V1, the transconductance of the fourth P-channel field effect transistor 10626 is gm1. Ignoring its body effect, the small-signal resistance of the third N-channel field effect transistor 10627 is ro2. Then, due to the drop in the source voltage of the fourth P-channel field effect transistor 10626, its drain voltage will also drop: Vout = gm1 * ro2 * V1; and then the input current flowing through the first capacitor can be obtained as: Iin=(Vin - Vout)*s*C_NI=(1 - gm1*ro2)*V1*s*C_NI; At this time, the equivalent input impedance of the negative impedance conversion circuit 1062 is: Zin = Vin / Iin = 1 / (1 - gm1*ro2)*(1 / (s*C_NI)); When the design satisfies 1 < gm1*ro2, it can be obtained that the negative impedance conversion circuit 1062 has an equivalent input capacitance that is (1 - gm1*ro2) times that of the first capacitor 10625, and the first capacitor 10625 exhibits a negative capacitance. By reasonably designing gm1 and ro2, the negative impedance conversion circuit 1062 can have a negative capacitance that can cancel the parasitic capacitance 1102, thereby achieving the acceleration of the small-signal establishment speed.

[0034] Refer to Fig. 9 In Figure 8In the negative impedance conversion circuit 1062, since the common gate amplifier with active load is used to generate negative capacitance to offset the load parasitic capacitance 1102 of the vertical signal line node VSL1007, the speed of small signal establishment is accelerated. However, when using the common gate amplifier, the drain swing of the fourth P-channel field effect transistor 10626 limits the working point of the negative impedance conversion circuit 1062. For example: when the voltage drop amplitude of the vertical signal line output node VSL_OUT1103 is large, the fourth P-channel field effect transistor 10626 will be forced to turn off, thereby making the negative impedance conversion circuit 1062 invalid. Therefore, in some feasible schemes, the common gate amplifier can be replaced by a source follower, and other circuit structures are similar to Figure 8In the present embodiment, the negative impedance conversion circuit 1062 further includes: a fourth N-channel field effect transistor 10628, wherein the fourth N-channel field effect transistor 10628 replaces the fourth P-channel field effect transistor 10626, wherein the gate of the fourth N-channel field effect transistor 10628 is electrically connected to the pixel driving module 101, the drain of the fourth N-channel field effect transistor 10628 is connected to a power supply, and the source of the fourth N-channel field effect transistor 10628 is electrically connected to the drain of the third N-channel field effect transistor 10627; wherein one end of the first capacitor 10625 is electrically connected to the source of the fourth N-channel field effect transistor 10628, and the other end of the first capacitor 10625 is electrically connected to the current mirror circuit 1061. That is, in the negative impedance conversion circuit 1062 of the present embodiment, the third N-channel field effect transistor 10627 is used as a bias current source for the fourth N-channel field effect transistor 10628; the fourth N-channel field effect transistor 10628 is used as a source follower, the gate of the fourth N-channel field effect transistor 10628 is connected to the vertical signal line output node VSL_OUT1103, the drain of the fourth N-channel field effect transistor 10628 is connected to the power supply, and the source of the fourth N-channel field effect transistor 10628 is connected to the drain of the third N-channel field effect transistor 10627 and one end of the first capacitor 10625. The other end of the first capacitor 10625 is connected to the source of an N-channel field effect transistor 10611 in the common source and common gate current mirror circuit 1061. Therefore, in this embodiment, when the vertical signal line output node VSL_OUT1103 drops Vin=V1, assuming that the input current is Iin and ignoring the body effect of the fourth N-channel field effect transistor 10628 (for example, connecting its substrate to the source), it can be considered that the transfer gain of the source follower is approximately equal to 1 at this time. At this time, for the negative impedance conversion circuit 1062 in this embodiment, the transconductance of an N-channel field effect transistor 10611 in the common source and common gate current mirror circuit 1061 is gm1, and its source voltage change is Vx, the source voltage change of the fourth N-channel field effect transistor 10628 is Vy, the output impedance of the third N-channel field effect transistor 10627 is Ro, and the transconductance of the fourth N-channel field effect transistor 10628 is gm2. According to Kirchhoff's current-voltage theorem, it can be obtained that: gm2*(Vin-Vy)+(Vx-Vy) / (1 / (s*C_NI))=Vy / Ro; Iin=-gm1*Vx=(Vx-Vy) / (1 / (s*C_NI)); After transforming and simplifying the above equations, we can get approximately: Zin=Vin / Iin=[gm1+gm1*gm2*Ro+s*C_NI*(gm2*Ro+gm1*Ro)] / gm1*gm2*Ro*s*C_NI; It can be seen from the above formula that at this time, the equivalent input impedance of the negative impedance conversion circuit 1062 at low frequency is expressed as the sum of negative resistance and negative capacitance, and the equivalent input impedance at high frequency is expressed as negative resistance, but the resistance value is small; therefore, gm2 and Ro can be reasonably designed according to actual conditions, so that the negative impedance conversion circuit 1062 can have a negative capacitance that can offset the parasitic capacitance 1102, thereby accelerating the speed of small signal establishment.

[0035] Reference Figure 1 In the second aspect, the present invention provides an image sensor readout system, which adopts a load current source module for image sensor readout described in any one of the first aspects, and the readout system further comprises: a pixel noise detection module 102, a reference slope generation module 103, a comparator 107, a counter 108, and a data transmission module 109, wherein the pixel noise detection module 102 is electrically connected to the pixel driving module 101, and the pixel noise detection module 102 is used to detect the pixel array 100 in the pixel driving module 101; the reference slope generation module 103 is electrically connected to the pixel driving module 101 through a signal input terminal 104; the comparator 107 is electrically connected to the load current source module 106 and the reference slope generation module through a signal output terminal 105 respectively; the counter 108 is electrically connected to the comparator 107; and the data transmission module 109 is electrically connected to the counter 108. By adopting the load current source module 106 described in the first aspect, the readout system can effectively accelerate the establishment of small signals of VSL and large signals of VSL.

[0036] It should be noted that in this readout system, Figure 6 , Figure 7 , Figure 8 , Fig. 9 The negative impedance conversion circuit in the load current source module performs the readout work. That is, in the readout system, Figure 6 , Figure 7 , Figure 8 , Fig. 9 The negative impedance conversion circuit in the load current source module can be used in combination to achieve the formation of negative impedance and offset the parasitic capacitance or resistance of VSL itself.

[0037] In some embodiments, the readout system can communicate using any currently known or future developed network protocol such as HTTP (HyperTextTransferProtocol), and can be interconnected with digital data communication (e.g., communication network) of any form or medium. Examples of communication networks include local area networks ("LAN"), wide area networks ("WAN"), internets (e.g., the Internet), and peer-to-peer networks (e.g., adhoc peer-to-peer networks), as well as any currently known or future developed networks. The functions described above in this article can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), etc.

[0038] In a third aspect, the present invention further provides an imaging device, which uses an image sensor readout load current source module 106 described in any one of the first aspects or an image sensor readout system described in the second aspect. That is, in the imaging device, the VSL signal can be established by using the current mirror circuit 1061, the negative impedance conversion circuit 1062, and the charge and discharge acceleration circuit 1063 in the load current source module 106 described above, so as to meet the imaging requirements.

[0039] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0040] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A load current source module for image sensor readout, wherein the load current source module is electrically connected to a pixel array in a pixel driving module, and is characterized in that: include: A current mirror circuit, the current mirror circuit is electrically connected to the pixel driving module, and the current mirror circuit is used to provide a bias current; Wherein, the current mirror circuit comprises: a cascode current mirror or two N-channel field effect transistors; A negative impedance conversion circuit, wherein the negative impedance conversion circuit is used to generate a negative resistance or a negative capacitance to offset the parasitic resistance or capacitance of the VSL itself; Wherein, the negative impedance conversion circuit comprises: an amplifier, the amplifier is in a negative feedback state; A charge and discharge acceleration circuit is used to provide charge and discharge current during the VSL establishment period.

2. The load current source module for image sensor readout according to claim 1, characterized in that: The current mirror circuit further includes: Two N-channel field effect transistors are connected via a common source and a common gate, the gates of the N-channel field effect transistors connected via a common source and a common gate are connected to a bias voltage, and the sources of the N-channel field effect transistors connected via a common source and a common gate are electrically connected to a pixel driving module, a negative impedance conversion circuit, and a charge and discharge acceleration circuit, respectively.

3. The load current source module for image sensor readout according to claim 1, characterized in that: The charge and discharge acceleration circuit comprises: A voltage-current conversion circuit, one end of which is connected to a drain power supply voltage, and the voltage-current conversion circuit is used for performing voltage-current conversion; A current amplifying circuit is electrically connected to the voltage-current conversion circuit, and is used to amplify the voltage-current conversion current.

4. The load current source module for image sensor readout according to claim 3, characterized in that: The voltage-current conversion circuit comprises: A first P-channel field effect transistor, one end of which is connected to a drain power supply voltage, and the first P-channel field effect transistor is used to provide a current source; a second P-channel field effect transistor, one end of which is also connected to a drain power supply voltage, and the second P-channel field effect transistor is used to provide a bias current; A capacitor, the capacitor is arranged at one side of the second P-channel field effect transistor, the capacitor is electrically connected to the second P-channel field effect transistor, and the capacitor is a bypass capacitor of the second P-channel field effect transistor; a third P-channel field effect transistor, wherein a gate of the third P-channel field effect transistor is connected to a vertical signal line signal output node, and a source of the third P-channel field effect transistor is connected to the second P-channel field effect transistor; A first N-channel field effect transistor, wherein the first N-channel field effect transistor is connected to the second P-channel field effect transistor, and the first N-channel field effect transistor is connected to a drain of the third P-channel field effect transistor; A second N-channel field effect transistor, wherein the second N-channel field effect transistor and the first N-channel field effect transistor form a current mirror.

5. The load current source module for image sensor readout according to claim 4, characterized in that: The amplifier is an operational amplifier, and the negative impedance conversion circuit further includes: A first resistor, the first resistor is electrically connected to the non-inverting input terminal of the amplifier; a second resistor, the second resistor being electrically connected to the inverting input terminal of the amplifier; A third resistor is electrically connected to the inverting input terminal of the amplifier, and the third resistor is connected in parallel with the second resistor.

6. The load current source module for image sensor readout according to claim 5, characterized in that: The negative impedance conversion circuit also includes: A first capacitor, wherein the first capacitor replaces the first resistor, and the first capacitor is electrically connected to the non-inverting input terminal of the amplifier.

7. The load current source module for image sensor readout according to claim 4, characterized in that: The amplifier is a common-gate amplifier, and the negative impedance conversion circuit further includes: A first capacitor, one end of which is electrically connected to the pixel driving module; a fourth P-channel field effect transistor, wherein a source of the fourth P-channel field effect transistor is electrically connected to the pixel driving module and is electrically connected to the first capacitor, and a gate of the fourth P-channel field effect transistor is connected to a bias voltage; A third N-channel field effect transistor, wherein a gate of the third N-channel field effect transistor is electrically connected to a bias voltage, and a source of the third N-channel field effect transistor is electrically connected to a drain of the fourth P-channel field effect transistor.

8. The load current source module for image sensor readout according to claim 7, characterized in that: The common gate amplifier is replaced by a source follower, and the negative impedance conversion circuit further includes: a fourth N-channel field effect transistor, wherein the fourth N-channel field effect transistor replaces the fourth P-channel field effect transistor, a gate of the fourth N-channel field effect transistor is electrically connected to a pixel driving module, a drain of the fourth N-channel field effect transistor is connected to a power supply, and a source of the fourth N-channel field effect transistor is electrically connected to a drain of the third N-channel field effect transistor; One end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit.

9. An image sensor readout system, characterized in that: An image sensor readout load current source module according to any one of claims 1 to 8 is used, and the readout system further comprises: A pixel noise detection module, the pixel noise detection module is electrically connected to the pixel driving module, and the pixel noise detection module is used to detect the pixel array in the pixel driving module; A reference slope generating module, wherein the reference slope generating module is electrically connected to the pixel driving module; A comparator, the comparator being electrically connected to the load current source module and the reference ramp generating module respectively; a counter, the counter being electrically connected to the comparator; A data transmission module is electrically connected to the counter.

10. An imaging device, characterized in that: An image sensor readout load current source module as claimed in any one of claims 1 to 8 or an image sensor readout system as claimed in claim 9 is used.

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