Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. A display device includes a display panel, a circuit board coupled to the display panel, and a metal pattern. The display panel includes: a base layer including a pad electrode exposed through an opening; and a circuit layer disposed on the base layer and including at least one signal line electrically connected to the pad electrode. The circuit board includes a base film including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; and a bump electrode disposed on the first portion. The first portion is disposed between the pad electrode and the bump electrode, and the metal pattern is disposed on the pad electrode and the bump electrode and electrically connects the pad electrode and the bump electrode to each other.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device including a base film capable of backside bonding to a circuit board and a method of manufacturing the display device. Background Art

[0002] Electronic devices such as smart phones, tablet computers, laptop computers, vehicle navigation systems, and smart televisions have been developed. These electronic devices are provided with display devices to display visual information to users.

[0003] Various types of display devices have been developed to meet desired user experience (UX) / user interface (UI) designs. Display devices have been developed to provide a wide display area and a narrow non-display area, so that the display device can provide an increased screen size while reducing the overall size of the device (particularly the bezel that can surround the displayed image). Summary of the invention

[0004] A display device includes: a display panel that displays an image; a circuit board that is coupled to the display panel; and a metal pattern that electrically connects the display panel and the circuit board to each other. The display panel includes: a base layer that includes a pad electrode exposed through an opening; and a circuit layer that is disposed on the base layer and includes at least one signal line electrically connected to the pad electrode. The circuit board includes: a base film that includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; and a protruding electrode that is disposed on the first portion. The first portion is disposed between the pad electrode and the protruding electrode, and the metal pattern is disposed on the pad electrode and the protruding electrode and electrically connects the pad electrode and the protruding electrode to each other.

[0005] The pad electrode may be a first pad electrode among a plurality of pad electrodes, and each of the plurality of pad electrodes may extend in a first direction and the plurality of pad electrodes may be arranged in a second direction intersecting the first direction.

[0006] The plurality of bump electrodes and the plurality of metal patterns may correspond to the plurality of pad electrodes.

[0007] The display device may further include an adhesive layer disposed between the first portion and the pad electrode.

[0008] The thickness of the adhesive layer may be greater than the first thickness.

[0009] The adhesive layer may include a non-conductive film.

[0010] The second portion includes a first sub-portion parallel to the base layer and a second sub-portion extending from the first sub-portion and including an inclined surface.

[0011] The second sub-portion may be disposed between the first sub-portion and the first portion, and may integrally connect the first sub-portion and the first portion.

[0012] The second portion may include an inclined portion whose thickness gradually decreases toward the first portion.

[0013] The inclined portion may be adjacent to the first portion.

[0014] The first portion may extend parallel to the pad electrode.

[0015] An edge of the first portion and an edge of the bump electrode may be aligned parallel to each other.

[0016] The base layer may include a first sub base layer defining an opening therein and a second sub base layer disposed on the first sub base layer. The pad electrode may be disposed between the first sub base layer and the second sub base layer.

[0017] The signal line may be disposed on an upper surface of the second sub base layer, and a contact hole may be formed in the second sub base layer, and the signal line and the pad electrode may be connected through the contact hole.

[0018] The first thickness may be in a range of about 3% to about 20% of the second thickness.

[0019] The display panel may include a display area and a non-display area, and the pad electrode may overlap the non-display area.

[0020] A method for manufacturing a display device, comprising: forming a display panel, the display panel comprising a base layer and a circuit layer, the base layer comprising a pad electrode exposed through an opening, the circuit layer comprising at least one signal line electrically connected to the pad electrode; forming a circuit board, the circuit board comprising a base film and a plurality of protruding electrodes, the base film comprising a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, the plurality of protruding electrodes being arranged on the first portion; aligning the display panel and the circuit board so that the first portion faces the pad electrode; bending the base film so that the first portion is parallel to the pad electrode; and forming a plurality of metal patterns on the protruding electrodes and the pad electrodes to electrically connect the protruding electrodes and the pad electrodes to each other through the metal patterns.

[0021] Forming a circuit board may include: providing a preliminary base film and a preliminary protruding electrode on the upper surface of the preliminary base film; forming a recess extending in a first direction on the lower surface of the preliminary base film facing the upper surface; and cutting the preliminary base film and the preliminary protruding electrode in a direction parallel to the first direction while overlapping with the recess.

[0022] Forming the circuit board may further include disposing an adhesive layer on the recesses before cutting the preliminary base film and the preliminary bump electrodes.

[0023] An edge of the adhesive layer, an edge of the first portion, and an edge of the bump electrode may be aligned parallel to each other in a thickness direction of the base film.

[0024] Forming the circuit board may further include inverting the preliminary base film and the preliminary bump electrodes before forming the recesses.

[0025] The bending the base film may include bending the base film by pressing the bump electrode disposed on the first portion directly toward the pad electrode.

[0026] An angle formed between the first portion and the second portion before the base film is bent may be an obtuse angle.

[0027] Forming the metal pattern may include: disposing a metal layer on the pad electrode and the bump electrode; and patterning the metal layer to form the metal pattern.

[0028] Patterning the metal layer may include exposing a portion of the metal layer in a region not overlapping the pad electrode with a laser beam. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0030] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0031] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0032] Figure 3 It is along Figure 2 A cross-sectional view of the display device taken along line II'.

[0033] Figure 4 is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure.

[0034] Figure 5 is a plan view of a display panel according to an embodiment of the present disclosure.

[0035] Figure 6 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0036] Figure 7 is a plan view of a display panel according to an embodiment of the present disclosure.

[0037] Figure 8 is an enlarged plan view showing a portion of a display device according to an embodiment of the present disclosure.

[0038] Fig. 9 It is along Figure 8 A cross-sectional view of the display device taken along line II-II'.

[0039] Fig. 10A is a cross-sectional view of a flexible circuit board according to an embodiment of the present disclosure.

[0040] Fig. 10B is a cross-sectional view of a flexible circuit board according to an embodiment of the present disclosure.

[0041] Fig.11 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0042] FIG. 12A to FIG. 12F , FIG. 13A to FIG. 13C as well as FIG. 14A to FIG. 14B are views illustrating some operations of a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In describing the embodiments of the present disclosure illustrated in the accompanying drawings, specific terminology is employed for the sake of clarity. However, the present disclosure is not necessarily intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner.

[0044] In this specification, the expression that a first component (or a first region, a first layer, a first part, a first portion, etc.) is "disposed on", "connected to" or "coupled to" a second component may mean that the first component is directly disposed on / directly connected to / directly coupled to the second component, or may mean that a third component is interposed between the first component and the second component.

[0045] Throughout the specification and the drawings, the same reference numerals may represent the same components. In addition, in the drawings, in order to effectively describe the technical content, the thickness, ratio and size of the components may be exaggerated.

[0046] The term "and / or" includes all combinations of one or more components that can be defined by the relevant configurations.

[0047] The terms "first", "second", etc. are used to describe various components, but these components should not necessarily be limited by these terms. These terms are used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. Singular expressions include plural expressions unless otherwise clearly indicated in the context.

[0048] In addition, the terms "under", "below", "on", "over", etc. are used to describe the relationship between components shown in the drawings. These terms have relative concepts and are described with reference to the directions shown in the drawings.

[0049] It will be understood that the terms “include,” “comprising,” “having,” etc. specify the presence of the features, quantities, steps, operations, elements or components, or a combination thereof, described in the specification, but do not exclude the presence or possibility of adding one or more other features, quantities, steps, operations, elements or components, or a combination thereof.

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure. Figure 3 It is along Figure 2 A cross-sectional view of the display device taken along line II'.

[0052] refer to Figure 1 , the electronic device ED according to an embodiment of the present disclosure may include a display surface DS defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The electronic device ED may provide an image IM to a user through the display surface DS.

[0053] The display surface DS may include a display area DA and a non-display area NDA that at least partially surrounds the display area DA (as used herein, the phrase "at least partially surrounds" may mean touching on one or more sides, up to and including completely surrounding on all sides). The display area DA may be an area where the image IM is displayed, and the non-display area NDA may be an area where the image IM is not displayed. The non-display area NDA may completely surround the display area DA. However, the present disclosure is not necessarily limited thereto, and the shape of the display area DA and the shape of the non-display area NDA may be modified.

[0054] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The third direction DR3 is used as a criterion for distinguishing the front surface and the rear surface of each of the structures. In this specification, the wording "on a plane" or "in a plan view" may be defined as a state in which the display device DD is observed in the third direction DR3.

[0055] In an embodiment of the present disclosure, the electronic device ED may be a foldable electronic device that can be folded around a folding axis without breaking or otherwise being damaged. The folding axis may be parallel to the first direction DR1 or the second direction DR2, and the folding area may be defined in a portion of the display area DA. The electronic device ED may be folded inwardly so that the display areas DA face each other (thereby creating a state in which the display is protected while folding) or folded outwardly so that the display areas DA face away from each other (thereby creating a state in which the display can still be observed while folding).

[0056] like Figure 2 As shown in FIG, the electronic device ED may include a display device DD, an electronic module EM, a power supply module PSM and a housing HM. Figure 2 The electronic device ED is briefly shown, and may further include a mechanical structure (eg, a hinge) for controlling the operation (eg, folding or rolling) of the display device DD.

[0057] The display device DD generates an image IM and senses external input. The display device DD includes a window WM, an upper structure UM, a display module DM, a lower structure LM, a flexible circuit board (or circuit board) FCB, and a driving chip DIC. The upper structure UM includes a structure arranged on the display module DM, and the lower structure LM includes a structure arranged under the display module DM. As used herein, the phrase "structure" means a layer or an element.

[0058] The window WM provides a front surface of the electronic device ED. The window WM includes a transmissive area TA and a bezel area BZA. Figure 1 The display area DA and the non-display area NDA of the display surface DS shown in FIG. 1 are defined by the transmissive area TA and the bezel area BZA. The transmissive area TA is a region through which an image passes, and the bezel area BZA is a region covering a structure disposed under the window WM.

[0059] The display module DM includes Figure 1 The display area DA and the non-display area NDA shown in the figure correspond to the display area DM-DA and the non-display area DM-NDA. In this specification, the expression "the area / portion and the area / portion correspond to each other" means that the area / portion and the area / portion overlap each other and are not necessarily limited to the same area.

[0060] The pad area PA is disposed on one side of the non-display area DM-NDA. The pad area PA is an area electrically bonded (or connected) to a flexible circuit board FCB to be described below. In an embodiment, the pad area PA is defined on the rear surface of the display module DM.

[0061] The display module DM has a substantially quadrilateral shape in a plan view. Here, the "substantially quadrilateral shape" includes not only a quadrilateral shape in a mathematical sense, but also a shape similar to a quadrilateral shape that can be recognized as a quadrilateral shape by a user. For example, the substantially quadrilateral shape may include a quadrilateral shape having a rounded corner area. In addition, in the substantially quadrilateral shape, the edge of the display module DM is not necessarily limited to a straight line shape, and the edge may include a curved area.

[0062] The upper structure UM may include a protective film or an optical film. The optical film may include a polarizer and a retarder to reduce the reflection of external light. The lower structure LM may include a protective film for protecting the display module DM, a supporting structure for supporting the display module DM, a digitizer, etc. The upper structure UM and the lower structure LM will be described in detail below.

[0063] The flexible circuit board FCB is disposed under the display module DM. The flexible circuit board FCB may be bonded to the rear surface of the display module DM. The flexible circuit board FCB connects the display module DM and the main circuit board MCB (see Figure 3 ) are electrically connected to each other. The flexible circuit board FCB includes at least one insulating layer and at least one conductive layer. The conductive layer may include a plurality of signal lines.

[0064] The driving chip DIC may be mounted on the flexible circuit board FCB. The driving chip DIC may include a chip for driving the display panel DP (see Figure 4 ) of the pixel driving circuit (eg, data driving circuit). Figure 2 , a structure in which the driving chip DIC is mounted on the flexible circuit board FCB is shown, but the present disclosure is not necessarily limited thereto. For example, the driving chip DIC may be mounted on the display module DM or the main circuit board MCB.

[0065] The electronic module EM may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, etc. The electronic module EM may include a main circuit board MCB, and the module may be mounted on the main circuit board MCB or may be electrically connected to the main circuit board MCB through a flexible circuit board FCB. The electronic module EM is electrically connected to a power supply module PSM.

[0066] The electronic device ED may further include an electro-optical module. The electro-optical module may be an electronic component that outputs or receives an optical signal. The electro-optical module may include a camera module and / or a proximity sensor. The camera module may capture an external image through a portion of the display module DM.

[0067] Figure 2The housing HM shown in FIG. 1 is coupled to a display device DD (e.g., a window WM) to accommodate other modules. The housing HM is shown to have an integral shape (e.g., a single uninterrupted structure), but the present disclosure is not necessarily limited thereto. The housing HM may include a plurality of portions (e.g., a side edge portion and a bottom portion) coupled to each other.

[0068] refer to Figure 3 The window WM may include a base substrate BS and a frame pattern BM disposed on the lower surface of the base substrate BS. The base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multi-layer structure. The base substrate BS may include a thin film glass substrate, a protective film disposed on the thin film glass substrate, and an adhesive layer bonding the thin film glass substrate and the protective film.

[0069] The frame pattern BM as a colored light shielding film can be formed by, for example, a coating method. The frame pattern BM may include a base material and a dye or pigment mixed with the base material. Figure 1 The non-display area NDA and Figure 2 The frame area BZA shown in FIG. overlaps. The frame pattern BM may be disposed on the lower surface of the base substrate BS. When the base substrate BS has a multilayer structure, the frame pattern BM may be disposed between interfaces defined by multiple layers. For example, the frame pattern BM may be disposed between the thin film glass substrate and the protective film. The window WM may also include a hard coating, an anti-fingerprint layer, and / or an anti-reflection layer on the upper surface of the base substrate BS.

[0070] The upper structure UM may include an upper film. The upper film may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, triacetyl cellulose, polymethyl methacrylate, or polyethylene terephthalate.

[0071] The upper film can absorb external impact applied to the front surface of the display device DD. In an embodiment of the present disclosure, the display module DM may include a color filter as an anti-reflection structure instead of a polarizing film, and therefore, the front impact strength of the display device DD may be reduced. The upper film can compensate for the reduced impact strength by applying a color filter.

[0072] The upper structure UM and the border area BZA (see Figure 2 ) and the transmissive area TA (see Figure 2 ) overlap. The upper structure UM may overlap only a portion of the border pattern BM. The portion of the border pattern BM may be exposed from the upper structure UM. In an embodiment of the present disclosure, the upper structure UM may be omitted. In an embodiment of the present disclosure, the upper structure UM may be replaced with an optical film including a polarizer and a retarder.

[0073] An adhesive layer bonding the upper structure UM and the window WM to each other may further be included between the upper structure UM and the window WM. The adhesive layer may be, for example, a pressure sensitive adhesive (PSA) film or an optically clear adhesive (OCA) structure.

[0074] The display module DM is disposed under the upper structure UM. The display module DM overlaps the frame area BZA and the transmission area TA. The display module DM may completely overlap the upper structure UM within the frame area BZA. The side surface of the display module DM may be aligned with the side surface of the upper structure UM, and the edge of the display module DM may be aligned with the edge of the upper structure UM on a plane (e.g., in a plan view).

[0075] The pad area PA of the display module DM within the bezel area BZA may overlap with the upper structure UM. A portion of the display module DM corresponding to the pad area PA may be bonded to the lower surface of the upper structure UM by an adhesive layer. The pad area PA overlaps with the upper structure UM, and a portion of the display module DM overlapping with the pad area PA is coupled to the upper structure UM. Therefore, when the flexible circuit board FCB is bonded to the pad area PA, the upper structure UM may fully support the pad area PA.

[0076] The lower structure LM may include a lower film PF and a cover panel CP. In an embodiment of the present disclosure, the lower structure LM may further include a support plate and a digitizer.

[0077] The lower film PF may expose the pad area PA of the display module DM. The lower film PF may have a size smaller than that of the display module DM. For example, the lower film PF may overlap only with the display area DM-DA of the display module DM. An opening area PF-OP corresponding to the non-display area DM-NDA may be defined in the lower film PF. Optionally, the lower film PF may have a size substantially corresponding to the display module DM. In this case, an opening area PF-OP corresponding to the pad area PA may be defined in the lower film PF. The pad area PA may be exposed through the opening area PF-OP.

[0078] The lower film PF may expose the pad area PA. The lower film PF may have an area smaller than that of the display module DM. For example, the lower film PF may overlap only with the display area DA. The lower film PF may have an area substantially the same as that of the display module DM. An opening area PF-OP corresponding to the pad area PA may be defined in the lower film PF. The pad area PA may be exposed through the opening area PF-OP.

[0079] The cover panel CP may be disposed under the lower film PF. The cover panel CP may increase the resistance against the compressive force generated by the external pressure. Therefore, the cover panel CP may prevent deformation of the display module DM. The cover panel CP may include a flexible plastic material such as polyimide or polyethylene terephthalate. In addition, the cover panel CP may be a colored film with low light transmittance. The cover panel CP may absorb ambient light. For example, the cover panel CP may be a black synthetic resin film. When the display device DD is observed from the front side of the window WM, the components arranged under the cover panel CP may not be visually recognized by the user.

[0080] The support plate may be further arranged under the cover panel CP. The support plate may include a metal with high strength. The support plate may also include a reinforced fiber composite material. The support plate may include a reinforcing fiber arranged inside the base portion. The reinforcing fiber may be a carbon fiber or a glass fiber. The base portion may include a polymer resin. The base portion may include a thermoplastic resin. For example, the base portion may include a polyamide-based resin or a polypropylene-based resin. For example, the reinforced fiber composite material may be a carbon fiber reinforced plastic (CFRP) or a glass fiber reinforced plastic (GFRP).

[0081] The main circuit board MCB may be placed on the lower surface of the flexible circuit board FCB. The flexible circuit board FCB may include an insulating film and a conductive wiring line mounted on the insulating film. The main circuit board MCB may include signal lines and various other electronic components. The electronic components may be connected to the signal lines and electrically connected to the display module DM. The electronic components generate various electrical signals (for example, signals for generating images or signals for detecting external inputs) or process sensed signals. Different main circuit boards MCB may correspond to each of the electrical signals for generation and processing, and three or more main circuit boards MCB may be provided, but the present disclosure is not necessarily limited thereto.

[0082] The main circuit board MCB may include a driver chip DIC mounted in the main circuit board MCB (see Figure 2 ).

[0083] refer to Figure 2 and Figure 3 , the flexible circuit board FCB is bonded (rear surface bonded) to the rear surface of the display module DM. Since the non-display area DM-NDA of the display module DM is not bent, defects occurring in the non-display area DM-NDA of the display module DM during bending can be prevented. In addition, the area of ​​the bezel area BZA of the window WM for covering the non-display area DM-NDA of the display module DM can be reduced.

[0084] Figure 4 is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure.

[0085] refer to Figure 4 The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-ED and an encapsulation layer TFE.

[0086] The circuit layer DP-CL is disposed on the upper surface of the base layer BL. The base layer BL may be a flexible substrate that can be bent, folded, and rolled. The base layer BL may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiments of the present disclosure are not necessarily limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. For example, the base layer BL has the same shape as that of the display panel DP.

[0087] The base layer BL may have a multi-layer structure. For example, the base layer BL may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed between the first synthetic resin layer and the second synthetic resin layer. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, but the present disclosure is not necessarily particularly limited thereto.

[0088] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and signal lines. The circuit layer DP-CL may include a driving circuit for a pixel. Hereinafter, unless otherwise specified, when component A and component B are arranged on the same layer, it is interpreted that component A and component B are formed by the same process and therefore include the same material or are part of the same stacked structure. Conductive patterns or semiconductor patterns arranged on the same layer may be interpreted as described above.

[0089] The display element layer DP-ED may be disposed on the circuit layer DP-CL. The display element layer DP-ED may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro light emitting diode (LED), or a nano LED.

[0090] The encapsulation layer TFE may be disposed on the display element layer DP-ED. The encapsulation layer TFE may protect the display element layer DP-ED (i.e., the light emitting element) from foreign matter such as moisture, oxygen, and dust particles. The encapsulation layer TFE may include at least one inorganic encapsulation layer. The encapsulation layer TFE may include a stacked structure of a first inorganic encapsulation layer / an organic encapsulation layer / a second inorganic encapsulation layer.

[0091] The input sensing layer ISL may be directly disposed on the display panel DP. The input sensing layer ISL may detect the user's input using, for example, an electromagnetic induction method or a capacitive method. The display panel DP and the input sensing layer ISL may be formed by a continuous process. Here, saying that the input sensing layer ISL is directly disposed on the display panel DP may mean that no third component is disposed between the input sensing layer ISL and the display panel DP. For example, a separate adhesive layer may not be disposed between the input sensing layer ISL and the display panel DP.

[0092] Figure 5 is a plan view of a display panel according to an embodiment of the present disclosure. Figure 6 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0093] like Figure 5 As shown in FIG. 1 , the display panel DP may include a scan drive circuit SDC, a plurality of signal lines SGL, and a plurality of pixels PX. The plurality of pixels PX are arranged in the display area DM-DA. Each of the pixels PX includes a light emitting element and a pixel drive circuit connected thereto. The scan drive circuit SDC, the plurality of signal lines SGL, and the pixel drive circuit may include Figure 4 The circuit layer DP-CL is shown in FIG.

[0094] The scan drive circuit SDC may include a gate drive circuit. The gate drive circuit generates a plurality of scan signals and sequentially outputs the plurality of scan signals to a plurality of scan lines GL to be described below. The scan drive circuit SDC may also include a light emitting drive circuit separate from the gate drive circuit. The light emitting drive circuit may output scan signals to another group of scan lines.

[0095] The scan driving circuit SDC may include a plurality of thin film transistors formed by the same process as that of the pixel driving circuit (eg, a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process).

[0096] The plurality of signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the scan lines GL is connected to a corresponding pixel PX among the plurality of pixels PX, and each of the data lines DL is connected to a corresponding pixel PX among the plurality of pixels PX. The power lines PL are connected to the plurality of pixels PX. The data lines DL provide data signals to the pixels PX. The control signal lines CSL may provide control signals to the scan drive circuit SDC.

[0097] A plurality of power lines PL may be provided. For example, the power lines PL may include a first power line receiving a first power voltage and a second power line receiving a second power voltage having a level higher than that of the first power voltage. The first power voltage is provided to the pixel PX through the first power line, and the second power voltage is provided to the pixel PX through the second power line. Figure 5 Although one control signal line CSL is exemplarily shown in FIG. 1 , a plurality of control signal lines CSL may be provided.

[0098] The scan lines GL, the data lines DL, and the power lines PL may overlap the display area DM-DA and the non-display area DM-NDA, and the control signal lines CSL may overlap the non-display area DM-NDA. The distal ends of the plurality of signal lines SGL may be aligned on one side of the non-display area DM-NDA. The plurality of signal lines SGL may have an integral shape (e.g., a single uninterrupted structure), but may optionally include a plurality of portions arranged on different layers. The different portions divided by the insulating layer may be connected by contact holes passing through the insulating layer. For example, the data line DL may include a first portion disposed in the display area DM-DA and a second portion disposed in the non-display area DM-NDA and disposed on a layer different from that of the first portion. The first portion and the second portion may include different materials and have different stacked structures.

[0099] The plurality of signal lines SGL may be electrically connected to the pad area PA. Figure 3 The main circuit board MCB shown in FIG.

[0100] Figure 6 shows the display module DM and Figure 5 The cross section corresponding to the pixel PX.

[0101] The pixel driving circuit PC driving the light emitting element LD may include a plurality of pixel driving elements. The pixel driving circuit PC may include a plurality of transistors S-TFT and O-TFT and a capacitor Cst. The plurality of transistors S-TFT and O-TFT may include a silicon transistor S-TFT and an oxide transistor O-TFT. Figure 6 A silicon transistor S-TFT and an oxide transistor O-TFT are exemplarily shown. Figure 6 The pixel driving circuit PC of FIG. 1 is only an embodiment, and the configuration of the pixel driving circuit PC is not necessarily limited thereto. The pixel driving circuit PC may include only one type of transistor of a silicon transistor S-TFT and an oxide transistor O-TFT.

[0102] refer to Figure 6, the base layer BL is shown as a single layer. The base layer BL may include a synthetic resin such as polyimide. The base layer BL may be formed by coating a working substrate (or a carrier substrate) with a synthetic resin layer. When the display module DM is completed through a subsequent process, the working substrate may be removed.

[0103] refer to Figure 6 , the barrier layer BRL may be disposed on the base layer BL. The barrier layer BRL prevents foreign objects from penetrating into the lower layer. The barrier layer BRL may include at least one inorganic layer. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plurality, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0104] The barrier layer BRL may include a lower barrier layer BRL1 and an upper barrier layer BRL2. The first shielding electrode BML1 may be disposed between the lower barrier layer BRL1 and the upper barrier layer BRL2. The first shielding electrode BML1 may correspond to a silicon transistor S-TFT. The first shielding electrode BML1 may include a metal, for example, molybdenum.

[0105] The first shielding electrode BML1 may receive a bias voltage. The first shielding electrode BML1 may also receive a first power voltage. The first shielding electrode BML1 may prevent the potential caused by the polarization phenomenon from affecting the silicon transistor S-TFT. The first shielding electrode BML1 may prevent external light from reaching the silicon transistor S-TFT. In an embodiment of the present disclosure, the first shielding electrode BML1 may also be a floating electrode isolated from other electrodes or wiring lines.

[0106] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BL to the upper first semiconductor pattern SC1. The buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0107] The first semiconductor pattern SC1 may be disposed on the buffer layer BFL. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 may include low temperature polycrystalline silicon (LTPS).

[0108] The first semiconductor pattern SC1 may have different electrical properties depending on whether the first semiconductor pattern SC1 is doped. The first semiconductor pattern SC1 may include a first region having a relatively high conductivity and a second region having a relatively low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped at a lower concentration than that of the first region. In an embodiment, the first semiconductor pattern SC1 may be an N-type transistor.

[0109] The conductivity of the first region is greater than that of the second region, and the first region can be substantially used as an electrode or a signal line. The second region can substantially correspond to a channel region (or an active region) of a transistor. For example, a portion of the first semiconductor pattern SC1 can be a channel region of a transistor, another portion of the first semiconductor pattern SC1 can be a source region or a drain region of the transistor, and another portion of the first semiconductor pattern SC1 can be a connection electrode or a connection signal line.

[0110] A source region SE1, a channel region AC1 (or active region), and a drain region DE1 of the silicon transistor S-TFT may be formed of the first semiconductor pattern SC1. The source region SE1 and the drain region DE1 may extend in opposite directions from the channel region AC1 in a cross section.

[0111] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layer silicon oxide layer. The first insulating layer 10 and an inorganic layer of the circuit layer DP-CL to be described below may have a single-layer structure or a multi-layer structure and include at least one of the above materials, but the present disclosure is not necessarily limited thereto.

[0112] The gate GT1 of the silicon transistor S-TFT is disposed on the first insulating layer 10. The gate GT1 may be a part of the metal pattern. The gate GT1 overlaps the channel region AC1. The gate GT1 may be used as a mask in the process of doping the first semiconductor pattern SC1. The first electrode CE10 of the capacitor Cst is disposed on the first insulating layer 10. Figure 6 Different from the illustration, the first electrode CE10 may have a shape integral with the gate electrode GT1.

[0113] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate electrode GT1. In an embodiment of the present disclosure, an upper electrode overlapping the gate electrode GT1 may be further disposed on the second insulating layer 20. A second electrode CE20 overlapping the first electrode CE10 may be disposed on the second insulating layer 20. The upper electrode may have a shape integral with the second electrode CE20, for example, they may be a single uninterrupted structure.

[0114] The second shielding electrode BML2 is disposed on the second insulating layer 20. The second shielding electrode BML2 may correspond to the oxide transistor O-TFT. In an embodiment of the present disclosure, the second shielding electrode BML2 may be omitted. According to an embodiment of the present disclosure, the first shielding electrode BML1 may extend to a lower portion of the oxide transistor O-TFT and replace the second shielding electrode BML2.

[0115] The third insulating layer 30 may be disposed on the second insulating layer 20. The second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a metal oxide semiconductor such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x ) or indium oxide (In 2 O 3 )'s transparent conductive oxide (TCO).

[0116] The metal oxide semiconductor may include a plurality of regions SE2, AC2, and DE2 divided according to whether the TCO is reduced. The region in which the TCO is reduced (hereinafter, referred to as the reduction region) has a higher conductivity than the region in which the TCO is not reduced (hereinafter, referred to as the non-reduction region). The reduction region is basically used as a source / drain region or a signal line of a transistor. The non-reduction region basically corresponds to a semiconductor region (or channel region) of a transistor. For example, a portion of the second semiconductor pattern SC2 may be a semiconductor region of a transistor, another portion of the second semiconductor pattern SC2 may be a source region SE2 / drain region DE2 of the transistor, and another portion of the second semiconductor pattern SC2 may be a signal transmission region.

[0117] The fourth insulating layer 40 may be disposed on the third insulating layer 30. Figure 6 As shown in FIG. 4 , the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In an embodiment of the present disclosure, the fourth insulating layer 40 may be an insulating pattern overlapping the gate electrode GT2 of the oxide transistor O-TFT and exposing the source region SE2 and the drain region DE2 of the oxide transistor O-TFT.

[0118] The gate GT2 of the oxide transistor O-TFT is disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a part of the metal pattern. The gate GT2 of the oxide transistor O-TFT overlaps with the channel region AC2.

[0119] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40, and the fifth insulating layer 50 may cover the gate GT2. Each of the first to fifth insulating layers 10 to 50 may be an inorganic layer.

[0120] The first connection pattern CNP1 and the second connection pattern CNP2 may be arranged on the fifth insulating layer 50. The first connection pattern CNP1 and the second connection pattern CNP2 may be formed by the same process, and thus may be composed of the same material, and may be part of the same stacked structure. The first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT through a first pixel contact hole PCH1 passing through the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT through a second pixel contact hole PCH2 passing through the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship between the first connection pattern CNP1 and the second connection pattern CNP2 for the silicon transistor S-TFT and the oxide transistor O-TFT is not necessarily limited thereto.

[0121] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The third connection pattern CNP3 may be disposed on the sixth insulating layer 60. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 through the third pixel contact hole PCH3 passing through the sixth insulating layer 60. The data line DL may be disposed on the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL may be formed by the same process, and thus may be composed of the same material, and may be part of the same stacked structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0122] The first shielding electrode BML1, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT may include molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium having excellent heat resistance. The first connection pattern CNP1 and the second connection pattern CNP2 may include aluminum having high electrical conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a three-layer structure in which titanium / aluminum / titanium are stacked.

[0123] The light emitting element LD may include an anode AE ​​(or a first electrode), a light emitting layer EL, and a cathode CE (or a second electrode). The anode AE ​​of the light emitting element LD may be disposed on the seventh insulating layer 70. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may include a stacked structure in which ITO / Ag / ITO are stacked in sequence. The positions of the anode AE ​​and the cathode CE may be changed with each other.

[0124] The pixel defining film PDL may be disposed on the seventh insulating layer 70. The pixel defining film PDL may be an organic layer. The pixel defining film PDL may have a property of absorbing light, and for example, the pixel defining film PDL may have a black color. The pixel defining film PDL may include a black colorant. The black colorant may include a black dye and / or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining film PDL may correspond to a shading pattern having a shading property.

[0125] The pixel defining film PDL may cover a portion of the anode AE. For example, an opening PDL-OP may be defined in the pixel defining film PDL, and a portion of the anode AE ​​is exposed through the opening PDL-OP. The light emitting area LA may be defined to correspond to the opening PDL-OP. In an embodiment of the present disclosure, a hole control layer may be disposed between the anode AE ​​and the light emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. The electron control layer may be disposed between the light emitting layer EL and the cathode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer.

[0126] The encapsulation layer TFE may cover the light emitting element LD. The encapsulation layer TFE may include a first encapsulation insulating layer IL1, a second encapsulation insulating layer IL2, and a third encapsulation insulating layer IL3. However, the present disclosure is not necessarily limited thereto, and the encapsulation layer TFE may also include a plurality of inorganic layers and a plurality of organic layers.

[0127] The first encapsulation insulating layer IL1 may be an inorganic layer. The first encapsulation insulating layer IL1 may prevent external moisture or oxygen from penetrating into the light emitting element LD. For example, the first encapsulation insulating layer IL1 may include silicon nitride, silicon oxide, or a compound obtained by combining them. The first encapsulation insulating layer IL1 may be formed by a chemical vapor deposition process.

[0128] The second encapsulation insulating layer IL2 may be an organic layer. The second encapsulation insulating layer IL2 may be disposed on the first encapsulation insulating layer IL1 and may be in contact with the first encapsulation insulating layer IL1. The second encapsulation insulating layer IL2 may provide a flat surface to the first encapsulation insulating layer IL1. The curved surface formed on the upper surface of the first encapsulation insulating layer IL1 and the particles present on the first encapsulation insulating layer IL1 are covered by the second encapsulation insulating layer IL2, and thus the surface condition of the upper surface of the first encapsulation insulating layer IL1 may be prevented from affecting the components formed on the second encapsulation insulating layer IL2. In addition, the second encapsulation insulating layer IL2 may relieve stress between contact layers. The second encapsulation insulating layer IL2 may be formed by a solution process such as spin coating, slit coating, and inkjet process.

[0129] The third encapsulation insulating layer IL3 is disposed on the second encapsulation insulating layer IL2 and covers the second encapsulation insulating layer IL2. Compared with a state in which the third encapsulation insulating layer IL3 is disposed on the first encapsulation insulating layer IL1, the third encapsulation insulating layer IL3 can be stably formed on a relatively flat surface. The third encapsulation insulating layer IL3 encapsulates moisture released from the second encapsulation insulating layer IL2 and thus prevents the introduction of external moisture.

[0130] The third encapsulation insulating layer IL3 may be optically transparent. For example, the third encapsulation insulating layer IL3 may have a visible light transmittance of about 90% or more. The third encapsulation insulating layer IL3 may have a relatively high light transmittance compared to the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 may be an inorganic layer. The third encapsulation insulating layer IL3 may include silicon oxide (SiO x ) or silicon oxynitride (SiON). The third encapsulation insulating layer IL3 may be formed by a chemical vapor deposition process. Each of the first encapsulation insulating layer IL1, the second encapsulation insulating layer IL2, and the third encapsulation insulating layer IL3 may include a plurality of layers, but the present disclosure is not necessarily limited to the embodiments.

[0131] The input sensing layer ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In an embodiment, the input sensing layer ISL may include a first sensing insulating layer IS-IL1, a first conductive layer ICL1, a second insulating layer IS-IL2, a second conductive layer ICL2, and a third insulating layer IS-IL3. Figure 6 The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 are briefly shown.

[0132] The first sensing insulating layer IS-IL1 may be directly disposed on the display panel DP. The first sensing insulating layer IS-IL1 may be an inorganic layer including silicon nitride, silicon oxynitride and / or silicon oxide. Each of the first conductive layer ICL1 and the second conductive layer ICL2 may have a single-layer structure or a multi-layer structure in which layers are stacked in the third direction DR3. The first conductive layer ICL1 and the second conductive layer ICL2 may include conductive lines defining a mesh electrode. The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 may or may not be connected through contact holes passing through the second insulating layer IS-IL2. The connection relationship between the conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 may be determined according to the type of sensor formed in the input sensing layer ISL.

[0133] The first conductive layer ICL1 and the second conductive layer ICL2 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ) or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire, graphene, etc.

[0134] The first conductive layer ICL1 and the second conductive layer ICL2 having a multilayer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The first conductive layer ICL1 and the second conductive layer ICL2 having a multilayer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer IS-IL2 may be disposed between the first conductive layer ICL1 and the second conductive layer ICL2. The third insulating layer IS-IL3 may cover the second conductive layer ICL2. In an embodiment of the present disclosure, the third insulating layer IS-IL3 may be omitted. The second insulating layer IS-IL2 and the third insulating layer IS-IL3 may include an inorganic layer or an organic layer.

[0135] Figure 7 is a plan view of a display panel according to an embodiment of the present disclosure. Figure 7 is a plan view of the display panel DP when viewed from a third direction DR3.

[0136] refer to Figure 7 The pad electrode PD may be arranged on the rear surface of the display panel DP. For example, the pad electrode PD may be arranged in the pad area PA. The pad electrode PD may be arranged in the second direction DR2.

[0137] A plurality of signal lines SGL (see Figure 5) can be electrically connected to the pad area PA Figure 3 For example, a plurality of signal lines SGL may be arranged in the pad area PA and connected to pad electrodes PD spaced apart from each other in the second direction DR2 through connection electrodes or the like. The pad electrodes PD may be arranged on the rear surface of the display panel DP and electrically connected to the flexible circuit board FCB (see Figure 2 ). A detailed description will be made below in which the flexible circuit board FCB and the plurality of signal lines SGL are connected.

[0138] Figure 8 is an enlarged plan view showing a portion of a display device according to an embodiment of the present disclosure. Fig. 9 It is along Figure 8 A cross-sectional view of the display device taken along line II-II'. Figure 8 and Fig. 9 is a view showing a state in which the flexible circuit board FCB is attached to the display panel DP. Hereinafter, in the case where an element is not described in detail with reference to the drawing, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0139] refer to Figure 8 and Fig. 9 According to the present disclosure, the display device DD may include a connection electrode CNE and a plurality of pad electrodes PD. The connection electrode CNE is disposed at Figure 6 The first connection pattern CNP1 shown in FIG. 1 is on the same layer as the first connection pattern CNP1, and a portion of the data link line DL-C overlapping the non-display area DM-NDA is disposed on the same layer as the first connection pattern CNP1 shown in FIG. Figure 6 The gate electrode GT1 of the silicon transistor S-TFT is on the same layer. The data connection line DL-C can be electrically connected to Figure 6 The data line DL in.

[0140] The pad electrode PD may be exposed through the lower surface BL-LS of the base layer BL for rear surface bonding with the flexible circuit board FCB. However, the present disclosure is not necessarily limited thereto, and the pad electrode PD may not be directly exposed but may be exposed through a contact hole, etc. The lower surface BL-LS of the base layer BL faces the upper surface BL-US of the base layer BL in the third direction DR3.

[0141] The base layer BL may include a first sub-base layer SBL1, a first base insulating layer BIL1, a second base insulating layer BIL2, and a second sub-base layer SBL2. The first base insulating layer BIL1 is disposed on the first sub-base layer SBL1, and the second base insulating layer BIL2 is disposed on the first base insulating layer BIL1 and covers the pad electrode PD. The second sub-base layer SBL2 is disposed on the second base insulating layer BIL2.

[0142] The first sub-base layer SBL1 and the second sub-base layer SBL2 may include a synthetic resin material, for example, polyimide. The first basic insulating layer BIL1 and the second basic insulating layer BIL2 may include an inorganic material. For example, the first basic insulating layer BIL1 and the second basic insulating layer BIL2 may include silicon nitride, silicon oxynitride, or silicon oxide.

[0143] The first basic insulating layer BIL1 is disposed on the first sub-base layer SBL1, and a first opening B1-OP is defined in the first basic insulating layer BIL1, and a portion of the pad electrode PD is exposed through the first opening B1-OP. The first sub-base layer SBL1 may be disposed below the first basic insulating layer BIL1. The first sub-base layer SBL1 provides a lower surface BL-LS of the base layer BL, and a second opening B2-OP is defined in the first sub-base layer SBL1, and the pad electrode PD is exposed to the outside of the display module DM through the second opening B2-OP. The second opening B2-OP may expose a portion of the first basic insulating layer BIL1. The size of the second opening B2-OP is greater than the size of the first opening B1-OP.

[0144] The pad electrode PD may be embedded in the base layer BL. For example, in an embodiment, the base layer BL includes a pad electrode PD exposed through a first opening B1-OP and a second opening B2-OP. However, the present disclosure is not necessarily limited thereto, and the pad electrode PD may be arranged on the lower surface BL-LS of the base layer BL. Even when the base layer BL includes a single synthetic resin layer or a plurality of layers, the first opening B1-OP and the second opening B2-OP described above may not be limited. The pad electrode PD arranged on the lower surface BL-LS of the base layer BL may be connected to a conductive pattern disposed on the upper surface BL-US of the base layer BL through a contact hole passing through the base layer BL.

[0145] The connection electrode CNE may be connected to the pad electrode PD through the first contact hole CH1, and connected to the data connection line DL-C through the second contact hole CH2. The first contact hole CH1 and the second contact hole CH2 may be arranged in the non-display area DM-NDA. The first contact hole CH1 may be formed by passing through a plurality of insulating layers 10 to 50, a barrier layer BRL, a buffer layer BFL, and a portion of a base layer BL. The first contact hole CH1 may be connected to the pad electrode PD through a second base insulating layer BIL2 and a second sub-base layer SBL2 of the base layer BL. The second contact hole CH2 may be formed by passing through the second insulating layer 20 to the fifth insulating layer 50. The connection electrode CNE may be connected to the data line DL through the second contact hole CH2 (see Figure 6 ).

[0146] The pad electrode PD may extend in the first direction DR1 and be arranged in the second direction DR2. The shape and arrangement of the pad electrode PD are not necessarily limited to the above illustrations. The pad electrode PD may overlap the non-display area DM-NDA. For example, the pad electrode PD may be arranged in the pad area PA.

[0147] The flexible circuit board FCB may include a base film BF and a protruding electrode BMP disposed under the base film BF. The flexible circuit board FCB may be attached to the display panel DP in a bent state on the rear surface of the display panel DP. An adhesive layer may be disposed between the flexible circuit board FCB and the lower surface BL-LS of the base layer BL to fix the flexible circuit board FCB to the lower surface BL-LS of the base layer BL.

[0148] According to an embodiment of the present disclosure, the base film BF may include a first portion B1 and a second portion B2 having different thicknesses. For example, the thickness of the second portion B2 may be greater than the thickness of the first portion B1. The first portion B1 may overlap the pad electrode PD on a plane (e.g., in a plan view). The first portion B1 may be arranged parallel to the pad electrode PD relative to a plane defined by the first direction DR1 and the second direction DR2. The second portion B2 may include a first sub-portion SB1 and a second sub-portion SB2, the first sub-portion SB1 being parallel to the base layer BL, the second sub-portion SB2 extending from the first sub-portion SB1 and including an inclined surface formed relative to the first sub-portion SB1 toward the second opening B2-OP. The first portion B1 and the second portion B2 may be, for example, integrally formed into a single uninterrupted structure. For example, the second sub-portion SB2 may be arranged between the first sub-portion SB1 and the first portion B1, and is formed by integrally connecting the first sub-portion SB1 and the first portion B1. The base film BF may include a synthetic resin material, for example, polyimide.

[0149] The raised electrode BMP may be arranged on the lower surface of the base film BF. According to an embodiment of the present disclosure, the raised electrode BMP may be provided on the lower surface of the first portion B1 of the base film BF. However, the present disclosure is not necessarily limited thereto, and as shown, the raised electrode BMP may be provided on the lower surfaces of the first portion B1 and the second portion B2.

[0150] The raised electrode BMP may overlap the pad electrode PD on a plane (e.g., in a plan view). The raised electrode BMP may contact the pad electrode PD and be electrically connected to the pad electrode PD. A plurality of raised electrodes BMP may be provided. A plurality of raised electrodes BMP may correspond to a plurality of pad electrodes PD. For example, one raised electrode BMP may correspond to one pad electrode PD. The raised electrode BMP may extend in a first direction DR1 and be arranged in a second direction DR2. The area of ​​the pad electrode PD on a plane (e.g., in a plan view) may be greater than the area of ​​the raised electrode BMP on a plane (e.g., in a plan view).

[0151] The base film BF may include a curved structure. For example, the space between the first sub-portion SB1 and the second sub-portion SB2 may be curved toward the second opening B2-OP, and the space between the second sub-portion SB2 and the first portion B1 may be curved parallel to the pad electrode PD. Therefore, the bump electrode BMP arranged to be in direct contact with the base film BF may also include a curved structure that is the same as that of the base film BF.

[0152] The adhesive layer AF may be disposed between the base film BF and the pad electrode PD. For example, the adhesive layer AF may be disposed between the first portion B1 and the pad electrode PD. According to an embodiment of the present disclosure, the adhesive layer AF may include a non-conductive material. For example, the adhesive layer AF may include a non-conductive film. The thickness of the adhesive layer AF may be greater than the thickness of the first portion B1.

[0153] The edge of the adhesive layer AF may be defined as a first edge BE1, the edge of the base film BF may be defined as a second edge BE2, and the edge of the bump electrode BMP may be defined as a third edge BE3. In an embodiment, the edge of the first portion B1 of the base film BF may be defined as a second edge BE2. According to an embodiment of the present disclosure, the first edge BE1, the second edge BE2, and the third edge BE3 may be aligned in parallel with respect to the third direction DR3. However, the present disclosure is not necessarily limited to the above example, and only the second edge BE2 and the third edge BE3 may be aligned in parallel with respect to the third direction DR3.

[0154] The protruding electrode BMP disposed under the first portion B1 may be electrically connected to the pad electrode PD disposed on the first portion B1. For example, the display device DD may further include a metal pattern MP electrically connecting the protruding electrode BMP and the pad electrode PD. The metal pattern MP is disposed on the pad electrode PD and the protruding electrode BMP, and electrically connects the pad electrode PD and the protruding electrode BMP. A plurality of metal patterns MP may correspond to the pad electrode PD and the protruding electrode BMP. In an embodiment, the metal pattern MP may electrically connect the display panel DP and the flexible circuit board FCB to each other.

[0155] Each of the metal patterns MP may be a pattern in which metal ink is cured. The metal pattern MP may include solder paste. The metal pattern MP may be formed of metal ink containing silver or copper. The metal patterns MP may be arranged on the pad electrodes PD, respectively.

[0156] The metal pattern MP may be formed by curing and then patterning the metal ink. The metal pattern MP may be formed at a low temperature and may electrically connect and simultaneously bond the pad electrode PD and the bump electrode BMP without a process of pressing at a high temperature. The process of forming the metal pattern MP will be described below.

[0157] In the display device DD, according to an exemplary embodiment of the present disclosure, the protruding electrode BMP may be directly disposed on the lower surface of the first portion B1 having a thickness smaller than that of the second portion B2, and electrically connected to the pad electrode PD through the metal pattern MP. Since the protruding electrode BMP is directly disposed on the lower surface of the first portion B1, in the process of arranging the flexible circuit board FCB so that the flexible circuit board FCB faces the pad electrode PD, a phenomenon in which the protruding electrode BMP is bent in the second direction DR2 or lifted in the third direction DR3 may be prevented. As a result, defects caused by alignment between the protruding electrode BMP and the pad electrode PD may be prevented, and thus a display device DD having increased reliability may be provided.

[0158] Fig. 10A is a cross-sectional view of a flexible circuit board according to an embodiment of the present disclosure. Fig. 10B is a cross-sectional view of a flexible circuit board according to an embodiment of the present disclosure. Fig. 10A and Fig. 10B Shown with Fig. 9 The bent flexible circuit board FCB shown in FIG. 1 is different from the flexible circuit boards FCB and FCBa before bending, and is shown in an inverted orientation. Fig. 9 The bent flexible circuit board FCB shown in FIG.

[0159] refer to Fig. 10A , the flexible circuit board FCB may include a base film BF, a bump electrode BMP disposed on the base film BF, and an adhesive layer AF disposed under the base film BF.

[0160] The base film BF may include a first portion B1 and a second portion B2 having different thicknesses. The first portion B1 may have a first thickness Th1, and the second portion B2 may have a second thickness Th2. The second thickness Th2 may be greater than the first thickness Th1. According to an embodiment of the present disclosure, the first thickness Th1 may be in a range of about 3% to about 20% of the second thickness Th2. For example, the second thickness Th2 may be in a range of about 30 μm to about 40 μm, and the first thickness Th1 may be in a range of about 1 μm to about 7 μm.

[0161] The raised electrode BMP may be disposed on the base film BF. As shown, the raised electrode BMP may be disposed on the first portion B1 and the second portion B2 of the base film BF. However, the present disclosure is not necessarily limited thereto, and the raised electrode BMP may be disposed only on the first portion B1. The thickness of the raised electrode BMP may be defined as a third thickness Th3. The third thickness Th3 may be greater than the first thickness Th1. For example, the third thickness Th3 may be in the range of about 8 μm to about 10 μm.

[0162] The adhesive layer AF may be disposed under the base film BF. For example, the adhesive layer AF may be disposed under the first portion B1 of the base film BF. The thickness of the adhesive layer AF may be defined as a fourth thickness Th4. The fourth thickness Th4 may be greater than the first thickness Th1 and the third thickness Th3. For example, the fourth thickness Th4 may be in a range of about 12 μm to about 18 μm.

[0163] refer to Fig. 10B , the flexible circuit board FCBa may include a base film BFa, a protruding electrode BMP disposed on the base film BFa, and an adhesive layer AF disposed under the base film BFa. The base film BFa may include a first portion B1 and a second portion B2a having different thicknesses. The second portion B2a may include a main portion MB having a uniform thickness and an inclined portion IB whose thickness gradually decreases. The thickness of the inclined portion IB may gradually decrease toward the first portion B1. The inclined portion IB may be adjacent to the first portion B1. For example, the inclined portion IB may be between the main portion MB and the first portion B1, and may be formed by integrally connecting the main portion MB and the first portion B1.

[0164] The angle formed between the first portion B1 and the second portion B2a may be an obtuse angle. For example, the angle formed between the inclined portions IB of the first portion B1 and the second portion B2a may be an obtuse angle. The angle formed between the inclined portions IB of the first portion B1 and the second portion B2a may be defined as a first angle θ. The first angle θ may be in the range of about 100° to about 170°.

[0165] refer to Fig. 9 and Fig. 10B, the flexible circuit board FCBa may be disposed on the rear surface of the display panel DP. In this case, the flexible circuit board FCBa may be bent between the first portion B1 and the second portion B2a and attached to the rear surface of the display panel DP. Since the first angle θ formed between the first portion B1 and the second portion B2a is in the range of about 100° to about 170°, the compressive stress or tensile stress occurring when the flexible circuit board FCBa is bent may be dispersed to prevent deformation of the flexible circuit board FCBa.

[0166] Fig.11 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. FIG. 12A to FIG. 14B is a diagram illustrating some operations of a method for manufacturing a display device according to an embodiment of the present disclosure. Figures 11 to 14B A method of manufacturing a display device DD according to the present disclosure is described.

[0167] refer to Figures 11 to 14B The method of manufacturing the display device DD according to the embodiment of the present disclosure may include an operation S100 of forming a display panel DP, an operation S200 of forming a flexible circuit board (or circuit board) FCB, an operation S300 of aligning the display panel DP and the flexible circuit board FCB, an operation S400 of bending the base film BF, and an operation S500 of forming a metal pattern MP. The display panel DP, the flexible circuit board FCB, and the metal pattern MP may include Fig. 9 The configurations of the display panel DP, the flexible circuit board FCB, and the metal pattern MP shown in FIG. 5 are the same configurations.

[0168] FIG. 12A to FIG. 12F FIG. 2 is a diagram showing operation S200 of forming a flexible circuit board FCB (see FIG. Fig.11 ) view.

[0169] refer to Fig. 12A and Fig. 12B , an operation of providing the preliminary base film P-BF and the preliminary bump electrode P-BMP on the upper surface BF-US of the preliminary base film P-BF and an operation of inverting the preliminary base film P-BF and the preliminary bump electrode P-BMP may be performed.

[0170] The preliminary base film P-BF may include a synthetic resin material, for example, polyimide. The preliminary raised electrode P-BMP on the preliminary base film P-BF may be formed by patterning a metal portion formed integrally. As a result, a plurality of preliminary raised electrodes P-BMP may be formed on the upper surface BF-US of the preliminary base film P-BF. In addition, an adhesive including conductivity or the like may be provided between the preliminary base film P-BF and the preliminary raised electrode P-BMP. Therefore, the preliminary base film P-BF and the preliminary raised electrode P-BMP may be fixedly attached to each other.

[0171] After forming the preliminary base film P-BF and the preliminary bump electrode P-BMP, an operation of inverting the inverted preliminary base film P-BF may be performed. For example, the lower surface BF-BS of the preliminary base film P-BF facing the upper surface BF-US of the preliminary base film P-BF may face the third direction DR3. Since the preliminary base film P-BF and the preliminary bump electrode P-BMP are fixedly attached to each other, even when the preliminary base film P-BF is inverted, the preliminary bump electrode P-BMP may be attached to the preliminary base film P-BF and may not be separated from the preliminary base film P-BF.

[0172] refer to Fig. 12C , a recessed DEP may be formed on the lower surface BF-BS of the preliminary base film P-BF. The recessed DEP may be formed by etching using a laser device LZD. The recessed DEP may be formed by irradiating the lower surface BF-BS of the preliminary base film P-BF with laser light emitted from the laser device LZD and etching the preliminary base film P-BF. The laser device LZD may move in the first direction DR1 and etch the preliminary base film P-BF. As a result, the recessed DEP may extend in the first direction DR1. The depth of the recessed DEP in the third direction DR3 may be in the range of about 80% to about 97% of the preliminary base film P-BF. The recessed DEP is shown to be perpendicular to the lower surface BF-BS, but the present disclosure is not necessarily limited thereto, and the recessed DEP may be inclined relative to the lower surface BF-BS.

[0173] refer to Fig.12D , an operation of arranging the preliminary adhesive layer P-AF in the recess DEP of the preliminary base film P-BF may be performed. The width of the preliminary adhesive layer P-AF in the second direction DR2 may be the same as the width of the recess DEP in the second direction DR2. The thickness of the preliminary adhesive layer P-AF in the third direction DR3 may be less than the depth of the recess DEP.

[0174] refer to Fig.12E and Fig.12F, an operation of forming a flexible circuit board FCB can be performed by cutting a preliminary base film P-BF, a preliminary adhesive layer P-AF, and a preliminary convex electrode P-BMP. The preliminary base film P-BF, the preliminary adhesive layer P-AF, and the preliminary convex electrode P-BMP can be cut relative to a cutting line CL that is parallel to the first direction DR1 and overlaps with the recess DEP on a plane (for example, in a plan view). The operation of cutting the preliminary base film P-BF, the preliminary adhesive layer P-AF, and the preliminary convex electrode P-BMP can be performed using a laser device LZD. The laser device LZD can move in the first direction DR1 and cut the preliminary base film P-BF, the preliminary adhesive layer P-AF, and the preliminary convex electrode P-BMP along the cutting line CL. As a result, a flexible circuit board FCB including a base film BF, a convex electrode BMP arranged under the base film BF, and an adhesive layer AF can be provided. The base film BF may include a first portion B1 and a second portion B2 having different thicknesses. The thickness of the second portion B2 may be greater than the thickness of the first portion B1.

[0175] refer to FIG. 12A to FIG. 12F In the operation of forming the flexible circuit board FCB according to the embodiment of the present disclosure, the protruding electrode BMP may be arranged and formed on the first portion B1. As a result, compared with the case where the protruding electrode BMP is not arranged on the first portion B1, the first portion B1 is removed, and the protruding electrode BMP is exposed, the process of removing the first portion B1 is omitted, and thus the process of forming the flexible circuit board FCB may be simplified.

[0176] Fig.13A FIG. 2 is an operation S300 showing the alignment of the display panel DP and the flexible circuit board FCB (see FIG. 2 ). Fig.11 ) cross-sectional view.

[0177] refer to Fig.13A , the flexible circuit board FCB may be disposed under the display panel DP. For example, the flexible circuit board FCB may be disposed on the lower surface BL-LS of the base layer BL of the display panel DP. The flexible circuit board FCB may be disposed in the second opening B2-OP of the base layer BL. For example, a portion of the flexible circuit board FCB overlapping the first portion B1 may be arranged in the second opening B2-OP. The adhesive layer AF of the flexible circuit board FCB may be in direct contact with the pad electrode PD. When viewed in the third direction DR3, the first portion B1 and the pad electrode PD may face each other.

[0178] Fig. 13B FIG. 4 is an operation S400 showing the bending of the base film BF (see FIG. Fig.11 ) cross-sectional view.

[0179] refer to Fig. 13B, the base film BF may be bent toward the pad electrode PD. For example, the base film BF may be bent so that the first portion B1 is parallel to the pad electrode PD. As shown, the base film BF may be bent by pressing the raised electrode BMP overlapping the first portion B1 toward the pad electrode PD. The space between the first portion B1 and the second portion B2 may be bent toward the pad electrode PD by applying a force F directly to the raised electrode BMP overlapping the first portion B1. As a result, the adhesive layer AF may be brought into direct contact with the pad electrode PD, and the first portion B1 may be disposed in parallel with the pad electrode PD.

[0180] FIG. 13C to FIG. 14B FIG. 5 is an operation S500 of forming the metal pattern MP (see FIG. Figure 1 ) view. Fig.14A and Fig. 14B is a cross-sectional view of a portion of the display device DD according to the present disclosure to illustrate an operation of forming the metal pattern MP.

[0181] refer to Fig. 13C and Fig.14A , a metal layer MTL may be disposed on the pad electrode PD and the bump electrode BMP. The metal layer MTL may be integrally formed in a region overlapping the pad electrode PD and the bump electrode BMP and in a region disposed between the bump electrodes BMP and not overlapping the bump electrode BMP. The metal layer MTL may be exposed with a laser beam LZ. The laser beam LZ may be guided to the metal layer MTL disposed in a region not overlapping the pad electrode PD and the bump electrode BMP.

[0182] refer to Fig.14A and Fig. 14B When the metal layer MTL disposed in the region not overlapping the pad electrode PD and the bump electrode BMP is exposed by the laser beam LZ, the metal layer MTL disposed in the region not overlapping the pad electrode PD and the bump electrode BMP may be patterned. As a result, a plurality of metal patterns MP disposed on the pad electrode PD and the bump electrode BMP may be formed. The metal pattern MP may electrically connect the pad electrode PD and the bump electrode BMP.

[0183] A flexible circuit board includes: a base film including a first portion and a second portion having different thicknesses; and a plurality of protruding electrodes arranged on a lower surface of the first portion having a small thickness. Since the protruding electrodes are directly arranged on the lower surface of the first portion, in a process of arranging the flexible circuit board so that the protruding electrodes and the pad electrodes arranged on the rear surface of the display panel face each other, a phenomenon in which the protruding electrodes are bent or lifted can be prevented. As a result, defects caused by alignment of the protruding electrodes and the pad electrodes can be prevented, and thus a display device with increased reliability can be provided.

[0184] Although the above description is made with reference to the embodiments of the present disclosure, it will be appreciated that a person skilled in the art or a person of ordinary skill in the art may make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure.

[0185] Therefore, the technical scope of the present disclosure is not necessarily limited to the detailed description of the specification.

Claims

1. A display device, comprising: a display panel configured to display an image; A circuit board connected to the display panel; as well as a metal pattern, electrically connecting the display panel and the circuit board to each other, Wherein, the display panel comprises: a base layer including a pad electrode exposed through the opening; and a circuit layer disposed on the base layer and including at least one signal line electrically connected to the pad electrode, Wherein, the circuit board comprises: a base film including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness; and a raised electrode disposed on the first portion, wherein the first portion is disposed between the pad electrode and the protruding electrode, and The metal pattern is disposed on the pad electrode and the bump electrode and electrically connects the pad electrode and the bump electrode to each other.

2. The display device according to claim 1, wherein: The pad electrode is a first pad electrode among a plurality of pad electrodes, and Each of the plurality of pad electrodes extends in a first direction and the plurality of pad electrodes are arranged in a second direction intersecting the first direction.

3. The display device according to claim 2, wherein: A plurality of bump electrodes and a plurality of metal patterns correspond to the plurality of pad electrodes.

4. The display device according to claim 1, further comprising: An adhesive layer is disposed between the first portion and the pad electrode.

5. The display device according to claim 4, wherein: The thickness of the adhesive layer is greater than the first thickness.

6. The display device according to claim 4, wherein: The adhesive layer includes a non-conductive film.

7. The display device according to claim 1, wherein: The second part includes: a first sub-portion extending parallel to the base layer; and The second sub-portion extends from the first sub-portion and includes an inclined surface.

8. The display device according to claim 7, wherein: The second subsection is disposed between the first subsection and the first section, and integrally connects the first subsection and the first section to each other.

9. The display device according to claim 1, wherein: The second portion includes an inclined portion whose thickness gradually decreases toward the first portion.

10. The display device according to claim 9, wherein: The inclined portion is adjacent to the first portion.

11. The display device according to claim 1, wherein: The first portion extends parallel to the pad electrode.

12. The display device according to claim 1, wherein: An edge of the first portion and an edge of the bump electrode are aligned parallel to each other.

13. The display device according to claim 1, wherein: The base layer includes: a first sub-base layer having the opening defined therein; and A second sub-base layer is provided on the first sub-base layer, Wherein, the pad electrode is arranged between the first sub-base layer and the second sub-base layer.

14. The display device according to claim 13, wherein: The signal line is disposed on an upper surface of the second sub-base layer, and A contact hole is formed in the second sub-base layer, and the signal line and the pad electrode are connected through the contact hole.

15. The display device according to claim 1, wherein: The first thickness is in a range of 3% to 20% of the second thickness.

16. The display device according to claim 1, wherein: The display panel includes a display area and a non-display area, and Wherein, the pad electrode overlaps with the non-display area.

17. A method for manufacturing a display device, the method comprising: forming a display panel, the display panel comprising a base layer and a circuit layer, the base layer comprising a pad electrode exposed through the opening, the circuit layer comprising at least one signal line electrically connected to the pad electrode; forming a circuit board, the circuit board comprising a base film and a plurality of protruding electrodes, the base film comprising a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, the plurality of protruding electrodes being disposed on the first portion; aligning the display panel and the circuit board so that the first portion faces the pad electrode; bending the base film so that the first portion is parallel to the pad electrode; as well as A plurality of metal patterns are formed on the bump electrodes and the pad electrodes to electrically connect the bump electrodes and the pad electrodes to each other through the metal patterns.

18. The method according to claim 17, wherein: Forming the circuit board includes: providing a preliminary base film and a preliminary bump electrode on an upper surface of the preliminary base film; forming a recess extending in a first direction on a lower surface of the preliminary base film facing the upper surface; and The preliminary base film and the preliminary bump electrode are cut in a direction parallel to the first direction while overlapping with the recess.

19. The method according to claim 18, wherein: Forming the circuit board also includes: Before cutting the preliminary base film and the preliminary bump electrodes, an adhesive layer is disposed on the recesses.

20. The method according to claim 19, wherein: An edge of the adhesive layer, an edge of the first portion, and an edge of the bump electrode are aligned parallel to each other in a thickness direction of the base film.

21. The method according to claim 18, wherein: Forming the circuit board also includes: The preliminary base film and the preliminary bump electrode are reversed before forming the recess.

22. The method according to claim 17, wherein: Bending the base film comprises: The base film is bent by pressing the bump electrode provided on the first portion directly toward the pad electrode.

23. The method according to claim 17, wherein: An angle formed between the first portion and the second portion before bending the base film is an obtuse angle.

24. The method of claim 17, wherein: Forming the metal pattern comprises: disposing a metal layer on the pad electrode and the bump electrode; and The metal layer is patterned to form the metal pattern.

25. The method according to claim 24, wherein: Patterning the metal layer includes exposing a portion of the metal layer in a region not overlapping the pad electrode with a laser beam.

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